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    Test1-S 2014

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    Prabhpreet Singh Ajmani
    The document contains a test for a microprocessor programming and interfacing course. It includes 6 multiple choice questions related to 80486 assembly language programming and machine cycles.

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    Test1-S 2014

    Uploaded by

    Prabhpreet Singh Ajmani
    40 views3 pages
    The document contains a test for a microprocessor programming and interfacing course. It includes 6 multiple choice questions related to 80486 assembly language programming and machine cycles.

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    test1-s_2014

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    The document contains a test for a microprocessor programming and interfacing course. It includes 6 multiple choice questions related to 80486 assembly language programming and machine cycles.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    40 views3 pages

    Test1-S 2014

    Uploaded by

    Prabhpreet Singh Ajmani
    The document contains a test for a microprocessor programming and interfacing course. It includes 6 multiple choice questions related to 80486 assembly language programming and machine cycles.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI- KK Birla Goa Campus

    II SEMESTER 2013-2014
    EEEF241/CSF241/INSTRF241MICROPROCESSOR PROGRAMMING AND INTERFACING
    TEST I (OPEN BOOK)-Solutions
    TIME: 60 Min. 28/02/2014 MM: 40
    IDNO: Name:

    Q1. Construct the machine code in hexadecimal for the following 80486(operating in 32-bit mode)
    instructions. [4]
    (i) MOV AL, ES: [EAX+2*ESI] 26 8A 04 70

    (ii) MOV CX,[SI+BX+10] 67668B4810


    Q2. Replace the following program segments by a single instruction of 80486 [8]
    Program Instruction Program Instruction
    A PUSH SI XADD SI,DI B JNC X1 ADC BX,CX
    ADD SI,DI ADD BX,1
    POP DI X1: ADD BX,CX
    C MOV EBX,EAX BSWAP EAX D BT AX,15 CWDE
    MOV ECX,EAX JC X1
    MOV EDX,EAX AND EAX,0000FFFFH
    AND EAX,000000FFH JMP X2
    AND EBX,0000FF00H X1: OR EAX, FFFF0000H
    AND ECX,00FF0000H X2:
    AND EDX,FF000000H
    ROL EDX, 8
    ROR ECX,8
    ROL EBX,8
    ROR EAX,8
    OR EAX,EBX
    OR EAX,ECX
    OR EAX,EDX

    Q3. For the following Instructions what will be the machine cycles executed by 8086 [4]
    Instruction Cycles Instruction Cycles
    A POP AX MEMR – Instruction B ADD [SI],AX MEMR – Instruction
    MEMR – operand
    MEMR – Into AX
    MEMW - Result
    C CBW MEMR – Instruction D INC Word Ptr [SI] MEMR – Instruction
    MEMR – Operand
    MEMW - Result

    Q4. Write an 80486 ALP that will add the two nibbles in a data byte together and if there is a carry in the
    nibble addition it will right ‘C’ into a memory location. If there is no carry in nibble addition it will write
    ‘N’ into the location. This has to be done on array of 25d data bytes stored from location dat1. The
    result for each byte must be written from location car1.
    For E.g. If
    dat1 db 45h,89h,27h, 0F2h, 3Eh and so on
    The program has to add 4 and 5 in case of first byte and there will be no carry in adding the two nibbles
    (4-bit addition) so N has to be written into car1 and if case of 2nd data 8 and 9 will be added and result
    will have a carry in the nibble addition so C will be written into next location.
    Hence after the program is executed the location
    car1 will have the values ‘N’, ‘C’, ‘N’,’C’,’C’ and so on [10]
    .model Tiny
    .486
    .data
    dat1 db 89h,3eh,0f1h,45h,23h,89h,3eh,0f1h,45h,23h,89h,3eh,0f1h,45h,23h,89h,3eh,0f1h,
    45h,23h,89h,3eh,0f1h,45h,23h
    car1 db 25 dup('N')
    .code
    .start
    lea si,dat1
    lea di,car1
    mov cx,25
    mov dh,'C'
    x1: lodsb
    mov ah,al
    and al,0fh
    and ah,0f0h
    rol al,4
    add ah,al
    jnc x2
    mov [di],dh
    x2: inc di
    loop x1
    .exit
    end

    Q5. Given below is an 8086 assembly program.


    .Model Tiny
    . DATA
    DAT1 DB 45H, 54H, 46H
    P1 EQU 97H
    DAT2 DW 23F8H, 2435H
    DAT3 DB ‘’INTER’’
    DAT4 DB 6 DUP (122)
    DAT5 DB 3 DUP (?)
    DAT6 DW 33H
    DAT7 DB 0FH
    .CODE
    .STARTUP
    MOV AL, DAT1+1
    ADD AL,DAT4
    CBW
    MOV BX, 12AH
    MOV CX, [BX+4]
    XOR CH,P1
    (a) Write the contents of memory in data segment that result from data declarations in the above
    program in the tabular format given below. (i.e., for 24 locations in data segment assume starting
    from offset 0118H to 012FH) (You may use ‘A’ to represent ASCII byte for the character A. If the
    contents cannot be determined put a ‘X’ in the box. All values except for ASCII values must be in
    hexadecimal)

    DS:0118H 45 54 46 F8 23 35 24 ‘I’
    DS:0120H ‘N’ ‘T’ ‘E’ ‘R’ 7A 7A 7A 7A
    DS:0128H 7A 7A X X X 33 00 0F
    (b) For the code section of the above program. Fill in the table below. (You can assume that all status flags
    are cleared initially). You only need to show contents of registers that are affected. Values must of
    registers must be given in hexadecimal.

    Instruction Register Addressing Mode ACF OF SF PF CF ZF


    contents

    MOV AL,DAT1+1 AL =54 Direct 0 0 0 0 0 0

    ADD AL,DAT4 AL = CE Direct 0 1 1 0 0 0

    CBW AX = FFCE Implied 0 1 1 0 0 0

    MOV BX, 12AH BX = 012A Immediate 0 1 1 0 0 0

    MOV CX,[BX+4] CX = 0F00 Register Relative 0 1 1 0 0 0

    XOR CH,P1 CH = 98 Immediate 0 0 1 0 0 0

    [3+9]
    Q6. If a processor is working at 5 MHz and Ready Signal is made low for 3 T states a normal MEMR
    machine cycle will execute for 1400 ns [2]

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