ACS781 Datasheet

ACS781xLR
High-Precision Linear Hall-Effect-Based

Current Sensor IC with 200 µΩ Current Conductor
FEATURES AND BENEFITS DESCRIPTION

▪ Core-less, micro-sized, 100 A continuous current package The Allegro ACS781xLR is a fully integrated current sensor
▪ Ultra-low power loss: 200 µΩ internal conductor linear IC in a new core-less package designed to sense AC and
resistance DC currents up to 100 A. This automotive-grade, low-profile
▪ Immunity to common-mode field interference (1.5 mm thick) sensor IC package has a very small footprint.
▪ Greatly improved total output error through digitally The Hall sensor technology also incorporates common-mode
programmed and compensated gain and offset over the full field rejection to optimize performance in the presence of
operating temperature range interfering magnetic fields generated by nearby current carrying
▪ Industry-leading noise performance through proprietary conductors.
amplifier and filter design techniques
The device consists of a precision, low-offset linear Hall circuit
▪ Integrated shield greatly reduces capacitive coupling from
with a copper conduction path located near the die. Applied
current conductor to die due to high dV/dt signals, and
current flowing through this copper conduction path generates
prevents offset drift in high-side, high-voltage applications
a magnetic field which the Hall IC converts into a proportional
▪ Monolithic Hall IC for high reliability
voltage. Device accuracy is optimized through the proximity
▪ 3 to 3.6 V, single supply operation
of the primary conductor to the Hall transducer and factory
▪ 120 kHz typical bandwidth
programming of the sensitivity and quiescent output voltage
▪ 3.6 µs output rise time in response to step input current
at the Allegro factory.
▪ Output voltage proportional to AC or DC currents
▪ Factory-trimmed for accuracy Chopper-stabilized signal path and digital temperature
▪ Extremely stable quiescent output voltage compensation technology also contribute to the stability of the
▪ AEC-Q100 automotive qualification device across the operating temperature range.
High-level immunity to current conductor dV/dt and stray
PACKAGE: electric fields, offered by Allegro proprietary integrated shield
7-pin PSOF package (suffix LR) technology for low-output voltage ripple and low-offset drift
in high-side, high-voltage applications.
The output of the device has a positive slope (>VCC / 2) when an
increasing current flows through the primary copper conduction
Continued on the next page…
Not to scale
ACS781xLR
RF
5 3
IP+ VOUT VOUT
CF
IP 2
GND
CBYP 3.3 V
6
IP– 0.1 µF
1
VCC
Typical Application
Application 1: The ACS781xLR outputs an analog signal, VOUT , that varies linearly with the bidirectional AC or DC primary
current, IP , within the range specified. CF is for optimal noise management, with values that depend on the application.
ACS781xLR-DS, Rev. 6 May 17, 2021

MCO-0000276
ACS781xLR Current Sensor IC with 200 µΩ Current Conductor
DESCRIPTION (CONTINUED)
path (from terminal 5 to terminal 6), which is the path used for 4, and 7), and allows the device to operate safely with voltages up
current sampling. The internal resistance of this conductive path is to 100 V peak on the primary conductor.
200 µΩ typical, providing low power loss.
The device is fully calibrated prior to shipment from the factory.
The thickness of the copper conductor allows survival of the device The ACS781xLR family is lead (Pb) free. All leads are plated with
at high overcurrent conditions. The terminals of the conductive 100% matte tin, and there is no Pb inside the package. The heavy
path are electrically isolated from the signal leads (pins 1 through gauge leadframe is made of oxygen-free copper.
SELECTION GUIDE
Primary Sampled Sensitivity
Sensed Current TOP
Part Number Current, IP Sens (Typ.) Packing [1]
Direction (°C)
(A) (mV/A)
ACS781LLRTR-050B-T Bidirectional ±50 26.4
ACS781LLRTR-050U-T Unidirectional 0 to 50 39.6
–40 to 150
ACS781LLRTR-100B-T Bidirectional ±100 13.2
ACS781LLRTR-100U-T Unidirectional 0 to 100 26.4 Tape and reel
±150 transient
ACS781KLRTR-150B-T Bidirectional 8.8
±100 continuous
–40 to 125
0 to 150 transient
ACS781KLRTR-150U-T Unidirectional 17.6
0 to 100 continuous
[1] Contact Allegro for additional packing options.
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 6 V
Reverse Supply Voltage VRCC –0.5 V
Forward Output Voltage VOUT 25 V
Reverse Output Voltage VRIOUT –0.5 V
Output Source Current IOUT(Source) VOUT to GND 2.8 mA
Output Sink Current IOUT(Sink) Minimum pull-up resistor of 500 Ω 10 mA
Range K –40 to 125 °C
Nominal Operating Ambient Temperature TOP
Range L –40 to 150 °C
Maximum Junction TJ(max) 165 °C
Storage Temperature Tstg –65 to 165 °C
THERMAL CHARACTERISTICS: May require derating at maximum conditions

Characteristic Symbol Test Conditions [1] Value Unit
Mounted on the Allegro evaluation board ASEK781
85-0807-001 with FR4 substrate and 8 layers of 2 oz.
copper (with an area of 1530 mm2 per layer) connected to
Package Thermal Resistance RθJA the primary leadframe and with thermal vias connecting 18 °C/W
the copper layers. Performance is based on current flow-
ing through the primary leadframe and includes the power
consumed by the PCB.
[1] Additional thermal information available on the Allegro website
TYPICAL OVERCURRENT CAPABILITIES [2][3]

Characteristic Symbol Notes Rating Unit
TA = 25°C, 1 s on time, 60 s off time 285 A
Overcurrent IPOC
[2] Test was done with Allegro evaluation board (85-0807-001). The maximum allowed current is limited by TJ(max) only.
[3] For more overcurrent profiles, please see FAQ on the Allegro website, www.allegromicro.com.
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IP+ VCC
ACS781xLR
To all subcircuits
Master Current
Supply
Temperature EEPROM and Programming

Sensor Control Logic Control
Hall Current
Drive
Sensitivity Offset
Control Control
Dynamic Offset
Cancellation
Tuned VOUT
Amp Filter
IP– GND
Functional Block Diagram
NC Pinout List
4 Number Name Description
IP+ 5 3 VOUT
1 VCC Device power supply terminal
2 GND 2 GND Signal ground terminal
3 VOUT Analog output signal
IP– 6 1 VCC
No connection, connect to GND for optimal
7 4 NC
ESD performance
NC
5 IP+ Terminal for current being sampled
6 IP– Terminal for current being sampled
Pinout Diagram No connection, connect to GND for optimal
7 NC
ESD performance
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COMMON OPERATING CHARACTERISTICS: Valid at TOP = –40°C to 150°C and VCC = 3.3 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage VCC 3 3.3 3.6 V
Supply Current ICC Output open – 11 15 mA
Power-On Time tPO TA = 25°C, CBYPASS = Open, CL = 1 nF – 180 – µs
Temperature Compensation
tTC CBYPASS = Open, CL= 1 nF – 50 – µs
Time
VPORH TA = 25°C, VCC rising – 2.85 – V
Power-On Reset Voltage
VPORL TA = 25°C, VCC falling – 2.6 – V
Power-On Reset Hysteresis VPORHYST – 250 – mV
Power-On Reset Release Time tPORR TA = 25°C, VCC rising – 150 – µs
Power-On Reset Disable Time tPORD TA = 25°C, CL = 1 nF – 14 – µs
Supply Zener Clamp Voltage Vz TA = 25°C, ICC = 30 mA 6.5 7.5 – V
Internal Bandwidth BWi Small signal –3 dB, CL = 1 nF, TA = 25°C – 120 – kHz
Chopping Frequency fC TA = 25°C – 500 – kHz
Oscillator Frequency fOSC TA = 25°C – 8 – MHz
OUTPUT CHARACTERISTICS
Propagation Delay Time tpd TA = 25°C, CL = 1 nF – 2.2 – µs
Rise Time tr TA = 25°C, CL = 1 nF – 3 – µs
Response Time tRESPONSE TA = 25°C, CL = 1 nF – 3.6 – µs
VSAT(HIGH) TA = 25°C, RLOAD = 10 kΩ to GND 3.1 – – V
Output Saturation Voltage
VSAT(LOW) TA = 25°C, RLOAD = 10 kΩ to VCC – – 200 mV
DC Output Resistance ROUT RL = 4.7 kΩ from VOUT to GND, VOUT = VCC / 2 – <1 – Ω
RL(PULLUP) VOUT to VCC 4.7 – – kΩ
Output Load Resistance
RL(PULLDWN) VOUT to GND 4.7 – – kΩ
Output Load Capacitance CL VOUT to GND – 1 10 nF
Primary Conductor Resistance RPRIMARY TA = 25°C – 200 – µΩ
VOUT(QBI) IP = 0 A, TA = 25°C – VCC/2 – V
Quiescent Output Voltage
VOUT(QU) Unidirectional variant, IP = 0 A, TA = 25°C – VCC × 0.1 – V
Ratiometry Quiescent Output
RatERRVOUT(Q) Through supply voltage range ( VCC = 3.3 V) – 0 – %
Voltage Error
Ratiometry Sensitivity Error RatERRSens Through supply voltage range ( VCC = 3.3 V) – < ±0.5 – %
Common-Mode Magnetic Field
CMFR Magnetic field perpendicular to Hall plates – –35 – dB
Rejection
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X050B PERFORMANCE CHARACTERISTICS [1]: TOP = –40°C to 150°C, VCC = 3.3 V, unless otherwise specified
Primary Sampled Current IP –50 – 50 A
SensTA Measured using 50% of full-scale IP , TA = 25°C 25.5 26.4 27.258 mV/A
Sensitivity Sens(TOP)HT Measured using 50% of full-scale IP , TOP = 25°C to 150°C 25.542 26.4 27.258 mV/A
Sens(TOP)LT Measured using 50% of full-scale IP , TOP = –40°C to 25°C 25.41 26.4 27.39 mV/A
VNOISEPP Peak-to-peak, TA= 25°C, 1 nF on VOUT pin to GND – 36 – mV
Noise [2] mARMS
INOISE Input referred – 0.6 – /√(Hz)
Nonlinearity ELIN Measured using ±32 A and ±16 A –1 – 1 %

VOE(TA) IP = 0 A, TA = 25°C –10 ±3 10 mV
Electrical Offset Voltage [3][4] VOE(TOP)HT IP = 0 A, TOP = 25°C to 150°C –10 ±5 10 mV
VOE(TOP)LT IP = 0 A, TOP = –40°C to 25°C –20 ±10 20 mV
Electric Offset Voltage Over TOP = –40°C to 150°C, estimated shift after AEC-Q100 grade 0
ΔVOE(LIFE) – ±1 – mV
Lifetime [5] qualification testing
ETOT(HT) Measured using 50% of full-scale IP , TOP = 25°C to 150°C –3.25 ±0.8 3.25 %
Total Output Error
ETOT(LT) Measured using 50% of full-scale IP , TOP = –40°C to 25°C –3.75 ±1.5 3.75 %
Total Output Error Including ETOT(HT,LIFE) Measured using 50% of full-scale IP , TOP = 25°C to 150°C –4.1 ±2.28 4.1 %
Lifetime Drift [6] ETOT(LT,LIFE) Measured using 50% of full-scale IP , TOP = –40°C to 25°C –5.6 ±2.98 5.6 %
[1] See Characteristic Performance Data page for parameter distributions over temperature range.
[2] ±3 sigma noise voltage.
[3] Drift is referred to ideal VOUT(QBI) = 1.65 V.
[4] This parameter may drift a maximum of ΔV
OE(LIFE) over lifetime.
[5] Based on characterization data obtained during standardized stress test for Qualification of Integrated Circuits, including Package Hysteresis. Cannot be guaranteed.
Drift is a function of customer application conditions. Contact Allegro MicroSystems for further information.
[6] The maximum drift of any single device during qualification testing was 4%. Total Output Error Including Lifetime Drift incorporates both sensitivity over lifetime and
electrical offset voltage over lifetime.
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X050U PERFORMANCE CHARACTERISTICS [1]: TOP = –40°C to 150°C, VCC = 3.3 V, unless otherwise specified
Primary Sampled Current IP 0 – 50 A
VNOISEPP Peak-to-peak, TA= 25°C, 1 nF on VOUT pin to GND – 35.6 – mV
Noise [2] mARMS
Nonlinearity ELIN Measured using 32 A and 16 A –1 – 1 %

VOE(TA) IP = 0 A, TA = 25°C –10 ±3 10 mV
Total Output Error
[3] Drift is referred to ideal VOUT(QU)= 0.33 V.
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Primary Sampled Current IP –100 – 100 A
Noise [2] mARMS

VOE(TA) IP = 0 A, TA = 25°C –10 ±3 10 mV
Total Output Error
[3] Drift is referred to ideal VOUT(QBI) = 1.65 V.
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Primary Sampled Current IP 0 – 100 A
Noise [2] mARMS

VOE(TA) IP = 0 A, TA = 25°C –10 ±3 10 mV
Total Output Error
[3] Drift is referred to ideal VOUT(QU) = 0.33 V.
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Transient –150 – 150 A
Primary Sampled Current IP
Continuous –100 – 100 A
Noise [2] mARMS

VOE(TA) IP = 0 A, TA = 25°C –10 ±3 10 mV
Total Output Error
[3] Drift is referred to ideal V
OUT(QBI) = 1.65 V.
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Transient 0 – 150 A
Primary Sampled Current IP
Continuous 0 – 100 A
Noise [2] mARMS

VOE(TA) IP = 0 A, TA = 25°C –10 ±3 10 mV
Total Output Error
[3] Drift is referred to ideal V
OUT(QU) = 0.33 V.
[5] Based on characterization data obtained during standardized stress test for Qualification of Integrated Circuits, including Package Hysteresis. Cannot be guaranteed. Drift
is a function of customer application conditions. Contact Allegro MicroSystems for further information.
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CHARACTERISTIC PERFORMANCE DATA

DATA TAKEN USING THE ACS781KLR-150B
Response Time (tRESPONSE)
IP = 90 A with 10-90% rise time = 1 µs, CBYPASS = 0.1 µF, CL = 1 nF
Rise Time (tr)

IP = 90 A with 10%-90% rise time = 1 µs, CBYPASS = 0.1 µF, CL = 1 nF
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Propagation Delay (tPD)

IP = 90 A with 10% - 90% rise time = 1 µs, CBYPASS = 0.1 µF, CL = 1 nF
Power-On Time (tPO)

IP = 60 A DC, CBYPASS = Open, CL = 1 nF
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CHARACTERISTIC PERFORMANCE
ACS781 TYPICAL FREQUENCY RESPONSE
-5
Magnitude [dB]
-10
-15
10 1 10 2 10 3 10 4 10 5
Frequency [Hz]
50
0
Phase [°]
-50
-100
-150
10 1 10 2 10 3 10 4 10 5
Frequency [Hz]
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CHARACTERISTIC DEFINITIONS
Definitions of Accuracy Characteristics

SENSITIVITY (Sens) and the ratiometric change (%) in sensitivity is defined as:
The change in device output in response to a 1 A change through
the primary conductor. The sensitivity is the product of the mag-
netic circuit sensitivity (G / A) and the linear IC amplifier gain
RatERRSens =
( 1–
Sens(VCC)
VCC
Sens(3.3V)
3.3 V ) × 100%
(mV/G). The linear IC amplifier gain is programmed at the factory

QUIESCENT OUTPUT VOLTAGE (VOUT(Q))
to optimize the sensitivity (mV/A) for the half-scale current of the
device. The output of the device when the primary current is zero. For
bidirectional sensors, it nominally remains at VCC ⁄ 2 and for
NOISE (V NOISE) unidirectional sensors at 0.1 × VCC. Thus, VCC = 3.3 V trans-
The noise floor is derived from the thermal and shot noise lates into VOUT(BI) = 1.65 V and VOUT(QU) = 0.33 V. Variation in
observed in Hall elements. Dividing the noise (mV) by the sen- VOUT(Q) can be attributed to the resolution of the Allegro linear
sitivity (mV/A) provides the smallest current that the device can IC quiescent voltage trim and thermal drift.
resolve.
ELECTRICAL OFFSET VOLTAGE (VOE)
NONLINEARITY (E LIN) The deviation of the device output from its ideal quiescent value
The ACS781xLR is designed to provide a linear output in due to nonmagnetic causes.
response to a ramping current. Consider two current levels: I1
TOTAL OUTPUT ERROR (E TOT)
and I2. Ideally, the sensitivity of a device is the same for both
currents, for a given supply voltage and temperature. Nonlinear- The maximum deviation of the actual output from its ideal value,
ity is present when there is a difference between the sensitivities also referred to as accuracy, illustrated graphically in the output
measured at I1 and I2. Nonlinearity is calculated separately for voltage versus current chart on the following page.
the positive (ELINpos ) and negative (ELINneg ) applied currents as ETOT is divided into four areas:
follows:
• 0 A at 25°C. Accuracy at the zero current flow at 25°C,
ELINpos = 100 (%) × {1 – (SensIPOS2 / SensIPOS1 ) } without the effects of temperature.
• 0 A over Δ temperature. Accuracy at the zero current flow
ELINneg = 100 (%) × {1 – (SensINEG2 / SensINEG1 )} including temperature effects.
where: • Full-scale current at 25°C. Accuracy at the full-scale current at
25°C, without the effects of temperature.
SensIx = (VIOUT(Ix) – VIOUT(Q))/ Ix • Full-scale current over Δ temperature. Accuracy at the full-
scale current flow including temperature effects.
and IPOSx and INEGx are positive and negative currents.
Then: VIOUT(IP) – VIOUT_IDEAL(IP)
ETOT(IP) = × 100 (%)
SensIDEAL × IP
ELIN = max( ELINpos , ELINneg )
where
RATIOMETRY VIOUT_IDEAL(IP) = VIOUT(Q) + (SensIDEAL × IP )

The device features a ratiometric output. This means that the
quiescent voltage output, VOUTQ, and the magnetic sensitivity,
Sens, are proportional to the supply voltage, VCC.The ratiometric
change (%) in the quiescent voltage output is defined as:
RatERRVOUT(Q) =
( 1–
VOUT(Q)(VCC)
VCC
VOUT(Q)(3.3V)
3.3 V ) × 100%
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DEFINITIONS OF DYNAMIC RESPONSE CHARACTERISTICS
POWER-ON TIME (tPO)

When the supply is ramped to its operating voltage, the device
requires a finite time to power its internal components before
responding to an input magnetic field.
Power-On Time, tPO, is defined as the time it takes for the output
voltage to settle within ±10% of its steady state value under an
applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in the
chart at right.
RISE TIME (tr)

The time interval between a) when the device reaches 10% of
its full-scale value, and b) when it reaches 90% of its full scale
value. Both tr and tRESPONSE are detrimentally affected by eddy
current losses observed in the conductive IC ground plane.
Power-On Time (tPO)
RESPONSE TIME (tRESPONSE)
The time interval between a) when the applied current reaches
(%) Primary Current
80% of its final value, and b) when the sensor reaches 80% of its
output corresponding to the applied current.
90
VOUT
PROPAGATION DELAY (tPD)
The time interval between a) when the input current reaches 20%
Rise Time, tr
of its final value, and b) when the output reaches 20% of its final
value. 20
10
POWER-ON RESET VOLTAGE (V POR ) 0
Propagation Delay, tPROP t
At power-up, to initialize to a known state and avoid current
spikes, the sensor is held in Reset state. The Reset signal is
Propagation Delay (tPD) and Rise Time (tr)
disabled when VCC reaches VPORH and time tPORR has elapsed,
allowing output voltage to go from a high-impedance state
into normal operation. During power-down, the Reset signal is
enabled when VCC reaches VPORL , causing output voltage to go
into a high-impedance state. (Note that a detailed description of (%) Primary Current
POR operation can be found in the Functional Description sec-
tion.) 80
VOUT
Response Time, tRESPONSE
0
t
Response Time (tRESPONSE)
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POWER-ON RESET RELEASE TIME (tPORR) Accuracy

Increasing VIOUT(V) Over ∆Temp erature
When VCC rises to VPORH , the Power-On Reset Counter starts.

Accuracy
The sensor output voltage will transition from a high-impedance 25°C Only
state to normal operation only when the Power-On Reset Counter Average
has reached tPORR. VIOUT
Accuracy
Over ∆Temp erature
Accuracy
25°C Only
IP(min)
–IP (A) +IP (A)
Half Scale
IP(max)
0A
Decreasing VIOUT(V)
Accuracy
25°C Only
Accuracy
Over ∆Temp erature
Output Voltage versus Sampled Current

Total Output Error at 0 A and at Full-Scale Current
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FUNCTIONAL DESCRIPTION
Power-On Reset (POR)

The descriptions in this section assume: temperature = 25°C, no device Sensitivity and QVO after time tTC [5], [5’]. VCC drops
output load (RL , CL ) , and IP = 0 A. below VCC(min) = 3.0 V. If VCC drops below VPORH [6’] but
remains higher than VPORL [7’] the output will continue to be
• Power-Up. At power-up, as VCC ramps up, the output is in a VCC /2.
high-impedance state. When VCC crosses VPORH (location [1]
in Figure 1 and [1’] in Figure 2), the POR Release counter • Power-Down. As VCC ramps down below VPORL [6],[8’], the
starts counting for tPORRC [2], [2’]. At this point, the EEPROM output will enter a high-impedance state.
content will be loaded in volatile memory after tEELOAD
[3],[3’] and the output will go to VCC / 2 after tPORD [4], [4’].
The temperature compensation engine will then adjust the
EEPROM Error Checking and Correction

Hamming code methodology is implemented for EEPROM
checking and correction. The device has ECC enabled after
power-up. If an uncorrectable error has occurred, the VOUT pin
will go to high impedance and the device will not respond to
applied magnetic field.
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VCC 4
1 2 3 5 6
3.3
VPORH
VPORL
GND
Time
VOUT tTC
tPORD
1.65
tPORRC
tPORR
Slope =
tEELOAD VCC / 2
GND
High Impedance High Impedance Time
Figure 1: POR Operation: Slow Rise Time Case
VCC 1’ 2’ 4’
3’ 5’ 6’ 7’ 8’
3.3
VPORH
VPORL
GND
Time
tTC
VOUT
tPORD
Slope = Slope =
VCC / 2 VCC / 2
1.65
tEELOAD
High Impedance
GND
tPORR High Impedance Time
tPORRC
Figure 2: POR Operation: Fast Rise Time Case
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Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for switch sourced signal then can pass through a low-pass filter, while the
point accuracy is the small signal voltage developed across the modulated DC offset is suppressed.
Hall element. This voltage is disproportionally small relative to
In addition to the removal of the thermal and stress-related offset,
the offset that can be produced at the output of the Hall sensor IC.
this novel technique also reduces the amount of thermal noise
This makes it difficult to process the signal while maintaining an
in the Hall sensor IC while completely removing the modulated
accurate, reliable output over the specified operating temperature
residue resulting from the chopper operation. The chopper sta-
and voltage ranges.
bilization technique uses a high-frequency sampling clock. For
Chopper stabilization is a unique approach used to minimize demodulation process, a sample-and-hold technique is used. This
Hall offset on the chip. Allegro employs a technique to remove high-frequency operation allows a greater sampling rate, which
key sources of the output drift induced by thermal and mechani- results in higher accuracy and faster signal-processing capability.
cal stresses. This offset reduction technique is based on a signal This approach desensitizes the chip to the effects of thermal and
modulation-demodulation process. The undesired offset signal is mechanical stresses, and produces devices that have extremely
separated from the magnetic field-induced signal in the frequency stable quiescent Hall output voltages and precise recoverability
domain, through modulation. The subsequent demodulation acts after temperature cycling. This technique is made possible by
as a modulation process for the offset, causing the magnetic field- using a BiCMOS process, which allows the use of low-offset,
induced signal to recover its original spectrum at baseband, while low-noise amplifiers in combination with high-density logic inte-
the DC offset becomes a high-frequency signal. The magnetic- gration and sample-and-hold circuits.
Regulator
Clock/Logic
Hall Element
Amp
Anti-Aliasing Tuned
LP Filter Filter
Concept of Chopper Stabilization Technique
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APPLICATION-SPECIFIC INFORMATION
Field from Nearby Current Path ┌ ┐

To best use the CMR capabilities of these devices, the circuit 2×I │ 1 1 │
Error = × –
board containing the ICs should be designed to make the external Cf │ Hspace Hspace │
magnetic fields on both Hall plates equal. This helps to minimize │ d – 2 × cosθ d + 2 × cosθ │
error due to external fields generated by the current-carrying └ ┘
PCB traces themselves. There are three main parameters for each where Hspace is the distance between the two Hall plates and Cf is
current-carrying trace that determine the error that it will induce the coupling factor of the IC. This coupling factor varies between
on an IC: distance from the IC, width of the current-carrying the different ICs. The ACS781 has a coupling factor of 5 to 5.5
conductor, and the angle between it and the IC. Figure 3 shows G/A, whereas other Allegro ICs can range from 10 to 15 G/A.
an example of a current-carrying conductor routed near an IC.
The distance between the device and the conductor, d, is the Other Layout Practices to Consider
distance from the device center to the center of the conductor. When laying out a board that contains an Allegro current sensor
The width of the current path is w. The angle between the device IC with CMR, the direction and proximity of all current-carrying
and the current path, θ, is defined as the angle between a straight paths are important, but they are not the only factors to consider
line connecting the two Hall plates and a line perpendicular to the when optimizing IC performance. Other sources of stray fields
current path. that can contribute to system error include traces that connect to
the IC’s integrated current conductor, as well as the position of
nearby permanent magnets.
The way that the circuit board connects to a current sensor IC
must be planned with care. Common mistakes that can impact
performance are:
• The angle of approach of the current path to the IP pins
H2
I • Extending the current trace too far beneath the IC
θ d
H1 THE ANGLE OF APPROACH
One common mistake when using an Allegro current sensor IC is
to bring the current in from an undesirable angle. Figure 4 shows
an example of the approach of the current traces to the IC (in this
case, the ACS781). In this figure, traces are shown for IP+ and
w IP–. The light green region is the desired area of approach for the
current trace going to IP+. This region is from 0° to 85°. This rule
Figure 3: ACS781 with nearby current path, viewed applies likewise for the IP– trace.
from the bottom of the sensor
The limitation of this region is to prevent the current-carrying
When it is not possible to keep θ close to 90°, the next best
trace from contributing any stray field that can cause error on
option is to keep the distance from the current path to the current
the IC output. When the current traces connected to IP are outside
sensor IC, d, as large as possible. Assuming that the current path
this region, they must be treated as discussed above (Field from a
is at the worst-case angle in relation to the IC, θ = 0° or 180°, the
Nearby Current Path).
equation:
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Figure 4: ACS781 Current Trace Approach – the desired

range of the angle θ is from 0° to 85°
ENCROACHMENT UNDER THE IC

In the LR package, the encroachment of the current-carrying
trace under the device changes the path of the current flowing
through the IP bus. This can cause a change in the coupling factor
of the IP bus to the IC and can significantly reduce device perfor-
mance. Using ANSYS Maxwell Electromagnetic Suites, the cur-
rent density and magnetic field generated from the current flow
were simulated. In Figure 5, there are results from two different
simulations. The first is the case where the current trace leading
up to the IP bus terminates at the desired point. The second case
is where the current trace encroaches far up the IP bus. The red
arrows in both simulations represent the areas of high current Figure 5: Simulations of ACS781 Leadframe with Differ-
density. In the simulation with no excess overlap, the red areas, ent Overlap of the Current Trace and the IP Bus
and hence the current density, are very different from the simula-
tion with the excess overlap. It was also observed that the field
on H1 was larger when there was no excess overlap. This can be
observed by the darker shade of blue.
22
955 Perimeter Road
PACKAGE OUTLINE DRAWING
6.40 ±0.10
2.99 ±0.10 NNN

1.79 ±0.10 ×2 0.38 +0.05
–0.03
7 YYWW
0.81 ±0.10 ×2 Parting Line (Plating Included) LLLLLLL
1
5º ±2º ×2
0.80 ±0.10 C Standard Branding Reference View
12º ±2º ×2 = Supplier emblem
D1 1.37 ±0.20 N = Last three numbers of device part number
0.38 ±0.10 ×2 D D2 Y = Last two digits of year of manufacture
6.40 ±0.10
W = Week of manufacture
7 3.06 ±0.20
4.80 ±0.10 L = Lot identifier
5º ±2º ×2
A 12º ±2º ×2
1.56 ±0.20
3.00
1.80 MIN
1 2 B
6 5
0.80
1.41 ×2
0.38 ±0.10 ×3 0.90
1.60 ±0.10 ×2
0.60 2.40
5.60
7 4
Branded Face 12º ±2º ×2 4.80
A
0.9
1.50 ±0.10 0.02 +0.03

-0.02 0.70
SEATING
PLANE 0.90
1 2 3
5º ±2º ×2 1.60
0.50
E PCB Layout Reference View

R0.97 ±0.05 1 2
R0.25 ±0.05 0.70 ±0.10
7 For Reference Only, not for tooling use (DWG-0000428)

Dimensions in millimeters
0.28 ×2 Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.37±0.10 ×2 A Terminal #1 mark area

0.90 ±0.10 ×2
B Dambar removal protrusion (10×)
R0.50 ×2 C Branding scale and appearance at supplier discretion
0.81 0.50 ×2 D Hall elements (D1 and D2); not to scale

×2
0.88 E Reference land pattern layout;
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB
layout tolerances
Package LR, 7-Pin PSOF Package
23
955 Perimeter Road
REVISION HISTORY
Number Date Description
– August 8, 2016 Initial release
1 August 14, 2017 Added Typical Frequency Response charts (p. 14)
Corrected Primary Conductor Resistance value (p. 5), Nonlinearity test conditions (p. 6-11), and Package
2 October 23, 2017
Outline Drawing (p. 22)
3 January 30, 2018 Added EEPROM Error Checking and Correction section (page 18)
4 February 7, 2019 Minor editorial updates
5 February 12, 2020 Minor editorial updates
6 May 17, 2021 Removed footnote 2 and updated footnote 6 (pages 6-11)
Copyright 2021, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

24
955 Perimeter Road

ACS781 Datasheet

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ACS781 Datasheet

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ACS781xLR

High-Precision Linear Hall-Effect-Based

FEATURES AND BENEFITS DESCRIPTION

Continued on the next page…

ACS781xLR-DS, Rev. 6 May 17, 2021

[1] Contact Allegro for additional packing options.

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS: May require derating at maximum conditions

TYPICAL OVERCURRENT CAPABILITIES [2][3]

Temperature EEPROM and Programming

Functional Block Diagram

Nonlinearity ELIN Measured using ±32 A and ±16 A –1 – 1 %

Nonlinearity ELIN Measured using 32 A and 16 A –1 – 1 %

Nonlinearity ELIN Measured using ±36 A and ±18 A –1 – 1 %

Nonlinearity ELIN Measured using 36 A and 18 A –1 – 1 %

Nonlinearity ELIN Measured using ±38 A and ±19 A –1 – 1 %

Nonlinearity ELIN Measured using 38 A and 19 A –1 – 1 %

CHARACTERISTIC PERFORMANCE DATA

Rise Time (tr)

Propagation Delay (tPD)

Power-On Time (tPO)

Definitions of Accuracy Characteristics

(mV/G). The linear IC amplifier gain is programmed at the factory

RATIOMETRY VIOUT_IDEAL(IP) = VIOUT(Q) + (SensIDEAL × IP )

DEFINITIONS OF DYNAMIC RESPONSE CHARACTERISTICS

POWER-ON TIME (tPO)

RISE TIME (tr)

Response Time, tRESPONSE

POWER-ON RESET RELEASE TIME (tPORR) Accuracy

When VCC rises to VPORH , the Power-On Reset Counter starts.

has reached tPORR. VIOUT

–IP (A) +IP (A)

Output Voltage versus Sampled Current

Power-On Reset (POR)

EEPROM Error Checking and Correction

Chopper Stabilization Technique

Concept of Chopper Stabilization Technique

Field from Nearby Current Path ┌ ┐

Figure 4: ACS781 Current Trace Approach – the desired

ENCROACHMENT UNDER THE IC

PACKAGE OUTLINE DRAWING

2.99 ±0.10 NNN

1.50 ±0.10 0.02 +0.03

E PCB Layout Reference View

R0.25 ±0.05 0.70 ±0.10

7 For Reference Only, not for tooling use (DWG-0000428)

1.37±0.10 ×2 A Terminal #1 mark area

R0.50 ×2 C Branding scale and appearance at supplier discretion

0.81 0.50 ×2 D Hall elements (D1 and D2); not to scale

Package LR, 7-Pin PSOF Package

Copyright 2021, Allegro MicroSystems.

For the latest version of this document, visit our website:

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