ST7565R

ST
Sitronix 65 x 132 Dot Matrix LCD Controller/Driver

ST7565R
Features
Directly display RAM data through Display Data RAM. Independent input (VDD2) for boost reference voltage.
RAM capacity : 65 x 132 = 8580 bits High-accuracy Regulator circuit:
Display duty selectable by select pin Build-in Electronic volume function for the contrast
1/65 duty : 65 common x 132 segment control. Thermal gradient = –0.05%/°C.
1/49 duty : 49 common x 132 segment Embedded voltage Follower circuit for LCD driving.
1/33 duty : 33 common x 132 segment Embedded R-C oscillator circuit.
1/55 duty : 55 common x 132 segment The external clock is also supported.
1/53 duty : 53 common x 132 segment Extremely low power consumption: 60uA, bare dice
High-speed 8-bit MPU interface: (using the internal power). Settings:
ST7565R can be connected directly to both the 80x86 VDD – VSS = VDD2 – VSS =3.0 V, Booster Ratio=4,
series MPUs and the 6800 series MPUs. V0 – VSS = 11.0 V. Display OFF and the normal mode is
Serial interface (SPI-4) is also supported. selected.
Abundant command functions Logic power supply : VDD – VSS = 2.4V to 3.3 V
Display data Read/Write, display ON/OFF, Normal/ Analog Power (Boost reference voltage):
Reverse display mode, page address set, display start VDD2 – VSS = 2.4V to 3.3V
line set, column address set, status read, display all Booster maximum voltage limited
points ON/OFF, LCD bias set, electronic volume, VOUT= 13.5V
read/modify/write, segment driver direction selects, Liquid crystal drive power supply:
power saver, common output status select, V0 voltage V0 – VSS = 3.0V to 12.0 V
regulation internal resistor ratio set. Wide range of operating temperatures: –30 to 85°C
Embedded analog power supply circuits for Liquid Package type: COG only.
Crystal driving: Booster, Regulator and Follower. The chip is not designed to resist the light or to resist
Embedded Booster circuit: the radiation.
2X,3X,4X,5X and 6X boost ratios are supported. Support LCD Module Size up to 2"
General Description
The ST7565R is a single-chip dot matrix LCD driver that can 132 segment output circuits, so that a single chip can drive a
be connected directly to a microprocessor bus. 8-bit parallel 65x132 dot display (capable of displaying 8 columns x4 rows
or 4-line SPI display data sent from the microprocessor is of a 16x16 dot kanji font).
stored in the internal display data RAM and the chip The chips are able to minimize power consumption because
generates a LCD drive signal independent of the no external operating clock is necessary for the display data
microprocessor. Because the chips in the ST7565R contain RAM read/write operation. Furthermore, because each chip
65x132 bits of display data RAM and there is a 1-to-1 is equipped internally with a low-power LCD driver power
correspondence between the LCD panel pixels and the supply, resistors for LCD driver power voltage adjustment
internal RAM bits, these chips enable displays with a high and a display clock CR oscillator circuit, the ST7565R can be
degree of freedom. used to create the lowest power display system with the
The ST7565R chips contain 65 common output circuits and fewest components for high-performance portable devices.
PART NO. VRS temperature gradient VRS range

ST7565R -0.05%/°C 2.1V ±0.03V
Ver 1.7c 1/72 2009/09/14

ST7565R
ST7565R Pad Arrangement (COG)
Chip Size: 5900µm x 1000µm
Bump Pitch: 34µm(Min.)
Bump Size: PAD No. 001～067 42µm x 54µm
PAD No. 068～073 56µm x 54µm
PAD No. 074～084 42µm x 54µm
PAD No. 085～282 17µm x 118µm
Bump Height: 15µm

Chip Thickness: 480µm
Recommend panel size is small than 1.8” (A.A.).
Ver 1.7c 2/72 2009/09/14

ST7565R
Pad Center Coordinates (1/65 Duty) Units: µm
PAD No. PIN Name X Y PAD No. PIN Name X Y

1 TEST[6] 2575 392 49 VSS -333 392
2 FR 2515 392 50 VRS -408 392
3 CL 2455 392 51 VRS -468 392
4 DOF 2395 392 52 VDD2 -542 392
5 VSS 2335 392 53 VDD -602 392
6 CS1B 2275 392 54 V4 -676 392
7 CS2 2215 392 55 V4 -736 392
8 VDD 2155 392 56 V3 -796 392
9 RST 2095 392 57 V3 -856 392
10 A0 2035 392 58 V2 -916 392
11 VSS 1975 392 59 V2 -976 392
12 /WR(R/W) 1915 392 60 V1 -1036 392
13 /RD(E) 1855 392 61 V1 -1096 392
14 VDD 1795 392 62 V0 -1156 392
15 D0 1735 392 63 V0 -1216 392
16 D1 1675 392 64 VR -1276 392
17 D2 1615 392 65 VR -1336 392
18 D3 1555 392 66 VDD -1410 392
19 D4 1495 392 67 VDD2 -1470 392
20 D5 1435 392 68 TEST[0] -1537 392
21 D6 1375 392 69 TEST[1] -1611 392
22 D7 1315 392 70 TEST[2] -1685 392
23 VDD 1255 392 71 TEST[3] -1759 392
24 VDD2 1195 392 72 TEST[4] -1833 392
25 VDD2 1135 392 73 TEST[5] -1907 392
26 VSS 1075 392 74 VDD -1974 392
27 VSS 1015 392 75 TEST[7] -2034 392
28 VSS 955 392 76 CLS -2094 392
29 VSS 895 392 77 C86 -2154 392
30 VOUT 821 392 78 PSB -2214 392
31 VOUT 761 392 79 HPMB -2274 392
32 CAP5P 701 392 80 IRS -2334 392
33 CAP5P 641 392 81 SEL1 -2394 392
34 CAP1N 581 392 82 SEL2 -2454 392
35 CAP1N 521 392 83 SEL3 -2514 392
36 CAP3P 461 392 84 VSS -2574 392
37 CAP3P 401 392 85 COM[31] -2810 373
38 CAP1N 341 392 86 COM[30] -2810 339
39 CAP1N 281 392 87 COM[29] -2810 305
40 CAP1P 221 392 88 COM[28] -2810 271
41 CAP1P 161 392 89 COM[27] -2810 237
42 CAP2P 101 392 90 COM[26] -2810 203
43 CAP2P 41 392 91 COM[25] -2810 169
44 CAP2N -19 392 92 COM[24] -2810 135
45 CAP2N -79 392 93 COM[23] -2810 101
46 CAP4P -139 392 94 COM[22] -2810 67
47 CAP4P -199 392 95 COM[21] -2810 33
48 VSS -273 392 96 COM[20] -2810 -1
Ver 1.7c 3/72 2009/09/14

ST7565R
97 COM[19] -2810 -35 149 SEG[31] -1173 -360
98 COM[18] -2810 -69 150 SEG[32] -1139 -360
99 COM[17] -2810 -103 151 SEG[33] -1105 -360
100 COM[16] -2810 -137 152 SEG[34] -1071 -360
101 COM[15] -2810 -171 153 SEG[35] -1037 -360
102 COM[14] -2810 -205 154 SEG[36] -1003 -360
103 COM[13] -2810 -239 155 SEG[37] -969 -360
104 COM[12] -2810 -273 156 SEG[38] -935 -360
105 COM[11] -2810 -307 157 SEG[39] -901 -360
106 COM[10] -2810 -341 158 SEG[40] -867 -360
107 COM[9] -2810 -375 159 SEG[41] -833 -360
108 COM[8] -2573 -360 160 SEG[42] -799 -360
109 COM[7] -2539 -360 161 SEG[43] -765 -360
110 COM[6] -2505 -360 162 SEG[44] -731 -360
111 COM[5] -2471 -360 163 SEG[45] -697 -360
112 COM[4] -2437 -360 164 SEG[46] -663 -360
113 COM[3] -2403 -360 165 SEG[47] -629 -360
114 COM[2] -2369 -360 166 SEG[48] -595 -360
115 COM[1] -2335 -360 167 SEG[49] -561 -360
116 COM[0] -2301 -360 168 SEG[50] -527 -360
117 COMS2 -2267 -360 169 SEG[51] -493 -360
118 SEG[0] -2227 -360 170 SEG[52] -459 -360
119 SEG[1] -2193 -360 171 SEG[53] -425 -360
120 SEG[2] -2159 -360 172 SEG[54] -391 -360
121 SEG[3] -2125 -360 173 SEG[55] -357 -360
122 SEG[4] -2091 -360 174 SEG[56] -323 -360
123 SEG[5] -2057 -360 175 SEG[57] -289 -360
124 SEG[6] -2023 -360 176 SEG[58] -255 -360
125 SEG[7] -1989 -360 177 SEG[59] -221 -360
126 SEG[8] -1955 -360 178 SEG[60] -187 -360
127 SEG[9] -1921 -360 179 SEG[61] -153 -360
128 SEG[10] -1887 -360 180 SEG[62] -119 -360
129 SEG[11] -1853 -360 181 SEG[63] -85 -360
130 SEG[12] -1819 -360 182 SEG[64] -51 -360
131 SEG[13] -1785 -360 183 SEG[65] -17 -360
132 SEG[14] -1751 -360 184 SEG[66] 17 -360
133 SEG[15] -1717 -360 185 SEG[67] 51 -360
134 SEG[16] -1683 -360 186 SEG[68] 85 -360
135 SEG[17] -1649 -360 187 SEG[69] 119 -360
136 SEG[18] -1615 -360 188 SEG[70] 153 -360
137 SEG[19] -1581 -360 189 SEG[71] 187 -360
138 SEG[20] -1547 -360 190 SEG[72] 221 -360
139 SEG[21] -1513 -360 191 SEG[73] 255 -360
140 SEG[22] -1479 -360 192 SEG[74] 289 -360
141 SEG[23] -1445 -360 193 SEG[75] 323 -360
142 SEG[24] -1411 -360 194 SEG[76] 357 -360
143 SEG[25] -1377 -360 195 SEG[77] 391 -360
144 SEG[26] -1343 -360 196 SEG[78] 425 -360
145 SEG[27] -1309 -360 197 SEG[79] 459 -360
146 SEG[28] -1275 -360 198 SEG[80] 493 -360
147 SEG[29] -1241 -360 199 SEG[81] 527 -360
148 SEG[30] -1207 -360 200 SEG[82] 561 -360
Ver 1.7c 4/72 2009/09/14

ST7565R
201 SEG[83] 595 -360 246 SEG[128] 2125 -360
202 SEG[84] 629 -360 247 SEG[129] 2159 -360
203 SEG[85] 663 -360 248 SEG[130] 2193 -360
204 SEG[86] 697 -360 249 SEG[131] 2227 -360
205 SEG[87] 731 -360 250 COM[32] 2267 -360
206 SEG[88] 765 -360 251 COM[33] 2301 -360
207 SEG[89] 799 -360 252 COM[34] 2335 -360
208 SEG[90] 833 -360 253 COM[35] 2369 -360
209 SEG[91] 867 -360 254 COM[36] 2403 -360
210 SEG[92] 901 -360 255 COM[37] 2437 -360
211 SEG[93] 935 -360 256 COM[38] 2471 -360
212 SEG[94] 969 -360 257 COM[39] 2505 -360
213 SEG[95] 1003 -360 258 COM[40] 2539 -360
214 SEG[96] 1037 -360 259 COM[41] 2573 -360
215 SEG[97] 1071 -360 260 COM[42] 2810 -375
216 SEG[98] 1105 -360 261 COM[43] 2810 -341
217 SEG[99] 1139 -360 262 COM[44] 2810 -307
218 SEG[100] 1173 -360 263 COM[45] 2810 -273
219 SEG[101] 1207 -360 264 COM[46] 2810 -239
220 SEG[102] 1241 -360 265 COM[47] 2810 -205
221 SEG[103] 1275 -360 266 COM[48] 2810 -171
222 SEG[104] 1309 -360 267 COM[49] 2810 -137
223 SEG[105] 1343 -360 268 COM[50] 2810 -103
224 SEG[106] 1377 -360 269 COM[51] 2810 -69
225 SEG[107] 1411 -360 270 COM[52] 2810 -35
226 SEG[108] 1445 -360 271 COM[53] 2810 -1
227 SEG[109] 1479 -360 272 COM[54] 2810 33
228 SEG[110] 1513 -360 273 COM[55] 2810 67
229 SEG[111] 1547 -360 274 COM[56] 2810 101
230 SEG[112] 1581 -360 275 COM[57] 2810 135
231 SEG[113] 1615 -360 276 COM[58] 2810 169
232 SEG[114] 1649 -360 277 COM[59] 2810 203
233 SEG[115] 1683 -360 278 COM[60] 2810 237
234 SEG[116] 1717 -360 279 COM[61] 2810 271
235 SEG[117] 1751 -360 280 COM[62] 2810 305
236 SEG[118] 1785 -360 281 COM[63] 2810 339
237 SEG[119] 1819 -360 282 COMS1 2810 373
238 SEG[120] 1853 -360
239 SEG[121] 1887 -360
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
Ver 1.7c 5/72 2009/09/14

ST7565R

1 TEST[6] 2575 392 50 VRS -408 392
2 FR 2515 392 51 VRS -468 392
3 CL 2455 392 52 VDD2 -542 392
4 DOF 2395 392 53 VDD -602 392
5 VSS 2335 392 54 V4 -676 392
6 CS1B 2275 392 55 V4 -736 392
7 CS2 2215 392 56 V3 -796 392
8 VDD 2155 392 57 V3 -856 392
9 RST 2095 392 58 V2 -916 392
10 A0 2035 392 59 V2 -976 392
11 VSS 1975 392 60 V1 -1036 392
12 /WR(R/W) 1915 392 61 V1 -1096 392
13 /RD(E) 1855 392 62 V0 -1156 392
14 VDD 1795 392 63 V0 -1216 392
15 D0 1735 392 64 VR -1276 392
16 D1 1675 392 65 VR -1336 392
17 D2 1615 392 66 VDD -1410 392
18 D3 1555 392 67 VDD2 -1470 392
19 D4 1495 392 68 TEST[0] -1537 392
20 D5 1435 392 69 TEST[1] -1611 392
21 D6 1375 392 70 TEST[2] -1685 392
22 D7 1315 392 71 TEST[3] -1759 392
23 VDD 1255 392 72 TEST[4] -1833 392
24 VDD2 1195 392 73 TEST[5] -1907 392
25 VDD2 1135 392 74 VDD -1974 392
26 VSS 1075 392 75 TEST[7] -2034 392
27 VSS 1015 392 76 CLS -2094 392
28 VSS 955 392 77 C86 -2154 392
29 VSS 895 392 78 PSB -2214 392
30 VOUT 821 392 79 HPMB -2274 392
31 VOUT 761 392 80 IRS -2334 392
32 CAP5P 701 392 81 SEL1 -2394 392
33 CAP5P 641 392 82 SEL2 -2454 392
34 CAP1N 581 392 83 SEL3 -2514 392
35 CAP1N 521 392 84 VSS -2574 392
36 CAP3P 461 392 85 Reserve -2810 373
37 CAP3P 401 392 86 Reserve -2810 339
38 CAP1N 341 392 87 Reserve -2810 305
39 CAP1N 281 392 88 Reserve -2810 271
40 CAP1P 221 392 89 Reserve -2810 237
41 CAP1P 161 392 90 Reserve -2810 203
42 CAP2P 101 392 91 Reserve -2810 169
43 CAP2P 41 392 92 Reserve -2810 135
44 CAP2N -19 392 93 COM[23] -2810 101
45 CAP2N -79 392 94 COM[22] -2810 67
46 CAP4P -139 392 95 COM[21] -2810 33
47 CAP4P -199 392 96 COM[20] -2810 -1
48 VSS -273 392 97 COM[19] -2810 -35
49 VSS -333 392 98 COM[18] -2810 -69
Ver 1.7c 6/72 2009/09/14

ST7565R
99 COM[17] -2810 -103 151 SEG[33] -1105 -360
100 COM[16] -2810 -137 152 SEG[34] -1071 -360
101 COM[15] -2810 -171 153 SEG[35] -1037 -360
102 COM[14] -2810 -205 154 SEG[36] -1003 -360
103 COM[13] -2810 -239 155 SEG[37] -969 -360
104 COM[12] -2810 -273 156 SEG[38] -935 -360
105 COM[11] -2810 -307 157 SEG[39] -901 -360
106 COM[10] -2810 -341 158 SEG[40] -867 -360
107 COM[9] -2810 -375 159 SEG[41] -833 -360
108 COM[8] -2573 -360 160 SEG[42] -799 -360
109 COM[7] -2539 -360 161 SEG[43] -765 -360
110 COM[6] -2505 -360 162 SEG[44] -731 -360
111 COM[5] -2471 -360 163 SEG[45] -697 -360
112 COM[4] -2437 -360 164 SEG[46] -663 -360
113 COM[3] -2403 -360 165 SEG[47] -629 -360
114 COM[2] -2369 -360 166 SEG[48] -595 -360
115 COM[1] -2335 -360 167 SEG[49] -561 -360
116 COM[0] -2301 -360 168 SEG[50] -527 -360
117 COMS2 -2267 -360 169 SEG[51] -493 -360
118 SEG[0] -2227 -360 170 SEG[52] -459 -360
119 SEG[1] -2193 -360 171 SEG[53] -425 -360
120 SEG[2] -2159 -360 172 SEG[54] -391 -360
121 SEG[3] -2125 -360 173 SEG[55] -357 -360
122 SEG[4] -2091 -360 174 SEG[56] -323 -360
123 SEG[5] -2057 -360 175 SEG[57] -289 -360
124 SEG[6] -2023 -360 176 SEG[58] -255 -360
125 SEG[7] -1989 -360 177 SEG[59] -221 -360
126 SEG[8] -1955 -360 178 SEG[60] -187 -360
127 SEG[9] -1921 -360 179 SEG[61] -153 -360
128 SEG[10] -1887 -360 180 SEG[62] -119 -360
129 SEG[11] -1853 -360 181 SEG[63] -85 -360
130 SEG[12] -1819 -360 182 SEG[64] -51 -360
131 SEG[13] -1785 -360 183 SEG[65] -17 -360
132 SEG[14] -1751 -360 184 SEG[66] 17 -360
133 SEG[15] -1717 -360 185 SEG[67] 51 -360
134 SEG[16] -1683 -360 186 SEG[68] 85 -360
135 SEG[17] -1649 -360 187 SEG[69] 119 -360
136 SEG[18] -1615 -360 188 SEG[70] 153 -360
137 SEG[19] -1581 -360 189 SEG[71] 187 -360
138 SEG[20] -1547 -360 190 SEG[72] 221 -360
139 SEG[21] -1513 -360 191 SEG[73] 255 -360
140 SEG[22] -1479 -360 192 SEG[74] 289 -360
141 SEG[23] -1445 -360 193 SEG[75] 323 -360
142 SEG[24] -1411 -360 194 SEG[76] 357 -360
143 SEG[25] -1377 -360 195 SEG[77] 391 -360
144 SEG[26] -1343 -360 196 SEG[78] 425 -360
145 SEG[27] -1309 -360 197 SEG[79] 459 -360
146 SEG[28] -1275 -360 198 SEG[80] 493 -360
147 SEG[29] -1241 -360 199 SEG[81] 527 -360
148 SEG[30] -1207 -360 200 SEG[82] 561 -360
149 SEG[31] -1173 -360 201 SEG[83] 595 -360
150 SEG[32] -1139 -360 202 SEG[84] 629 -360
Ver 1.7c 7/72 2009/09/14

ST7565R
203 SEG[85] 663 -360 246 SEG[128] 2125 -360
204 SEG[86] 697 -360 247 SEG[129] 2159 -360
205 SEG[87] 731 -360 248 SEG[130] 2193 -360
206 SEG[88] 765 -360 249 SEG[131] 2227 -360
207 SEG[89] 799 -360 250 Reserve 2267 -360
208 SEG[90] 833 -360 251 Reserve 2301 -360
209 SEG[91] 867 -360 252 Reserve 2335 -360
210 SEG[92] 901 -360 253 Reserve 2369 -360
211 SEG[93] 935 -360 254 Reserve 2403 -360
212 SEG[94] 969 -360 255 Reserve 2437 -360
213 SEG[95] 1003 -360 256 Reserve 2471 -360
214 SEG[96] 1037 -360 257 Reserve 2505 -360
215 SEG[97] 1071 -360 258 COM[24] 2539 -360
216 SEG[98] 1105 -360 259 COM[25] 2573 -360
217 SEG[99] 1139 -360 260 COM[26] 2810 -375
218 SEG[100] 1173 -360 261 COM[27] 2810 -341
219 SEG[101] 1207 -360 262 COM[28] 2810 -307
220 SEG[102] 1241 -360 263 COM[29] 2810 -273
221 SEG[103] 1275 -360 264 COM[30] 2810 -239
222 SEG[104] 1309 -360 265 COM[31] 2810 -205
223 SEG[105] 1343 -360 266 COM[32] 2810 -171
224 SEG[106] 1377 -360 267 COM[33] 2810 -137
225 SEG[107] 1411 -360 268 COM[34] 2810 -103
226 SEG[108] 1445 -360 269 COM[35] 2810 -69
227 SEG[109] 1479 -360 270 COM[36] 2810 -35
228 SEG[110] 1513 -360 271 COM[37] 2810 -1
229 SEG[111] 1547 -360 272 COM[38] 2810 33
230 SEG[112] 1581 -360 273 COM[39] 2810 67
231 SEG[113] 1615 -360 274 COM[40] 2810 101
232 SEG[114] 1649 -360 275 COM[41] 2810 135
233 SEG[115] 1683 -360 276 COM[42] 2810 169
234 SEG[116] 1717 -360 277 COM[43] 2810 203
235 SEG[117] 1751 -360 278 COM[44] 2810 237
236 SEG[118] 1785 -360 279 COM[45] 2810 271
237 SEG[119] 1819 -360 280 COM[46] 2810 305
238 SEG[120] 1853 -360 281 COM[47] 2810 339
239 SEG[121] 1887 -360 282 COMS1 2810 373
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
Ver 1.7c 8/72 2009/09/14

ST7565R

1 TEST[6] 2575 392 50 VRS -408 392
2 FR 2515 392 51 VRS -468 392
3 CL 2455 392 52 VDD2 -542 392
4 DOF 2395 392 53 VDD -602 392
5 VSS 2335 392 54 V4 -676 392
6 CS1B 2275 392 55 V4 -736 392
7 CS2 2215 392 56 V3 -796 392
8 VDD 2155 392 57 V3 -856 392
9 RST 2095 392 58 V2 -916 392
10 A0 2035 392 59 V2 -976 392
11 VSS 1975 392 60 V1 -1036 392
12 /WR(R/W) 1915 392 61 V1 -1096 392
13 /RD(E) 1855 392 62 V0 -1156 392
14 VDD 1795 392 63 V0 -1216 392
15 D0 1735 392 64 VR -1276 392
16 D1 1675 392 65 VR -1336 392
17 D2 1615 392 66 VDD -1410 392
18 D3 1555 392 67 VDD2 -1470 392
19 D4 1495 392 68 TEST[0] -1537 392
20 D5 1435 392 69 TEST[1] -1611 392
21 D6 1375 392 70 TEST[2] -1685 392
22 D7 1315 392 71 TEST[3] -1759 392
23 VDD 1255 392 72 TEST[4] -1833 392
24 VDD2 1195 392 73 TEST[5] -1907 392
25 VDD2 1135 392 74 VDD -1974 392
26 VSS 1075 392 75 TEST[7] -2034 392
27 VSS 1015 392 76 CLS -2094 392
28 VSS 955 392 77 C86 -2154 392
29 VSS 895 392 78 PSB -2214 392
30 VOUT 821 392 79 HPMB -2274 392
31 VOUT 761 392 80 IRS -2334 392
32 CAP5P 701 392 81 SEL1 -2394 392
33 CAP5P 641 392 82 SEL2 -2454 392
34 CAP1N 581 392 83 SEL3 -2514 392
35 CAP1N 521 392 84 VSS -2574 392
36 CAP3P 461 392 85 Reserve -2810 373
37 CAP3P 401 392 86 Reserve -2810 339
38 CAP1N 341 392 87 Reserve -2810 305
39 CAP1N 281 392 88 Reserve -2810 271
40 CAP1P 221 392 89 Reserve -2810 237
41 CAP1P 161 392 90 Reserve -2810 203
42 CAP2P 101 392 91 Reserve -2810 169
43 CAP2P 41 392 92 Reserve -2810 135
44 CAP2N -19 392 93 Reserve -2810 101
45 CAP2N -79 392 94 Reserve -2810 67
46 CAP4P -139 392 95 RESERVED -2810 33
47 CAP4P -199 392 96 RESERVED -2810 -1
48 VSS -273 392 97 RESERVED -2810 -35
49 VSS -333 392 98 RESERVED -2810 -69
Ver 1.7c 9/72 2009/09/14

ST7565R
99 RESERVED -2810 -103 151 SEG[33] -1105 -360
100 RESERVED -2810 -137 152 SEG[34] -1071 -360
101 COM[15] -2810 -171 153 SEG[35] -1037 -360
102 COM[14] -2810 -205 154 SEG[36] -1003 -360
103 COM[13] -2810 -239 155 SEG[37] -969 -360
104 COM[12] -2810 -273 156 SEG[38] -935 -360
105 COM[11] -2810 -307 157 SEG[39] -901 -360
106 COM[10] -2810 -341 158 SEG[40] -867 -360
107 COM[9] -2810 -375 159 SEG[41] -833 -360
108 COM[8] -2573 -360 160 SEG[42] -799 -360
109 COM[7] -2539 -360 161 SEG[43] -765 -360
110 COM[6] -2505 -360 162 SEG[44] -731 -360
111 COM[5] -2471 -360 163 SEG[45] -697 -360
112 COM[4] -2437 -360 164 SEG[46] -663 -360
113 COM[3] -2403 -360 165 SEG[47] -629 -360
114 COM[2] -2369 -360 166 SEG[48] -595 -360
115 COM[1] -2335 -360 167 SEG[49] -561 -360
116 COM[0] -2301 -360 168 SEG[50] -527 -360
117 COMS2 -2267 -360 169 SEG[51] -493 -360
118 SEG[0] -2227 -360 170 SEG[52] -459 -360
119 SEG[1] -2193 -360 171 SEG[53] -425 -360
120 SEG[2] -2159 -360 172 SEG[54] -391 -360
121 SEG[3] -2125 -360 173 SEG[55] -357 -360
122 SEG[4] -2091 -360 174 SEG[56] -323 -360
123 SEG[5] -2057 -360 175 SEG[57] -289 -360
124 SEG[6] -2023 -360 176 SEG[58] -255 -360
125 SEG[7] -1989 -360 177 SEG[59] -221 -360
126 SEG[8] -1955 -360 178 SEG[60] -187 -360
127 SEG[9] -1921 -360 179 SEG[61] -153 -360
128 SEG[10] -1887 -360 180 SEG[62] -119 -360
129 SEG[11] -1853 -360 181 SEG[63] -85 -360
130 SEG[12] -1819 -360 182 SEG[64] -51 -360
131 SEG[13] -1785 -360 183 SEG[65] -17 -360
132 SEG[14] -1751 -360 184 SEG[66] 17 -360
133 SEG[15] -1717 -360 185 SEG[67] 51 -360
134 SEG[16] -1683 -360 186 SEG[68] 85 -360
135 SEG[17] -1649 -360 187 SEG[69] 119 -360
136 SEG[18] -1615 -360 188 SEG[70] 153 -360
137 SEG[19] -1581 -360 189 SEG[71] 187 -360
138 SEG[20] -1547 -360 190 SEG[72] 221 -360
139 SEG[21] -1513 -360 191 SEG[73] 255 -360
140 SEG[22] -1479 -360 192 SEG[74] 289 -360
141 SEG[23] -1445 -360 193 SEG[75] 323 -360
142 SEG[24] -1411 -360 194 SEG[76] 357 -360
143 SEG[25] -1377 -360 195 SEG[77] 391 -360
144 SEG[26] -1343 -360 196 SEG[78] 425 -360
145 SEG[27] -1309 -360 197 SEG[79] 459 -360
146 SEG[28] -1275 -360 198 SEG[80] 493 -360
147 SEG[29] -1241 -360 199 SEG[81] 527 -360
148 SEG[30] -1207 -360 200 SEG[82] 561 -360
149 SEG[31] -1173 -360 201 SEG[83] 595 -360
150 SEG[32] -1139 -360 202 SEG[84] 629 -360
Ver 1.7c 10/72 2009/09/14

ST7565R
203 SEG[85] 663 -360 246 SEG[128] 2125 -360
204 SEG[86] 697 -360 247 SEG[129] 2159 -360
205 SEG[87] 731 -360 248 SEG[130] 2193 -360
206 SEG[88] 765 -360 249 SEG[131] 2227 -360
207 SEG[89] 799 -360 250 Reserve 2267 -360
208 SEG[90] 833 -360 251 Reserve 2301 -360
209 SEG[91] 867 -360 252 Reserve 2335 -360
210 SEG[92] 901 -360 253 Reserve 2369 -360
211 SEG[93] 935 -360 254 Reserve 2403 -360
212 SEG[94] 969 -360 255 Reserve 2437 -360
213 SEG[95] 1003 -360 256 Reserve 2471 -360
214 SEG[96] 1037 -360 257 Reserve 2505 -360
215 SEG[97] 1071 -360 258 Reserve 2539 -360
216 SEG[98] 1105 -360 259 Reserve 2573 -360
217 SEG[99] 1139 -360 260 Reserve 2810 -375
218 SEG[100] 1173 -360 261 Reserve 2810 -341
219 SEG[101] 1207 -360 262 Reserve 2810 -307
220 SEG[102] 1241 -360 263 Reserve 2810 -273
221 SEG[103] 1275 -360 264 Reserve 2810 -239
222 SEG[104] 1309 -360 265 Reserve 2810 -205
223 SEG[105] 1343 -360 266 COM[16] 2810 -171
224 SEG[106] 1377 -360 267 COM[17] 2810 -137
225 SEG[107] 1411 -360 268 COM[18] 2810 -103
226 SEG[108] 1445 -360 269 COM[19] 2810 -69
227 SEG[109] 1479 -360 270 COM[20] 2810 -35
228 SEG[110] 1513 -360 271 COM[21] 2810 -1
229 SEG[111] 1547 -360 272 COM[22] 2810 33
230 SEG[112] 1581 -360 273 COM[23] 2810 67
231 SEG[113] 1615 -360 274 COM[24] 2810 101
232 SEG[114] 1649 -360 275 COM[25] 2810 135
233 SEG[115] 1683 -360 276 COM[26] 2810 169
234 SEG[116] 1717 -360 277 COM[27] 2810 203
235 SEG[117] 1751 -360 278 COM[28] 2810 237
236 SEG[118] 1785 -360 279 COM[29] 2810 271
237 SEG[119] 1819 -360 280 COM[30] 2810 305
238 SEG[120] 1853 -360 281 COM[31] 2810 339
239 SEG[121] 1887 -360 282 COMS1 2810 373
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
Ver 1.7c 11/72 2009/09/14

ST7565R

1 TEST[6] 2575 392 50 VRS -408 392
2 FR 2515 392 51 VRS -468 392
3 CL 2455 392 52 VDD2 -542 392
4 DOF 2395 392 53 VDD -602 392
5 VSS 2335 392 54 V4 -676 392
6 CS1B 2275 392 55 V4 -736 392
7 CS2 2215 392 56 V3 -796 392
8 VDD 2155 392 57 V3 -856 392
9 RST 2095 392 58 V2 -916 392
10 A0 2035 392 59 V2 -976 392
11 VSS 1975 392 60 V1 -1036 392
12 /WR(R/W) 1915 392 61 V1 -1096 392
13 /RD(E) 1855 392 62 V0 -1156 392
14 VDD 1795 392 63 V0 -1216 392
15 D0 1735 392 64 VR -1276 392
16 D1 1675 392 65 VR -1336 392
17 D2 1615 392 66 VDD -1410 392
18 D3 1555 392 67 VDD2 -1470 392
19 D4 1495 392 68 TEST[0] -1537 392
20 D5 1435 392 69 TEST[1] -1611 392
21 D6 1375 392 70 TEST[2] -1685 392
22 D7 1315 392 71 TEST[3] -1759 392
23 VDD 1255 392 72 TEST[4] -1833 392
24 VDD2 1195 392 73 TEST[5] -1907 392
25 VDD2 1135 392 74 VDD -1974 392
26 VSS 1075 392 75 TEST[7] -2034 392
27 VSS 1015 392 76 CLS -2094 392
28 VSS 955 392 77 C86 -2154 392
29 VSS 895 392 78 PSB -2214 392
30 VOUT 821 392 79 HPMB -2274 392
31 VOUT 761 392 80 IRS -2334 392
32 CAP5P 701 392 81 SEL1 -2394 392
33 CAP5P 641 392 82 SEL2 -2454 392
34 CAP1N 581 392 83 SEL3 -2514 392
35 CAP1N 521 392 84 VSS -2574 392
36 CAP3P 461 392 85 Reserve -2810 373
37 CAP3P 401 392 86 Reserve -2810 339
38 CAP1N 341 392 87 Reserve -2810 305
39 CAP1N 281 392 88 Reserve -2810 271
40 CAP1P 221 392 89 Reserve -2810 237
41 CAP1P 161 392 90 COM[26] -2810 203
42 CAP2P 101 392 91 COM[25] -2810 169
43 CAP2P 41 392 92 COM[24] -2810 135
44 CAP2N -19 392 93 COM[23] -2810 101
45 CAP2N -79 392 94 COM[22] -2810 67
46 CAP4P -139 392 95 COM[21] -2810 33
47 CAP4P -199 392 96 COM[20] -2810 -1
48 VSS -273 392 97 COM[19] -2810 -35
49 VSS -333 392 98 COM[18] -2810 -69
Ver 1.7c 12/72 2009/09/14

ST7565R
99 COM[17] -2810 -103 151 SEG[33] -1105 -360
100 COM[16] -2810 -137 152 SEG[34] -1071 -360
101 COM[15] -2810 -171 153 SEG[35] -1037 -360
102 COM[14] -2810 -205 154 SEG[36] -1003 -360
103 COM[13] -2810 -239 155 SEG[37] -969 -360
104 COM[12] -2810 -273 156 SEG[38] -935 -360
105 COM[11] -2810 -307 157 SEG[39] -901 -360
106 COM[10] -2810 -341 158 SEG[40] -867 -360
107 COM[9] -2810 -375 159 SEG[41] -833 -360
108 COM[8] -2573 -360 160 SEG[42] -799 -360
109 COM[7] -2539 -360 161 SEG[43] -765 -360
110 COM[6] -2505 -360 162 SEG[44] -731 -360
111 COM[5] -2471 -360 163 SEG[45] -697 -360
112 COM[4] -2437 -360 164 SEG[46] -663 -360
113 COM[3] -2403 -360 165 SEG[47] -629 -360
114 COM[2] -2369 -360 166 SEG[48] -595 -360
115 COM[1] -2335 -360 167 SEG[49] -561 -360
116 COM[0] -2301 -360 168 SEG[50] -527 -360
117 COMS2 -2267 -360 169 SEG[51] -493 -360
118 SEG[0] -2227 -360 170 SEG[52] -459 -360
119 SEG[1] -2193 -360 171 SEG[53] -425 -360
120 SEG[2] -2159 -360 172 SEG[54] -391 -360
121 SEG[3] -2125 -360 173 SEG[55] -357 -360
122 SEG[4] -2091 -360 174 SEG[56] -323 -360
123 SEG[5] -2057 -360 175 SEG[57] -289 -360
124 SEG[6] -2023 -360 176 SEG[58] -255 -360
125 SEG[7] -1989 -360 177 SEG[59] -221 -360
126 SEG[8] -1955 -360 178 SEG[60] -187 -360
127 SEG[9] -1921 -360 179 SEG[61] -153 -360
128 SEG[10] -1887 -360 180 SEG[62] -119 -360
129 SEG[11] -1853 -360 181 SEG[63] -85 -360
130 SEG[12] -1819 -360 182 SEG[64] -51 -360
131 SEG[13] -1785 -360 183 SEG[65] -17 -360
132 SEG[14] -1751 -360 184 SEG[66] 17 -360
133 SEG[15] -1717 -360 185 SEG[67] 51 -360
134 SEG[16] -1683 -360 186 SEG[68] 85 -360
135 SEG[17] -1649 -360 187 SEG[69] 119 -360
136 SEG[18] -1615 -360 188 SEG[70] 153 -360
137 SEG[19] -1581 -360 189 SEG[71] 187 -360
138 SEG[20] -1547 -360 190 SEG[72] 221 -360
139 SEG[21] -1513 -360 191 SEG[73] 255 -360
140 SEG[22] -1479 -360 192 SEG[74] 289 -360
141 SEG[23] -1445 -360 193 SEG[75] 323 -360
142 SEG[24] -1411 -360 194 SEG[76] 357 -360
143 SEG[25] -1377 -360 195 SEG[77] 391 -360
144 SEG[26] -1343 -360 196 SEG[78] 425 -360
145 SEG[27] -1309 -360 197 SEG[79] 459 -360
146 SEG[28] -1275 -360 198 SEG[80] 493 -360
147 SEG[29] -1241 -360 199 SEG[81] 527 -360
148 SEG[30] -1207 -360 200 SEG[82] 561 -360
149 SEG[31] -1173 -360 201 SEG[83] 595 -360
150 SEG[32] -1139 -360 202 SEG[84] 629 -360
Ver 1.7c 13/72 2009/09/14

ST7565R
203 SEG[85] 663 -360 246 SEG[128] 2125 -360
204 SEG[86] 697 -360 247 SEG[129] 2159 -360
205 SEG[87] 731 -360 248 SEG[130] 2193 -360
206 SEG[88] 765 -360 249 SEG[131] 2227 -360
207 SEG[89] 799 -360 250 Reserve 2267 -360
208 SEG[90] 833 -360 251 Reserve 2301 -360
209 SEG[91] 867 -360 252 Reserve 2335 -360
210 SEG[92] 901 -360 253 Reserve 2369 -360
211 SEG[93] 935 -360 254 Reserve 2403 -360
212 SEG[94] 969 -360 255 COM[27] 2437 -360
213 SEG[95] 1003 -360 256 COM[28] 2471 -360
214 SEG[96] 1037 -360 257 COM[29] 2505 -360
215 SEG[97] 1071 -360 258 COM[30] 2539 -360
216 SEG[98] 1105 -360 259 COM[31] 2573 -360
217 SEG[99] 1139 -360 260 COM[32] 2810 -375
218 SEG[100] 1173 -360 261 COM[33] 2810 -341
219 SEG[101] 1207 -360 262 COM[34] 2810 -307
220 SEG[102] 1241 -360 263 COM[35] 2810 -273
221 SEG[103] 1275 -360 264 COM[36] 2810 -239
222 SEG[104] 1309 -360 265 COM[37] 2810 -205
223 SEG[105] 1343 -360 266 COM[38] 2810 -171
224 SEG[106] 1377 -360 267 COM[39] 2810 -137
225 SEG[107] 1411 -360 268 COM[40] 2810 -103
226 SEG[108] 1445 -360 269 COM[41] 2810 -69
227 SEG[109] 1479 -360 270 COM[42] 2810 -35
228 SEG[110] 1513 -360 271 COM[43] 2810 -1
229 SEG[111] 1547 -360 272 COM[44] 2810 33
230 SEG[112] 1581 -360 273 COM[45] 2810 67
231 SEG[113] 1615 -360 274 COM[46] 2810 101
232 SEG[114] 1649 -360 275 COM[47] 2810 135
233 SEG[115] 1683 -360 276 COM[48] 2810 169
234 SEG[116] 1717 -360 277 COM[49] 2810 203
235 SEG[117] 1751 -360 278 COM[50] 2810 237
236 SEG[118] 1785 -360 279 COM[51] 2810 271
237 SEG[119] 1819 -360 280 COM[52] 2810 305
238 SEG[120] 1853 -360 281 COM[53] 2810 339
239 SEG[121] 1887 -360 282 COMS1 2810 373
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
Ver 1.7c 14/72 2009/09/14

ST7565R

1 TEST[6] 2575 392 50 VRS -408 392
2 FR 2515 392 51 VRS -468 392
3 CL 2455 392 52 VDD2 -542 392
4 DOF 2395 392 53 VDD -602 392
5 VSS 2335 392 54 V4 -676 392
6 CS1B 2275 392 55 V4 -736 392
7 CS2 2215 392 56 V3 -796 392
8 VDD 2155 392 57 V3 -856 392
9 RST 2095 392 58 V2 -916 392
10 A0 2035 392 59 V2 -976 392
11 VSS 1975 392 60 V1 -1036 392
12 /WR(R/W) 1915 392 61 V1 -1096 392
13 /RD(E) 1855 392 62 V0 -1156 392
14 VDD 1795 392 63 V0 -1216 392
15 D0 1735 392 64 VR -1276 392
16 D1 1675 392 65 VR -1336 392
17 D2 1615 392 66 VDD -1410 392
18 D3 1555 392 67 VDD2 -1470 392
19 D4 1495 392 68 TEST[0] -1537 392
20 D5 1435 392 69 TEST[1] -1611 392
21 D6 1375 392 70 TEST[2] -1685 392
22 D7 1315 392 71 TEST[3] -1759 392
23 VDD 1255 392 72 TEST[4] -1833 392
24 VDD2 1195 392 73 TEST[5] -1907 392
25 VDD2 1135 392 74 VDD -1974 392
26 VSS 1075 392 75 MS -2034 392
27 VSS 1015 392 76 CLS -2094 392
28 VSS 955 392 77 C86 -2154 392
29 VSS 895 392 78 PSB -2214 392
30 VOUT 821 392 79 HPMB -2274 392
31 VOUT 761 392 80 IRS -2334 392
32 CAP5P 701 392 81 SEL1 -2394 392
33 CAP5P 641 392 82 SEL2 -2454 392
34 CAP1N 581 392 83 SEL3 -2514 392
35 CAP1N 521 392 84 VSS -2574 392
36 CAP3P 461 392 85 Reserve -2810 373
37 CAP3P 401 392 86 Reserve -2810 339
38 CAP1N 341 392 87 Reserve -2810 305
39 CAP1N 281 392 88 Reserve -2810 271
40 CAP1P 221 392 89 Reserve -2810 237
41 CAP1P 161 392 90 Reserve -2810 203
42 CAP2P 101 392 91 COM[25] -2810 169
43 CAP2P 41 392 92 COM[24] -2810 135
44 CAP2N -19 392 93 COM[23] -2810 101
45 CAP2N -79 392 94 COM[22] -2810 67
46 CAP4P -139 392 95 COM[21] -2810 33
47 CAP4P -199 392 96 COM[20] -2810 -1
48 VSS -273 392 97 COM[19] -2810 -35
49 VSS -333 392 98 COM[18] -2810 -69
Ver 1.7c 15/72 2009/09/14

ST7565R
99 COM[17] -2810 -103 151 SEG[33] -1105 -360
100 COM[16] -2810 -137 152 SEG[34] -1071 -360
101 COM[15] -2810 -171 153 SEG[35] -1037 -360
102 COM[14] -2810 -205 154 SEG[36] -1003 -360
103 COM[13] -2810 -239 155 SEG[37] -969 -360
104 COM[12] -2810 -273 156 SEG[38] -935 -360
105 COM[11] -2810 -307 157 SEG[39] -901 -360
106 COM[10] -2810 -341 158 SEG[40] -867 -360
107 COM[9] -2810 -375 159 SEG[41] -833 -360
108 COM[8] -2573 -360 160 SEG[42] -799 -360
109 COM[7] -2539 -360 161 SEG[43] -765 -360
110 COM[6] -2505 -360 162 SEG[44] -731 -360
111 COM[5] -2471 -360 163 SEG[45] -697 -360
112 COM[4] -2437 -360 164 SEG[46] -663 -360
113 COM[3] -2403 -360 165 SEG[47] -629 -360
114 COM[2] -2369 -360 166 SEG[48] -595 -360
115 COM[1] -2335 -360 167 SEG[49] -561 -360
116 COM[0] -2301 -360 168 SEG[50] -527 -360
117 COMS2 -2267 -360 169 SEG[51] -493 -360
118 SEG[0] -2227 -360 170 SEG[52] -459 -360
119 SEG[1] -2193 -360 171 SEG[53] -425 -360
120 SEG[2] -2159 -360 172 SEG[54] -391 -360
121 SEG[3] -2125 -360 173 SEG[55] -357 -360
122 SEG[4] -2091 -360 174 SEG[56] -323 -360
123 SEG[5] -2057 -360 175 SEG[57] -289 -360
124 SEG[6] -2023 -360 176 SEG[58] -255 -360
125 SEG[7] -1989 -360 177 SEG[59] -221 -360
126 SEG[8] -1955 -360 178 SEG[60] -187 -360
127 SEG[9] -1921 -360 179 SEG[61] -153 -360
128 SEG[10] -1887 -360 180 SEG[62] -119 -360
129 SEG[11] -1853 -360 181 SEG[63] -85 -360
130 SEG[12] -1819 -360 182 SEG[64] -51 -360
131 SEG[13] -1785 -360 183 SEG[65] -17 -360
132 SEG[14] -1751 -360 184 SEG[66] 17 -360
133 SEG[15] -1717 -360 185 SEG[67] 51 -360
134 SEG[16] -1683 -360 186 SEG[68] 85 -360
135 SEG[17] -1649 -360 187 SEG[69] 119 -360
136 SEG[18] -1615 -360 188 SEG[70] 153 -360
137 SEG[19] -1581 -360 189 SEG[71] 187 -360
138 SEG[20] -1547 -360 190 SEG[72] 221 -360
139 SEG[21] -1513 -360 191 SEG[73] 255 -360
140 SEG[22] -1479 -360 192 SEG[74] 289 -360
141 SEG[23] -1445 -360 193 SEG[75] 323 -360
142 SEG[24] -1411 -360 194 SEG[76] 357 -360
143 SEG[25] -1377 -360 195 SEG[77] 391 -360
144 SEG[26] -1343 -360 196 SEG[78] 425 -360
145 SEG[27] -1309 -360 197 SEG[79] 459 -360
146 SEG[28] -1275 -360 198 SEG[80] 493 -360
147 SEG[29] -1241 -360 199 SEG[81] -207 -374
148 SEG[30] -1207 -360 200 SEG[82] -149 -374
149 SEG[31] -1173 -360 201 SEG[83] -91 -374
150 SEG[32] -1139 -360 202 SEG[84] -33 -374
Ver 1.7c 16/72 2009/09/14

ST7565R
203 SEG[85] 25 -374 246 SEG[128] 2519 -374
204 SEG[86] 83 -374 247 SEG[129] 2577 -374
205 SEG[87] 141 -374 248 SEG[130] 2635 -374
206 SEG[88] 199 -374 249 SEG[131] 2693 -374
207 SEG[89] 257 -374 250 Reserve 2751 -374
208 SEG[90] 315 -374 251 Reserve 2809 -374
209 SEG[91] 373 -374 252 Reserve 2867 -374
210 SEG[92] 431 -374 253 Reserve 2925 -374
211 SEG[93] 489 -374 254 Reserve 2983 -374
212 SEG[94] 547 -374 255 Reserve 3041 -374
213 SEG[95] 605 -374 256 COM[26] 3099 -374
214 SEG[96] 663 -374 257 COM[27] 3157 -374
215 SEG[97] 721 -374 258 COM[28] 3215 -374
216 SEG[98] 779 -374 259 COM[29] 3273 -374
217 SEG[99] 837 -374 260 COM[30] 3331 -374
218 SEG[100] 895 -374 261 COM[31] 3389 -374
219 SEG[101] 953 -374 262 COM[32] 3447 -374
220 SEG[102] 1011 -374 263 COM[33] 3505 -374
221 SEG[103] 1069 -374 264 COM[34] 3563 -374
222 SEG[104] 1127 -374 265 COM[35] 3621 -374
223 SEG[105] 1185 -374 266 COM[36] 3679 -374
224 SEG[106] 1243 -374 267 COM[37] 3737 -374
225 SEG[107] 1301 -374 268 COM[38] 3795 -374
226 SEG[108] 1359 -374 269 COM[39] 3853 -374
227 SEG[109] 1417 -374 270 COM[40] 3911 -374
228 SEG[110] 1475 -374 271 COM[41] 3969 -374
229 SEG[111] 1533 -374 272 COM[42] 4027 -374
230 SEG[112] 1591 -374 273 COM[43] 4085 -374
231 SEG[113] 1649 -374 274 COM[44] 4143 -374
232 SEG[114] 1707 -374 275 COM[45] 4201 -374
233 SEG[115] 1765 -374 276 COM[46] 4259 -374
234 SEG[116] 1823 -374 277 COM[47] 4542 -345
235 SEG[117] 1881 -374 278 COM[48] 4542 -287
236 SEG[118] 1939 -374 279 COM[49] 4542 -229
237 SEG[119] 1997 -374 280 COM[50] 4542 -171
238 SEG[120] 2055 -374 281 COM[51] 4542 -113
239 SEG[121] 2113 -374 282 COMS1 4542 -55
240 SEG[122] 2171 -374
241 SEG[123] 2229 -374
242 SEG[124] 2287 -374
243 SEG[125] 2345 -374
244 SEG[126] 2403 -374
245 SEG[127] 2461 -374
Ver 1.7c 17/72 2009/09/14

ST7565R
Block Diagram
SEG131
COM63
COMS
COM0
SEG0
VDD
V0
V1
COMS
V2 132 SEGMENT 64 COMMON
V3
V4 DRIVERS DRI VERS
VSS
COM output control circuit
Voltage Display data latch
Display timing generator circuit

HPM circuit
follower FRS
circuit
Line address circuit

M/S
Page address
V0 CL
I/O buffer
circuit
VR DOF
Voltage DISPLAY DATA RAM
VRS Regulator FR
circuit
IRS
65 X 132 = 8580 Bits
VOUT
CAP1N
Voltage Column address circuit
CAP1P
CAP2N booster
CAP2P circuit
Oscillator
CAP3N
circuit
CAP4P CLS
CAP5P Power Supply
Circuit
VDD2
Command
Status Bus holder
VSS decoder
MPU INTERFACE ( Parallel and Serial )

RW(/WR)
SEL1
SEL2
SEL3
E(/RD)
A0
CS1
CS2
/RES
C86
P/S
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
Ver 1.7c 18/72 2009/09/14

ST7565R
Pin Descriptions
Power Supply Pins
Pin Name I/O Function No. of Pins

Power
VDD Power supply 13
Supply
Power
VDD2 Power supply 10
Supply
Power
VSS Ground 2
Supply
Power This is the internal-output VREG power supply for the LCD power supply voltage
VRS 2
Supply regulator.
This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is
determined by the liquid crystal cell, and is changed through the use of a resistive voltage
divided or through changing the impedance using an op. amp. Voltage levels are
determined based on Vss, and must maintain the relative magnitudes shown below.
V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss

V0, V1,
Power When the power supply turns ON, the internal power supply circuits produce the V1 to V4
V2, V3, 10
Supply voltages shown below. The voltage settings are selected using the LCD bias set
V4,Vss
command.
1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY
V1 8/9*V0,6/7*V0 7/8*V0,5/6*V0 5/6*V0,4/5*V0 7/8*V0,5/6*V0 7/8*V0,5/6*V0
V2 7/9*V0,5/7*V0 6/8*V0,4/6*V0 4/6*V0,3/5*V0 6/8*V0,4/6*V0 6/8*V0,4/6*V0
V3 2/9*V0,2/7*V0 2/8*V0,2/6*V0 2/6*V0,2/5*V0 2/8*V0,2/6*V0 2/8*V0,2/6*V0
V4 1/9*V0,1/7*V0 1/8*V0,1/6*V0 1/6*V0,1/5*V0 1/8*V0,1/6*V0 1/8*V0,1/6*V0
LCD Power Supply Pins

DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N
CAP1P O 4
terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1P
CAP1N O 2
terminal.
CAP2P O 2
terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2P
CAP2N O 2
terminal.
CAP3P O 2
terminal.
CAP4P O 2
terminal.
CAP5P O 2
terminal.
DC/DC voltage converter. Connect a capacitor between this terminal and VSS or VDD
VOUT O 2
terminal.
Output voltage regulator terminal. Provides the voltage between VSS and V0 through a
resistive voltage divider.
VR I 2
IRS = “L” : the V0 voltage regulator internal resistors are not used.
IRS = “H” : the V0 voltage regulator internal resistors are used.
Ver 1.7c 19/72 2009/09/14

ST7565R
System Bus Connection Pins

This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU
D5 to D0 data bus.
When the serial interface (SPI-4) is selected (P/S = “L”) :
D6 (SCL) I/O D7 : serial data input (SI) ; D6 : the serial clock input (SCL).
8
D7 (SI) D0 to D5 should be connected to VDD or floating.
When the chip select is not active, D0 to D7 are set to high impedance.
This is connect to the least significant bit of the normal MPU address bus, and it
determines whether the data bits are data or command.
A0 I A0 = “H”: Indicates that D0 to D7 are display data.
1
A0 = “L”: Indicates that D0 to D7 are control data.
When /RES is set to “L”, the register settings are initialized (cleared).
/RES I The reset operation is performed by the /RES signal level.
1
CS1B This is the chip select signal. When CS1B = “L” and CS2 = “H”, then the chip select
I becomes active, and data/command I/O is enabled.
2
CS2
• When connected to 8080 series MPU, this pin is treated as the “/RD” signal of the 8080
MPU and is LOW-active.
/RD The data bus is in an output status when this signal is “L”.
I • When connected to 6800 series MPU, this pin is treated as the “E” signal of the 6800
1
(E)
MPU and is HIGH-active.
This is the enable clock input terminal of the 6800 Series MPU.
• When connected to 8080 series MPU, this pin is treated as the “/WR” signal of the 8080
MPU and is LOW-active.
The signals on the data bus are latched at the rising edge of the /WR signal.
/WR
I • When connected to 6800 series MPU, this pin is treated as the “R/W” signal of the 6800 1
(R/W) MPU and decides the access type :
When R/W = “H”: Read.
When R/W = “L”: Write.
This is the MPU interface selection pin.
C86 I C86 = “H”: 6800 Series MPU interface. 1
C86 = “L”: 8080 Series MPU interface.
This pin configures the interface to be parallel mode or serial mode.
P/S = “H”: Parallel data input/output.
P/S = “L”: Serial data input.
The following applies depending on the P/S status:
P/S Data/Command Data Read/Write 4-line SPI Clock

P/S I “H” A0 D0 to D7 /RD, /WR X 1
“L” A0 SI (D7) Write only SCL (D6)
When P/S = “L”, D0 to D5 must be fixed to “H”.

/RD (E) and /WR (R/W) are fixed to either “H” or “L”.
The serial access mode does NOT support read operation.
Ver 1.7c 20/72 2009/09/14

ST7565R
Selection pin to enable or disable the internal display clock oscillator circuit.
CLS = “H” : use internal oscillator circuit .
CLS I
CLS = “L” : use external clock input (internal oscillator is disabled).
1
When CLS = “L”, input the external display clock through the CL terminal.
This is the display clock input terminal
The following is true depending on the CLS status.
CLS CL
CL I/O “H” Output 1
“L” Input
“H” Input
“L” Input
FR O This is the liquid crystal alternating current signal terminal. 1
/DOF O This is the LCD blanking control terminal. 1

This terminal selects the resistors for the V0 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS I
IRS = “L”: Do not use the internal resistors. The V0 voltage level is
1
regulated by an external resistive voltage divider attached to the VR terminal
This is the power control terminal for the power supply circuit for liquid crystal drive.
/HPM I /HPM = “H”: Normal mode 1
/HPM = “L”: High power mode (suggested)
These pins are DUTY selection.
SEL 3, 2, 1 DUTY BIAS
0, 0, 0 1/65 1/9 or 1/7
SEL3 0, 0, 1 1/49 1/8 or 1/6
SEL2 I 0, 1, 0 1/33 1/6 or 1/5 3
SEL1
0, 1, 1 1/55 1/8 or 1/6
1, 0, 0 1/53 1/8 or 1/6
1, X, X ----- -----
These are terminals for IC testing.
TEST0 ~ 7 I TEST0 ~ 6: left them open. 6
TEST7 must connected to VDD
Ver 1.7c 21/72 2009/09/14

ST7565R
LCD Driver Pins
These are the LCD segment drive outputs. Through a combination of the contents of the
display RAM and with the FR signal, a single level is selected from VSS, V3, V2, and V0.
Output Voltage
RAM DATA FR
Normal Display Reverse Display
SEG0
H H V0 V2
to O 132
SEG131 H L VSS V3
L H V2 V0
L L V3 Vss
Power save VSS
Through a combination of the contents of the scan data and with the FR signal, a single
level is selected from VSS, V4, V1, and V0.
Scan Data FR Output Voltage
COM0 H H VSS
to O H L V0 67
COMn
L H V1
L L V4
Power save VSS
These are the COM output terminals for the indicator. Both terminals output the same
COMS O signal. 2
Leave these open if they are not used.
ST7565R I/O PIN ITO Resister Limitation

PIN Name ITO Resister
CL, FR, /DOF, C86, PSB, HPMB, SEL1…SEL3, CLS, IRS No Limitation
TEST0 ~ 7, VRS Floating
VDD, VDD2, VSS, VOUT, VR <100Ω
V0, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N, CAP3P, CAP4P, CAP5P <300Ω
CS1B, CS2, /RD, /WR, A0, D0 …D7 <1KΩ
RST <10KΩ
Ver 1.7c 22/72 2009/09/14

ST7565R
Description Of Functions
The MPU Interface

Selecting the Interface Type
With the ST7565R chips, data transfers are done through an to the “H” or “L” it is possible to select either parallel
8-bit parallel data bus (D7 to D0) or through a 4-line SPI data input or 4-line SPI data input as shown in Table 1.
data input (SI). Through selecting the P/ S terminal polarity
Table 1
P/S /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0
H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0

L: 4-line SPI Input /CS1 CS2 A0 — — — SI SCL (HZ)
“—” indicates fixed to “H”
The Parallel Interface

When the parallel interface has been selected (P/S =“H”), 8080-system MPU or a 6800 Series MPU (shown in Table 2)
then it is possible to connect directly to either an by selecting the C86 terminal to either “H” or to “L”.
Table 2
C86 (P/S=H) /CS1 CS2 A0 E(/RD) R/W(/WR) D7~D0
H: 6800 Series /CS1 CS2 A0 E R/W D7~D0

L: 8080 Series /CS1 CS2 A0 /RD /WR D7~D0
Moreover, data bus signals are recognized by a combination

of A0, /RD (E), /WR (R/W) signals, as shown in Table 3.
Table 3
Shared 6800 Series 8080 Series
Function
A0 R/W /RD /WR
1 1 0 1 Reads the display data
1 0 1 0 Writes the display data
0 1 0 1 Status read
0 0 1 0 Write control data (command)
Ver 1.7c 23/72 2009/09/14

ST7565R
The 4-line SPI Interface
When the 4-line SPI interface has been selected (P/S = “L”) eighth 4-line SPI clock for the processing. The A0 input is
then when the chip is in active state (/CS1 = “L” and CS2 = used to determine whether or the 4-line SPI data input is
“H”) the 4-line SPI data input (SI) and the 4-line SPI clock display data or command data; when A0 = “H”, the data is
input (SCL) can be received. The 4-line SPI data is read from display data, and when A0 = “L” then the data is command
the 4-line SPI data input pin in the rising edge of the 4-line data. The A0 input is read and used for detection every 8th
SPI clocks D7, D6 through D0, in this order. This data is rising edge of the 4-line SPI clock after the chip becomes
converted to 8 bits parallel data in the rising edge of the active. Figure 1 is a 4-line SPI interface signal chart.
CS1
CS2
SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A0
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their initial states.
* Reading is not possible while in 4-line SPI interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation
be rechecked on the actual equipment.
The Chip Select

The ST7565R have two chip select terminals: /CS1 and When the chip select is inactive, D0 to D7 enter a high
CS2. The MPU interface or the 4-line SPI interface is impedance state, and the A0, /RD, and /WR inputs are
enabled only when /CS1 = “L” and CS2 = “H”. inactive. When the 4-line SPI interface is selected, the shift
register and the counter are reset.
The Accessing the Display Data RAM and the Internal Registers
Data transfer at a higher speed is ensured since the MPU is the first data read cycle (dummy) stores the read data in the
required to satisfy the cycle time (tCYC) requirement alone in bus holder, and then the data is read from the bus holder to
accessing the ST7565R. Wait time may not be considered. the system bus at the next data read cycle.
And, in the ST7565R, each time data is sent from the MPU, a There is a certain restriction in the read sequence of the
type of pipeline process between LSIs is performed through display data RAM. Please be advised that data of the
the bus holder attached to the internal data bus. Internal specified address is not generated by the read instruction
data bus. issued immediately after the address setup. This data is
For example, when the MPU writes data to the display data generated in data read of the second time. Thus, a dummy
RAM, once the data is stored in the bus holder, then it is read is required whenever the address setup
written to the display data RAM before the next data write or write cycle operation is conducted.
cycle. Moreover, when the MPU reads the display data RAM, This relationship is shown in Figure 2.
The Busy Flag

When the busy flag is “1” it indicates that the ST7565R is (tCYC) is maintained, it is not necessary to check for this flag
running internal processes, and at this time no command before each command. This makes vast improvements in
aside from a status read will be received. The busy flag is MPU processing capabilities possible.
outputted to D7 pin with the read instruction. If the cycle time
Ver 1.7c 24/72 2009/09/14

ST7565R
Writing
WR
MPU
DATA N N+1 N+2 N+3

Internal Timing
BUS
N N+1 N+2 N+3
Holder
Write
Signal
Reading
WR
MPU
RD
DATA N N n n+1
Address
Preset
Internal Timing
Read
Signal
Column
Address Preset N Increment N+1 N+2
Bus Holder N n n+1 n+2
Address Dummy Data Read Data Read

Set #n Read #n #n+1
Figure 2
Ver 1.7c 25/72 2009/09/14

ST7565R
Display Data RAM
The display data RAM stores the dot data for the LCD. It has freedom.
a 65 (8 page x 8 bit +1) x 132 bit structure. Moreover, reading from and writing to the display RAM from
As is shown in Figure 3, the D7 to D0 display data from the the MPU side is performed through the I/O buffer, which is
MPU corresponds to the LCD display common direction; an independent operation from signal reading for the liquid
there are few constraints at the time of display data transfer crystal driver. Consequently, even if the display data RAM is
when multiple ST7565R are used, thus and display accessed asynchronously during liquid crystal display, it will
structures can be created easily and with a high degree of not cause adverse effects on the display (such as flickering).
D0 0 1 1 1 0 COM0
D1 1 0 0 0 0 COM1
D2 0 0 0 0 0 COM2
D3 0 1 1 1 0 COM3
D4 1 0 0 0 0 COM4
- -
Display data RAM Liquid crystal display
Figure 3
The Page Address Circuit
Page address of the display data RAM is specified through Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special
the Page Address Set Command. The page address must RAM for icons, and only display data D0 is used.
be specified again when changing pages to perform access. (see Figure 4)
The Column Addresses

The display data RAM column address is specified by the it is necessary to respective both the page address and the
Column Address Set command. The specified column column address.
address is incremented (+1) with each display data Furthermore, as is shown in Table 4, the ADC command
read/write command. This allows the MPU display data to be (segment driver direction select command) can be used to
accessed continuously. Moreover, the incrementing of reverse the relationship between the display data RAM
column addresses stops with 83H. Because the column column address and the segment output. Because of this,
address is independent of the page address, when moving, the constraints on the IC layout when the LCD module is
for example, from page 0 column 83H to page 1 column 00H, assembled can be minimized. As is shown in Figure 4,
Table 4
SEG Output
ADC SEG0 SEG 131
(D0) “0” 0 (H) → Column Address → 83 (H)
(D0) “1” 83 (H) ← Column Address ← 0 (H)
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies the for ST7565R, the detail is shown page.11 The display area
line address relating to the COM output when the contents of is a 65 line area for the ST7565R.
the display data RAM are displayed. Using the display start If the line addresses are changed dynamically using the
line address set command, what is normally the top line of display start line address set command, screen scrolling,
the display can be specified (this is the COM0 output when page swapping, etc. can be performed.
the common output mode is normal, and the COM63 output
Ver 1.7c 26/72 2009/09/14

ST7565R
Page Address Line When the common COM
Data output is normal
D3 D2 D1 D0 Address Output
D0 00H COM0
D1 01H COM1
D2 02H COM2
D3 03H COM3
0 0 0 0 Page 0
D4 04H COM4
D5 05H COM5
D6 06H COM6
D7 07H COM7
D0 08H COM8
D1 09H COM9
D2 0AH COM10
D3 0BH COM11
0 0 0 1 Page 1
D4 0CH COM12
D5 0DH COM13
D6 0EH COM14
D7 0FH COM15
D0 10H COM16
D1 11H COM17
D2 12H COM18
D3 13H COM19
0 0 1 0 Page 2
D4 14H COM20
D5 15H COM21
D6 16H COM22
D7 17H COM23
D0 18H COM24
D1 19H COM25
D2 1AH COM26
D3 1BH COM27
0 0 1 1 Page 3
D4 1CH COM28
D5 1DH COM29
D6 1EH COM30
D7 1FH COM31
D0 20H COM32
D1 21H COM33
D2 22H COM34
D3 23H COM35
0 1 0 0 Page 4
D4 24H COM36
D5 25H COM37
D6 26H COM38
D7 27H COM39
D0 28H COM40
D1 29H COM41
D2 2AH COM42
D3 2BH COM43
0 1 0 1 Page 5
D4 2CH COM44
D5 2DH COM45
D6 2EH COM46
D7 2FH COM47
D0 30H COM48
D1 31H COM49
D2 32H COM50
D3 33H COM51
0 1 1 0 Page 6
D4 34H COM52
D5 35H COM53
D6 36H COM54
D7 37H COM55
D0 38H COM56
D1 39H COM57
D2 3AH COM58
D3 3BH COM59
0 1 1 1 Page 7
D4 3CH COM60
D5 3DH COM61
D6 3EH COM62
D7 3FH COM63
1 0 0 0 D0 Page 8 COMS
Regardless of the display
address
Column
7C
7D
D0 D0
7B
7E
7F
00
01
02
03
04
05
06
07
08
80
81
82
83
start line address,

0
ADC
1/65duty => 64th line,

7D
7C
7E
7B
7F
83
82
81
80
08
07
06
05
04
03
02
01
00
1/49duty =>48th line.

1
1/33duty =>32th line,

S123
S124
S125
S126
S127
S128
S129
S130
S131
LCD
1/55duty =>54th line,

Out
S0
S1
S2
S3
S4
S5
S6
S7
S8
1/53duty =>52th line.
Figure 4
Ver 1.7c 27/72 2009/09/14

ST7565R
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily status, and display all points ON/OFF commands control
stores the display data that is output to the liquid crystal only the data within the latch, they do not change
driver circuit from the display data RAM. the data within the display data RAM itself.
Because the display normal/reverse status, display ON/OFF
The Oscillator Circuit

This is a CR-type oscillator that produces the display clock. When CLS = “L” the oscillation stops, and the external
The oscillator circuit is only enabled when CLS = “H”. clock is input through the CL terminal.
Display Timing Generator Circuit

The display timing generator circuit generates the timing RAM is accessed asynchronously during liquid crystal
signal to the line address circuit and the display data latch display, there is absolutely no adverse effect (such as
circuit using the display clock. The display data is latched flickering) on the display.
into the display data latch circuit synchronized with the Moreover, the display timing generator circuit generates the
display clock, and is output to the data driver output terminal. common timing and the liquid crystal alternating current
Reading to the display data liquid crystal driver circuits is signal (FR) from the display clock. It generates a drive wave
completely independent of accesses to the display data form using a 2 frame alternating current drive method, as is
RAM by the MPU. Consequently, even if the display data shown in Figure 5, for the liquid crystal drive circuit.
Two-frame alternating current drive waveform
64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6
CL
FR
V0
V1
COM0
V4
VSS
V0
V1
COM1
V4
Vss
RAM
Data
V0
V2
SEGn
V3
VSS
Figure 5
Ver 1.7c 28/72 2009/09/14

ST7565R
The Common Output Status Select Circuit
In the ST7565R chips, the COM output scan direction can be (See Table 6.) Consequently, the constraints in IC layout at
selected by the common output status select command. the time of LCD module assembly can be minimized.
Table 6
COM Scan Direction
Status
1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY
Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51
Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0
COM Common output pins

Duty
dir COM[0:15] COM[16:23] COM[24:26] COM[27:36] COM[37:39] COM[40:47] COM[48:63] COMS
0 COM[0:63] COMS
1/65
1 COM[63:0] COMS
0 COM[0:23] Reserved COM[24:47] COMS
1/49
1/33
1/55
1/53
Ver 1.7c 29/72 2009/09/14

ST7565R
The LCD Driver Circuits
These are a 187-channel that generates four voltage levels crystal drive voltage output.
for driving the LCD . The combination of the display data, the Figure 6 shows examples of the SEG and COM output
COM scan signal, and the FR signal produces the liquid wave form.
VDD
COM0 M VSS
COM1 V0
V1
COM2 V2
COM0 V3
COM3 V4
VSS
COM4
V0
COM5 V1
V2
COM6 COM1 V3
V4
COM7 VSS
V0
COM8 V1
V2
COM9 COM2 V3
V4
COM10 VSS
COM11 V0
V1
COM12 V2
SEG0 V3
COM13 V4
VSS
COM14
V0
COM15 V1
V2
SEG1 V3
SEG 0 1 2 3 4 V4
VSS
V0
V1
V2
V3
COM0 V4
to VSS
-V4
SEG0 -V3
-V2
-V1
-V0
V0
V1
V2
V3
COM0 V4
to VSS
-V4
SEG1 -V3
-V2
-V1
-V0
Figure 6
Ver 1.7c 30/72 2009/09/14

ST7565R
The Power Supply Circuits
The power supply circuits are low-power consumption power independently through the use of the Power Control Set
supply circuits that generate the voltage levels required for command. Consequently, it is possible to make an external
the LCD drivers. They are Booster circuits, voltage regulator power supply and the internal power supply function
circuits, and voltage follower circuits. The power supply somewhat in parallel. Table 7 shows the Power Control Set
circuits can turn the Booster circuits, the voltage regulator Command 3-bit data control function, and Table 8 shows
circuits, and the voltage follower circuits ON or OFF reference combinations.
Table 7
Status
bit function
“1” “0”
D2 Booster circuit control bit ON OFF

D1 Voltage regulator circuit control bit (V/R circuit) ON OFF
D0 Voltage follower circuit control bit (V/F circuit) ON OFF
The Control Details of Each Bit of the Power Control Set Command
Table 8
External
Voltage Voltage Voltage Step-up
Use Settings D2 D1 D0 voltage
booster regulator follower voltage
input
Only the internal power supply is used 1 1 1 ON ON ON VDD2 Used

Only the voltage regulator circuit and the
0 1 1 OFF ON ON VOUT, VDD2 Open
voltage follower circuit are used
Only the V/F circuit is used 0 0 1 OFF OFF ON V0, VDD2 Open
Only the external power supply is used 0 0 0 OFF OFF OFF V0 to V4 Open
Reference Combinations
* The “step-up system terminals” refer CAP1N, CAP1P, CAP2N, CAP2P, and CAP3N.
* While other combinations, not shown above, are also possible, these combinations are not recommended
because they have no practical use.
The Step-up Voltage Circuits

Using the step-up voltage circuits equipped within the 4X step-up: Connect capacitor C1 between CAP1N and
ST7565R chips it is possible to product a 2X,3X,4X,5X or 6X CAP1P, between CAP2N and CAP2P, between
step-up of the VSS – VDD2 voltage levels. CAP1N and CAP3P, and between VDD2 and
6X step-up: Connect capacitor C1 between CAP1N and VOUT, to produce a voltage level in the positive
CAP1P, between CAP2N and CAP2P, between direction at the VOUT terminal that is 4 times the
CAP1N and CAP3P, between CAP2N and voltage level between VSS and VDD2.
CAP4P,between CAP1N and CAP5P, and 3X step-up: Connect capacitor C1 between CAP1N and
between VDD2 and VOUT, to produce a voltage CAP1P, between CAP2N and CAP2P and between
level in the positive direction at the VOUT VDD2 and VOUT, and short between CAP3P and
terminal that is 6 times the voltage level VOUT to produce voltages level in the positive direction
between VSS and VDD2. at the VOUT terminal that is 3 times the voltage difference
5X step-up: Connect capacitor C1 between CAP1N and between VSS and VDD2.
CAP1P, between CAP2N and CAP2P, between 2X step-up: Connect capacitor C1 between CAP1N and
CAP1N and CAP3P, between CAP2N and CAP1P, and between VDD2 and VOUT, leave
CAP4P,and between VDD2 and VOUT, to CAP2N open, and short between CAP2P,
produce a voltage level in the positive direction CAP3P and VOUT to produce a voltage in the
at the VOUT terminal that is 5 times the voltage positive direction at the VOUT terminal that Is
level between VSS and VDD2. twice the voltage between VSS and VDD2.
The step-up voltage relationships are shown in Figure 7.
Ver 1.7c 31/72 2009/09/14

ST7565R
VDD2 or VSS VDD2 or VSS VDD2 or VSS
C1 C1 C1
VOUT VOUT VOUT
CAP3P CAP3P CAP3P
C1
CAP1N CAP1N CAP1N
C1 C1 C1
CAP1P CAP1P CAP1P
CAP2P CAP2P CAP2P
C1 C1
OPEN CAP2N CAP2N CAP2N
OPEN CAP4P OPEN CAP4P OPEN CAP4P

OPEN CAP5P OPEN CAP5P OPEN CAP5P
2x voltage booster circuit 3x voltage booster circuit 4x voltage booster circuit
VOUT<=2xVDD2 VOUT<=3xVDD2 VOUT<=4xVDD2

Do NOT over voltage Do NOT over voltage Do NOT over voltage
limitation limitation limitation
VDD2 VDD2 VDD2
VSS VSS VSS
2x boost voltage relationship 3x boost voltage relationship 4x boost voltage relationship
VDD2 or VSS VDD2 or VSS

C1 C1
VOUT VOUT
CAP3P CAP3P
C1 C1
CAP1N CAP1N
C1 C1
CAP1P CAP1P
CAP2P CAP2P
C1 C1
CAP2N CAP2N
C1 C1
CAP4P CAP4P
C1
OPEN CAP5P CAP5P
5x voltage booster circuit 6x voltage booster circuit
VOUT<=5xVDD2 VOUT<=6xVDD2
Do NOT over voltage Do NOT over voltage
limitation limitation
VDD2 VDD2
VSS VSS
5x boost voltage relationship 6x boost voltage relationship
Figure 7
* The VDD2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value.
* The maximum voltage of the booster capacitor terminals are :
VMAX: CAP5P > CAP4P > CAP3P > CAP2P > CAP1P > CAP2N = CAP1N.
Ver 1.7c 32/72 2009/09/14

ST7565R
The Voltage Regulator Circuit
The step-up voltage generated at VOUT outputs the LCD function and internal resistors for the V0 voltage regulator,
driver voltage V 0 through the voltage regulator circuit. systems can be constructed without having to include
Because the ST7565R chips have an internal high-accuracy high-accuracy voltage regulator circuit components.
fixed voltage power supply with a 64-level electronic volume (VREG thermal gradients approximate -0.05%/°C)
(A) When the V0 Voltage Regulator Internal Resistors Are Used

Through the use of the V0 voltage regulator internal resistors adjust the liquid crystal display brightness. The V0 voltage
and the electronic volume function the liquid crystal power can be calculated using equation A-1 over the range where
supply voltage V0 can be controlled by commands alone | V0 | < | VOUT |.
(without adding any external resistors), making it possible to
( Rb
V0 = 1 +
Ra )
V EV
Rb α
=( 1 + ) ( 162 )
1- V REG
Ra
α
[∵ V = ( 1 - 162
EV ) V ] REG
VSS
VEV(constant voltage supply+electronic volume)

Internal Ra
V0
Internal Rb
Figure 8
VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9.
Table 9
Part no. Equipment Type Thermal Gradient VREG
ST7565R Internal Power Supply –0.05 %/°C 2.1V
α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic
volume registers. Table 10 shows the value for α depending on the electronic volume register settings.
Rb/Ra is the V0 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V0 voltage regulator
internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data
settings in the V0 voltage regulator internal resistor ratio register.
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ST7565R
Table 10
D5 D4 D3 D2 D1 D0 α
0 0 0 0 0 0 63
0 0 0 0 0 1 62
0 0 0 0 1 0 61
: :
: :
1 1 1 1 0 1 2
1 1 1 1 1 0 1
1 1 1 1 1 1 0
V0 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value)
Table 11
Register ST7565R
D2 D1 D0 (1) –0.05 %/°C
0 0 0 3.0
0 0 1 3.5
0 1 0 4.0
0 1 1 4.5
1 0 0 5.0
1 0 1 5.5
1 1 0 6.0
1 1 1 6.5
Figures 9, 10 show V0 voltage measured by values of the internal resistance ratio resistor for V0 voltage adjustment and electric
volume resister for each temperature grade model.
V0
UNIT:V Ta = 25 °C and booster off ,regulator,follower on
VDD=3V
15
14
13 111
12 110
11 101
10
100
9 011
8 010
7 001
6 000
V0 voltage regulator
5
internal resistor ratio
4
set D2,D1,D0
3
2 Electronic volume
1 registered
0 D5 ~ D0
00H 1FH 3FH
Figure 9 : (1) For ST7565R the Thermal Gradient = -0.05%/°C
The V0 voltage as a function of the V0 voltage regulator internal resistor ratio register and the electronic volume register.
Setup example: When selecting Ta = 25°C and V 0 = 7V for an ST7565R on which Temperature gradient = –0.05%/°C.
Using Figure 9 and the equation A-1, the following setup is enabled.
At this time, the variable range and the notch width of the V0 voltage is, as shown Table 13, as dependent on the electronic
volume.
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ST7565R
Table 12
Register
Contents
D5 D4 D3 D2 D1 D0
For V0 voltage regulator — — — 0 1 0
Electronic Volume 1 0 0 1 0 1
Table 13
V0 Min Typ Max Units
Variable Range 5.1 (63 levels) 7.0 (central value) 8.4 (0 level) [V]
Notch width 51 [mV]
(B) When an External Resistance is Used (The V0 Voltage Regulator Internal Resistors Are Not Used) (1)
The liquid crystal power supply voltage V0 can also be set by controlling the liquid crystal power supply voltage V0
without using the V0 voltage regulator internal resistors (IRS through commands.
terminal = “L”) by adding resistors Ra’ and Rb’ between VDD In the range where | V0 | < | VOUT |, the V0 voltage can be
and VR, and between VR and V0, respectively. When this is calculated using equation B-1 based on the external
done, the use of the electronic volume function makes it resistances Ra’ and Rb’.
possible to adjust the brightness of the liquid crystal display
( Rb'
V0 = 1 +
Ra' )
V EV
Rb' α
=( 1 +
Ra' ) ( 162 )
1- V REG
α
[∵ V = ( 1 - 162
EV ) V ] REG
VSS
VEV(fixed voltage power supply+electronic volume)

External
resistor Ra'
V0
External
resistor Rb'
Figure 11
Setup example: When selecting Ta = 25°C and V 0 = 7 V for Moreover, when the value of the current running through
ST7565R the temperature gradient = –0.05%/°C. Ra’ and Rb’ is set to 5 uA,
When the central value of the electron volume register is Ra’ + Rb’ = 1.4MΩ (Equation B-3)
(D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and Consequently, by equations B-2 and B-3,
VREG = 2.1V so, according to equation B-1, Rb'
= 3.12
Ra'
α
( Rb'
V0 = 1 +
Ra' ) (
1-
162 )
VREG Ra' = 340kΩ
Rb' 31
7V = ( 1 +
Ra' ) ( 162 )
1- (2.1) Rb' = 1060kΩ
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ST7565R
At this time, the V0 voltage variable range and notch width, based on the electron volume function, is as given in Table 14.
Table 14
Notch width 52 [mV]
(C) When External Resistors are Used (The V0 Voltage Regulator Internal Resistors Are Not Used) (2)
W hen the external resistor described above are used, crystal display brightness.
adding a variable resistor as well makes it possible to In the range where | V0 | < | VOUT | the V0 voltage can be
perform fine adjustments on Ra’ and Rb’, to set the liquid calculated by equation C-1 below based on the R1 and R2
crystal drive voltage V0. In this case, the use of the electronic (vari a bl e re s is tor) and R 3 settings, where R 2 can
volume function makes it possible to control the liquid crystal be subjected to fine adjustments (Δ R2).
power supply voltage V0 by commands to adjust the liquid
ΔR2
( R3+R2-
V0 = 1 +
R1+ΔR2 )
V EV
R3+R2-ΔR2 α
=( 1 +
R1+ΔR2 ) ( 162 )
1- VREG
α
[∵ V = ( 1 - 162
EV ) V ] REG
VSS
VEV(fixed voltage power supply+electronic volume)

Ra' External
resistor R1
ΔR2 V0
External
resistor R2
VR
External
Rb' resistor R3
Figure 12
Setup example: When selecting Ta = 25°C and V 0= 5 to 9 V R1 + R2 + R3 = 1.4MΩ (Equation C-4)

(using R2) for an ST7565R the temperature gradient With this, according to equation C-2, C-3 and C-4,
= –0.05%/°C.
When the central value for the electronic volume register is R1 = 264kΩ
set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α =
R2 = 211kΩ
31 and VREG = 2.1 V so, according to equation C-1, when Δ
R2 = 0 Ω, in order to make V0 = 9 V, R3 = 925kΩ
R3+R2 31
(
9V = 1 +
R1 ) ( 1 - 162 ) (2.1) The V0 voltage variable range and notch width based on the
electron volume function is as shown in Table 15.
When ΔR2 = R2, in order to make V = –5 V,
R3 31
(
5V = 1 +
R1+R2 ) ( 1 - 162 ) (2.1)
When the current flowing VDD and V0 is set to 5 uA,
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ST7565R
Table 15
Notch width 53 [mV]
* When the V0 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the
voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands.
Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF.
* The VR terminal is enabled only when the V0 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”).
When the V0 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal is left open.
* Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables,
etc. to handle noise.
The LCD Voltage Generator Circuit

The V0 voltage is produced by a resistive voltage divider when the voltage follower changes the impedance, it
within the IC, and can be produced at the V1, V2, V3, and V4 provides V1, V2, V3 and V4 to the liquid crystal drive circuit.
voltage levels required for liquid crystal driving. Moreover,
High Power Mode

The power supply circuit equipped in the ST7565R chips has SITRONIX recommends that the display be checked on
very low power consumption (normal mode: HPM = “H”). actual equipment to determine whether or not to use this
However, for LCD panels with large loads (size), this mode. Moreover, if the improvement to the display is
low-power power supply may cause display quality to inadequate even after high power mode has been set, then it
degrade. When this occurs, set the HPM terminal to “L” is necessary to add a liquid crystal drive power supply
(high power mode) can improve the display quality. externally.
The Internal Power Supply Shutdown Command Sequence

The sequence shown in Figure 13 is recommended for the internal power supply OFF. The power consumption can
shutting down the internal power supply, first placing the be reduced by this sequence. Please refer to the “Sleep
internal power supply in power saver mode and then turning Mode Set” section for the detailed power saving information.
Sequence Details Command address

(Command, status) D7 D6 D5 D4 D3 D2 D1 D0
Step1 Display OFF 1 0 1 0 1 1 1 0 Power saver
Step2 Display all points ON 1 0 1 0 0 1 0 1 commands
End Internal power supply OFF (compound)
Figure 13
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ST7565R
Reference Circuit Examples
1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit
(1) When the voltage regulator internal resistor (2) When the voltage regulator internal resistor
is used. is not used.
(Example where VDD2 = VDD, with 4x step-up) (Example where VDD2 = VDD, with 4x step-up)
VDD VSS VDD
IRS M/S IRS M/S

VDD2 or VSS C1 VDD2 or VSS C1
VOUT VOUT
CAP3P CAP4P CAP3P CAP4P

C1 C1
CAP1N CAP5P CAP1N CAP5P
C1 C1
CAP1P CAP1P
CAP2N CAP2N
C1 C1
CAP2P CAP2P
ST7565R
ST7565R
VSS VSS
R2
VR VR
R1
R3
C2 C2
V0 V0
C2 C2
V1 V1
C2 C2
V2 V2
C2 C2
V3 V3
C2 C2
V4 V4
2. When the voltage regulator circuit and V/F circuit alone are used
(1) W hen the V 0 voltage regulator internal resistor (2) W hen the V 0 voltage regulator internal resistor
is not used. is used.
VSS VDD VDD
IRS M/S IRS M/S

VOUT VOUT
External External
power power
CAP3P CAP4P CAP3P CAP4P
supply supply
CAP1N CAP5P CAP1N CAP5P
CAP1P CAP1P
CAP2N CAP2N
CAP2P CAP2P
ST7565R
ST7565R
VSS VSS
R2
VR VR
R1
R3
C2 C2
V0 V0
C2 C2
V1 V1
C2 C2
V2 V2
C2 C2
V3 V3
C2 C2
V4 V4
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ST7565R
(3) When the V/F circuit alone is used (4) When the built-in power is not used
VDD VDD
IRS M/S IRS M/S
VDD2 or VSS VSS VSS

VDD2 or VSS
VOUT VOUT
CAP3P CAP4P
CAP3P CAP4P
CAP1N CAP5P
CAP1N CAP5P
CAP1P
CAP1P
CAP2N
CAP2N
CAP2P
CAP2P
ST7565R
ST7565R
VSS VSS
External
power VR VR
supply
C2
V0 V0
C2
V1 V1
C2
V2 External power supply V2
C2
V3 V3
C2
V4 VDD2 or VSS V4
VDD2 or VSS
VDD2 or VSS
Item Set value unit

C1 1 ~ 2.2 uF
C2 0.1 ~ 1 uF
Note:
C1 ~ C2 are determined by the size of the LCD being driven.
The recommended panel size is smaller than 1.8”.
If the panel loading is too heavy and cause poor display quality, adding V0 capacitor can improve display quality.
* 1. Because the VR terminal input impedance is high, use short leads and shielded lines.
* 2. C1 ~ C2 are determined by the LCD loading (size). Select a suitable value that matches the module.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting the capacitor that
stabilizes the liquid crystal drive voltages (V0 to V4). Note that all C2 capacitors must have the same capacitance value.
• Next, remove external VOUT and turn all internal power supplies ON and then select C1.
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ST7565R
The Reset Circuit
When the /RES input comes to the “L” level, these LSIs
return to the default state. Their default states are as follows:
1. Display OFF
2. Normal display On the other hand, when the reset command is used, the
3. ADC select: Normal (ADC command D0 = “L”) above default settings from 11 to 17 are only executed.
4. Power control register: (D2, D1, D0) = (0, 0, 0) When the power is turned on, the IC internal state becomes
5. 4-line SPI interface internal register data clear unstable, and it is necessary to initialize it using the /RES
6. LCD power supply bias rate: terminal. After the initialization, each input terminal should
1/65 DUTY = 1/9 bias be controlled normally.
1/49,1/55,1/53 DUTY = 1/8 bias Moreover, when the control signal from the MPU is in the
1/33 DUTY = 1/6 bias high impedance, an over current may flow to the IC. After
7. Power saving clear applying a current, it is necessary to take proper measures
8. V 0 voltage regulator internal resistors Ra and Rb to prevent the input terminal from getting into the high
separation impedance state.
9 . O utp u t c o nd it io ns o f SE G a nd CO M terminals If the internal liquid crystal power supply circuit is not used
SEG=VSS, COM=VSS on ST7565R,it is necessary that /RES is “H” when the
10. Read modify write OFF external liquid crystal power supply is turned on. This IC has
11. Display start line set to first line the function to discharge V0 when /RES is “L,” and the
12. Column address set to Address 0 external power supply short-circuits to Vss when /RES is “L.”
13. Page address set to Page 0 This means that an internal resistor is connected between
14. Common output status normal VSS and V0.
15. V0 voltage regulator internal resistor ratio set mode clear While /RES is “L,” the oscillator works but the display timing
16. Electronic volume register set mode clear Electronic generator stops, and the CL, FR and /DOF terminals are
volume register : fixed to “H.” The terminals D0 to D7 are not affected. The
(D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0,0) VSS level is output to the SEG and COM output terminals
17. Test mode clear after a successful hardware reset.
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ST7565R
Commands
The ST7565R identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and
execution does not depend on the external clock, but rather is performed through internal timing only, and
thus the processing is fast enough that normally a busy check is not required.
In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low
pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H”
signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the
command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than
the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display
data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU
interface as the example.
When the 4-line SPI interface is selected, the data is input in sequence starting with D7.
<Explanation of Commands>
Display ON/OFF
This command turns the display ON and OFF.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0 Setting
A0 /RD /WR
0 1 0 1 0 1 0 1 1 11 Display ON
0 Display OFF
When the display OFF command is executed when in the display all points ON mode, Sleep mode is entered. See the
section on the Sleep Mode Set for details.
Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details
see the explanation of this function in “The Line Address Circuit”.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0 Line address
A0 /RD /WR
0 1 0 0 1 0 0 0 0 0 0 0
0 0 0 0 0 1 1
0 0 0 0 1 0 2
↓ ↓
1 1 1 1 1 0 62
1 1 1 1 1 1 63
Page Address Set

This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM
(see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM.
Changing the page address does not accompany a change in the status display.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0 Page address
A0 /RD /WR
0 1 0 1 0 1 1 0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
↓ ↓
0 1 1 1 7
1 0 0 0 8
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ST7565R
Column Address Set
This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two
sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM
is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write
to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See
the function explanation in “The Column Address Circuit,” for details.
E R/W Column
D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0
A0 /RD /WR address
High bits → 0 1 0 0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0 0
Low bits → 0 A3 A2 A1 A0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 2
↓ ↓
1 0 0 0 0 0 1 0 130
1 0 0 0 0 0 1 1 131
Status Read
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0
BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process.
BUSY BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check for
BUSY conditions.
This shows the relationship between the column address and the segment driver.
ADC 0: Reverse (column address 131-n ↔ SEG n)
1: Normal (column address n ↔ SEG n)
(The ADC command switches the polarity.)
ON/OFF: indicates the display ON/OFF state.
ON/OFF 0: Display ON
1: Display OFF
(This display ON/OFF command switches the polarity.)
This indicates that the chip is in the process of initialization either because of a /RES signal or because of a reset
command.
RESET 0: Operating state
1: Reset in progress
Display Data Write

This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically
incremented by “1” after the write, the MPU can write the display data.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
1 1 0 Write data
Display Data Read

This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically
incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately
after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the
internal registers. When the 4-line SPI interface is used, reading of the display data becomes unavailable.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
1 0 1 Read data
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ST7565R
ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence between the display RAM data column address and the segment driver output.
Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit for the
detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done
according to the column address indicated in Figure 4.
E R/W
A0 /RD /WR
1 0 1 0 0 0 0 0 Normal
0 1 0
1 Reverse
Display Normal/Reverse
This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done
the display data RAM contents are maintained.
E R/W
A0 /RD /WR
0 1 0 1 0 1 0 0 1 1 0 RAM Data “H”
LCD ON voltage (normal)
1 RAM Data “L”
LCD ON voltage (reverse)
Display All Points ON/OFF

This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents
of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse
command.
E R/W
A0 /RD /WR
1 0 1 0 0 1 0 0 Normal display mode
0 1 0
1 Display all points ON
When the display is in an OFF mode, executing the display all points ON command will place the display in sleep mode.
For details, see the Sleep Mode Set section.
LCD Bias Set

This command selects the voltage bias ratio required for the liquid crystal display.
E R/W Select Status

D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty
1 0 1 0 0 0 1 0 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias
0 1 0
1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias
Read-Modify-Write
This command is used paired with the “END” command. Once this command has been input, the display data read command
does not change the column address, but only the display data write command increments (+1) the column address. This
mode is maintained until the END command is input. When the END command is input, the column address returns to the
address it was at when the Read-Modify-Write command was entered. This function makes it possible to reduce the load on
the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 1 0 1 1 1 0 0 0 0 0
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Ver 1.7c 43/72 2009/09/14
ST7565R
Read-Modify-Write
Page Address Set
Column Address Set
Read-Modify-Write Cycle
Dummy Read
Data Read
No
Modify Data
Data Write (at same Address)
Finished?
Yes
Done
Figure 24 Command Sequence For read modify write
Return
Column address N N+1 N+2 N+3 N+m N
Read-modify-write mode set End

Figure 25
End
This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode
was entered.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 1 0 1 1 1 0 1 1 1 0
Reset
This command initializes the display start line, the column address, the page address, the common output mode, the V0 voltage
regulator internal resistor ratio, the electronic volume, and the read/modify/write mode and test mode are released. There is no
impact on the display data RAM. See the function explanation in “Reset” for details.
The reset operation is performed after the reset command is entered.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 1 0 1 1 1 0 0 0 1 0
The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset
command must not be used instead.
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ST7565R
Common Output Mode Select
This command can select the scan direction of the COM output terminal. For details, see the function explanation in
“Common Output Mode Select Circuit.”
E R/W Selected Mode

D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty
1 1 0 0 0 * * * Normal COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0→COM51
0 1 0 Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0
1
* Disabled bit
Power Controller Set

This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details
E R/W
D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode
A0 /RD /WR
0 0 1 0 1 0 Booster circuit: OFF
1 Booster circuit: ON
0 Voltage regulator circuit: OFF
0 1 0
1 Voltage regulator circuit: ON
0 Voltage follower circuit: OFF
1 Voltage follower circuit: ON
V0 Voltage Regulator Internal Resistor Ratio Set

This command sets the V0 voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage
Regulator circuit " and table 11 .
E R/W
D7 D6 D5 D4 D3 D2 D1 D0 Rb/Ra Ratio
A0 /RD /WR
0 0 1 0 0 0 0 0 Small
0 0 1
0 1 0
0 1 0
↓ ↓
1 1 1
1 1 1 Large
The Electronic Volume (Double Byte Command)

This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V0
through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte
command used as a pair with the electronic volume mode set command and the electronic volume register set
command, and both commands must be issued one after the other.
The Electronic Volume Mode Set

When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume
mode has been set, no other command except for the electronic volume register command can be used. Once the electronic
volume register set command has been used to set data into the register, then the electronic volume mode is released.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 1 0 1 0 0 0 0 0 0 1
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ST7565R
Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V0 assumes one
of the 64 voltage levels.
When this command is input, the electronic volume mode is released after the electronic volume register has been set.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0 | V0 |
A0 /RD /WR
* * 0 0 0 0 0 1 Small
* * 0 0 0 0 1 0
* * 0 0 0 0 1 1
0 1 0
↓ ↓
* * 1 1 1 1 1 0
* * 1 1 1 1 1 1 Large
* Inactive bit (set “0”)
When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0)
The Electronic Volume Register Set Sequence
Figure 26
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ST7565R
Sleep Mode Set (Double Byte Command)
This command is a two byte command used as a pair with preceding command and following command, and both commans
must issued one after the other.
This command stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the
consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows:
1. The oscillator circuit and the LCD power supply circuit are halted.
2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VSS level.
E R/W
A0 D7 D6 D5 D4 D3 D2 D1 D0 Status
/RD /WR
1 0 1 0 1 1 0 0 Sleep Mode
Preceding Command
0 1 0 1 Normal Mode
Following Command * * * * * * 0 0
* Disabled bit (set “0”)
Figure 27
In the sleep mode, the MPU is still able to access the display data RAM.
Refer to figure 28 for sleep mode sequence.
Normal Mode
Sleep Mode Setting (Sleep Mode)
Display OFF
Display all points ON
Sleep Mode
Display all points OFF
Sleep Mode Setting (Normal Mode)
Normal Mode
(Exit Sleep Mode)
Figure 28
Ver 1.7c 47/72 2009/09/14

ST7565R
The Booster Ratio (Double Byte Command)
This command makes it possible to select step-up ratio. It is used when the power control set have turn on the internal booster
circuit. This command is a two byte command used as a pair with the booster ratio select mode set command and the booster
ratio register set command, and both commands must be issued one after the other.
Booster Ratio Select Mode Set
When this command is input, the Booster ratio register set command becomes enabled. Once the booster ratio select mode
has been set, no other command except for the booster ratio register command can be used. Once the booster ratio register
set command has been used to set data into the register, then the booster ratio select mode is released.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 1 0 1 1 1 1 1 0 0 0
Booset Ratio Register Set

By using this command to set two bits of data to the booster ratio register, it can be select what kind of the booster ratio can be
used.
When this command is input, the booster ratio select mode is released after the booster ratio register has been set.
E R/W Booster
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR ratio select
* * * * * * 0 0 2x,3x,4x
0 1 0 * * * * * * 0 1 5x
* * * * * * 1 1 6x
* Inactive bit (set “0”)
When the booster ratio select function is not used, set this to (0, 0) 2x,3x,4x step-up mode
The booster ratio Register Set Sequence
Booster Ratio Set
Booster Ratio Select Mode

Set
Booster Ratio Register Set
No
Set Complete?
Yes
Done
Figure 29
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ST7565R
NOP
Non-Operation Command
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 1 0 1 1 1 0 0 0 1 1
Test
This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by
applying a “L” signal to the /RES input by the reset command or by using an NOP.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
A0 /RD /WR
0 1 0 1 1 1 1 1 1 * *
* Inactive bit
Note: The ST7565R maintain their operating modes until something happens to change them. Consequently, excessive
external noise, etc., can change the internal modes of the ST7565R . Thus in the packaging and system design it is
necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is
recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated
noise.
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ST7565R
Table 16: Table of ST7565R Commands (Note) *: ignored data
Command Code
Command Function
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 1 1 1 0 LCD display ON/OFF
(1) Display ON/OFF 0 1 0
1 0: OFF, 1: ON
Sets the display RAM display start line
(2) Display start line set 0 1 0 0 1 Display start address
address
(3) Page address set 0 1 0 1 0 1 1 Page address Sets the display RAM page address
(4) Column address set Most significant Sets the most significant 4 bits of the display
0 0 0 1
upper bit column address RAM column address.
0 1 0
Column address set Least significant Sets the least significant 4 bits of the display
0 0 0 0
lower bit column address RAM column address.
(5) Status read 0 0 1 Status 0 0 0 0 Reads the status data
(6) Display data write 1 1 0 Write data Writes to the display RAM
(7) Display data read 1 0 1 Read data Reads from the display RAM
1 0 1 0 0 0 0 0 Sets the display RAM address SEG output
(8) ADC select 0 1 0 correspondence
1 0: normal, 1: reverse
(9) Display normal/ 1 0 1 0 0 1 1 0 Sets the LCD display normal/ reverse
0 1 0
reverse 1 0: normal, 1: reverse
1 0 1 0 0 1 0 0 Display all points
(10) Display all points
0 1 0 0: normal display
ON/OFF 1 1: all points ON
1 0 1 0 0 0 1 0 Sets the LCD drive voltage bias ratio
(11) LCD bias set 0 1 0
1 0: 1/9 bias, 1: 1/7 bias (ST7565R)
Column address increment
(12) Read-modify-write 0 1 0 1 1 1 0 0 0 0 0 At write: +1
At read: 0
(13) End 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write
(14) Reset 0 1 0 1 1 1 0 0 0 1 0 Internal reset
1 1 0 0 0 * * * Select COM output scan direction
(15) Common output
0 1 0 0: normal direction
mode select 1 1: reverse direction
Operating
(16) Power control set 0 1 0 0 0 1 0 1 Select internal power supply operating mode
mode
(17) V0 voltage
regulator internal 0 1 0 0 0 1 0 0 Resistor ratio Select internal resistor ratio(Rb/Ra) mode
resistor ratio set
(18) Electronic volume
1 0 0 0 0 0 0 1
mode set Set the V0 output voltage
0 1 0
Electronic volume electronic volume register
0 0 Electronic volume value
register set
1 0 1 0 1 1 0 0 0: Sleep mode, 1: Normal mode
(19) Sleep mode set 0 1 0 1
* * * * * * 0 0
select booster ratio
1 1 1 1 1 0 0 0
00: 2x,3x,4x
(20) Booster ratio set 0 1 0
step-up 01: 5x
0 0 0 0 0 0
value 11: 6x
(21) NOP 0 1 0 1 1 1 0 0 0 1 1 Command for non-operation
Command for IC test. Do not
(22) Test 0 1 0 1 1 1 1 * * * *
use this command
Ver 1.7c 50/72 2009/09/14

ST7565R
Command Description
Instruction Setup: Reference
(1) Initialization
Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM
pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing
capacitor connecting between the LCD driving voltage output pins (V0 ~ V4) and the VSS pin, the picture on the display may
become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the
following flow when turning on the power.
1. When the built-in power is being used immediately after turning on the power:
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.

*1: Description of functions; Resetting circuit
*2: Command description; LCD bias setting
*3: Command description; ADC selection
*4: Command description; Common output state selection
*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of
the V0 voltage
*6: Description of functions; Power circuit & Command description; Electronic volume control
*7: Description of functions; Power circuit & Command description; Power control setting
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ST7565R
2. When the built-in power is not being used immediately after turning on the power:
* The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing
capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment.
Notes: Refer to respective sections or paragraphs listed below.

*1: Description of functions; Resetting circuit
*2: Command description; LCD bias setting
*3: Command description; ADC selection
*4: Command description; Common output state selection
*5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V0
voltage
*6: Description of functions; Power circuit & Command description; Electronic volume control
*7: Description of functions; Power circuit & Command description; Power control setting
*8: Command description; Sleep mode (multiple commands)
Ver 1.7c 52/72 2009/09/14

ST7565R
(2) Data Display
Write Display Data (After Initialized)
Function setup by command

(user setting)
(2) Display Start Line Set ...* 9
(3) Page Address Set ...* 10
(4) Column Address Set ...* 11
Data setup by Data Write

(6) Display Data Write ...* 12
Function setup by command

(user setting)
(1) Display ON/ OFF ...* 13
End of Write Display Data
Notes: Reference items

*9: Command Description; Display start line set
*10: Command Description; Page address set
*11: Command Description; Column address set
*12: Command Description; Display data write
*13: Command Description; Display ON/OFF
Avoid displaying all the data at the data display start (when the display is ON) in white.
(3) Power OFF *14
Notes: Reference items

*14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply VSS –V0. So, if the
power supply VDD - VSS is cut off when the LCD power supply VSS –V0 has still any residual voltage, the driver
(COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic
procedures:
• After turning off the internal power supply, make sure that the potential V0 ~ V4 has become below the threshold
voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS). 6. Description of Function, 6.7
Power Circuit
*15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power
supply VDD - VSS is turned off. 7. Command Description (19) Sleep Mode Set
*16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply
VDD - VSS is turned off. 7. Command Description (19) Sleep Mode Set
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ST7565R
Refresh
It is recommended to turn on the refresh sequence regularly at a specified interval.
Precautions on Turning off the power

<Turning the power (VDD - VSS) off>
1) Power Save (The LCD powers (V0 - VSS) are off.) → Reset input → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of
V0 ~ V4) and the driver’s discharging capacity.
Reset Power Off

Power
save
tL
VDD
1.8V
RES
Since the power (VDD-VSS) is cut off,

SEG the output comes not to be fixed.
VSS
COM
VSS
VOUT
V0
V1
Above Vth of the LCD Panel.
V2
V3
Under Vth of the LCD Panel.
V4
Depends on the LCD Module
characteristic (around 0.2~1V).
tH
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ST7565R
<Turning the power (VDD - VSS) off : When command control is not possible.>
2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF
• Observe tL > tH.
• When tL < tH, an irregular display may occur.
For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method.
tH is determined according to the external capacity C2 (smoothing capacity of V0 to V4) and the driver’s discharging capacity.
Reset Power Off
tL
VDD 1.8V
RES
Since the power (VDD-VSS) is cut

SEG off,the output comes not be fixed.
VSS
COM
VSS
VOUT
V0
V1
Above Vth of the LCD Panel.
V2
V3
Under Vth of the LCD Panel.
V4
Depends on the LCD Module
characteristic (around 0.2~1V).
tH
<Reference Data>
V0 voltage falling (discharge) time (tH) after the process of operation → power save → reset.
V0 voltage falling (discharge) time (tH) after the process of operation → reset.
100
VDD-VSS(V)
V0 voltage falling time (mSec)
1.8
2.4
50
3.0
4.0
5.0
0 0.5 1.0
C2 : V0 to V4 capacity (uF)
Figure 31
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ST7565R
Absolute Maximum Ratings
Unless otherwise noted, Vss = 0V
Table 17
Parameter Symbol Conditions Unit
Power Supply Voltage VDD -0.3 ~ 3.6 V
Power supply voltage (VDD standard) VDD2 -0.3 ~ 3.6 V
Power supply voltage (VDD standard) V0, VOUT -0.3 ~ 13.5 V
Power supply voltage (VDD standard) V1, V2, V3, V4 -0.3 to V0 V
Operating temperature TOPR –30 to +85 °C
Storage temperature Bare chip TSTR –65 to +150 °C
V0
V1 to V4
VDD VDD
VSS VSS VSS
System (MPU) side ST7565R chip side
Figure 30
Notes and Cautions

1. The VDD2, V0 to V4 and VOUT are relative to the VSS = 0V reference.
2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUT ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4.
3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is
recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI
outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI
reliability as well.
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ST7565R
DC Characteristics
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V, Ta = –30 to 85°C
Table 18
Rating Applicable
Item Symbol Condition Units
Min. Typ. Max. Pin
Operating Voltage (1) VDD 2.4 — 3.3 V VDD*1
Operating Voltage (2) VDD2 (Relative to VSS) 2.4 — 3.3 V VDD
High-level Input Voltage VIHC 0.8 x VDD — VDD V *3
Low-level Input Voltage VILC VSS — 0.2 x VDD V *3
High-level Output Voltage VOHC IOH = –0.5 mA 0.8 x VDD — VDD V *4
Low-level Output Voltage VOLC IOL = 0.5 mA VSS — 0.2 x VDD V *4
Input leakage current ILI VIN = VDD or VSS –1.0 — 1.0 µA *5
Output leakage current ILO VIN = VDD or VSS –3.0 — 3.0 µA *6

Ta = 25°C V0 = 13.0 V — 2.0 3.5
Liquid Crystal Driver ON SEGn
RON (Relative KΩ
Resistance V0 = 8.0 V — 3.2 5.4 COMn *7
to VSS)
Static Consumption Current ISSQ — 0.01 2 µA VDD, VDD2
V0 = 13.0 V
(Relative To VSS)
Output Leakage Current I0Q — 0.01 10 µA V0
Input Terminal Capacitance CIN Ta = 25°C, f = 1 MHz — 5.0 8.0 pF

Internal
fOSC 17 20 24 kHz *8
Oscillator 1/65 duty
Ta = 25°C
External 1/33 duty
fCL 17 20 24 kHz CL
Oscillator Input
Frequency Internal
fOSC 1/49 duty 25 30 35 kHz *8
Oscillator
1/53 duty Ta = 25°C
External
fCL 1/55 duty 25 30 35 kHz CL
Input
Table 19
Rating Applicable
Item Symbol Condition Units
Min. Typ. Max. Pin
Input voltage VDD2 (Relative To VSS) 2.4 — 3.3 V VDD
Supply Step-up output
VOUT (Relative To VSS) — — 13.5 V VOUT
voltage Circuit
Internal Power
Voltage regulator
Circuit Operating VOUT (Relative To VSS) 6.0 — 13.5 V VOUT
Voltage
Voltage Follower
Circuit Operating V0 (Relative To VSS) 4.0 — 13.5 V V0 * 9
Voltage
Ta = 25°C, (Relative To V SS)
Base Voltage VRS 2.07 2.10 2.13 V *10
–0.05%/°C
Ver 1.7c 57/72 2009/09/14

ST7565R
• Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs
when an external power supply is used .
Table 20
Rating
Test pattern Symbol Condition Units Notes
Min. Typ. Max.
Display Pattern VDD = 3.0 V,
OFF
IDD
V0 – VSS = 11.0 V
— 16 27 µA *11
Display Pattern VDD = 3.0 V,

Checker
IDD
V0 – VSS = 11.0 V
— 19 32 µA *11
• Dynamic Consumption Current : During Display, with the Internal Power Supply ON
Table 21
Rating
Test pattern Symbol Condition Units Notes
Min. Typ. Max.
VDD = 3.0 V, Normal Mode — 90 130
Display
Pattern OFF
IDD Quad step-up voltage. µA *12
V0 – VSS = 11.0 V High-Power Mode — 128 193
Display VDD = 3.0 V, Normal Mode — 100 147

Pattern IDD Quad step-up voltage. µA *12
Checker V0 – VSS = 11.0 V High-Power Mode — 135 205
• Consumption Current at Time of Power Saver Mode : VDD = 3.0 V

Table 22
Rating
Item Symbol Condition Units Notes
Min. Typ. Max.
Sleep mode IDD Ta = 25°C — 0.1 4 µA
• The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate
Frequency fFR
Table 23
Item fCL fFR
Used internal oscillator circuit fOSC / 4 fOSC / (4*65)

1/65 DUTY
Used external display clock External input (fCL) fCL / 260

1/49 DUTY

1/33 DUTY

1/55 DUTY

1/53 DUTY
(fFR is the liquid crystal alternating current period, and not the FR signal period.)
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ST7565R
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
*2 The operating voltage range for the VSS system and the V0 system is. This applies when the external power supply is
being used.
*3 The A0, D0 to D5, D6 (SCL), D7 (SI), /RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, C86, P/S, /DOF, /RES, IRS, and /HPM
terminals.
*4 The D0 to D7, FR, /DOF, and CL terminals.
*5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, C86, P/S, /RES, IRS, and /HPM terminals.
*6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state.
*7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V1, V 2, V 3, and V4). These are specified for the operating voltage (3) range.
RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.)
*8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency.
*9 The V0 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
*10 This is the internal voltage reference supply for the V0 voltage regulator circuit. In the ST7565R, the temperature range
approximately –0.05%/°C.
*11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
The ST7565R is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity.
Applicable only when there is no access from the MPU.
*12 It is the value on a ST7565R having the VREG temperature gradient is –0.05%/°C when the V 0 voltage regulator
internal resistor is used.
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ST7565R
Timing Characteristics
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8 tAH8
CS1
(CS2="1")
tCYC8
tCCLR,tCCLW
WR,RD
tCCHR,tCCHW
tDH8
tDS8
D0 to D7
(Write)
tACC8 tOH8
D0 to D7
(Read)
Figure 37
Table 24
(VDD = 3.3V, Ta = –30 to 85°C)
Rating
Item Signal Symbol Condition Units
Min. Max.
Address hold time tAH8 0 —
Address setup time A0 tAW8 0 —
System cycle time tCYC8 240 —
Enable L pulse width (WRITE) tCCLW 80 —
WR
Enable H pulse width (WRITE) tCCHW 80 —
Enable L pulse width (READ) tCCLR 140 — Ns
RD
Enable H pulse width (READ) tCCHR 80
WRITE Data setup time tDS8 40 —
WRITE Address hold time tDH8 0 —
D0 to D7
READ access time tACC8 CL = 100 pF — 70
READ Output disable time tOH8 CL = 100 pF 5 50
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ST7565R
Table 25
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Min. Max.
Enable L pulse width (WRITE) tCCLW 220 —
WR
Enable H pulse width (WRITE) tCCHW 180 —
Enable L pulse width (READ) tCCLR 220 — ns
RD
Enable H pulse width (READ) tCCHR 180 —
D0 to D7
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW ) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.
Ver 1.7c 61/72 2009/09/14

ST7565R
System Bus Read/Write Characteristics 2 (For the 6800 Series MPU)
A0
R/W
tAW6 tAH6
CS1
(CS2="1")
tCYC6
tewLR,tewLW
E
tewHR,tewHW
tDH6
tDS6
D0 to D7
(Write)
tACC6 tOH6
D0 to D7
(Read)
Figure 38
Table 26
(VDD = 3.3V,Ta = –30 to 85°C)
Rating
Min. Max.
Enable L pulse width (WRITE) tEWLW 80 —
WR
Enable H pulse width (WRITE) tEWHW 80 —
Enable L pulse width (READ) tEWLR 80 — ns
RD
Enable H pulse width (READ) tEWHR 140
D0 to D7
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ST7565R
Table 27
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Min. Max.
Enable L pulse width (WRITE) tEWLW 220 —
WR
Enable H pulse width (WRITE) tEWHW 180 —
Enable L pulse width (READ) tEWLR 220 — ns
RD
Enable H pulse width (READ) tEWHR 180 —
D0 to D7
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW ) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.
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ST7565R
The 4-line SPI Interface
tCCSS tCSH
CS1
(CS2="1")
tSAS tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS tSDH
SI
Figure 39
Table 28
(VDD = 3.3V,Ta = –30 to 85°C)
Rating
Min. Max.
4-line SPI Clock Period Tscyc 50 —
SCL “H” pulse width SCL Tshw 25 —
SCL “L” pulse width TSLW 25 —
Address setup time TSAS 20 —
A0
Address hold time Tsah 10 — ns
Data setup time Tsds 20 —
SI
Data hold time TSDH 10 —
CS-SCL time Tcss 20 —
CS
CS-SCL time Tcsh 40 —
Table 29
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Min. Max.
4-line SPI Clock Period Tscyc 100 —
SCL “H” pulse width SCL TSHW 50 —
SCL “L” pulse width TSLW 50 —
Address setup time TSAS 30 —
A0
Address hold time TSAH 20 — ns
Data setup time TSDS 30 —
SI
Data hold time TSDH 20 —
CS-SCL time TCSS 30 —
CS
CS-SCL time TCSH 60 —
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ST7565R
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Reset Timing
tRW
RES
tR
Internal
During reset Reset complete
status
Figure 41
Table 30
(VDD = 3.3V,Ta = –30 to 85°C)
Rating
Min. Typ. Max.
Reset time tR — — 1.0 us
Reset “L” pulse width /RES tRW 1.0 — — us
Table 31
(VDD = 2.7V,Ta = –30 to 85°C)
Rating
Min. Typ. Max.
Reset time tR — — 2.0 us
Reset “L” pulse width /RES tRW 2.0 — — us
*1 All timing is specified with 20% and 80% of VDD as the standard.
Ver 1.7c 65/72 2009/09/14

ST7565R
The MPU Interface (Reference Examples)
The ST7565R Series can be connected to either 80X86 Series MPUs or to 68000 Series MPUs. Moreover, using the 4-line SPI
interface it is possible to operate the ST7565R series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7565R Series chips. When this is done, the chip select signal can be
used to select the individual ICs to access.
(1) 8080 Series MPUs

VDD
VCC VDD
A0 A0 C86
A1 to A7 CS1
Decoder
ST7565R
IORQ CS2
MPU
DO to D7 DO to D7
RD RD
WR WR
RES RES P/S
GND VSS
RESET
VSS
Figure 42-1
(2) 6800 Series MPUs
VDD
VCC VDD
A0 A0 C86
A1 to A15 CS1
ST7565R
Decoder
VMA CS2
MPU
DO to D7 DO to D7
E E
R/W R/W
RES RES P/S
GND VSS
RESET
VSS
Figure 42-2
(3) Using the 4-line SPI Interface
VDD or VSS
VCC VDD
A0 A0 C86
CS1
ST7565R
A1 to A7 Decoder
CS2
MPU
Port 1 SI
Port 2 SCL
RES RES P/S
GND RESET VSS
VSS
Figure 42-3
Ver 1.7c 66/72 2009/09/14

ST7565R
Connections Between LCD Drivers (Reference Example)
Figure 43
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ST7565R
Application Notes
(1) 4-line interface, 4x booster, 65 duty, internal resistor, high power mode, internal oscillator
C2
C2
C2
C2
C2
C1
C1
C1
C1
Ver 1.7c 68/72 2009/09/14

ST7565R
(2) 80 interface, 3x booster, 49 duty, internal resistor, high power mode, internal oscillator
Ver 1.7c 69/72 2009/09/14

2009/09/14
68 interface, 3x booster, 55 duty, internal resistor, high power mode, internal oscillator
70/72
V V R AR C
S D
DDDDDDDD
7 65 43 21 0 E / 0S
T
S
1
S D W B
COMS1
VS SS I H PCCT V T T T T T T VV V V V V V V CC CC C CCC CC C CCCC CV V V V V V V V V V / / V RVCCV D T COM53
SE EERPS8 LED E E E E E E D D V V V V V V V V V V V V D D R R S S A A A A A A A A A A A A A A A A O O S S S S D D D D D D D D D D D D R WS A S D S S S O C F E
SL L L SMB 6 S S D S S S S S S DD R R 0 0 1 1 2 2 3 3 4 4 DD S S S S PP PP P P P P P P P P P P P PU U S S S SD DD 7 6 5 4 3 2 1 0 DDR S 0 TD 2 1 S F L RS
COM26 3 21 B T T T T T T T 2 2 44 22 2 2 11 11 3 3115 5T T 2 B T
ST7565R
7 5 4 3 2 1 0 PP NN P P P P NN P PNNP P 6
S
C E C
Ver 1.7c
C CO S G O
O OM E 1 M
M MS G 3 2
8 02 0 1 7
COM9 COM32
(3)
ST7565R
Recommend LCD Setting
Item Set value unit Item Set value unit

C1 1 ~ 2.2 uF C1 1 ~ 2.2 uF
C2 0.1~ 1 uF C2 0.1~ 1 uF
Recommend Setting: Recommend Setting 1:

VDD = VDD2 = 3.0V VDD = VDD2 = 3.0V
Booster = X3 Booster = X3
BIAS = 1/6 BIAS = 1/6
Vop = 5.5~6.7V Vop = 6.0~7.0V
Duty = 1/33 Duty = 1/49
Recommend Setting: Recommend Setting 2:

BIAS = 1/5 BIAS = 1/8
Vop = 5.0~6.1V Vop = 7.0~8.5V
Duty = 1/33 Duty = 1/49
Item Set value unit Item Set value unit

C1 1 ~ 2.2 uF C1 1 ~ 2.2 uF
C2 0.1~ 1 uF C2 0.1~ 1 uF
Recommend Setting 1: Recommend Setting:

BIAS = 1/6 BIAS = 1/7
Vop = 6.0~7.5V Vop = 7.0~8.5V
Duty = 1/55 Duty = 1/65
Recommend Setting 2:
VDD = VDD2 = 3.0V
Booster = X4
BIAS = 1/8
Vop = 7.0~8.5V
Duty = 1/55
Ver 1.7c 71/72 2009/09/14

ST7565R
Change Notes:
2005/03/24 Ver 0.1 Preliminary
2005/05/20 Ver 0.2 Bump Height
Shipping Forms
Pad Arrangement, Bump Height, Bump Pitch, Bump Height
Pad Names- remove ”:P”, “:g”, rename FUSE, VSSF as TEST
2005/08/10 Ver 0.3 Connections Between LCD Drivers
Application Notes
Unused Data Pin In 4-Line SPI Fixed To ‘H’
ITO Resister Limitation
Modify the Absolute Maximum Ratings.
Modify the operating range of VDD, VDD2, VOUT and V0.
Modify the description of features.
2005/09/29 Ver 0.4
Modify the Operating Temperature.
Modify the Ta value of DC Characteristics and Reset Timing.
Remove redundant features on Page 2.
Remove Preliminary
2005/10/20 Ver 1.0 Modify the Pad Arrangement(COG) on Page 2.
Modify the I/O PIN ITO Resister Limitation on Page 22.
2005/10/21 Ver 1.1 Modify the Operating Temperature
Unused Data Pin In 4-Line C86 Fixed To ‘H’
2005/11/07 Ver 1.2 Unused Data Pin In 4-Line /RD Fixed To ‘H’
Unused Data Pin In 4-Line /WR Fixed To ‘H’
2005/11/25 Ver 1.3 Modify the flow chart on Page 46, 47 and 49.
Modify the description of DC characteristics.
Modify function description.
Redraw figures.
2006/02/13 Ver 1.4
Redraw the PAD DIAGRAM.
Highlight the HPM (High Power Mode) description.
Put emphasis on the power OFF procedure (Page 54-55).
2006/03/10 Ver 1.5 Fix Ver. 1.4: Booster Circuit mistake (Booster X6, Page 32).
Add V0 capacitor notes.
Add application notes.
2007/04/24 Ver 1.6
Modify ITO resistance limitation.
Modify operation voltage.
Add a section for “Recommend LCD Setting”.
2007/05/14 Ver 1.6a
Modify the recommend setting of “Recommend LCD Setting”.
Remove slave function.
2007/06/01 Ver 1.7
Remove static indicator function.
2007/07/24 Ver 1.7a Modify version mark mistake.
2009/02/23 Ver 1.7b Modify mistake of Status Read.
2009/09/14 Ver 1.7c Modify the mistake of The Reset Circuit.
Ver 1.7c 72/72 2009/09/14

ST7565R

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ST

Sitronix 65 x 132 Dot Matrix LCD Controller/Driver

PART NO. VRS temperature gradient VRS range

Ver 1.7c 1/72 2009/09/14

Bump Height: 15µm

Recommend panel size is small than 1.8” (A.A.).

Ver 1.7c 2/72 2009/09/14

PAD No. PIN Name X Y PAD No. PIN Name X Y

Ver 1.7c 3/72 2009/09/14

Ver 1.7c 4/72 2009/09/14

Ver 1.7c 5/72 2009/09/14

PAD No. PIN Name X Y PAD No. PIN Name X Y

Ver 1.7c 6/72 2009/09/14

Ver 1.7c 7/72 2009/09/14

Ver 1.7c 8/72 2009/09/14

PAD No. PIN Name X Y PAD No. PIN Name X Y

Ver 1.7c 9/72 2009/09/14

Ver 1.7c 10/72 2009/09/14

Ver 1.7c 11/72 2009/09/14

PAD No. PIN Name X Y PAD No. PIN Name X Y

Ver 1.7c 12/72 2009/09/14

Ver 1.7c 13/72 2009/09/14

Ver 1.7c 14/72 2009/09/14

PAD No. PIN Name X Y PAD No. PIN Name X Y

Ver 1.7c 15/72 2009/09/14

Ver 1.7c 16/72 2009/09/14

Ver 1.7c 17/72 2009/09/14

COM output control circuit

Voltage Display data latch

Display timing generator circuit

Line address circuit

MPU INTERFACE ( Parallel and Serial )

Ver 1.7c 18/72 2009/09/14

Pin Name I/O Function No. of Pins

V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss

LCD Power Supply Pins

Pin Name I/O Function No. of Pins

Ver 1.7c 19/72 2009/09/14

Pin Name I/O Function No. of Pins

P/S Data/Command Data Read/Write 4-line SPI Clock

“L” A0 SI (D7) Write only SCL (D6)

When P/S = “L”, D0 to D5 must be fixed to “H”.

Ver 1.7c 20/72 2009/09/14

FR O This is the liquid crystal alternating current signal terminal. 1

/DOF O This is the LCD blanking control terminal. 1

Ver 1.7c 21/72 2009/09/14

Pin Name I/O Function No. of Pins

ST7565R I/O PIN ITO Resister Limitation

Ver 1.7c 22/72 2009/09/14

The MPU Interface

H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0

The Parallel Interface

H: 6800 Series /CS1 CS2 A0 E R/W D7~D0

Moreover, data bus signals are recognized by a combination

1 0 1 0 Writes the display data

0 0 1 0 Write control data (command)

Ver 1.7c 23/72 2009/09/14

The Chip Select

The Busy Flag

Ver 1.7c 24/72 2009/09/14