Bm-Atom1 0-V1 6

MiDAS Family
ATOM Family
BM-ATOM1.0-V1.6
Brief Manual of ATOM1.0 Family
4-bit Microcontrollers
with Reduced 8051 Architecture
V1.6
July 2008
CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, and other
changes to its products and services at any time.
CORERIVER shall give customers at least a three month advance notice of intended discontinuation of a product or a
service through its homepage.
Customers should obtain the latest relevant information before placing orders and should verify that such information is
current and complete.
The CORERIVER products listed in this document are intended for usage in general electronics applications. These
CORERIVER products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality
and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury.
www.coreriver.com (E-mail : tech@coreriver.com)

Contents Preliminary
1. Product Overview 7. Absolute Maximum Ratings

2. Features 8. DC Characteristics
3. Block Diagram 9. AC Characteristics
4. Pin Configurations 10. Package Dimensions
5. Pin Descriptions 11. Product Numbering System
6. Function Descriptions 12. Supporting Tools
9 CPU Descriptions
- Memory Organization
- SFR Map and Description
- Instruction Set Summary 13. Appendix
- CPU Timing
A. Instruction Set
9 Peripheral Descriptions
B. SFR Descriptions
- I/O Ports
- Clock Configuration C. Update History
- Carrier Frequency Generation
- LVD (Low Voltage Detector)
- WDT (Watchdog Timer)
- Reset Circuit
- Power Management
- IAP (In Application Programming)
ATOM1.0 Family [2]

1. Product Overview (1/2) Preliminary
ATOM1.0 Family - GC49C501 Series (Low Cost, Low Power Application MCU)
Mask-ROM FLASH EEPROM RAM Volt Freq. T/C Serial REM IR. LED I/O Available
Product WDT Package Others
(byte) (byte) (byte) (Nibble) (V) (MHz) (16bits) I/O Output Drive Tr. Pins Time
10 18 POR/LVD
GC49C501G0-SO24I - 1K (128) 64 1.8~5.5 - - 1 1 Yes 24-SOIC Ring OSC NOW
(5) (20) ISP/IAP
10 14 20-SOIC POR/LVD
GC49C501G0-SO20I - 1K (128) 64 1.8~5.5 - - 1 1 Yes Ring OSC NOW
(5) (16) (Narrow) ISP/IAP
10 14 20-SOIC POR/LVD
GC49C501G0-SJ20I - 1K (128) 64 1.8~5.5 - - 1 1 Yes Ring OSC NOW
(5) (16) (JEDEC) ISP/IAP
POR/LVD
10 18 Calibrated
GC49C501R0-SO24I - 1K (128) 64 1.8~5.5 - - 1 1 Yes 24-SOIC NOW
(5) (20) Ring OSC
ISP/IAP
POR/LVD
10 14 20-SOIC Calibrated
GC49C501R0-SO20I - 1K (128) 64 1.8~5.5 - - 1 1 Yes NOW
(5) (16) (Narrow) Ring OSC
ISP/IAP
POR/LVD
10 14 220-SOIC Calibrated
GC49C501R0-SJ20I - 1K (128) 64 1.8~5.5 - - 1 1 Yes NOW
(5) (16) (JEDEC) Ring OSC
ISP/IAP
POR/LVD
10 Calibrated
GC49C501RP-SO8I - 1K (128) 64 1.8~5.5 - - 1 - - 6 8-SOIC NOW
(5) Ring OSC
ISP/IAP
POR/LVD
10 Calibrated
GC49C501RP-SP8I - 1K (128) 64 1.8~5.5 - - 1 - - 6 8-SPDIP NOW
(5) Ring OSC
ISP/IAP
* User may use part of program area (128 bytes) as EEPROM, which can be modified by IAP function during S/W operation.
* Max. operating frequency of ATOM1.0 family is 5 MHz when VDD is less than 2.7 V.
ATOM1.0 Family [3]

1. Product Overview (2/2) Preliminary
ATOM1.0 Family - GC49C501 Series (Low Cost, Low Power Application MCU)
Mask-ROM FLASH EEPROM RAM Volt Freq. T/C Serial REM IR. LED I/O Available
Product WDT Package Others
(byte) (byte) (byte) (Nibble) (V) (MHz) (16bits) I/O Output Drive Tr. Pins Time
POR/LVD
10 18
GC41C501G0-SO24I 1K - - 64 1.8~5.5 - - 1 1 Yes 24-SOIC Ring OSC NOW
(5) (20)
POR/LVD
10 14 20-SOIC
GC41C501G0-SO20I 1K - - 64 1.8~5.5 - - 1 1 Yes Ring OSC NOW
(5) (16) (Narrow)
POR/LVD
10 14 20-SOIC
GC41C501G0-SJ20I 1K - - 64 1.8~5.5 - - 1 1 Yes Ring OSC NOW
(5) (16) (JEDEC)
POR/LVD
10
GC41C501G0-SO8I 1K - - 64 1.8~5.5 - - 1 - - 6 8-SOIC Ring OSC NOW
(5)
POR/LVD
10
GC41C501G0-SP8I 1K - - 64 1.8~5.5 - - 1 - - 6 8-SPDIP Ring OSC NOW
(5)
* User may use part of program area (128 bytes) as EEPROM, which can be modified by IAP function during S/W operation.
* Max. operating frequency of ATOM1.0 family is 5 MHz when VDD is less than 2.7 V.
ATOM1.0 Family [4]

2. Features Preliminary
CPU REM output (Remote control transmitter)

94-bit reduced 8051 architecture 9 Built-in Transistor for I.R. LED Drive
9Continuous program addressing, not paged. 9 IOL= 300 mA (Max.) at VDD = 3V and VO = 0.4V
951 instructions including push, pop and logic inst.
Carrier Pulse Generation : 7 types
9Instruction cycle : FSYS/6
9Multi-level subroutine nesting with RAM based Built-in Oscillator
stack. 9 Crystal/Ceramic resonator
9 Precision internal oscillator
On-chip Memories
Factory Calibrated to ± 3% at 2.1 ~ 3.3V
9 FLASH : 1024 bytes (including 128 EEPROM)
Factory Calibrated to ± 1% at 2.5V
9 RAM : 64 nibbles (including stack)
9 The Factory Calibration for 7.28MHz is applied
ISP (In System Programming) of FLASH only for GC49C501RX devices.
IAP (In Application Programming) of FLASH Built-in Reset
I/O Ports 9 Power-on Reset, Power-fail Reset
9 P0 : 4-bit parallel I/O (Open drain output) 9 WDT (Watch-Dog Timer) Reset
9 P1 : Parallel I/O (Open drain output), 9 Clock switching reset
4-bit for 24-pin, 2-bit for 20-pin. Power Management
9 P2, P3 : 4-bit parallel/bit-selectable I/O (Open 9 Power-down (stop) mode
drain output) 9 Release stop by input changes
9 P4 : Parallel I/O (Open drain output). 9 Sleep mode
Two bits if internal clock is used.
Additional two bits for 24-pin packages.
ATOM1.0 Family [5]

2. Features Preliminary
Power Consumption
9 Stop mode : ＜0.1uA (Typ.) at 2.0V
1 uA (Max.) at 5.0V
9 Normal mode : 400 uA (Typ.) at 2.0V, FSYS = 4 MHz
Operating frequency vs. voltage
9 Max. FOSC= 10 MHz (2.7 V ≤ VDD ≤ 5.5V)
9 Max. FOSC= 5 MHz (1.8 V ≤ VDD ＜ 2.7V)
Operating temperature : -40 °C ~ 85 °C
ESD protection up to 2,000V
Latch-up protection up to ±200mA
Package
9 24-pin SOIC
9 20-pin SOIC
9 8-pin SOIC/SPDIP
ATOM1.0 Family [6]

3. Block Diagram (24-PIN) Preliminary
Instruction RomAddr( )
10
FLASH Program
Decoder
1K Bytes Counter
(IR) RomOut( ) RomOut( )
8
8
4 4
CPU BUS(4)
4 4 4
WDT
Data Address RAM
ALU
(SPH,SPL, 64 X 4
6
(C, ACC)
POR/LVD DPH, DPL) bits
RING OSC. 4 DPL 4
VSS
REM IR LED
OSC. SFR & Ports IFF
Generation Driver TR VDD
XI/P4[0] XO/P4[1] P4[3:2] P0[3:0] P1[3:0] P2[3:0] P3[3:0] TVSS REM
ATOM1.0 Family [7]

10
FLASH Program
Decoder
1K Bytes Counter
8
8
4 4
CPU BUS(4)
4 4 4
WDT
Data Address RAM
ALU
(SPH,SPL, 64 X 4
6
(C, ACC)
POR/LVD DPH, DPL) bits
RING OSC. 4 DPL 4
VSS
REM IR LED
OSC. SFR & Ports IFF
Generation Driver TR VDD
XI/P4[0] XO/P4[1] P0[3:0] P1[1:0] P2[3:0] P3[3:0] TVSS REM
ATOM1.0 Family [8]

10
FLASH Program
Decoder
1K Bytes Counter
8
8
4 4
CPU BUS(4)
4 4 4
Data Address RAM

ALU
(SPH,SPL, 64 X 4
6
(C, ACC)
WDT DPH, DPL) bits
POR/LVD 4 DPL 4
VSS
RING OSC. SFR & Ports IFF
VDD
P0[2:0] P2[2:0]
ATOM1.0 Family [9]

4. Pin Configurations Preliminary
VSS 1 20 VDD VSS 1 24 VDD

XI / P4.0 2 19 REM XI / P4.0 2 23 REM
GC49C501G0-SO20IP
GC49C501R0-SO20IP
GC49C501G0-SJ20IP
GC49C501R0-SJ20IP
GC49C501G0-SO24IP
GC49C501R0-SO24IP
XO / P4.1 3 18 TVSS XO / P4.1 3 22 TVSS
P0.0 4 17 P2.0/SCLK P4.2 4 21 P2.0/SCLK
P0.1 5 16 P2.1/SDAT P0.0 5 20 P2.1/SDAT
P0.2 6 15 P2.2 P0.1 6 19 P2.2
P0.3 7 14 P2.3 P0.2 7 18 P2.3
P1.0 8 13 P3.0 P0.3 8 17 P4.3
P1.1 9 12 P3.1 P1.0 9 16 P3.0
P3.3 10 11 P3.2 P1.1 10 15 P3.1
P1.2 11 14 P3.2
P1.3 12 13 P3.3
[ 20-SOIC]
GC49C501G0-SO20I [ 24-SOIC]
GC49C501R0-SO20I GC49C501G0-SO24I
GC49C501G0-SJ20I GC49C501R0-SO24I
GC49C501R0-SJ20I
VDD 1 8 VSS
AT10RP
P0.0 2 7 P2.0/SCLK
P0.1 3 6 P2.1/SDAT
P0.2 4 5 P2.2
[ 8-SOIC/SPDIP]
GC49C501RP-SO8I
GC49C501RP-SP8I
ATOM1.0 Family [10]

5. Pin Description (20-pin/24-pin) Preliminary
Symbol Direction Description Remark

VDD Power Power Supply
VSS Power Ground
REM Output Output for IR LED drive Transistor. The transistor is n-channel device.
TVSS Power Ground for IR LED drive Transistor

Input to the inverting oscillator amplifier.
XI / P4[0] Input/Output If configured, P4[0] of parallel Input/Output port.
Schmitt Trigger input and open-drain output with internal pull-up TR.
Output from the inverting oscillator amplifier.
XO / P4[1] Input/Output If configured, P4[1] of parallel Input/Output port.
Parallel Input/Output port (Only for 24-pin packages)
P4[3:2] Input/Output Each bit can be individually set or cleared.
Parallel Input/Output port.
P0[3:0] Input/Output Schmitt Trigger input and open-drain output with internal pull-up TR.
The STOP mode is released by "L" input of each pin.
Parallel Input/Output port (Only for 24-pin packages)
Parallel Input/Output port. Each bit can be individually set or cleared.
P2[3:0] Input/Output
P2 can be configured as a push-pull output port.
P2[0] and P2[1] are also used for ISP of FLASH memory.
ATOM1.0 Family [11]

5. Pin Description (8-pin) Preliminary
Symbol Direction Description Remark

VDD Power Power Supply
VSS Power Ground

P2 can be configured as a push-pull output port.
P2[0] and P2[1] are also used for ISP of FLASH memory.
ATOM1.0 Family [12]

6.1. Memory Organization Preliminary
Address Space
9 Program memory : 1K Bytes.
[RAM Map]
Continuously addressed by Byte.
9 Indirect data memory : 64 Nibbles. 3FH
... Page 3
Bit accessible.
30H
9 Special function registers : 16 Registers.
2FH Stack Pointer (SP)
Directly addressed.
... Page 2 SPH SPL
9 Indirect function flags : 16 bits. 20H
Bit position is selected by DPL.
1FH DPH DPL
... Page 1 Data Pointer (DPTR)
10H
[Program Memory Map]
0FH
3FFH ... Page 0
... Internal FLASH 00H
... 1K Bytes
000H
[Special Function Register Map] [Indirect Function Flag Map]

0CH P3 CKCFG IOCFG LVCFG 15 14 13 12 11 10 9 8
08H P2 IAPCON GDL GDH STOP SLEEP WDTE WDTR MAP1 MAP0 P4.2 P4.3
04H P1 REMC SPL SPH 7 6 5 4 3 2 1 0
00H P0 P4 DPL DPH P3.3 P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 P2.0
ATOM1.0 Family [13]

6.2. SFR Brief Description Preliminary
Power-On Other
Register Address Description
Reset Value Reset Value
P0 00H Port 0 output register. 1111 1111
DPL 02H The low nibble of data pointer (DPTR). 0000 0000
DPH 03H The high nibble of data pointer (DPTR). --00 --00
REMC 05H REM output control register. 0000 0000
SPL 06H The low nibble of stack pointer (SP). 1111 1111
SPH 07H The high nibble of stack pointer (SP). --01 --01
IAP (In Application Programming) Control register.

IAPCON 09H 0000 0000
Can be accessed only if MAP1 is set and MAP0 is cleared.
GDL 0AH The low nibble of general purpose data register 0000 0000
GDH 0BH The high nibble of general purpose data register 0000 0000
P3 0CH Port 3 output register. 1111 1111
CKCFG 0DH The clock configuration register. Initialized only by power-on-reset. 0000 uuuu
IOCFG 0EH The I/O port configuration register. Initialized only by power-on-reset. 0000 uu0u
LVCFG 0FH The LVD configuration register. Initialized only by power-on-reset. 1x00 uxuu
- : Unimplemented bit. Read as 0. Note for 8-pin devices.

u: Remains unchanged. - Not supported SFRs : P1, P3, P4, REMC.
x: The value of the bit is not determined. - Writing to the not-supported SFRs may cause unexpected behavior.
ATOM1.0 Family [14]

6.2. Indirect Function Flag (IFF) Description Preliminary
Indirect Function Flag (IFF)

9 Write only, access using the instructions: MOV L, #n, SETB @L, CLR @L
9 The individual set/clear of ports is available only if the package type supports corresponding parallel port.
Flag Address (DPL) Description Reset Value

STOP 15 Enter stop mode. Not set until all pins of P0 and P1 are high. 0
SLEEP 14 Enter sleep mode. Released by WDT reset. 0
Enable flag of WDT. If this flag is cleared, WDT stops running and holds the state.
WDTE 13 This flag can be modified if and only if MAP1 bit is set and MAP0 bit is cleared. 1
This flag is also set by H/W when user sets SLEEP flag or writes IAPCON SFR.
WDTR 12 Reset Watch Dog Timer. Set by S/W. Cleared by H/W after WDT is reset. 0
MAP1 11 Address map extension bit 1 for SFR/IFF. 0
MAP0 10 Address map extension bit 0 for SFR/IFF. Do not set this flag for the future compatibility. 0
P4.2 9 Individual bit set/clear for P4 1
ATOM1.0 Family [15]

6.3. Instruction Set Summary (1/2) Preliminary
Refer to Appendix A (Instruction Set) for more details.

Type Instruction Description
ADD A, #data Add data to ACC.
INC A Increment ACC.
DEC A Decrement ACC.
ADD A, @DP Add the indirect memory nibble to ACC.
Arithmetic
ADDC A, @DP Add the indirect memory nibble to ACC with the Carry in C.
SUB A, @DP Subtract the indirect memory nibble from ACC.
INC @DP Increment the indirect memory nibble.
DEC @DP Decrement the indirect memory nibble.
CLR A Clear ACC.

CPL A Complement ACC.
RRC A Rotate right ACC with Carry flag.
Logical
ANL A, @DP Logical AND for ACC and the indirect memory nibble.
ORL A, @DP Logical OR for ACC and the indirect memory nibble.
XRL A, @DP Logical Exclusive-OR for ACC and the indirect memory nibble.
MOV dir, A Move ACC to the special function register.

MOV A, dir Move the special function register to ACC.
MOV A, @DP Move the indirect memory nibble to ACC.
MOV A, #data Move data to ACC.
MOV L, @DP Move the indirect memory nibble to DPL.
MOV @DP, A Move ACC to the indirect memory nibble.
MOVI @DP, A Move ACC to the indirect memory nibble and increment the data pointer (DPH,DPL).
Data Transfer
MOVD @DP, A Move ACC to the indirect memory nibble and decrement the data pointer (DPH,DPL).
XCH A, @DP Exchange ACC and the indirect memory nibble.
MOVI @DP, #data Move data to the indirect memory nibble and increment the data pointer (DPH,DPL).
MOV L, #data Move data to DPL.
MOV H, #data Move data to DPH.
PUSH A Push ACC to stack.
POP A Pop stack to ACC.
ATOM1.0 Family [16]

6.3. Instruction Set Summary (2/2) Preliminary
Refer to Appendix A (Instruction Set) for more details.
Type Instruction Description

CJNE @DP, #data, rel Jump if the indirect memory nibble is not equal to the data.
CJNE L, #data, rel Jump if DPL is not equal to the data.
CJNE A, dir, rel Jump if ACC is not equal to the special function register.
CJNE A, @DP, rel Jump if ACC is not equal to the indirect memory nibble.
CJLE A, @DP, rel Jump if ACC is less than or equal to the indirect memory nibble.
CJNE A, #data, rel Jump if ACC is not equal to the data.
DJNZ A, rel Decrement ACC. Jump if the result is not zero.
Branch JB bit, rel Jump if the indirect memory bit is 1.
JNB bit, rel Jump if the indirect memory bit is 0.
JC rel Jump if C is 1.
JNC rel Jump if C is 0.
JMP addr Jump to given address.
CALL addr Call subroutine.
RET Return from subroutine.
NOP No operation.
SETB @L Set the indirect function flag.

CLR @L Clear the indirect function flag.
SETB bit Set the indirect memory bit.
CLR bit Clear the indirect memory bit.
Bit & Misc.
SETB C Set Carry flag.
CLR C Clear Carry flag.
INC DPTR Increment the data pointer.
DEC DPTR Decrement the data pointer.
ATOM1.0 Family [17]

6.4. CPU Timing Preliminary
CPU takes 6 clocks for a machine cycle.

Any instruction except branch instructions completes in one machine cycle.
All branch instruction consumes 2 machine cycles whether the branch is taken or not.
The state of SFR, I/O ports, or IFF flags changes at the end of an instruction (S6).
System Clock
CPU State S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
Program Counter N N+1
Instruction
Op. Code (N-1) Op. Code (N)
Register
Machine Cycle Machine Cycle
Fetch Cycle N Fetch Cycle N+1

Execution Cycle N-1 Execution Cycle N
ATOM1.0 Family [18]

6.5. I/O Ports : PORT0 ~ PORT4 Preliminary
All ports are initialized asynchronously on power-up.

Pull-up enable and input by default (reset).
Open drain active low output.
P2[3:0] may be configured as push-pull output port.
CPU always write to SFR register, but reads port pin.
Retains the previous state in stop mode or sleep mode.
P2OEN
30 KΩ
30 KΩ
Q P0.1
CPU Write Q P2.1
P0.1 CPU Write
P2.1
SFR
SFR
QB
QB
CPU Read
CPU Read
Circuit of P0[3:0], P1[3:0], P3[3:0], P4[3:2] Circuit of P2[3:0]
ATOM1.0 Family [19]

6.5. I/O Ports : PORT4[1:0] (XI/XO) Preliminary
XI/XO for Clock Input/Output IOCFG

9 Enabled if XT/RG bit in CKCFG SFR is set. 9 This SFR is initialized to default state only by power-on-
9 Disabled in STOP mode (XI and XO are in low state). reset. Only the P2OEN bit is cleared by other resets.
XI/XO as an I/O Port 9 For 8-pin devices, only P2OEN bit is available. User
should not set other bits.
9 XI and XO can be configured as I/O port if IOXEN bit in
IOCFG SFR is set.
9 User should not set XT/RG and IOXEN at the same time.
9 Pull-up enable and input by default (reset).
9 Open drain active low output. IOXEN
30 KΩ
9 CPU always write to SFR register, but reads port pin.
9 Retains the previous state at stop mode.
CPU Write Q XI
9 IOCFG (0Eh) : I/O Port Configuration Register P4.0
/ P4.0
SFR
IOMAP1 IOMAP0 P2OEN IOXEN QB
R/W(0) R/W(0) R/W(0) R/W(0)
z IOXEN : Enable XI and XO as I/O ports. CPU Read

0 = XI and XO are used for clock input (Default). XT/RG
1 = XI and XO is used for PORT4[1:0]. 30 KΩ
z P2OEN : Configure P2 as a push-pull output port . 500 KΩ
z IOMAP[1:0] : Configure I/O ports mapping .
CPU Write Q XO
IOMAP1 IOMAP0 Ports Mapping P4.1
SFR / P4.1
0 0 Default. QB
0 1 Optional 20-pin I/O Port Mapping
1 0 Optional 24-pin I/O Port Mapping CPU Read

1 1 Reserved
ATOM1.0 Family [20]

6.5. I/O Ports : I/O Mapping Preliminary
User may select I/O port mapping by setting IOCFG SFR.

The functionality of each I/O pins is the same for any mapping.
This configuration option is useful when the pin-to-pin compatibility with existing devices is
essential.
IOCFG[3:2] == 0 IOCFG[3:2] == 1

XI / P4.0 2 19 REM XI / P4.0 2 19 REM
GC49C501G0-SO20IP
GC49C501G0-SO20IP
GC49C501R0-SO20IP
GC49C501R0-SO20IP
GC49C501G0-SJ20IP
GC49C501G0-SJ20IP
GC49C501R0-SJ20IP
GC49C501R0-SJ20IP
XO / P4.1 3 18 TVSS XO / P4.1 3 18 TVSS

P0.0 4 17 P2.0/SCLK P0.0 4 17 P2.0/SCLK
P0.1 5 16 P2.1/SDAT P0.1 5 16 P2.1/SDAT
P0.2 6 15 P2.2 P0.2 6 15 P2.2
P0.3 7 14 P2.3 P0.3 7 14 P2.3
P1.0 8 13 P3.0 P1.0 8 13 P3.0
P1.1 9 12 P3.1 P1.1 9 12 P3.1
P3.3 10 11 P3.2 P1.2 10 11 P1.3
IOCFG[3:2] == 0 IOCFG[3:2] == 2

XI / P4.0 2 23 REM XI / P4.0 2 23 REM
GC49C501G0-SO24IP
GC49C501G0-SO24IP
GC49C501R0-SO24IP
GC49C501R0-SO24IP
XO / P4.1 3 22 TVSS XO / P4.1 3 22 TVSS

P4.2 4 21 P2.0/SCLK P4.2 4 21 P2.0/SCLK
P0.0 5 20 P2.1/SDAT P3.3 5 20 P2.1/SDAT
P0.1 6 19 P2.2 P0.0 6 19 P2.2
P0.2 7 18 P2.3 P0.1 7 18 P2.3
P0.3 8 17 P4.3 P0.2 8 17 P4.3
P1.0 9 16 P3.0 P0.3 9 16 P3.0
P1.1 10 15 P3.1 P1.0 10 15 P3.1
P1.2 11 14 P3.2 P1.1 11 14 P3.2
P1.3 12 13 P3.3 P1.2 12 13 P1.3
ATOM1.0 Family [21]

6.6. Clock Configuration Preliminary
Two System Clock Sources : Internal Ring OSC. or External Resonator/Crystal

Default System Clock is Ring OSC.
When user changes the clock source (XT/RG bit), internal reset is generated.
Internal reset does not affect CKCFG.
The configuration SFR (CKCFG) is initialized by power-on reset.
User may change clock frequency during operation by changing divide option.
9 CKCFG (0Dh) : The clock configuration register.

XT/RG DIV2 DIV1 DIV0
R/W(0) R/W(0) R/W(0) R/W(0) DIV2 DIV1 DIV0 FSYS
0 0 0 FOSC
z XT/RG : System clock source selection.
0 = Internal Ring oscillator is selected as system clock. 0 0 1 FOSC/2
External clock osc. is disabled. 0 1 0 FOSC/4
1 = External clock is selected as system clock.
Internal Ring oscillator is disabled. 0 1 1 FOSC/8
Do not set this bit for 8-pin devices. 1 0 0 FOSC/16
z DIV[2:0] : System clock divider selection.
1 0 1 FOSC/32
1 1 0 FOSC/64
Internal Clock
0
FOSC FSYS 1 1 1 -
Divider System Clock
External Clock 1
DIV2 DIV1 DIV0

XT/RG
ATOM1.0 Family [22]

6.6. Clock Configuration : Internal Ring OSC. Preliminary
The Internal Ring OSC. Provides a Fixed System Clock

9 Factory calibrated to ±3% at 2.1V ~ 3.3V.
9 Factory calibrated to ±1% at 2.5V.
The Factory Calibration for 7.28MHz is applied only for GC49C501RX devices.
Frequency (MHz ) Error rate (%)
8.00 5.00
7.00
0.00
6.00
-5.00
5.00
4.00 -10.00
3.00
-15.00
2.00
-20.00
1.00
0.00 -25.00
5.5V
5.3V
5.1V
4.9V
4.7V
4.5V
4.3V
4.1V
3.9V
3.7V
3.5V
3.3V
3.1V
2.9V
2.7V
2.5V
2.3V
2.1V
1.9V
5.5V
5.3V
5.1V
4.9V
4.7V
4.5V
4.3V
4.1V
3.9V
3.7V
3.5V
3.3V
3.1V
2.9V
2.7V
2.5V
2.3V
2.1V
1.9V
VOLTAGE-FREQUENCY GRAPH
ATOM1.0 Family [23]

6.6. Clock Configuration: Guideline Preliminary
Resonator Oscillator Module Internal Ring Oscillator

/ Crystal Oscillator
ATOM ATOM ATOM

XO XO XO
Ring
XI XI XI
OSC.
OSC
Oscillator Module RC Oscillator
ATOM1.0 Family [24]

6.7. Carrier Frequency Generation Preliminary
Support 7 types of carrier frequency. REME PG2 PG1 PG0 Transmission Control ( REMI )
0 X X X 0 (Disable)
1 0 0 0 1/T = FSYS/12, T1/T = 1/3
1 0 0 1 1/T = FSYS/8, T1/T = 1/2

9 REMC (05h) : The REM Output Control Register.
1 0 1 0 1/T = FSYS/12, T1/T = 1/4
REME PG2 PG1 PG0
1 0 1 1 1 (No Carrier)
R/W(0) R/W(0) R/W(0) R/W(0)
1 1 0 0 1/T = FSYS/12, T1/T = 1/2
z PG[2:0] : Carrier Frequency Selection.
1 1 0 1 1/T = FSYS/8, T1/T = 1/4
z REME : REM Output Enable.
1 1 1 0 1/T = FSYS/11, T1/T = 4/11
1 1 1 1 1 (No Carrier)
I.R. LED
Drive Tr.
REM
FSYS Pulse REMI*
Generator
N-CH
PG2 PG1 PG0 REME TVSS

(STOP/SLEEP)
T1
ATOM1.0 Family [25]

6.7. Carrier Frequency Generation Preliminary
Waveform Example
9 REM output is the inverse of REMI*
9 Since the IR. LED drive transistor in ATOM is a N-Type, IR. LED is turned on when REMI* is high.
System Clock
(FSYS)
REME
REMI*
(FSYS/12, 1/3 Duty)
REMI*
(FSYS/8, 1/2 Duty)
REMI*
(FSYS/12, 1/4 Duty)
REMI*
(No Carrier)
REMI*
(FSYS/12, 1/2 Duty)
REMI*
(FSYS/8, 1/4 Duty)
REMI*
(FSYS/11, 4/11 Duty)
ATOM1.0 Family [26]

6.8. POR & LVD : Power-On Reset Preliminary
9 LVCFG (0Fh) : LVD Configuration Register

On-chip power-on reset is a logical OR of
RC-POR and LVD-POR POR Reserved Reserved Reserved
R/W(1) R(X) R/W(0) R/W(0)

RC-POR operates when the rising time of
power (VDD) is short. z Reserved: Do not set these bits for the future compatibility.
z POR : Power-on-reset flag to distinguish cold reset.
On-chip LVD User need to mask out the reserved bits
9 Provides power-on reset when the rising time by AND oprtation when referring to this bit.
of power is relatively long.
9 Power-on reset voltage is 1.7 V.
9 Provides power-fail reset when the power
goes down below 1.6 V.
After POR pulse is off, the internal clock
stabilization counter starts to run, which
lengthens power-on reset about 4.5 ms.
RC-POR Block
10 pF
3.3
VDD [V]
POR
A
1.7 STOP
B 1 MΩ
1.6
0 POR Reset
LVD_OFF
TIME
1.7V 1.6V LVD Pulse
LVD
LVD Pulse
Power-on Reset Power-fail Reset LVD-POR Block
ATOM1.0 Family [27]

6.8. POR & LVD : Condition for power notch Preliminary
Power-on-reset is independent of power-rising slope.
Voltage
Power slope = 1.0 V / 1 us
VDD
Yellow Region : Only RC-POR operates.
Blue Region : Only LVD-POR operates.
Green Region : Both POR's operate at the same time.
time
Power slope = 0.25 V / 1 us
The cases of reset generation by VDD notch

Voltage
VDD=2V
1V
0.5V
0V
time
T >10us T > 20us T > 40us
When VDD fails for a short time, the duration of notch (T) has limitation like
above for the successful POR operation.
The duration (T) will be changed by the VDD value and the transition time
ATOM1.0 Family [28]
6.9. WDT (Watchdog Timer) Preliminary
WDT Run Control of WDT

9 Free running counter which resets CPU every 2 17
9 WDT may be disabled if WDTE flag in IFF[13] is
system clock cycles. cleared.
9 Although the counter length is fixed, WDT 9 When disabled WDT holds the state before.
overflow period may vary according to the current 9 User can modify WDTE if and only if MAP1 flag
frequency of system clock. in IFF[11] is set and MAP0 flag in IFF[10] is
9 WDT is halt in STOP mode or disabled by user. cleared.
9 WDTE is set by internal reset and also set by
WDT is reset by H/W when user sets SLEEP flag in IFF[14] or
writes IAPCON SFR.
9 User S/W set WDTR bit in IFF[12]. WDTR bit is
automatically cleared by H/W after WDT is reset.
9 Internal reset caused by any source is activated. Program Sequence to disable WDT
MOV L, #11
9 Entering SLEEP mode.
SETB @L ; Enable MAP1
9 Start of FLASH programming (erase/write) by IAP.
MOV L, #13
CLR @L ; Disable WDT
MOV L, #11
CLR @L ; Disable MAP1
[Example of WDT Period]
XT/RG DIV2 DIV1 DIV0 FOSC (MHz) FSYS WDT Period (ms)
1 0 1 1 3.64 FOSC/8 288
0 0 0 0 7.28 FOSC 18
0 1 1 0 7.28 FOSC/64 1152
ATOM1.0 Family [29]

6.10. Reset Circuit Preliminary
Reset Sources
9 Power-on Reset (POR) when Power-Up.
9 Power-fail Reset
9 STOP mode Wake-up by changes in input port P0 or P1.
9 WDT Overflow for abnormal condition or SLEEP mode.
9 Clock source change (State change of CKCFG[3]).
Device Reset Timer
9 Once set, internal reset remains high until the DRT (Device Reset Timer) is expired.
9 The reset time depends on the configuration of system clock in CKCFG SFR.
9 For an instance, the period for 212 is 9 ms when FSYS is 455 KHz.
9 Note that CKCFG is not affected by internal reset.
9 For power-on reset, the reset time is about 4.5 ms.
VDD LVD RESET POR / PFR

Generation
P0,P1
Changes to Low Wake-Up
STOP mode S Q Internal RESET
R
WDT Overflow DRT Time
FSYS
Counter Reset Out
XT/RG
Clock Change Device Reset
FOSC Timer (212)
Generation FSYS
ATOM1.0 Family [30]

6.11. Power Management : 3 Modes Preliminary
Active Mode
9 CPU and peripheral are running.
Sleep Mode
9 Only WDT is running.
9 I/O ports hold the state before sleep mode.
9 Wake-up by WDT overflow.
9 The longest period of WDT overflow is 1.1 second when the internal RING clock is used.
9 Device is reset.
Stop Mode
9 All of the device function including external clock oscillator stops running.
9 I/O ports hold the state before stop mode.
9 Wake-up by input pin (P0, P1) changes.
9 Device is reset.
ATOM1.0 Family [31]

6.12. In Application Programming (IAP) Preliminary
In Application Programming IAP Enable Condition

9 User S/W can read or modify specific regions of 9 IAP can not erase or write INFO region.
FLASH with IAP function during operation. 9 IAPCON can be written if and only if
• MAP0 bit in IFF[10] is cleared,
9 The EEP0/1 regions may be used as program
• MAP1 bit in IFF[11] is set,
memory or data memory.
• and corresponding bit in CFGWD[2:1] is set.
9 CPU is halt during IAP and continues execution
9 When IAP is blocked by above condition, "MOV IAPCON, A"
after IAP from the next instruction which set instruction is like "NOP" instruction.
IAPCON.
9 It takes 6 system clocks to read a byte with IAP. 9 IAPCON (09h) : IAP Control Register
9 It takes about 2 ms to write(erase) a byte with IAP. RGS1 RGS0 OPS1 OPS0
9 When user attempts to write IAPCON, WDTE bit in R/W(0) R/W(0) R/W(0) R/W(0)
IFF[13] is also set.
z RGS[1:0] : Select IAP region
9 If IAP operation is erase or write, WDT is reset z OPS[1:0] : Select IAP function
before the programming is started.
RGS1 RGS0 IAP Region
IAP Related SFR 0 0 EEP0 (0x1C0 ~ 0x1FF)
9 DPH / DPL : Least significant 6-bit address for IAP. 0 1 EEP1 (0x3C0 ~ 0x3FF)
9 GDH / GDL : 8-bit data buffer for read or write by 1 0 INFO (0x0 ~ 0x7)
IAP. 1 1 Reserved
9 IAPCON : IAP control SFR. Automatically cleared to
OPS1 OPS0 IAP Function
zero after IAP is done.
0 0 No operation
0 1 Byte Read
1 0 Byte Erase
1 1 Byte Write
ATOM1.0 Family [32]

6.12. In Application Programming (IAP) Preliminary
Electrical Characteristic of IAP FLASH Regions

9 Note that the program time depends on the 9 EEPROM area is a part of program memory.
configuration of system clock frequency.
9 If the system clock frequency is out of IAP range,
user need to change FSYS before and after IAP by 0x3FF 0x3FF EEP1
configuring CKCFG SFR. 0x3C0
Parameter Symbol MIN TYP MAX Unit

Power Supply FLASH
VDD 2.7 - 5.5 V
Voltage 1 K Byte 0x1FF EEP0
System Clock 0x1C0
FSYS 5 8 11 MHz
Frequency
Write /Erase
Tp 1.5 2.0 3.3 ms
Time 0x000 0x000
Information Region CFGWD : Configuration Word

9 CFGWD[0] (ISP_LOCK) : Disable read, write, or
ADDRESS 0 1 2 3 4 5 6 7
erase by ISP except the full chip erase.
Mnemonic CFGWD
9 CFGWD[1] (IAP_RE) : Enable read by IAP.
9 CFGWD[2] (IAP_PE) : Enable write or erase by
9 The first byte contains CFGWD IAP.
9 May be used to store user ID, or checksum, etc.
9 Only the full chip erase function of ISP can erase this
region.
ATOM1.0 Family [33]

7. Absolute Maximum Ratings Preliminary
Absolute Maximum Ratings
Symbol Parameter Rating Unit

VDD DC supply voltage -0.5 to 6.5 V
VIN DC input voltage -0.5 to VDD+0.5 V
VOUT DC output voltage -0.5 to VDD+0.5 V
One I/O pin active : -25 mA
IOH DC output high current
All I/O pin active : -100 mA
One I/O pin active : 30 mA
IOL DC output low current
All I/O pin active : 150 mA
TSTG Storage temperature -55 to 125 oC
Recommended Operating Conditions
Symbol Parameter Rating Unit

VDD DC supply voltage 1.8 to 5.5 V
TA Industrial temperature range -40 to 85 oC
ATOM1.0 Family [34]

8. DC Characteristics Preliminary
* TA = = -40 oC ~ +85 oC, VDD = 1.8V ~ 5.5V unless otherwise specified.
Value
Parameter Symbol Pin Conditions Unit
Min. Typ. Max.
VIL1 P0, P1 ,P2 ,P3, P4.3, P4.2 -0.5 - 0.2VDD-0.1

Input Low Voltage VDD = 1.8V~5.5V V
VIL2 XI / P4.0, XO / P4.1 -0.5 - 0.3VDD
VIH1 P0, P1 ,P2 ,P3, P4.3, P4.2 0.2VDD+1.0 - VDD+0.5

Input high Voltage VDD = 1.8V~5.5V V
VIH2 XI / P4.0, XO / P4.1 0.7VDD - VDD+0.5
Input High
IIH All pins except XI, XO VIN = VDD -1 - +1 μA
Leakage Current
IOL = 20mA @VDD=5V

Output Low Voltage VOL P0, P1, P2, P3, P4 - - 0.3VDD V
(IOL = 3mA @VDD=2.2V)
Output Low Voltage VOL2 REM IOL2 = 280mA @VDD=3V - - 0.4 V
IOH = -15mA @VDD=5V

Output High Voltage VOH P2 (Configured as push-pull output) 0.7VDD - - V
(IOH= -2mA @VDD=2.2V)
IOHP= -40uA @VDD=5V

Output High Voltage VOHP Pull-up current 0.7VDD - - V
(IOHP = -15uA @VDD=2.2V)
Pin Capacitance CIO All VDD = 5V - 10 - pF
ATOM1.0 Family [35]

9. AC Characteristics Preliminary
* TA = -40 oC ~ +85 oC unless otherwise specified. TBD = To Be Determined.
Value
Parameter Symbol Pin Conditions Unit
Min. Typ. Max.
2.7 V ≤ VDD ≤ 5.5 V - 10

Oscillator Frequency
FOSC MHz
(Internal Clock) 1.8 V ≤ VDD < 2.7 V - 5
Oscillator Frequency 2.7 V ≤ VDD ≤ 5.5 V - - 10

FOSC XI, XO MHz
(External Clock) 1.8 V ≤ VDD < 2.7 V - - 5
System Frequency FSYS 1.8 V ≤ VDD ≤ 5.5 V 1/64 - 1 FOSC
External Input Width tINT P0, P1, P2, P3, P4 1.8 V ≤ VDD ≤ 5.5 V 12 - - FSYS
tINT
0.8VDD 0.8VDD
External Input to Port 0.2VDD 0.2VDD
tINT
ATOM1.0 Family [36]

10. Package Dimensions : 20-SOIC(Narrow/JEDEC) Preliminary
[20-SOIC (Narrow)]
HD Dimension in Inches Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
D
A - - 0.890 - - 2.25
A1 0.002 - - 0.05 - -
20 11 b 0.014 0.018 0.022 0.35 0.45 0.55
D - 0.450 - - 11.43 -
E 0.197 0.209 0.220 5.00 5.30 5.60
HD 0.492 0.500 0.510 12.50 12.70 12.95
20 pins E HE a HE 0.291 0.307 0.323 7.40 7.80 8.20
L 0.012 - 0.031 0.30 - 0.80
a 0̊ - 8̊ 0̊ - 8̊
L e 0.050 BSC 1.27 BSC
1 10
Notes:
A 1. Dimension D & E include mold mismatch and are determined at the mold
parting line.
Seating Plane A1 2. General appearance spec. should be based on final visual inspection spec.
b e
[20-SOIC (JEDEC)]
Symbol
A - - 0.106 - - 2.7
A1 0.004 - - 0.1 - -
20 11
b 0.013 0.016 0.020 0.324 0.4 0.51
E 0.264 0.295 0.324 6.71 7.5 8.23
HD 0.495 0.504 0.512 12.57 12.8 13
HE 0.394 0.406 0.419 10.0 10.3 10.643
20 pins E HE a
L 0.016 - 0.052 0.406 - 1.32
a 0̊ - 8̊ 0̊ - 8̊
L e 0.050 BSC 1.27 BSC
1 10
Notes:
parting line.
b e
ATOM1.0 Family [37]

10. Package Dimensions : 24-SOIC Preliminary
[24-SOIC]
Symbol
D
A 0.094 0.098 0.102 2.40 2.50 2.60
A1 0.004 0.008 0.012 0.10 0.20 0.30
20 11 b 0.014 0.017 0.019 0.36 0.42 0.49
D - 0.550 - - 13.97 -
E 0.291 0.295 0.299 7.40 7.50 7.60
HD 0.598 0.606 0.614 15.20 15.40 15.60
24 pins E HE a HE 0.398 0.406 0.413 10.10 10.30 10.50
L 0.004 0.010 0.016 0.10 0.25 0.40
a 0̊ - 8̊ 0̊ - 8̊
L e 0.050 BSC 1.27 BSC
1 10
Notes:
parting line.
b e
ATOM1.0 Family [38]

10. Package Dimensions : 8-SPDIP/SOIC Preliminary
[8-SPDIP]
Dimension in Inches Dimension in mm
D Symbol
A - 0.155 - - 3.93 -
8 5
A1 0.015 - - 0.380 - -
c A2 - 0.140 - - 3.55 -
E1 8 pins B 0.015 0.019 0.022 0.38 0.47 0.56
B1 0.050 0.057 0.065 1.27 1.46 1.65
c 0.008 0.011 0.014 0.20 0.28 0.36
1 4 D 0.367 0.377 0.387 9.33 9.58 9.83
E - 0.299 - - 7.60 -
E1 0.240 0.250 0.260 6.10 6.35 6.60
e1 - 0.100 - - 2.54 -
E L 0.120 0.130 0.140 3.05 3.30 3.55
a 0̊ - 15 ̊ 0̊ - 15 ̊
A1 eA 0.330 0.350 0.370 8.382 8.89 9.398
A A2 Base Plane
Notes:
L Seating Plane 1. Dimension D Max. & S include mold flash or tie bar Burns.
2. Dimension E1 dose not include interlead flash.
e1 eA
3. Dimension D & E1 include mold mismatch and are determined at the mold
a parting line.
4. Dimension B1 does not include dambar protrusion/intrusion.
B 5. General appearance spec. should be based on final visual inspection spec.
B1
[8-SOIC]
Symbol
D A 0.068 0.072 0.075 1.73 1.82 1.90
8 5 A1 0.004 0.007 0.010 0.10 0.18 0.26
b 0.012 0.016 0.020 0.31 0.41 0.51
D - 0.150 - - 3.81 -
8 pins E HE E 0.146 0.154 0.161 3.70 3.90 4.10
HD 0.185 0.193 0.201 4.70 4.90 5.10
a HE 0.224 0.236 0.248 5.70 6.00 6.30
1 4 L 0.017 0.026 0.035 0.42 0.65 0.88
a 0̊ - 8̊ 0̊ - 8̊
L e 0.050 BSC 1.27 BSC
Notes:
parting line.
e
ATOM1.0 Family [39]

11. Product Numbering System Preliminary
G C X X X X X X X X - X X X X X X X X
General Core Version
MCU Series 0-9 = Revision P = Pb-Free
P = Power position
Core Type
Temperature
4 = 4 bits
C = -20oC ~ 85oC
8 = 8 bits
I = -40oC ~ 85oC
16 = 16 bits
E = -40oC ~ 125oC
32 = 32 bits
ROM Type
0 = ROMless Package Pins
1 = Mask ROM
7 = EPROM Package Type
8 = EEPROM P = PDIP TS = TSSOP DF = DFN
9 = FLASH SP = SPDIP LQ = LQFP ML = MLF
PL = PLCC MQ = MQFP WL = WLCSP
SO = SOP/SOIC TQ = TQFP W = Wafer Biz.
Operating Voltage SS = SSOP CO = COB C = Chip Biz.
C = Common
(1.8V ~ 5.5V)
L = Low Voltage Custom ROM Code
(1.2V ~ 2.7V) Application (Option)
G = General
ROM Size A = ADC
320 = ROMless R = RCLK Calibration
500 = 2KB B = Battery
501 = 1KB L = LCD
510 = 4KB U = USB
520 = 8KB P = Printer
54X = 16KB E = Edu./Toy
58X = 32KB T = Telecom
59X = 64KB H = Home Application
ATOM1.0 Family [40]

12. Supporting tools Preliminary
MDS Code Generation Tools

(Microprocessor Development System)
Assembler & Linker for DOS &
In-Circuit Debugger Windows
Easy-to-Use GUI
User-Friendly
User-Friendly
Development
Development
Environment
Environment
ROM Writer
Application System
Optional Parallel/Serial Program

On-board Implemented Various
Application World Wide Programmable in
Anywhere
Various Sample Test Program
ATOM1.0 Family [41]

Appendix A : Instruction Set (1/19) Preliminary
Abbreviations and Symbols

Symbol Description Symbol Description
PC The program counter. (PC) The contents of PC.
A The accumulator register (ACC). (A) The contents of ACC.
C The carry flag. (C) The contents of C.
The stack pointer register.
SP M[SP] The contents of RAM addressed by SP.
Concatenation of SPH and SPL.
(DP) The contents of DPTR. (SP) The contents of SP.
The data pointer register (DPTR).
DP M[DP] The contents of RAM addressed by DPTR.
Concatenation of DPH and DPL.
H The high nibble of the data pointer (DPH). (H) The contents of DPH.
L The low nibble of the data pointer (DPL). (L) The contents of DPL.
The contents of indirect function flag (IFF) 8-bit signed displacement value for relative
F[L] rel
addressed by DPL. branch (-128 ≤ rel ≤ 127).
#data 4-bit data operand addr 12-bit absolute branch address.
dir 4-bit direct address of SFRs (0 ≤ dir ≤ 15) R[dir] The contents of SFR or read value of ports.
2-bit pointer of the bit in data memory The value of memory bit which is addressed
bit M[DP].bit
addressed by DPTR (0 ≤ bit ≤ 3). by DPTR and bit.
@ Prefix for indirect address Pm.n Value of bit n of I/O port m.
≤ Less than or equal to . Value of PC for current instruction.
← Transfer ↔ Exchange
= Equal to ≠ Not equal to
> Greater than < Less than
+ Addition - Subtraction
& Bitwise logical AND | Bitwise logical OR
^ Bitwise logical Exclusive-OR ~ Bitwise logical complement
{b,b} Concatenation of bits
ATOM1.0 Family [42]

OPCODE Map
H L 0 1 2 3 4 5 6 7 8 9 A B C D E F
ADD ADDC SUB ANL ORL XRL

SETB PUSH POP INC DEC INC DEC RRC
0 NOP A, A, CPL A A, A, A, A,
C A A DPTR DPTR @DP @DP A
@DP @DP @DP @DP @DP @DP
DEC
1 CLR C INC A ADD A, #data
A
2 MOV L, #data
3 MOV H, #data
4 MOVI @DP, #data
5 CLR A MOV A, #data
6 MOV dir, A
7 MOV A, dir
MOV
MOV XCH MOV MOV MOVI
D CLR SETB
8 A, A, L, @DP, @DP, CLR bit SETB bit
@DP, @L @L
@DP @DP @DP A A
A
CJNE CJLE
DJNZ JNC
9 RET A,@D A,@D JC rel JNB bit, rel JB bit, rel
A, rel rel
P, rel P, rel
A CJNE L, #data, rel
B CJNE @DP, #data, rel
C CJNE A, #data, rel
D CJNE A, dir, rel
E JMP addr
F CALL addr
ATOM1.0 Family [43]

ADD A, #data ADDC A, @DP

Binary Code 0001 dddd Binary Code 0000 1001
Description Adds the 4-bit data to the Accumulator. Description Simultaneously adds the contents of indirect
The result is stored in Accumulator. data memory, the carry flag and the
When adding unsigned integers, the carry flag Accumulator. The result is stored in
indicates an overflow. Accumulator.
When adding unsigned integers, the carry flag
Operation (A) ← (A) + #data indicates an overflow.
Carry Flag Set if a carry occurred, cleared otherwise. Operation (A) ← (A) + M[DP] + (C)
Bytes 1 Carry Flag Set if a carry occurred, cleared otherwise.
Cycles 1 Bytes 1
Example CLR A ; Clear ACC Cycles 1
ADD A, #2 ; Add 2 to ACC. ACC contains 2.
Example ; Assumes M[DP] contains 2 and C is 1.
ADD A, @DP MOV A, #8 ; Set ACC as 8.
ADDC A, @DP ; The result, 11 is stored in ACC.
Binary Code 0000 1000
Description Adds the contents of indirect data memory to

the Accumulator. The result is stored in
Accumulator. When adding unsigned integers,
the carry flag indicates an overflow.
Operation (A) ← (A) + M[DP]
Carry Flag Set if a carry occurred, cleared otherwise.
Bytes 1
Cycles 1
Example ; Assumes M[DP] contains 2
MOV A, #8 ; Set ACC as 8.
ADD A, @DP ; The result, 10 is stored in ACC.
ATOM1.0 Family [44]

ANL A, @DP CALL addr

Binary Code 0000 1100 Binary Code 1111 aaaa aaaa aaaa
Description ANL performs the bitwise logical-AND operation Description Unconditionally calls a subroutine located at the
between the indirect data memory and ACC. indicated 12-bit address. The instruction
The result is stored in Accumulator. increments the PC twice to obtain the address
of the following instruction, then push the
Operation (A) ← (A) & M[DP]
result onto the stack (low-order nibble first).
Carry Flag Not affected. The stack pointer is incremented three times.
The destination address is obtained by
Bytes 1 concatenating four low-order bits of the
Cycles 1 opcode byte and the second byte of the
instruction.
MOV A, #0xA ; Set ACC as 10. Operation (PC) ← (PC) + 2
ANL A, @DP ; The result, 2 is stored in ACC. (SP) ← (SP) + 1
M[SP] ← (PC3-0)
(SP) ← (SP) + 1
M[SP] ← (PC7-4)
(SP) ← (SP) + 1
M[SP] ← (PC11-8)
(PC) ← addr
Carry Flag Not affected.
Bytes 2
Cycles 2
Example CALL SUBR ; Call subroutine located
; at the label SUBR.
ATOM1.0 Family [45]

CJLE A, @DP, rel CJNE @DP, #data, rel

Binary Code 1001 0011 rrrr rrrr Binary Code 1011 dddd rrrr rrrr
Description Compares the contents of ACC and the indirect Description Compares the contents of the indirect memory
memory, and branches if the value in ACC is and data in four low-order bits of opcode, and
less than or equal to that in memory. branches if their values are not equal.
The branch destination is computed by adding The branch destination is computed by adding
the signed relative-displacement in the the signed relative-displacement in the
second byte of the instruction to the PC, after second byte of the instruction to the PC, after
incrementing the PC to the start of the next incrementing the PC to the start of the next
instruction. The contents of both operands are instruction. The contents of indirect memory is
not affected by comparison. not affected.
The carry flag is set if the contents are equal. The carry flag is set if the unsigned integer
value of M[DP] is less than the unsigned
Operation (PC) ← (PC) + 2
integer value of the data; otherwise, the carry
IF (A) ≤ M[DP] THEN (PC) ← (PC) + rel is cleared.
Carry Flag IF (A) = M[DP] THEN (C) ← 1 Operation (PC) ← (PC) + 2
ELSE (C) ← 0.
IF M[DP] ≠ #data THEN (PC) ← (PC) + rel
Bytes 2
Carry Flag IF M[DP] < #data THEN (C) ← 1
Cycles 2 ELSE (C) ← 0.
Example ; Assumes M[DP] contains 11, ACC 5. Bytes 2
CJLE A, @DP, CMP_LE; Branches to CMP_LE
Cycles 2
...... ; IF (A) > M[DP]
CMP_LE: JC CMP_EQ ; Example ; Assumes M[DP] contains 2.
...... ; IF (A) < M[DP] CJNE @DP, #8, CMP_NE; Branches to CMP_NE
CMP_EQ: ...... ; IF (A) = M[DP] ...... ; IF M[DP] = 8
CMP_NE: JC CMP_LT ; Branches to CMP_LT
...... ; IF M[DP] > 8
CMP_LT: ...... ; IF M[DP] < 8
ATOM1.0 Family [46]

CJNE A, #data, rel CJNE A, @DP, rel

Binary Code 1100 dddd rrrr rrrr Binary Code 1001 0010 rrrr rrrr
Description Compares the contents of Accumulator and Description Compares the contents of ACC and the indirect
data in four low-order bits of opcode, and memory, and branches if their values are not
branches if their values are not equal. equal.
instruction. The contents of ACC is not affected. instruction. The contents of both operands are
The carry flag is set if the unsigned integer not affected by comparison.
value of ACC is less than the unsigned The carry flag is set if the unsigned integer
integer value of the data; otherwise, the carry value of ACC is less than the unsigned
is cleared. integer value of M[DP]; otherwise, the carry is
cleared.
IF (A) ≠ #data THEN (PC) ← (PC) + rel Operation (PC) ← (PC) + 2
IF (A) ≠ M[DP] THEN (PC) ← (PC) + rel
Carry Flag IF (A) < #data THEN (C) ← 1
ELSE (C) ← 0. Carry Flag IF (A) < M[DP] THEN (C) ← 1
ELSE (C) ← 0.
Bytes 2
Bytes 2
Cycles 2
Cycles 2
Example ; Assumes ACC contains 11.
CJNE A, #8, CMP_NE ; Branches to CMP_NE Example ; Assumes M[DP] and ACC contain 15.
...... ; IF (A) = 8 CJNE A, @DP, CMP_NE ; Branch is not taken.
CMP_NE: JC CMP_LT ; Branch is not taken. ...... ; IF (A) = M[DP]
...... ; IF (A) > 8 CMP_NE: JNC CMP_GT ; IF (A) ≠ M[DP]
CMP_LT: ...... ; IF (A) < 8 ...... ; IF (A) < M[DP]
CMP_GT: ...... ; IF (A) > M[DP]
ATOM1.0 Family [47]

CJNE A, dir, rel CJNE L, #data, rel

Binary Code 1101 dddd rrrr rrrr Binary Code 1010 dddd rrrr rrrr
Description Compares the contents of ACC and that of SFR Description Compares the contents of DPL and data in four
addressed by four low-order bits of opcode, and low-order bits of opcode, and branches if their
branches if their values are not equal. values are not equal.
instruction. The contents of both operands are instruction. The contents of DPL is not affected.
not affected by comparison. The carry flag is set if the unsigned integer
The carry flag is set if the unsigned integer value of DPL is less than the unsigned
value of ACC is less than the unsigned integer integer value of the data; otherwise, the carry
value of the SFR; otherwise, the carry is cleared. is cleared.
Operation (PC) ← (PC) + 2 Operation (PC) ← (PC) + 2
IF (A) ≠ R[dir] THEN (PC) ← (PC) + rel IF (L) ≠ #data THEN (PC) ← (PC) + rel
Carry Flag IF (A) < R[dir] THEN (C) ← 1 Carry Flag IF (L) < #data THEN (C) ← 1
ELSE (C) ← 0. ELSE (C) ← 0.
Bytes 2 Bytes 2
Cycles 2 Cycles 2
Example ; Wait until P0 (Port 0) is 0xE. Example ; Looping with DPL
MOV A, #0xE MOV L, #9 ; (L) ← 9
CJNE A, P0, . ; Self looping with "." LOOP_L: ...... ; Operations in loop
...... ; Operations in loop
DEC DPTR ; (DP) ← (DP) - 1
CJNE L, #0, LOOP_L ; Repeat until (L) is 0.
ATOM1.0 Family [48]

CLR @L CLR C
Binary Code 1000 0110 Binary Code 0001 0000
Description Clears the indirect function flag Description Clears the carry flag.
addressed by DPL. This is the same as "ADD A, #0".
Operation F[L] ← 0 Operation (A) ← (A) + 0
Carry Flag Not affected. Carry Flag (C) ← 0
Bytes 1 Bytes 1
Cycles 1 Cycles 1
Example ; Assumes P2 contains 0xF. Example CLR C
MOV L, #1 ; (L) ← 1
CLR @L ; P2.1 ← 0
MOV A, #0xD ; (A) ← 13
CJNE A, P2, ERROR ; Check if P2.1 is 0.
CLR A CLR bit

Binary Code 0101 0000 Binary Code 1000 10bb
Description Clears the accumulator. Description Clears a bit in data memory addressed by
This is an abbreviation of MOV A, #0. DPTR. The bit position of the nibble is obtained
by the least significant two bits of opcode.
Operation (A) ← 0
Operation M[DP].bit ← 0
Bytes 1
Bytes 1
Cycles 1
Cycles 1
Example CLR A
Example ; Assumes M[DP] contains 7.
CLR 2 ; M[DP].2 ← 0
CJNE @DP, #3, ERROR ; Check result
ATOM1.0 Family [49]
CPL A DEC A
Description Complements the contents of ACC. Description Decrements the contents of ACC.
Operation (A) ← ~(A) This is the same as "ADD A, #15".
Carry is cleared when the borrow occurs;
Carry Flag Not affected. otherwise, carry is set.
Bytes 1 Operation (A) ← (A) + 15
Cycles 1 Carry Flag IF (A) = 0 THEN C ← 0
Example MOV A, P0 ; (A) ← P0 ELSE C ← 1.
CPL A ; ACC contains 1's Bytes 1
; complement of P0
Cycles 1
Example DEC A
DEC @DP DEC DPTR

Description Decrements the value of data memory Description Decrements the data pointer.
addressed indirectly by DPTR. Operation (DP) ← (DP) - 1
Operation M[DP] ← M[DP] - 1 Carry Flag Not affected.
Carry Flag Not affected. Bytes 1
Bytes 1 Cycles 1
Cycles 1 Example ; Assumes DPTR contains 0.
Example DEC @DP DEC DPTR ; By underflow, all bits
; of DPH and DPL are set.
DEC DP ; This is also valid.
ATOM1.0 Family [50]

DJNZ A, rel INC @DP

Binary Code 1001 0001 rrrr rrrr Binary Code 0000 0110
Description Decrements the contents of ACC, and Description Increments the value of data memory
branches if the result is not zero. addressed indirectly by DPTR.
The branch destination is computed by adding
the signed relative-displacement in the Operation M[DP] ← M[DP] + 1
second byte of the instruction to the PC, after Carry Flag Not affected.
incrementing the PC to the start of the next
instruction. Bytes 1
Carry is cleared when the borrow occurs; Cycles 1
otherwise, carry is set. Example INC @DP
(A) ← (A) - 1
IF (A) ≠ 0 THEN (PC) ← (PC) + rel INC A
Carry Flag IF (A) = 0 THEN (C) ← 0 Binary Code 0001 0001

ELSE (C) ← 1. Description Increments the contents of ACC.
Bytes 2 This is the same as "ADD A, #1".
Carry is set when the overflow occurs;
Cycles 2
otherwise, carry is cleared.
Example MOV A, @DP
Operation (A) ← (A) + 1
DJNZ A, ACC_NZ
...... Carry Flag IF (A) = 15 THEN C ← 1
ACC_NZ: JNC ACC_ZERO ELSE C ← 0.
...... Bytes 1
Cycles 1
Example INC A
ATOM1.0 Family [51]

INC DPTR JB bit, rel

Binary Code 0000 0100 Binary Code 1001 11bb rrrr rrrr
Description Increments the data pointer. Description Branches if the bit in data memory is 1. The
address is given by DPTR and bit position is
Operation (DP) ← (DP) + 1 given by two least significant bits of opcode .
Carry Flag Not affected. The branch destination is computed by adding
the signed relative-displacement in the
Bytes 1
second byte of the instruction to the PC, after
Cycles 1 incrementing the PC to the start of the next
instruction. The contents of memory is not
Example ; Assumes all bits of DPTR is 1. affected.
INC DPTR ; By roll over, all bits
; of DPH and DPL are cleared. Operation (PC) ← (PC) + 2
INC DP ; This is also valid. IF M[DP].bit = 1 THEN (PC) ← (PC) + rel
Bytes 2
Cycles 2
Example JB 0, L_BIT_SET
...... ; IF M[DP].0 = 0
L_BIT_SET: ...... ; IF M[DP].0 = 1
ATOM1.0 Family [52]

JC rel JMP addr

Binary Code 1001 0111 rrrr rrrr Binary Code 1110 aaaa aaaa aaaa
Description Branches if the carry flag is 1. Description Transfers program execution to the indicated
The branch destination is computed by adding 12-bit address.
the signed relative-displacement in the The destination address is obtained by
second byte of the instruction to the PC, after concatenating the four low-order bits of the
incrementing the PC to the start of the next opcode byte and the second byte of the
instruction. instruction.
Operation (PC) ← (PC) + 2 Operation (PC) ← addr
IF (C) = 1 THEN (PC) ← (PC) + rel
Bytes 2
Bytes 2
Cycles 2
Cycles 2
Example JMP LABEL ; Jumps to LABEL.
Example JC L_C_SET ......
...... ; IF (C) = 0 JMP . ; Infinite loop
L_C_SET: ...... ; IF (C) = 1
ATOM1.0 Family [53]

JNB bit, rel JNC rel

Binary Code 1001 10bb rrrr rrrr Binary Code 1001 0110 rrrr rrrr
Description Branches if the bit in data memory is 0. Description Branches if the carry flag is 0.
The address of memory is given by DPTR and The branch destination is computed by adding
bit position is given by two least significant bits the signed relative-displacement in the
of opcode . second byte of the instruction to the PC, after
The branch destination is computed by adding incrementing the PC to the start of the next
the signed relative-displacement in the instruction.
second byte of the instruction to the PC, after Operation (PC) ← (PC) + 2
incrementing the PC to the start of the next
instruction. The contents of memory is not IF (C) = 0 THEN (PC) ← (PC) + rel
affected. Carry Flag Not affected.
Operation (PC) ← (PC) + 2 Bytes 2
IF M[DP].bit = 0 THEN (PC) ← (PC) + rel
Cycles 2
Example JNC L_C_ZERO
Bytes 2 ...... ; IF (C) = 1
Cycles 2 L_C_ZERO: ...... ; IF (C) = 0
Example JNB 3, L_BIT_ZERO

...... ; IF M[DP].3 = 1
L_BIT_ZERO: ...... ; IF M[DP].3 = 0
ATOM1.0 Family [54]

MOV @DP, A MOV A, @DP

Description The contents of ACC is copied to data memory Description Copies the contents of data memory to ACC.
whose address is given by DPTR. The address of memory is given by DPTR.
Operation M[DP] ← (A) Operation (A) ← M[DP]
Carry Flag Not affected. Carry Flag Not affected.
Bytes 1 Bytes 1
Cycles 1 Cycles 1
Example MOV H, #2 ; (H) ← 2 Example MOV H, #1 ; (H) ← 1
MOV L, #14 ; (L) ← 14 MOV L, #0 ; (L) ← 0
MOV @DP, A MOV A, @DP
MOV A, #data MOV A, dir

Binary Code 0101 dddd Binary Code 0111 dddd
Description Sets ACC with the data given Description The contents of SFR is copied to ACC.
in four low-order bits of opcode. The address of SFR is given by four low-order
bits of opcode.
Operation (A) ← #data
Operation (A) ← R[dir]
Bytes 1
Bytes 1
Cycles 1
Cycles 1
Example MOV A, #-1 ; (A) ← 15
MOV A, #0xC ; (A) ← 12 Example MOV A, P0 ; Read Port-0 into ACC.
MOV A, L ; Move DPL to ACC.
MOV A, SPH ; Move SPH to ACC.
ATOM1.0 Family [55]

MOV H, #data MOV L, @DP

Binary Code 0011 dddd Binary Code 1000 0010
Description Sets DPH with the data given Description Copies the contents of data memory to DPL.
in four low-order bits of opcode. The address of memory is given by DPTR.
Operation (H) ← #data Operation (L) ← M[DP]
Carry Flag Not affected. Carry Flag Not affected.
Bytes 1 Bytes 1
Cycles 1 Cycles 1
Example MOV H, #1 ; (H) ← 1 Example MOV H, #0

MOV L, #3
MOV L, @DP ; L is changed to M[DP]
MOV L, #data MOV dir, A

Binary Code 0010 dddd Binary Code 0110 dddd
Description Sets DPL with the data given Description The contents of ACC is copied to SFR.
in four low-order bits of opcode. The address of SFR is given by four low-order
bits of opcode.
Operation (L) ← #data
Operation R[dir] ← (A)
Bytes 1
Bytes 1
Cycles 1
Cycles 1
Example MOV L, #5 ; (L) ← 5
Example MOV P0, A ; Output ACC to Port-0.
MOV H, A ; Move ACC to DPH.
MOV DPH, A ; Move ACC to DPH.
MOV SPL, A ; Move ACC to SPL.
ATOM1.0 Family [56]

MOVD @DP, A MOVI @DP, #data

Binary Code 1000 0101 Binary Code 0100 dddd
Description The contents of ACC is copied to data memory Description Set data memory whose address is given by
whose address is given by DPTR. After that the DPTR with the data given in four low-order bits
data pointer is decremented. of opcode. After that the data pointer is
incremented.
Operation M[DP] ← (A)
(DP) ← (DP) - 1 Operation M[DP] ← #data
(DP) ← (DP) + 1
Bytes 1
Bytes 1
Cycles 1
Cycles 1
Example MOVD @DP, A
Example ; Simple look-up of constant values
MOV L, #0 ; Pointer to store
MOVI @DP, A MOV H, #1 ; look-up values
CALL TABLE
.....
Description The contents of ACC is copied to data memory TABLE: MOVI @DP, #0xC
whose address is given by DPTR. After that the
MOVI @DP, #0x0
data pointer is incremented.
MOVI @DP, #0x0
Operation M[DP] ← (A) MOVI @DP, #0x1
(DP) ← (DP) +1 RET
Bytes 1
Cycles 1
Example MOVI @DP, A
ATOM1.0 Family [57]

NOP ORL A, @DP

Description No operation. Description ORL performs the bitwise logical-OR operation

Just fetches the next instruction. between the indirect data memory and ACC.
The result is stored in Accumulator.
Operation (A) ← (A) | M[DP]
Bytes 1
Bytes 1
Cycles 1
Cycles 1
Example NOP
POP A MOV A, #0xA ; Set ACC as 10.
Binary Code 0000 0011 ORL A, @DP ; The result, 11 is stored in ACC.
Description The contents of stack top is moved to ACC. PUSH A
After that the stack pointer is decremented by
1. Binary Code 0000 0010
Operation (A) ← M[SP] Description The stack pointer is incremented by 1. Then

the contents of ACC is copied to the stack.
(SP) ← (SP) - 1
Operation (SP) ← (SP) + 1
M[SP] ← (A)
Bytes 1
Cycles 1
Bytes 1
Example ; Looping with variable stored in stack
Cycles 1
MOV A, #7 ; Set loop count
LOOP_BGN: PUSH A ; Store loop index in stack. Example PUSH A ; Store ACC in stack
..... ; Operations in loop MOV A, #0xE ; Assign ACC for port output
POP A ; Restore loop index MOV P2, A ; Drive Port 2
DJNZ A, LOOP_BGN ; Iteration POP A ; Restore ACC from stack
ATOM1.0 Family [58]

RET RRC A
Description Returns from subroutine. Description Rotates right the contents of ACC with the carry
The stack pointer is decremented three times. flag.
Operation (PC11-8) ← M[SP] Operation (A) ← {(C), (A3-1)}

(SP) ← (SP) - 1 Carry Flag (C) ← (A0)
(PC7-4) ← M[SP]
Bytes 1
(SP) ← (SP) - 1
(PC3-0) ← M[SP] Cycles 1
(SP) ← (SP) - 1 Example RRC A
Carry Flag Not affected. JC A0_HIGH ; IF A0 = 1 Branches
Bytes 1
SETB @L
Cycles 2
Example RET
Description Sets the indirect function flag
addressed by DPL.
SETB C Operation F[L] ← 1
Binary Code 0000 0001 Carry Flag Not affected.
Description Sets the carry flag. Bytes 1
Operation Cycles 1
Carry Flag (C) ← 1 Example ; Assumes P2 contains 0.

MOV L, #1 ; (L) ← 1
Bytes 1
SETB @L ; P2.1 ← 1
Cycles 1 MOV A, #2 ; (A) ← 2
Example SETB C CJNE A, P2, . ; Wait until P2.1 is 1.
ATOM1.0 Family [59]

SETB bit XCH A, @DP

Binary Code 1000 11bb Binary Code 1000 0001
Description Sets a bit in data memory indirectly addressed Description Exchanges the contents of ACC and that of
by DPTR. The bit position is obtained at the data memory addressed by DPTR.
least significant two bits of opcode.
Operation (A) ↔ M[DP]
Operation M[DP].bit ← 1
Bytes 1
Bytes 1
Cycles 1
Cycles 1
Example XCH A, @DP
Example ; Assumes M[DP] contains 5.
SETB 2 ; M[DP].2 ← 1
CJNE @DP, #7, ERROR ; Check result
SUB A, @DP XRL A, @DP

Description Subtracts the contents of indirect data memory Description XRL performs the bitwise logical Exclusive-OR
from the Accumulator. The result is stored in operation between the indirect data memory
Accumulator. The carry flag is cleared if the and ACC. The result is stored in Accumulator.
unsigned value of ACC is less than unsigned
value of M[DP]; otherwise, C is set. Operation (A) ← (A) ^ M[DP]
Operation (A) ← (A) - M[DP] Carry Flag Not affected.
Carry Flag If (A) < M[DP] THEN (C) ← 0 Bytes 1

ELSE (C) ← 1. Cycles 1
Bytes 1 Example ; Assumes M[DP] contains 2
Cycles 1 MOV A, #0xA ; Set ACC as 10.
XRL A, @DP ; The result, 8 is stored in ACC.
Example SUB A, @DP
ATOM1.0 Family [60]

Appendix B : SFR Description [00h ~ 07h] (1/3)
Preliminary
[How to Read a SFR Descriptions] DPH (03h) : The High Nibble of Data Pointer (DPTR)
SFR Address Yellow Color : Bit Addressable - - DPH.1 DPH.0

White Color : Byte Addressable R/W(0) R/W(0)
P2 (08h) : Port 2 Output Register

P2.3 P2.2 P2.1 P2.0
P1.3 P1.2 P1.1 P1.0
R/W(1) R/W(1) R/W(1) R/W(1)
R/W(1) R/W(1) R/W(1) R/W(1)
R : Unrestricted Read
W : Unrestricted Write REMC (05h) : The REM Output Control Register
(n) : Reset Value
REME PG2 PG1 PG0
R/W(0) R/W(0) R/W(0) R/W(0)
PG[2:0] : Carrier frequency selection.

REME : REM output enable.
P0.3 P0.2 P0.1 P0.0
R/W(1) R/W(1) R/W(1) R/W(1) SPL (06h) : The Low Nibble of Stack Pointer (SP)
SP.3 SP.2 SP.1 SP.0
R/W(1) R/W(1) R/W(1) R/W(1)
P4.3 P4.2 P4.1 P4.0
Indicate where stack will start.
R/W(1) R/W(1) R/W(1) R/W(1)
Increment by PUSH and decrement by POP.
DPL (02h) : The Low Nibble of Data Pointer (DPTR)

SPH (07h) : The High Nibble of Stack Pointer (SP)
DPL.3 DPL.2 DPL.1 DPL.0
- - SPh.1 SPh.0
R/W(0) R/W(0) R/W(0) R/W(0)
R/W(0) R/W(1)
ATOM1.0 Family [61]

Appendix B : SFR Description [08h ~ 0Dh] (2/3)
Preliminary
P2 (08h) : Port 2 Output Register P3 (0Ch) : Port 3 Output Register

P2.3 P2.2 P2.1 P2.0 P3.3 P3.2 P3.1 P3.0
R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)
IAPCON (09h) : IAP Control Register CKCFG (0Dh) : The Clock Configuration Register
RGS1 RGS0 OPS1 OPS0 XT/RG DIV2 DIV1 DIV0
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
RGS[1:0] : Select IAP region. XT/RG : System clock source selection.

[0,0] : EEP0 (0x1C0 ~ 0x1FF) 0 : Internal Ring oscillator is selected as system clock.
[0,1] : EEP1 (0x3C0 ~ 0x3FF) External clock oscillator is disabled.
[1,0] : INFO (0x0 ~ 0x7) 1 : External clock oscillator is selected as system clock.
[1,1] : Reserved Internal Ring oscillator is disabled.
OPS[1:0] : Select IAP function. Do not set this bit for 8-pin devices.
[0,0] : N0 operation
[0,1] : Byte read DIV[2:0] : System clock divider selection.
[1,0] : Byte erase [0,0,0] : FOSC
[1,1] : Byte write [0.0,1] : FOSC/2
[0.1,0] : FOSC/4
[0.1,1] : FOSC/8
GDL (0Ah) : The Low Nibble of General Purpose Data Register
[1,0,0] : FOSC/16
GDL.3 GDL.2 GDL.1 GDL.0 [1.0,1] : FOSC/32
[1.1,0] : FOSC/64
R/W(0) R/W(0) R/W(0) R/W(0)
[1.1,1] : -
GDH (0Bh) : The High Nibble of General Purpose Data Register

GDH.3 GDH.2 GDH.1 GDH.0
R/W(0) R/W(0) R/W(0) R/W(0)
ATOM1.0 Family [62]

Appendix B : SFR Description [0Eh ~ 0Fh] (3/3)
Preliminary
IOCFG (0Eh) : I/O Port Configuration Register

IOMAP1 IOMAP0 P2OEN IOXEN
R/W(0) R/W(0) R/W(0) R/W(0)
IOXEN : Enable XI and XO as I/O ports.

0 : XI and XO are used for clock input (Default).
1 : XI and XO is used for PORT4[1:0]
P2OEN : Configure P2 as push-pull output port.
IOMAP [1:0] : Configure I/O ports mapping.
[0,0] : Default.
[0,1] : Optional 20-pin I/O port mapping
[1,0] : Optional 24-pin I/O port mapping
[1,1] : Reserved
LVCFG (0Fh) : LVD Configuration Register

POR Reserved Reserved Reserved
R/W(1) R(X) R/W(0) R/W(0)
Reserved : Do not set these bits for the future compatibility.

POR : Power-on-reset flag.
User S/W may use this flag to distinguish cold reset
and warm reset. User need to mask out the reserved bits
by AND oprtation when referring to this bit.
ATOM1.0 Family [63]

Appendix C : Update History Preliminary
V1.0 V1.6
9 First Official Release 9 Add 20-SOIC (JEDEC) Package
9 Modify Package Dimensions
V1.1 9 Now POR block has no limitation for the power
9 Modify Internal Ring Spec. rising slope.
9 Add Internal Ring OSC. Slide
V1.2
9 Modify Operating frequency
V1.3
9 Added GC49C501RX devices.
9 Description for POR condition.
9 LVOFF flag is not supported any more.
V1.4
9 Modify Internal Ring Spec.
9 Add E.S.D. Spec.
V1.5
9 Enhanced description for 8-pin devices.
9 Optional power-fail reset is not supported any
more.
ATOM1.0 Family [64]

Bm-Atom1 0-V1 6

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MiDAS Family

Brief Manual of ATOM1.0 Family

www.coreriver.com (E-mail : tech@coreriver.com)

1. Product Overview 7. Absolute Maximum Ratings

ATOM1.0 Family [2]

ATOM1.0 Family [3]

ATOM1.0 Family [4]

 CPU  REM output (Remote control transmitter)

ATOM1.0 Family [5]

ATOM1.0 Family [6]

RING OSC. 4 DPL 4

XI/P4[0] XO/P4[1] P4[3:2] P0[3:0] P1[3:0] P2[3:0] P3[3:0] TVSS REM

ATOM1.0 Family [7]

RING OSC. 4 DPL 4

XI/P4[0] XO/P4[1] P0[3:0] P1[1:0] P2[3:0] P3[3:0] TVSS REM

ATOM1.0 Family [8]

Data Address RAM

ATOM1.0 Family [9]

VSS 1 20 VDD VSS 1 24 VDD

ATOM1.0 Family [10]

Symbol Direction Description Remark

VSS Power Ground

TVSS Power Ground for IR LED drive Transistor

ATOM1.0 Family [11]

Symbol Direction Description Remark

VSS Power Ground

ATOM1.0 Family [12]

[Special Function Register Map] [Indirect Function Flag Map]

04H P1 REMC SPL SPH 7 6 5 4 3 2 1 0

ATOM1.0 Family [13]

P4 01H Port 4 output register. 1111 1111

P1 04H Port 1 output register. 1111 1111

REMC 05H REM output control register. 0000 0000

P2 08H Port 2 output register. 1111 1111

IAP (In Application Programming) Control register.

P3 0CH Port 3 output register. 1111 1111

- : Unimplemented bit. Read as 0. Note for 8-pin devices.

ATOM1.0 Family [14]

 Indirect Function Flag (IFF)

Flag Address (DPL) Description Reset Value

SLEEP 14 Enter sleep mode. Released by WDT reset. 0

MAP1 11 Address map extension bit 1 for SFR/IFF. 0

P4.2 9 Individual bit set/clear for P4 1

P4.3 8 Individual bit set/clear for P4 1

P3.3 7 Individual bit set/clear for P3 1

P3.2 6 Individual bit set/clear for P3 1

P3.1 5 Individual bit set/clear for P3 1

P3.0 4 Individual bit set/clear for P3 1

P2.3 3 Individual bit set/clear for P2 1

P2.2 2 Individual bit set/clear for P2 1

P2.1 1 Individual bit set/clear for P2 1

P2.0 0 Individual bit set/clear for P2 1

ATOM1.0 Family [15]

 Refer to Appendix A (Instruction Set) for more details.

CLR A Clear ACC.

MOV dir, A Move ACC to the special function register.

ATOM1.0 Family [16]

 Refer to Appendix A (Instruction Set) for more details.

Type Instruction Description

CPU REM output (Remote control transmitter)

Indirect Function Flag (IFF)

Refer to Appendix A (Instruction Set) for more details.

Refer to Appendix A (Instruction Set) for more details.

CPU takes 6 clocks for a machine cycle.

All ports are initialized asynchronously on power-up.

XI/XO for Clock Input/Output IOCFG

User may select I/O port mapping by setting IOCFG SFR.

Two System Clock Sources : Internal Ring OSC. or External Resonator/Crystal

The Internal Ring OSC. Provides a Fixed System Clock

Resonator Oscillator Module Internal Ring Oscillator

Power-on-reset is independent of power-rising slope.

The cases of reset generation by VDD notch

WDT Run Control of WDT

In Application Programming IAP Enable Condition

IAP Related SFR 0 0 EEP0 (0x1C0 ~ 0x1FF)

Electrical Characteristic of IAP FLASH Regions

Information Region CFGWD : Configuration Word

Absolute Maximum Ratings

Recommended Operating Conditions