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Dftadvisor Tutorial

DFT Advisor is a synthesis tool capable of design rule checking, scan insertion, and test point synthesis for full scan, partial scan, partition scan, and test points. It accepts gate-level netlists and performs flattening, learning and testability analysis, design for test rule checking, scan structure identification and insertion. It generates output files including a new netlist with scan cells, a do_file for test setup, and a test procedure file. FlexTest is a tool for non-scan to full scan conversion that supports partial scan and can insert test logic on non-controllable pins. It uses proprietary sequential ATPG. FastScan is a full-scan automatic test pattern generation tool that generates test patterns for fault

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Srikiran Devarabhotla
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© Attribution Non-Commercial (BY-NC)
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769 views

Dftadvisor Tutorial

DFT Advisor is a synthesis tool capable of design rule checking, scan insertion, and test point synthesis for full scan, partial scan, partition scan, and test points. It accepts gate-level netlists and performs flattening, learning and testability analysis, design for test rule checking, scan structure identification and insertion. It generates output files including a new netlist with scan cells, a do_file for test setup, and a test procedure file. FlexTest is a tool for non-scan to full scan conversion that supports partial scan and can insert test logic on non-controllable pins. It uses proprietary sequential ATPG. FastScan is a full-scan automatic test pattern generation tool that generates test patterns for fault

Uploaded by

Srikiran Devarabhotla
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Mentor Graphics Tools for DFT

DFTAdvisor, FastScan and FlexTest

DFT Tools

Saturday, October 22, 2005

DFTAdvisor
SynthesistoolcapableofdoingDRC,ScanInsertionandTestpointSynthesis Createsadofileandatestprocedurefileafterscaninsertion Supportsidentificationandinsertionoffullscan,partialscan,partitionscanandtestpoints Supportsmuxscan,clockedscanorLSSD Supportsbothmanualandautomaticscanidentifications Acceptsmostofthegatelevelnetlistformats

DFT Tools

Saturday, October 22, 2005

DFTAdvisorwhatitdoes?
Designflattening CircuitLearning&TestabilityAnalysis DFTRulesCheck(DRC) Scanstructureidentificationandinsertion Generateoutputfiles(dofileandtestprocedurefile)

DFT Tools

Saturday, October 22, 2005

DFTAdvisoroutputfiles
Itgenerates3files: Anewnetlistwithscancellsinserted do_file,whichprovidescircuitsetupandscancircuitryinformation,usedby fastscan/flextestforAutomaticTestPatternGeneration test_procedurefile,whichcontainscyclebasedproceduresandtimingdefinitions, usedbyfastscan/flextest,tooperatethescanstructureswithinadesign

DFT Tools

Saturday, October 22, 2005

DFTAdvisorFlow

DFTAdvisor: 2. 3. 4. 5. 6. Setup DRC TestStructureIdentification TestStructureInsertion WriteResults

DFT Tools

Saturday, October 22, 2005

DFT Tools

Saturday, October 22, 2005

DFT Tools

Saturday, October 22, 2005

DFT Tools

Saturday, October 22, 2005

DFT Tools

Saturday, October 22, 2005

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DFT Tools

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DFT Tools

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DFT Tools

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

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DFT Tools

Saturday, October 22, 2005

DFTAdvisorcommandsforFullscan
SETUP> addclocks0/CK SETUP> setsystemmodedft DFT> setupscanidentificationfull_scan DFT> setuptest_pointidentificationcontrol0observe0 noverbose DFT> run DFT> inserttestlogicscanontest_pointonramon DFT> reportstatistics DFT> writenetlist/project/mtech/../s27_fs.vverilog DFT> writeatpgsetup/project/mtech/../s27_fs.v
Note:ExitofSETUPmodetriggersthreemajoroperations: 1.Flatteningofdesignmodel, 2.Performinglearninganalysisontheflattnedmodeland 3.IfthedesignpassesDRC,thesystementersintoATPGmode

procfile

PerformingDFTrulescheck.

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DFT Tools

Saturday, October 22, 2005

Fastscan
FastscanisthefullscanATPGtool Offershighfaultcoverageandgoodruntime Supportstestingofstuckatfaults,iddq,transitionfaults Automaticallygeneratestestpatterns Runspatternsforgood&faultsimulations Generatestestreports Usesrandompatternsforfaultsimulationandstopswhenapatternfailstodetectatleast0.5%of remainingfaults Andthenusesdeterministicpatternstodetectremainingfaultswhichhaveaverylowchanceofdetectionby randompatterns
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FastScanFlow

2. 3. 4. 5. 6. 7. 8.
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Setup DRC Configuration(usedefaults) PatternGeneration FaultSimulation GoodSimulation Analysisofresults


DFT Tools Saturday, October 22, 2005

Fastscanfullscancommands
SETUP> SETUP> SETUP> SETUP> ATPG> ATPG> ATPG> ATPG> ATPG> FAULT> FAULT> FAULT> FAULT> GOOD> GOOD> GOOD>
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addclocks0/CK addscangroupsgrp1/project/mtech/../s27_fs.v.testproc addscanchainschain1grp1/scan_in1/scan_out1 setsystemmodeatpg addfaultsall run reportstatistics savepatterns/project/mtech/../s27_fs.v.pattern setsystemmodefault setpatternsourceexternal/project/../s27_fs.v.patternascii run reportstatistics setsystemmodegood setpatternsourceexternal/project/../s27_fs.v.patternascii run exitdiscard
DFT Tools Saturday, October 22, 2005

Flextest
Flextestisanonscantofullscantool Itismostsuitedfortestingdesignswithfewornoinsertedteststructures Supportspartialscanandpartitionscans (partialscanisextremelyusefulinsituationswherethedesigncannotaccomodateanyextradelayaddedtothe criticalpath,duetoaddedscanelementsdelay;thoseflipflopsinthecriticalpathcanbeexcludedinthe partialscan) Automaticallygeneratestestpatterns Runspatternsforgood&faultsimulations Generatesfaultanalysisreports

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DFT Tools

Saturday, October 22, 2005

Flextesthascapabilitiesforinsertingtestlogiccircuitryonuncontrollablepinslikeset, reset,tristateenableandRAMread/writecontrols FlextestusesaproprietorysequentialATPGalgorithmcalledBACK

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DFT Tools

Saturday, October 22, 2005

DFTAdvisorcommandsforpartialscanInsertion
SETUP> addclocks0/CK SETUP> setsystemmodedft DFT> setupscanidentificationsequentialatpginternal percent90controllability100observability100 cycle16time100 DFT> DFT> DFT> DFT> DFT> DFT> setuptest_pointidentificationcontrol0observe0 noverbose run inserttestlogicscanontest_pointonramon writenetlist/project/mtech/../s27_ps.vverilog writeatpgsetup/project/mtech/../s27_ps.vprocfile exitdiscard

min_detection0.01backtrack30

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DFT Tools

Saturday, October 22, 2005

Flextestcommandsforpartialscantesting
SETUP>addclocks0/CK SETUP>addscangroupsgrp1/project/mtech/../s27_ps.v.testproc SETUP>addscanchainsgrp1/scan_in1/scan_out1 SETUP>settestcycle2 SETUP>addpinconstraints/CKSR0111 SETUP>setsystemmodedrc DRC>setsystemmodeatpg ATPG>setfaulttypestuck ATPG>addfaultsall ATPG>run ATPG>savepatterns/project/mtech/s27_ps.v.patternprofile asciicell_placementbottomparallelbegin0all_test ATPG>reportstatistics ATPG>setsystemmodefault FAULT>setpatternsourceexternal /project/mtech/../s27_ps.v.patternascii
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Flextestcommandsforpartialscantestingcontd.

FAULT> run FAULT> reportstatistics FAULT> setsystemmodegood GOOD>setpatternsourceexternal project/mtech/../s27_ps.v.patternascii GOOD> run GOOD> exitdiscard

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DFT Tools

Saturday, October 22, 2005

ThankYou!!

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DFT Tools

Saturday, October 22, 2005

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