20EC01016 Lab3

Indian Institute of Technology Bhubaneswar
VLSI Design Laboratory (EC3L009)
Lab 3 : Layout Design
Designing Layout for Circuit Schematics
Sidharth A Narayanan
1
Designing Layout for Circuit Schematics
Sidharth A Narayanan
March 22, 2023
1 Objective
To create the Layout Design for circuits from Lab Experiment 1 and compare the difference between
its Schematic simulation and its Post-Layout simulation
2 Theory
In the schematics designed in Experiment 1 we assumed that the circuit components are connected
by ideal wires with zero-resistance, it also ignores other effects like capacitance between two closely
space metal paths. Post-Layout simulation gives a more accurate estimate of how our circuit will
perform
Also Before Fabrication, the components must be physically placed and routed on the p-substrate
But there are certain Design Rules set by the limitations of the process that have to be followed
while Designing the Layout
After we perform the connection we perform an LVS check (Layout vs Schematic) to ensure that
the connection between components are properly done.
3 Specifications
3.1 Layers
• NIMP : N-type implant on p-substrate
• PIMP : P-type implant on p-substrate
• Metal: 1,2 & 3 for connections
• Cont and Via: For Connections between different layers
• Oxide : Gate Oxide for insulation
• Poly : Connecting to the Gate terminal
• Capdum : Not sure, but something to do with capacitor
2
3.2 Technology Used
– GPDK 180nm Technology Library (Instances, DRC, LVS)
– 180nm PMOS and NMOS from the above library
– pmoscap from GPDK 180nm Library
4 Design
In this report, we will only focus on how we optimized the area usage of the layout. There are various
Design Rules that has to be abided by, by taking into consideration the exact value of minimum
spacing required between various materials in the layout, we could minimize unnecessary gap in
the layout
4.1 A few DRC spacing rules

• Poly to Cont spacing ≥ 0.2µm
• Nwell to Oxide spacing ≥ 0.5µm
• Oxide to Poly spacing ≥ 0.2 µm
• Metal {1,2,3} to Metal {1,2,3} spacing ≥ 0.3µm
• Nwell to Nwell spacing ≥ 1.0µm
• Poly to Poly spacing ≥ 0.18µm
There are many more such rules, but I wouldn’t finish my report on time if I were to meticulously
go through the .drc file to list them all.
5 Voltage Transfer Characteristics of Inverter (Layout vs Schematic)

The transfer characteristics are almost the same in both cases, with the threshold voltage in each
case as
• Schematic : Vth = 875.0mV
• Layout : Vth = 874.8mV
5.1 Configuration File

• To Get the Post-Layout result, we create an ”av_extracted” view of the layout after running
DRC and LVS (using spectre template)
• Then we create a configuration file of the same name for the schematic in which we are using
the ”av_extracted” view
• We then launch ADE L, from the configuration schematic that opens up along with the config
file
3
5.2 Graphs for Single Inverter
Figure 1: Schematic Circuit for Comparing Pre vs Post-Layout Simulation
Figure 2: Input and Ouput Voltage of a CMOS inverter plotted against the input DC sweep value for
both Schematic and Post-Layout simulation (Zoomed in near Vth to emphasize the slight deviation)
4
Figure 3: Rising Delay Comparison for a single inverter driven by an ideal pulse source (1pf rise/fall
time)
Figure 4: Falling Time Delay Comparison for a single inverter driven by an ideal pulse source
6 Transient Response under Load Condition

6.1 Modular Layouts used
• Inverter
• Inverter + Capacitor
• Quad (Inverter + Capacitor)
5
Figure 5 – Layout of Inverter Figure 6 – Layout of Inverter +
Capacitor Module
6
Figure 7: Schematic of Inverter + Capacitor Module
Figure 8: Schematic of Quad Inverter + Capacitor Load Module
7
8
Figure 9: Simulating Loading Condition of the Inverter
Figure 10: Quad Inverter+Capacitor Module (used to simulate Loading)
Figure 11: Schematic of Circuit for evaluating the difference in performance of Pre and Post-Layout
level under typical load condition
9
10
Figure 12: The Entire Layout for simulating the Loading Condition
6.2 Layout Views
Figure 13 – Exposed Layout View Figure 14 – Block Diagram View of

Layout
11
Figure 15: Transient Response Comparison Under Loading Condition
Figure 16: Comparison of Rising Delay under Load Condition
Figure 17: Comparison of Falling Delay under Load Condition
12
7 Discussion
• No significant difference was observed in the value of Vth , it differed by only 0.2mV
Vth (Ideal) = 875.0mV (1)

Vth (P ost Layout) = 874.8mV (2)
• The rising and falling delay had a huge hit especially under load-condition
• Average Delay for a Single Inverter
– Time Delay for a Single Inverter (Ideal)

19.87 + 22.87
τideal = = 21.37ps (3)
2
– Time Delay for a Single Inverter (av_extracted)
21.18 + 24.12
τav = = 22.65ps (4)
2
• Average Time Delay in Loading Condition
– Time Delay (Ideal)

89.2 + 86.8
τideal = = 88.0ps (5)
2
– Time Delay (Post-Layout)
104.3 + 101.6
τav = = 102.95ps (6)
2
8 Conclusion
• An efficient layout taking into consideration the various spacing constraints was accom-
plished
• Small changes in delay time of a single inverter can add up significantly while working in
non-ideal loading conditions
• Performing Layout Design Manually is a laborious task even for small circuits
• Various cool looking plots and figures were obtained
13

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Indian Institute of Technology Bhubaneswar

VLSI Design Laboratory (EC3L009)

Lab 3 : Layout Design

Designing Layout for Circuit Schematics

March 22, 2023

• PIMP : P-type implant on p-substrate

• Metal: 1,2 & 3 for connections

• Cont and Via: For Connections between different layers

• Oxide : Gate Oxide for insulation

• Poly : Connecting to the Gate terminal

• Capdum : Not sure, but something to do with capacitor

4.1 A few DRC spacing rules

• Nwell to Oxide spacing ≥ 0.5µm

• Oxide to Poly spacing ≥ 0.2 µm

• Metal {1,2,3} to Metal {1,2,3} spacing ≥ 0.3µm

• Nwell to Nwell spacing ≥ 1.0µm

• Poly to Poly spacing ≥ 0.18µm

5 Voltage Transfer Characteristics of Inverter (Layout vs Schematic)

• Layout : Vth = 874.8mV

5.1 Configuration File

Figure 1: Schematic Circuit for Comparing Pre vs Post-Layout Simulation

6 Transient Response under Load Condition

• Quad (Inverter + Capacitor)

Figure 8: Schematic of Quad Inverter + Capacitor Load Module

Figure 13 – Exposed Layout View Figure 14 – Block Diagram View of

Figure 16: Comparison of Rising Delay under Load Condition

Figure 17: Comparison of Falling Delay under Load Condition

Vth (Ideal) = 875.0mV (1)

• Average Delay for a Single Inverter

– Time Delay for a Single Inverter (Ideal)

– Time Delay (Ideal)

• Various cool looking plots and figures were obtained

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