DM54LS181/DM74LS181 4-Bit Arithmetic Logic Unit

June 1992

DM54LS181/DM74LS181
4-Bit Arithmetic Logic Unit
General Description Features
The ’LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can Y Provides 16 arithmetic operations: add, subtract, com-
perform all the possible 16 logic operations on two variables pare, double, plus twelve other arithmetic operations
and a variety of arithmetic operations. Y Provides all 16 logic operations of two variables: exclu-
sive-OR, compare, AND, NAND, OR, NOR, plus ten
other logic operations
Y Full lookahead for high speed arithmetic operation on
long words

Connection Diagram
Dual-In-Line Package

TL/F/9821 – 1
Order Number DM54LS181J, DM54LS181W or DM74LS181N
See NS Package Number J24A, N24A or W24C

Pin Names Description

A0 – A3 Operand Inputs (Active LOW)
B0 – B3 Operand Inputs (Active LOW)
S0–S3 Function Select Inputs
M Mode Control Input
Cn Carry Input
F0– F3 Function Outputs (Active LOW)
AeB Comparator Output
G Carry Generate Output (Active LOW)
P Carry Propagate Output (Active LOW)
Cn a 4 Carry Output

C1995 National Semiconductor Corporation TL/F/9821 RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Note)
Supply Voltage 7V Note: The ‘‘Absolute Maximum Ratings’’ are those values
Input Voltage 7V beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
Operating Free Air Temperature Range
parametric values defined in the ‘‘Electrical Characteristics’’
DM74LS 0§ C to a 70§ C
table are not guaranteed at the absolute maximum ratings.
Storage Temperature Range b 65§ C to a 150§ C
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.

Recommended Operating Conditions

DM54LS181 DM74LS181
Symbol Parameter Units
Min Max Min Nom Max
VCC Supply Voltage 4.5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current b 0.4 b 0.4 mA
IOL Low Level Output Current 4 8 mA
TA Free Air Operating Temperature b 55 125 0 70 §C

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b18 mA b 1.5 V
VOH High Level Output VCC e Min, IOH e Max, DM54 2.5
V
Voltage VIL e Max DM74 2.7
VOL Low Level Output VCC e Min, IOL e Max, DM54 0.4
Voltage VIH e Min V
DM74 0.35 0.5
IOL e 4 mA, VCC e Min DM74 0.25 0.4
II Input Current @ Max VCC e Max, VI e 7V M input 0.1
Input Voltage VI e 10V (DM54) An, Bn 0.3
mA
Sn 0.4
Cn 0.5
IIH High Level Input Current VCC e Max, VI e 2.7V M input 20
An, Bn 60
mA
Sn 80
Cn 100
IIL Low Level Input Current VCC e Max, VI e 0.4V M input b 0.4
An, Bn b 1.2
mA
Sn b 1.6
Cn b 2.0

IOS Short Circuit VCC e Max

b 20 b 100 mA
Output Current (Note 2)
ICC Supply Current VCC e Max, Bn, Cn e GND DM54 35
mA
Sn, M, An e 4.5V DM74 37
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

2
Switching Characteristics:
DM54/DM74LS
Symbol Parameter Conditions CL e 15 pF Units
Min Max
tPLH Propagation Delay M e GND 27
ns
tPHL Cn to Cn a 4 20
tPLH Propagation Delay M e GND 26
ns
tPHL Cn to F 20
tPLH Propagation Delay M, S1, S2 e GND; 29
ns
tPHL A or B to G (Sum) S1, S3 e 4.5V 23
tPLH Propagation Delay M, S0, S3 e GND; 32
ns
tPHL A or B to G (Diff) S1, S2 e 4.5V 26
tPLH Propagation Delay M, S1, S2 e GND; 30
ns
tPHL A or B to P (Sum) S0, S3 e 4.5V 30
tPLH Propagation Delay M, S0, S3 e GND; 30
ns
tPHL A or B to P (Diff) S1, S2 e 4.5V 33
tPLH Propagation Delay M, S1, S2 e GND; 32
ns
tPHL Ai or Bi to Fi (Sum) S0, S3 e 4.5V 25
tPLH Propagation Delay M, S0, S3 e GND; 32
ns
tPHL Ai or Bi to Fi (Diff) S1, S2 e 4.5V 33
tPLH Propagation Delay M e 4.5V 33
ns
tPHL A or B to F (Logic) 29
tPLH Propagation Delay M, S1, S2 e GND; 38
ns
tPHL A or B to Cn a 4 (Sum) S0, S3 e 4.5V 38
tPLH Propagation Delay M, S0, S3 e GND; 41
ns
tPHL A or B to Cn a 4 (Diff) S1, S2 e 4.5V 41
tPLH Propagation Delay M, S0, S3 e GND; 50
ns
tPHL A or B to A e B S1, S2 e 4.5V; 62
RL e 2 kX to 5.0V

3
Sum Mode Test Table I Function Inputs S0 e S3 e 4.5V, S1 e S2 e M e 0V
Other Input
Input Other Data Inputs Output
Same Bit
Symbol Under Under
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH Remaining
Ai Bi None Cn Fi
tPHL A and B
tPLH Remaining
Bi Ai None Cn Fi
tPHL A and B
tPLH Remaining
A B None None P
tPHL A and B, Cn
tPLH Remaining
B A None None P
tPHL A and B, Cn
tPLH Remaining Remaining
A None B G
tPHL B A, Cn
tPLH Remaining Remaining
B None A G
tPHL B A, Cn
tPLH Remaining Remaining
A None B Cn a 4
tPHL B A, Cn
tPLH Remaining Remaining
B None A Cn a 4
tPHL B A, Cn
tPLH All All Any F
Cn None None
tPHL A B or Cn a 4

Diff Mode Test Table II Function Inputs S1 e S2 e 4.5V, S0 e S3 e M e 0V

Other Input
Input Other Data Inputs Output
Same Bit
Symbol Under Under
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH Remaining Remaining
A None B Fi
tPHL A B, Cn
tPLH Remaining Remaining
B A None Fi
tPHL A B, Cn
tPLH B Remaining
A None None P
tPHL A and B, Cn
tPLH Remaining
B A None None P
tPHL A and B, Cn
tPLH Remaining
A B None None G
tPHL A and B, Cn
tPLH Remaining
B None A None G
tPHL A and B, Cn
tPLH Remaining Remaining
A None B AeB
tPHL A B, Cn
tPLH Remaining Remaining
B A None AeB
tPHL A B, Cn
tPLH Remaining
A B None None Cn a 4
tPHL A and B, Cn
tPLH Remaining
B None A None Cn a 4
tPHL A and B, Cn
tPLH All
Cn None None None Cn a 4
tPHL A and B

4
Logic Mode Test Table III Function Inputs S1 e S2 e M e 4.5V, S0 e S3 e 0V
Other Input
Input Other Data Inputs Output
Same Bit
Symbol Under Under
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tPLH Remaining
A B None None Any F
tPHL A and B, Cn
tPLH Remaining
B A None None Any F
tPHL A and B, Cn

Functional Description
The ’LS181 is a 4-bit high speed parallel Arithmetic Logic age is required for each group of four ’LS181 devices. Carry
Unit (ALU). Controlled by the four Function Select inputs lookahead can be provided at various levels and offers high
(S0 – S3) and the Mode Control input (M), it can perform all speed capability over extremely long word lengths.
the 16 possible logic operations or 16 different arithmetic The A e B output from the device goes HIGH when all four
operations on active HIGH or active LOW operands. The F outputs are HIGH and can be used to indicate logic equiv-
Function Table lists these operations alence over four bits when the unit is in the subtract mode.
When the Mode Control input (M) is HIGH, all internal car- The A e B output is open-collector and can be wired-AND
ries are inhibited and the device performs logic operations with other A e B outputs to give a comparison for more
on the individual bits as listed. When the Mode Control input than four bits. The A e B signal can also be used with the
is LOW, the carries are enabled and the device performs Cn a 4 signal to indicate A l B and A k B.
arithmetic operations on the two 4-bit words. The device The Function Table lists the arithmetic operations that are
incorporates full internal carry lookahead and provides for performed without a carry in. An incoming carry adds a one
either ripple carry between devices using the Cn a 4 output, to each operation. Thus, select code LHHL generates A
or for carry lookahead between packages using the signals minus B minus 1 (2s complement notation) without a carry
P (Carry Propagate) and G (Carry Generate). In the ADD in and generates A minus B when a carry is applied. Be-
mode, P indicates that F is 15 or more, while G indicates cause subtraction is actually performed by complementary
that F is 16 or more. In the SUBTRACT mode, P indicates addition (1s complement), a carry out means borrow; thus a
that F is zero or less, while G indicates that F is less than carry is generated when there is no underflow and no carry
zero. P and G are not affected by carry in. When speed is generated when there is underflow. As indicated, this de-
requirements are not stringent, it can be used in a simple vice can be used with either active LOW inputs producing
ripple carry mode by connecting the Carry output (Cn a 4) active LOW outputs or with active HIGH inputs producing
signal to the Carry input (Cn) of the next unit. For high speed active HIGH outputs. For either case the table lists the oper-
operation the device is used in conjunction with the 9342 or ations that are performed to the operands labeled inside the
93S42 carry lookahead circuit. One carry lookahead pack- logic symbol.

Function Table
Mode Select Active LOW Operands Active HIGH Operands
Inputs & Fn Outputs & Fn Outputs
Logic Arithmetic** Logic Arithmetic**
S3 S2 S1 S0 (M e H) (M e L) (Cn e L) (M e H) (M e L) (Cn e H)
L L L L A A minus 1 A A
L L L H AB AB minus 1 AaB AaB
L L H L AaB AB minus 1 AB AaB
L L H H Logic 1 minus 1 Logic 0 minus 1

L H L L AaB A plus (A a B) AB A plus AB

L H L H B AB plus (A a B) B (A a B) plus AB
L H H L AZB A minus B minus 1 AZB A minus B minus 1
L H H H AaB AaB AB AB minus 1

H L L L AB A plus (A a B) AaB A plus AB

H L L H AZB A plus B AZB A plus B
H L H L B AB plus (A a B) B (A a B) plus AB
H L H H AaB AaB AB AB minus 1

H H L L Logic 0 A plus A* Logic 1 A plus A*

H H L H AB AB plus A AaB (A a B) plus A
H H H L AB AB minus A AaB (A a B) plus A
H H H H A A A A minus 1
*Each bit is shifted to the next most significant position.
**Arithmetic operations expressed in 2s complement notation.

5
Logic Symbols
Active High Operands

TL/F/9821 – 3

Active Low Operands

TL/F/9821 – 4
VCC e Pin 24
GND e Pin 12

6
 TL/F/9821 – 5
Logic Diagram

7
8
Physical Dimensions inches (millimeters)

Package (J)
Order Number DM54LS181J
NS Package Number J24A

24-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS181N
NS Package Number N24A

9
DM54LS181/DM74LS181 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) (Continued)

Package (W)
Order Number DM54LS181W
NS Package Number W24C

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