PCI 9054

Highlights PCI Bus Master I/O Accelerator Chip

■ PCIv2.2 compliant 32-bit 33MHz
Bus Master Interface Controller
enables PCI Burst Transfers up to
132Mbytes/second
Continuing our tradition of providing the world’s most advanced and highest
■ General Purpose Bus Master performance PCI-to-Local bus devices, PLX is offering the PCI 9054 Bus Master
Interface featuring an advanced
I/O Accelerator. The PCI 9054 is an ideal solution for high performance
Data Pipe Architecture™ which
Motorola MPC 850/860 PowerQUICC® designs, CompactPCI® Hot Swap adapters,
includes two DMA engines, pro-
grammable Target and Initiator PCI bus master adapters, and embedded host designs. The PCI 9054 offers a
data transfer modes and PCI variety of technological advances and features designed to simplify complex
messaging functions telecom, networking and I/O adapter embedded designs.
■ PCIv2.2 Power Management Motorola MPC 850/860 PowerQUICC Designs
Spec compatible The 3.3V PCI 9054 is a perfect match for high performance MPC 850/860 adapter
■ PCI
v2.2 Vital Product Data designs. The PCI 9054 provides an advanced Data Pipe ArchitectureTM with two
(VPD) configuration support DMA engines, an enhanced direct-connect interface to the MPC 850/860, a
■ PCI
Dual Address Cycle 50MHz Local bus, and an industrial temperature range 225-ball PBGA.
(DAC) support
CompactPCI Hot Swap Adapter Designs
■ Programmable Interrupt Generator To address the expanding CompactPCI Hot Swap market, the PCI 9054 offers a
■ Programmable Burst configurable Local Bus, unlimited bursting, and Hot Swap Friendly features like
Management the Hot Swap Configuration Register, and resources for software connection
■ SupportsType 0 and Type 1 control of the ENUM# signal, ejector switch, and the status LED.
Configuration Cycles
Additional PCI Bus Master Features
■ SupportsLocal Bus Direct-
For advanced high performance adapter designs, the PCI 9054 also offers Hot
Connect to MPC 850/860
PowerQUICC, Intel i960, and Plug compatibility, power management and incorporates PLX’s proven industry
IBM PPC 401 CPUs and similar standard I2O v1.5 Ready messaging unit.
bus protocol devices The flexible PCI 9054 local bus allows easy connection to a wide variety of
■ 3.3V,
5V Tolerant PCI signaling memory, I/O peripherals and CPUs including direct connections to the Motorola
supports Universal PCI Adapter MPC 850/860, Intel i960, IBM PPC 401 processors and many others. Take advan-
designs tage of what industry leaders already know: PLX PCI Accelerators are the solution
■ Flexible
3.3V, 5V Tolerant Local for leading telecom, networking, and I/O adapter designs.
Bus operation up to 50MHz
■ 32-BitMultiplexed, or Non-
Multiplexed Local Bus Supports
8-, 16-, and 32-Bit Peripheral
and Memory devices
■ CompactPCI Hot Swap Friendly
■I
2O v1.5 Ready Messaging Unit
■ Industrial Temp Range Operation
■ 3.3VCMOS in 176-pin PQFP
or 225-ball PBGA packages
PCI 9054 I/O Accelerator PCI Initiator 850/860 processor. The PCI 9054’s flexi-
■ Type 0 and Type 1 configuration cycles ble, 3.3V, 5V tolerant I/O buffers com-
The PCI 9054, a 32-bit 33MHz Bus
Master I/O Accelerator, is the most ■ All PCI Memory and I/O cycles supported bined with a local bus operation up to
advanced general purpose bus master ■ Initiator READ prefetching 50MHz is ideally suited for current and
device available. It offers a robust PCI v2.2 ■ Burst length control—programmable future PowerQUICC processors. The
specification implementation enabling threshold pointer PCI 9054 also provides support for the
burst transfers up to 132Mbytes/second. ■ Unaligned transfer control MPC860 IDMA channel for movement of
The PCI 9054 incorporates PLX’s industry ■ Endian swapping
data between internal MPC860 I/O and
leading Data Pipe ArchitectureTM including the PCI bus. In addition, the PCI 9054
DMA engines, programmable PCI PCI Target also makes use of the advanced Data
■ Multiple independent address spaces
Initiator and Target data transfer modes Pipe Architecture including unlimited
■ Dynamic local bus width control
and PCI messaging functions. burst capability as shown in figure 1.
■ Target READ prefetching 1 For PowerQUICC IDMA operation,
Data Pipe Architecture ™ ■ Endian swapping the PCI 9054 transfers data to PCI
■ Local bus priority control under the control of the IDMA hand-
Dual DMA Channels
■ Dual independent channels—provides ■ Latency timer shake protocol.
flexible prioritization scheme 2 At the same time, the PCI 9054 Data
PCI Messaging Pipe Architecture™ DMA can be oper-
■ Direct H/W control of DMA
■ Complete messaging unit with mailbox
ated bi-directionally, with the PCI 9054
-Demand mode DMA operation registers, doorbell registers
as the master for both buses, to manage
-Block Mode or Scatter/Gather operation ■ Queue management pointers which can
transfers of data from the local bus
be used for message passing under the
-End of Transfer (EOT) signal to the PCI bus or from the PCI bus to
I2O protocol or a custom protocol.
■ Programmable
the local bus. This is a prime example
burst length including PCI 9054 PCI Applications
unlimited burst of how the PCI 9054 provides superior
■ Shuttle High performance Motorola MPC general purpose bus master perfor-
mode DMA channel support
850/860 PowerQUICC Designs mance and gives the designer using the
—Automatic invalidation of used
A key application for the PCI 9054 is PowerQUICC processor greater flexibility
DMA descriptors
Motorola MPC 850/860 based adapters in implementing multiple simultaneous
■ Unaligned transfer support
for telecom and networking applications. I/O transfers. The PCI 9054 has unlimit-
ed bursting capability which enhances
2
any MPC860 PowerQUICC design.
High Performance CompactPCI
1 PowerQUICC Adapter Designs
MPC860 MEM Another key application for the PCI 9054
IDMA is CompactPCI adapters for telecom and
PCI 9054 2 Local Bus
I/O Accelerator networking applications. These applica-
DMA 0 tions include high performance commu-
DMA 1
nications like WAN/LAN controller cards,
ROM
high speed modem cards, frame relay
cards, and telephony cards for telecom
switches and remote access systems.
Figure 1. The PCI 9054 has intergrated key
High Performance MPC860 features to enable live-insertion of Hot
PCI Bus PowerQUICC Adapter Design Swap CompactPCI adapters. The PCI
9054 PICMG 2.1 compatible Hot Swap
■ SupportsPCI bus mastering from local These applications include high perfor- Friendly PCI interface includes both Hot
slave-only devices mance communications like WAN/LAN Swap Capable and Friendly features:
■ Scatter/Gather list management controller cards, high speed modem cards, Hot Swap Capable
-Descriptors can be in the PCI or local frame relay cards, and networking cards ■ PCI specification v2.1 or better
bus memory for routers and switches to name a few. ■ Tolerant of V
The PCI 9054 simplifies designs by pro- cc from early power
-Allows independent scatter/gather ■ Tolerant of asynchronous reset
ring management viding an industry leading enhanced
■ Tolerant of precharge voltage
direct-connect interface to the MPC
■ Haslimited I/O pin leakage at ■ Programmable Prefetch Counter-The PCI ■ PostedMemory Writes-Supports Posted
precharge voltage 9054 can be programmed to prefetch Memory Writes (PMW) for maximum
data during PCI Initiator and PCI Target performance and to avoid potential
Hot Swap Friendly
operations. The prefetch size can be deadlock situations
■ Incorporatesthe Hot Swap programmed to match the master burst
Control/Status register (HS_CSR) length or can be used as Read Ahead PCI Bus Operation
■ PCI Dual-Address Cycle (DAC)-Support

(64-bit Address Space) enables 64-bit

I/O Chips (Datacom, Telecom, Storage, etc.) addressing in 64-bit PCI host systems
■ PCI Power Management-Supports four
I/O CPU power states for PCI functions D0, D1,
PCI Bus
D2, and D3hot and the Power
Local Bus Management Event interrupt (PME#)
PCI 9054
I/O Accelerator ■ New Capabilities Structure-Supports

New Capabilities registers to define

RAM ROM additional capabilities of PCI functions

Local Bus Operation

■ Programmable Local Bus-Runs up
Figure 2. High Performance CompactPCI Adapter to 50MHz and supports non-multi-
plexed 32-bit address/data, multiplexed
■ Incorporatesan Extended Capability mode data. The PCI 9054 reads single 32-bit, and slave accesses of 8-, 16-, or
Pointer (ECP) mechanism data (8-, 16-, or 32-bit) if the master 32-bit Local Bus devices. Allows Local
■ Incorporates initiates a single cycle; otherwise, the PCI Bus bursting up to 200Mbytes/second.
added resources for soft-
ware control of ENUM#, the ejector 9054 prefetches the programmed size. ■ Three PCI-to-Local Address Spaces-The

switch, and the status LED, which indi- ■ Six

Programmable FIFOs for concurrent PCI 9054 supports three PCI-to-Local
cates to the user insertion/removal burst transactions Address spaces when the PCI 9054 is
■ Zero
in PCI Target mode. These spaces (Space
wait state burst operation
PCI Bus Embedded Host Design 0, Space 1, and Expansion ROM spaces)
■ SerialEEPROM Interface-Contains an
Another application for the PCI 9054 is allow any PCI Bus Master to access
interface for an optional serial EEPROM the local memory spaces with program-
PCI host embedded system designs such
that can be used to load configuration mable wait states, bus width, and burst
as network switches and routers, printer
information. The PCI 9054 can also be capabilities.
engines, set-top boxes and industrial configured by a local CPU.
equipment. In this configuration, the PCI ■ Clock-The Local Bus interface runs from
9054 Data Pipe Architecture allows high a local TTL clock and asserts the neces- Figure 3.
performance transfer modes. In addition, sary internal clocks. This clock runs PCI Bus Embedded
the PCI 9054 supports both Type 0 and asynchronously to the PCI clock. Host Design
Type 1 PCI configuration cycles which ■ Big/LittleEndian Conversion-Supports
allows the PCI 9054 to configure other dynamic switching between Big
PCI devices or cards in the system. Endian and Little m, Storage, et
c.)
acom, Teleco
Endian data for PCI I/O Chips (Dat
Additional Features Initiator, PCI Target, I/O
CPU I/O
DMA, and internal
General Purpose Bus Master Operation register accesses on
■ Advanced Data Pipe Architecture
the Local Bus
includes DMA engines, PCI Initiator, PCI Local Bus
■ Fullysupports the
Target, and PCI messaging functions. PCI 9054
Vital Product or
■ Dual independently programmable I/O Accelerat I/O
Data (VPD) PCI MEM
Data Pipe Architecture DMA engines extension-Provides
with programmable FIFOs. Each channel an alternate access
supports block and scatter/gather method other than
DMA modes. Expansion ROM for PCI Bus PCI I/O
■ 5V Tolerant Operation-The PCI 9054 Vital Product Data
requires 3.3 Vcc. It provides 3.3V signal- ■ InterruptGenerator-
ing with 5V I/O tolerance on both the Can assert PCI and local PCI Slots
PCI and Local Buses. interrupts from external
and internal sources
 Internal
Registers
PCI Config
Local Config Serial
Run-Time EEPROM
DMA Initialization
I2O Messaging

PCI Bus Local Bus

State State
Machines FIFOs Machines
PCI Initiator Dir. Master Write Local Slave

Local Bus
(For Direct (for Direct
PCI Bus

Local Bus
Master Xfers) Dir. Master Read Master Xfers) Interface:

PCI Bus PCI Initiator Local Master – Dynamic Bus

DMA 0 PCI-Loc Width 8,16
Interface (for Ch 0/1 (for Ch 0/1
DMA Xfers) DMA Xfers) or 32-bit
DMA 1 PCI-Loc
– Endian
Conversion
PCI Target Read
Dir. Slave Write Local Master
(For Direct (for Direct – Muxed or
Slave Xfers) Slave Xfers) non-Muxe
Dir. Slave Read Addr/Data

Control I20 Messaging DMA DMA Scatter/Gather Unaligned Xfer

Logic

PCI 9054 Internal Block Diagram

Development Tool Support enable designers to quickly bring new through standard APIs, I 2O messaging
PLX recognizes that software often repre- designs to production without worrying protocols, PCI debug tools, and example
sents the largest investment in develop- about the complexities of implementing drivers.
ment. The PCI 9054 is supported by a PCI and I 2O. PCI 9054 design support is provided
variety of development tools designed The PCI 9054 is fully compatible through RDKs which provide a flexible
to assist the designer in the form of with PLX’s PCI SDK and I 2O SDK PCI development board, complete with
Reference Design Kits (RDK), and software development kits which allow Orcad schematics, documentation,
Software Design Kits (SDK). These Kits quick and easy development of high per- and software.
formance local and host PCI software

Product Ordering Information

PCI 9054-AC50BI PCI to Local Bus Master I/O Accelerator Chip PBGA Package
PLX Technology, Inc.
PCI 9054-AC50BI F PCI to Local Bus Master I/O Accelerator Chip PBGA Package (Lead-Free)
870 Maude Ave.
Sunnyvale, CA 94085 USA PCI 9054-AC50PI PCI to Local Bus Master I/O Accelerator Chip PQFP Package
Tel: 1-800-759-3735 PCI 9054-AC50PI F PCI to Local Bus Master I/O Accelerator Chip PQFP Package (Lead-Free)
Tel: 1-408-774-9060 CompactPCI 9054RDK-86 PCI 9054 Reference Design Kit with Motorola MPC860 PowerQUICC CPU
Fax: 1-408-774-2169 PCI SDK PCI Software Development Kit for Motorola MPC860 PowerQUICC CPU
Email: info@plxtech.com I2O SDK I2O Software Development Kit for Motorola MPC860 PowerQUICC CPU
Web Site: www.plxtech.com

© 2001 PLX Technology, Inc. All rights reserved. PLX and PLXMon are trademarks of PLX Technology, Inc. All other product names that appear in this material are for identification purposes only and are acknowledged to be
trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and r eliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this
material. PLX Technology reserves the right, without notice, to make changes in product design or specification. .

9054-SIL-PB-P2-2.0 6/00 4K