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    Dpco Iat 1 QP Set1

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    Laks Sadeesh
    This document contains an internal assessment test for a Digital Principles and Computer Organization course. The test has 3 parts: Part A contains 10 multiple choice questions worth 2 marks each, Part B contains 5 questions worth 13 marks each, and Part C contains 2 questions worth 15 marks each. The test focuses on analyzing and designing combinational and sequential circuits (CO1 and CO2). It contains questions on topics like half and full adders, decoders, multiplexers, flip-flops, counters, and Boolean algebra minimization. The test assesses different levels of learning from remembering to creating, as per Bloom's taxonomy.

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    Dpco Iat 1 QP Set1

    Uploaded by

    Laks Sadeesh
    133 views2 pages
    This document contains an internal assessment test for a Digital Principles and Computer Organization course. The test has 3 parts: Part A contains 10 multiple choice questions worth 2 marks each, Part B contains 5 questions worth 13 marks each, and Part C contains 2 questions worth 15 marks each. The test focuses on analyzing and designing combinational and sequential circuits (CO1 and CO2). It contains questions on topics like half and full adders, decoders, multiplexers, flip-flops, counters, and Boolean algebra minimization. The test assesses different levels of learning from remembering to creating, as per Bloom's taxonomy.

    Original Description:

    unit 1 digital qp

    Original Title

    DPCO IAT 1 QP SET1

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    This document contains an internal assessment test for a Digital Principles and Computer Organization course. The test has 3 parts: Part A contains 10 multiple choice questions worth 2 marks each, Part B contains 5 questions worth 13 marks each, and Part C contains 2 questions worth 15 marks each. The test focuses on analyzing and designing combinational and sequential circuits (CO1 and CO2). It contains questions on topics like half and full adders, decoders, multiplexers, flip-flops, counters, and Boolean algebra minimization. The test assesses different levels of learning from remembering to creating, as per Bloom's taxonomy.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    133 views2 pages

    Dpco Iat 1 QP Set1

    Uploaded by

    Laks Sadeesh
    This document contains an internal assessment test for a Digital Principles and Computer Organization course. The test has 3 parts: Part A contains 10 multiple choice questions worth 2 marks each, Part B contains 5 questions worth 13 marks each, and Part C contains 2 questions worth 15 marks each. The test focuses on analyzing and designing combinational and sequential circuits (CO1 and CO2). It contains questions on topics like half and full adders, decoders, multiplexers, flip-flops, counters, and Boolean algebra minimization. The test assesses different levels of learning from remembering to creating, as per Bloom's taxonomy.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    SET1

    DMI COLLEGE OF ENGINEERING


    DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
    INTERNAL ASSESSMENT TEST – I (2022-2023 –ODD SEM)
    IInd Year/ IIIrd Semester
    CS3352 – DIGITAL PRINCIPLES AND COMPUTER ORGANISATION

    DATE: TIME: 09.20 AM To 12.20 PM Max. : 100 Marks


    COURSE OUTCOMES:

    CO1: To analyze and design combinational circuits.


    CO2: To analyze and design sequential circuits
    Blooms Taxonomy:
    K1- Remembering, K2-Understanding, K3- Applying, K4-Analyzing, K5-Evaluating, K6-Creating

    Part – A (10*2=20)

    1 Define Half – subtractor CO1 K1

    2 List the steps of Analysis procedure CO1 K1

    Draw the truth table for 2-bit Magnitude comparator CO1 K2


    3
    4 Define Prime Implicant CO1 K1

    5 What is meant by decoder? CO1 K1

    6 Draw the Excitation table of JK Flip - flop CO2 K1

    7 Give the differences between combinational circuits and sequential circuits CO2 K1

    8 What is Synchronous counter? CO2 K1

    9 Draw the logic diagram of SK Flip flop CO2 K2

    10 Mention the types of Triggering Flip flops CO2 K1


    Part – B (5*13=65)

    11.a Define Design procedures with suitable example and logic diagrams CO1 K1
    Or
    11.b Explain in detail about half adder and full adder with CO1 K2
    logic diagram.
    12.a Explain in detail about Decoder and its types with suitable logic CO1 K1
    diagrams
    Or
    12.b Minimize the expression CO1 K3
    F (A, B, C, D) = Σm (1, 3, 7, 11, 15) + Σd (0, 2, 4) -draw the logic diagram
    13.a Simplify the following and draw logic diagram CO1 K3
    F (A, B, C) = Σm (1, 3, 6, 7)
    F (A, B, C, D) = Σm (0, 2, 3, 7, 11, 13, 14, 15)
    Or
    13.b Explain in detail about Demultiplexers CO1 K2
    14.a Explain in detail about SR Flip flop and D flip flop CO2 K1
    DMI College of Engineering Page 1 Chennai-600123
    Or CO2 K1
    14.b Develop a Modulo-4 Synchronous counter using JK Flip Flop CO2 K1
    CO2 K1

    15.a Convert JK Flip flop into D flip flop CO2 K2


    Or

    15.b Convert JK FF into SR FF CO2 K5

    Part C (1*15=15)

    16.a . Simply the Boolean Function Using Four Variable K-Maps


    F(W,X,Y,Z) = ∑ (0,1,2,4,5,6,8,9,12,13,14) CO1 K3
    Or
    16.b Develop a 4-bit Synchronous counter using JK Flip Flop CO2 K3

    SUBJECT IN-CHARGE HOD

    DMI College of Engineering Page 2 Chennai-600123

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