Ssc1s312a Ds Enm

Quasi-Resonant Off-Line Switching Control ICs
SSC1S310A Series Data Sheet

C5
Description D1 T1 D4
L1
VOUT
VAC
P
SSC1S310A series is the controller ICs of a quasi- C1 R6
R9
PC1
resonant mode for a switching power supplies. The IC D3 R5 C6
R10
R7
incorporates a startup circuit and a standby function to CV Q1 S C8
R4 RST C7 R8
reduce a power consumption and standby power. In R3
R12
U2
R11
normal operation, the quasi-resonant mode operation C9
8 7 6 5
D2 R2
D
achieves high efficiency and low noise. In addition, in GND VCC OCP DRV
C2 GND
U1
medium to low load conditions, the operation mode is SSC1S310A DZBD
automatically changes the quasi-resonant mode to the FB/OLP BD

1 2
ST
4
RBD1
bottom-skip mode to improve efficiency. The IC is ROCP

R1 RBD2
provided in the SOIC8 package. The power supply that C3 PC1
CBD
C4
is a low component counts and a high performance-to-
cost can be achieved by the rich set of protection
features. Packages
SOIC8
Features
● Multi-Mode Control
(High efficiency operation in all range of loads)
● Automatic Standby Function
(Standby power is inproved by burst oscillation mode)
● Input Power at No Load:
Not to scale
<30mW at 100 VAC
<50mW at 230 VAC
● Bottom-Skip Function Specifications
(Switching loss in medium to low loads is reduced) ● VCC Maximum rating: 35 V
● Step-on Burst Oscillation Function ● Operation Start Voltage,VCC(ON): 15.1 V (typ.)
(Transformer audible noises are reduced) ● PWM Operation Frequency, fOSC: 21.0 kHz (typ.)
● Bias Assist Function ● Maximum On-time, tON(MAX): 40.0 µs (typ.)
● Soft-Start Function
● Adjustable Startup Voltage
Selection Guide
● Maximum On-time Limitation Function
● VCC Operational Range Expanded Protection Operation
Part Number
● Leading Edge Blanking (LEB) Function (OVP, OLP, TSD)
(External Filter Components are reduced) SSC1S311A Auto-restart
● Protection Functions
Overcurrent Protection (OCP): Pulse-by-pulse SSC1S312A Latched Shutdown
Overvoltage Protection (OVP)
Overload Protection (OLP)
Thermal Shutdown (TSD) Applications
Typical Application ● Digital Appliance
● Office Automation (OA) Equipment
● White Goods
● Industrial Apparatus
● Communication Facilities
SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 1

May 24, 2022 https://www.sanken-ele.co.jp/en
© SANKEN ELECTRIC CO., LTD. 2012
SSC1S310A Series
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 3
2. Electrical Characteristics -------------------------------------------------------------------------------- 3
3. Block Diagram --------------------------------------------------------------------------------------------- 5
4. Pin Configuration Definitions --------------------------------------------------------------------------- 5
5. Typical Applications -------------------------------------------------------------------------------------- 6
6. Physical Dimensions -------------------------------------------------------------------------------------- 7
7. Marking Diagram ----------------------------------------------------------------------------------------- 7
8. Operational Description --------------------------------------------------------------------------------- 8
8.1. Startup Operation ----------------------------------------------------------------------------------- 8
8.1.1. Startup Period --------------------------------------------------------------------------------- 8
8.1.2. Undervoltage Lockout (UVLO) Circuit --------------------------------------------------- 8
8.1.3. Bias Assist Function--------------------------------------------------------------------------- 8
8.1.4. Auxiliary Winding ---------------------------------------------------------------------------- 9
8.1.5. Soft-Start Function -------------------------------------------------------------------------- 10
8.1.6. Operational Mode at Startup ------------------------------------------------------------- 10
8.2. Constant Voltage Control Operation ---------------------------------------------------------- 11
8.3. Quasi-Resonant Operation and Bottom-On Timing --------------------------------------- 12
8.3.1. Quasi-Resonant Operation ---------------------------------------------------------------- 12
8.3.2. Bottom-On Timing -------------------------------------------------------------------------- 12
8.3.3. BD Pin Blanking Time --------------------------------------------------------------------- 14
8.3.4. Bottom Skip Quasi-Resonant Operation ----------------------------------------------- 15
8.4. Auto Standby Function--------------------------------------------------------------------------- 16
8.5. Overvoltage Protection (OVP) ------------------------------------------------------------------ 17
8.6. Overload Protection (OLP) ---------------------------------------------------------------------- 17
8.7. Thermal Shutdown (TSD) ----------------------------------------------------------------------- 18
8.8. Overcurrent Protection (OCP) ----------------------------------------------------------------- 19
8.8.1. Overcurrent Input Compensation Function ------------------------------------------- 19
8.8.2. Reference BD Pin Peripheral Components Setting ----------------------------------- 21
8.8.3. Reference Example of No Overcurrent Input Compensation Required ---------- 21
8.9. Maximum On-Time Limitation Function ---------------------------------------------------- 21
8.10. DRV Pin Peripheral Components -------------------------------------------------------------- 22
9. Design Notes ---------------------------------------------------------------------------------------------- 22
9.1. Peripheral Components -------------------------------------------------------------------------- 22
9.2. Transformer Design ------------------------------------------------------------------------------ 22
9.3. Protection against Negative Input Voltage at Start-up Pin ------------------------------- 24
9.4. Phase Compensation ------------------------------------------------------------------------------ 24
9.5. PCB trace layout and Component placement ----------------------------------------------- 24
Important Notes ---------------------------------------------------------------------------------------------- 26

SSC1S310A Series
1. Absolute Maximum Ratings

Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming out
of the IC (sourcing) is negative current (−).
Unless otherwise specified, TA = 25 °C.
Parameter Symbol Conditions Pins Rating Unit
Supply Voltage of Control Part VCC 7−8 35 V
Startup Pin Voltage VST 4−8 −0.3 to 600 V
OCP Pin Voltage VOCP 6−8 −2.0 to 6.0 V
FB Pin Voltage VFB 1−8 −0.3 to 7.0 V
FB Pin Current IFB 1−8 10.0 mA
BD Pin Voltage VBD 2−8 −6.0 to 6.0 V
Allowable Power Dissipation PD ― 0.14 W
Operating Ambient Temperature TOP ― −40 to 125 °C
Storage Temperature Tstg ― −40 to 125 °C
Junction Temperature Tj ― 150 °C
2. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming out
of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 20 V.
Parameter Symbol Conditions Pins Min. Typ. Max. Unit
Power Supply Startup Operation

Operation Start Voltage VCC(ON) 7−8 13.8 15.1 17.3 V
Operation Stop Voltage (1)
VCC(OFF) 7−8 8.4 9.4 10.7 V
Circuit Current in Operation ICC(ON) 7−8 ― 1.3 3.7 mA
Circuit Current in Non-Operation ICC(OFF) VCC = 13 V 7−8 ― 4.5 50 μA
Startup Circuit Operation Voltage VSTART(ON) 4−8 18 21 24 V
Startup Current ICC(STARTUP) VCC = 13 V 7−8 −4.5 −3.1 −1.0 mA
Startup Current Supply Threshold
VCC(BIAS) 7−8 9.5 11.0 12.5 V
Voltage(1)
PWM Operation Frequency fOSC 5−8 18.4 21.0 24.4 kHz
Soft-Start Operation Period tSS 5−8 ― 6.05 ― ms
Normal Operation
Bottom-Skip Operation Threshold
VOCP(BS1) 6−8 0.487 0.572 0.665 V
Voltage 1
Bottom-Skip Operation Threshold
VOCP(BS2) 6−8 0.200 0.289 0.380 V
Voltage 2
Quasi-Resonant Operation Threshold
VBD(TH1) 2−8 0.14 0.24 0.34 V
Voltage 1(2)
(1)
VCC(BIAS) > VCC(OFF)
(2)
VBD(TH1) > VBD(TH2)

SSC1S310A Series
Parameter Symbol Conditions Pins Min. Typ. Max. Unit

Quasi-Resonant Operation Threshold
VBD(TH2) 2−8 0.07 0.17 0.27 V
Voltage 2(2)
Maximum Feedback Current IFB(MAX) 1−8 −320 −205 −120 μA
Standby Operation
Standby Operation Threshold Voltage VFB(STBOP) 1−8 0.45 0.80 1.15 V
Protection Operation
Maximum On-time tON(MAX) 5−8 30.0 40.0 50.0 µs
Leading Edge Blanking Time tBW 5−8 ― 495 ― ns
Overcurrent Detection Threshold Voltage
VOCP(H) 6−8 0.820 0.910 1.000 V
(Normal Operation)
Overcurrent Detection Threshold Voltage
VOCP(L) VBD = −3 V 6−8 0.560 0.660 0.760 V
(Input Compensation in Operation)
BD Pin Current IBD(O) VBD = −3 V 2−8 −250 −83 −30 μA
OLP Bias Current IFB(OLP) VFB/OLP = 5V 1−8 −15 −10 −5 μA
OLP Threshold Voltage VFB(OLP) 1−8 5.50 5.96 6.40 V
Circuit Current after OLP ICC(OLP) 7−8 ― 575 ― μA
VCC Pin OVP Threshold Voltage VCC(OVP) 7−8 28.5 31.5 34.0 V
FB Pin Maximum Voltage in Feedback IFB = −12
VFB(MAX) 1−8 3.70 4.05 4.40 V
Operation µA
Thermal Shutdown Temperature Tj(TSD) ― 135 ― ― °C
Drive Circuit
DRV Pin Output Voltage VDRV 5−8 7.5 8.1 8.7 V
DRV Pin Source Current (Peak) IDRV(SO) 5−8 ― −150 ― mA
DRV Pin Sink Current (Peak) IDRV(SI) 5−8 ― 608 ― mA
Thermal Characteristics
Thermal Resistance θj-A ― ― ― 180 °C /W

SSC1S310A Series
3. Block Diagram
VCC 7 Startup 4 ST
3 1
DRV 5 DRV
2
UVLO
Reg/Iconst
OCP/BS 6 OCP
2
Logic
FB/STB
OLP 1 FB/OLP
OSC 5
GND 8 BD 2 BD
4 6
4. Pin Configuration Definitions

Number Name Function
FB/OLP 1 8 GND Constant voltage control, standby control, and
1 FB/OLP
Overload detection signal input
BD 2 7 VCC Bottom detection and input compensation signal
2 BD
input
3 6 OCP 3 ― (Pin removed)
ST 4 5 DRV 4 ST Startup current input
5 DRV Gate drive output
6 OCP Overcurrent detection signal input
Supply voltage input and overvoltage detection
7 VCC
signal input
8 GND Ground

SSC1S310A Series
5. Typical Applications
The startup voltage of Figure 5-1 is about 21 V which is Startup Circuit Operation Voltage, VSTART(ON). When the
startup voltage increases more than this, Figure 5-2 is available, adding DZST in series with the ST pin.
The startup voltage after adding DZST, VSTART(ON)’ is calculated as follows:
VSTART(ON) ′ = VSTART(ON) + VZST (1)
where:
VSTART(ON) is the Startup Circuit Operation Voltage, about 21 V, and
VZST is the zener voltage of DZST.
C5
L1
D1 T1 D4 VOUT
VAC
P
R9
C1 R6
PC1
R10
D3 R5 C6
Q1 S R7 C8
CV
RST
R4 C7 R8
R3
R12
U2
C9 D2 R2 R11
8 7 6 5
D
C2 GND
GND VCC OCP DRV
U1
SSC1S310A DZBD
FB/OLP BD ST
RBD1
1 2 4
ROCP
R1 RBD2
CBD
C3 PC1
C4
Figure 5-1. Application Circuit Example 1
C5
L1
D1 T1 D4 VOUT
VAC
P
R9
DZST
C1 R6
PC1
R10
D3 R5 C6
Q1 S R7 C8
CV
RST
R4 C7 R8
R3
R12
U2
C9 D2 R2 R11
8 7 6 5
D
C2 GND
GND VCC OCP DRV
U1
SSC1S310A DZBD
FB/OLP BD ST
RBD1
1 2 4
ROCP
R1 RBD2
CBD
C3 PC1
C4
Figure 5-2. Application Circuit Example 2 (Adjustable Startup Voltage)

SSC1S310A Series
6. Physical Dimensions
NOTES:
- Dimensions in millimeters
- Pb-free
7. Marking Diagram
8
SC1S31x
Part Number
SKYMD A
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
1 M is the month of the year (1 to 9, O, N, or D)
D is the period of days represented by:
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the month (21st to 31st)
Control Number

SSC1S310A Series
8. Operational Description ICC, increases. In operation, when the VCC pin voltage
decreases to VCC(OFF) = 9.4 V, the control circuit stops
All the characteristic values given in this section are operation, by the UVLO (Undervoltage Lockout) circuit,
typical values, unless they are specified as minimum or and reverts to the state before startup.
maximum. Current polarities are defined as follows: The voltage rectified the auxiliary winding voltage,
current going into the IC (sinking) is positive current VD, in Figure 8-1 becomes a power source to the control
(+); current coming out of the IC (sourcing) is negative circuit after the operation start.
current (−). The VCC pin voltage should become as follows
within the specification of input voltage range and the
output load range of power supply, taking account of the
8.1. Startup Operation winding turns of the D winging. The target voltage of
the VCC pin voltage is about 20 V.
8.1.1. Startup Period VCC(BIAS) (max. ) < VCC < VCC(OVP) (min. )
Figure 8-1 shows VCC pin peripheral circuit.

The built-in startup circuit is connected to the ST pin,
→12.5 V < VCC < 28.5𝑉 (3)
and it generates a constant current, ICC(STARTUP) = –3.1
mA, to charge capacitor C2 connected to the VCC pin.
During this process, when the VCC pin voltage reaches
VCC(ON) = 15.1 V, the control circuit starts operation. Circuit current, ICC
After that, the startup circuit stops automatically, in
order to eliminate its own power consumption.
The approximate startup time, tSTART, is calculated as
follows:
Start
Stop
VCC(ON) − VCC(INT)
t START = C2 × (2)
|ICC(STARTUP) |
VCC pin voltage
where: VCC（OFF） VCC（ON）
tSTART is the startup time in s, and
VCC(INT) is the initial voltage of the VCC pin in V.
Figure 8-2. VCC vs. ICC
D1
T1
VAC 8.1.3. Bias Assist Function
RST C1 P Figure 8-3 shows the VCC pin voltage behavior
during the startup period. When the VCC pin voltage
reaches VCC(ON) = 15.1 V, the control circuit starts
4 operation, the circuit current, ICC, increases, and thus the
ST VCC pin voltage begins dropping. At the same time, the
D2 R2
7 auxiliary winding voltage, VD, increases in proportion to
VCC the output voltage rise. Thus, the VCC pin voltage is set
U1 by the balance between dropping by the increase of ICC
C2 VD
and rising by the increase of the auxiliary winding
8 D voltage, VD.
GND
Just at the turning-off of the power MOSFET, a surge
voltage occurs at the output winding. If the feedback
control is activated by the surge voltage under light load
Figure 8-1. VCC Pin Periheral Circuit condition at startup, and the VCC pin voltage decreases
to VCC(OFF) = 9.4 V, a startup failure can occur, because
the output power is restricted and the output voltage
8.1.2. Undervoltage Lockout (UVLO) decreases. In order to prevent this, during a state of
Circuit operating feedback control (that is, the FB/OLP pin
voltage is VFB(STBOP) = 0.8 V or less), when the VCC pin
Figure 8-2 shows the relationship of VCC and ICC. voltage falls to the Startup Current Supply Threshold
When the VCC pin voltage increases to VCC(ON) = 15.1 V, Voltage, VCC(BIAS) = 11.0 V, the bias assist function is
the control circuit starts operation and the circuit current, activated. While the bias assist function is operating, the

SSC1S310A Series
decrease of the VCC pin voltage is suppressed by D2 R2

providing the startup current, ICC(STARTUP), from the
Startup circuit. By the bias assist function, the use of a
7
small value C2 capacitor is allowed, resulting in
shortening startup time. Also, because the increase of VCC Added
D
VCC pin voltage becomes faster when the output runs U1 C2
with excess voltage, the response time of the
overvoltage protection can also be shortened. It is GND
required to check and adjust the process so that poor 8
starting conditions may be avoided.
VCC pin voltage IC startup Startup success
Target operating voltage

Figure 8-5. VCC pin peripheral circuit with R2
VCC(ON)= 15.1V Increasing by output voltage rising
VCC(BIAS)= 11.0V
Bias Assist period The variation of VCC pin voltage becomes worse if:
VCC(OFF)= 9.4V
● The coupling between the primary and secondary
Startup failure
windings of the transformer gets worse and the surge
voltage increases (low output voltage, large current
load specification, for example).
Time
● The coupling of the auxiliary winding, D, and the
secondary side stabilization output winding (winding
Figure 8-3. VCC during Startup Period of the output line which is controlling constant
voltage) gets worse and it is subject to surge voltage.
8.1.4. Auxiliary Winding

In order to reduce the influence of surge voltages on
In actual switch-mode power supply (SMPS) circuits, the VCC pin, alternative structures of the auxiliary
there are cases in which the VCC pin voltage fluctuates winding, D, can be used as examples of transformer
in proportion to the output of the SMPS (see Figure 8-4), structural designs see Figure 8-6.
and the Overvoltage Protection (OVP) on VCC pin may
be activated.
This happens because C2 is charged to a peak voltage ● Winding structural example (a)
on the auxiliary winding D, which is caused by the - Separating the auxiliary winding D from the primary
transient surge voltage coupled from the primary side windings P1 and P2.
winding when the power MOSFET turns off. - The primary side winding is divided into two
For alleviating C2 peak charging, it is effective to add windings, P1 and P2.
some value R2, of several tenths of ohms to several
ohms, in series with D2 (see Figure 8-5). The optimal
value of R2 should be determined using a transformer ● Winding structural example (b)
matching what will be used in the actual application,
because the variation of the auxiliary winding voltage is - Placing the auxiliary winding D within the secondary
affected by the transformer structural design. winding S1 in order to improve the coupling of those
windings.
- The output winding S1 is a stabilized output winding
VCC pin voltage Without R2
controlled to constant voltage.
With R2
Output current, IOUT
Figure 8-4. VCC versus IOUT with/without resistor R2

SSC1S310A Series
Core Bobbin Core Bobbin

Barrier tape Barrier tape
P1 S1 P2 S2 D P1 S1 D S2 S1 P2
Barrier tape Barrier tape
Pin side Pin side

Winding Structure Example (a) Winding Structure Example (B)
P1, P2: Primary winding

S1: Secondary winding of which the output voltage is controlled constant
S2: Secondary winding
D: Auxiliary winding for VCC
Figure 8-6. Winding Structure Example
8.1.5. Soft-Start Function 8.1.6. Operational Mode at Startup

Figure 8-7 shows the behavior of VCC pin voltage As shown in Figure 8-7 because the auxiliary winding
and the drain current during the startup period. voltage is low at startup, there is a certain period when
The IC activates the soft-start function during the the quasi-resonant signal has not yet reached a regulated
startup period. The soft-start operation period, tSS, is level (Quasi-Resonant Operation Threshold Voltage 1,
internally set to 6.05 ms, and the overcurrent protection VBD(TH1), is 0.24 V or more, and the effective pulse width
(OCP) threshold voltage steps up in four steps during for the quasi-resonant signal is 1.0μs or more). During
this period. This reduces the voltage and current stress this period, the operation is in PWM operation with
on the power MOSFET and on the secondary-side PWM operation frequency of fOSC = 21.0 kHz. Then,
rectifier. During the soft-start operation period, the when the output voltage rises, the auxiliary winding
operation is in PWM operation with PWM operation voltage will rise, and when a quasi-resonant signal
frequency of fOSC = 21.0 kHz. In addition, because the reaches the regulated level, quasi-resonant operation will
soft-start operation period is fixed internally, it is begin. In addition, during the soft-start operation period,
necessary to confirm and adjust the VCC pin voltage tSS, the operation is in PWM operation, even if the quasi-
and the overload protection (OLP) delay time during resonant signal reaches the regulated level.
startup, based on actual operation in the application.
Startup Steady operation

VCC pin voltage
VCC(ON)
VCC(OFF)
Time PWM operation Quasi-resonant operation

BD pin voltage A
VBD(TH1)
Time Pulse width 1.0µs(MIN)

Drain current,
ID BD pin waveform expanded at point A
Time
Soft-Start Operation Period, tSS=6.05ms
Operation mode
Quasi-resonant operation
PWM operation
（fOSC=21.0kHz）
Figure 8-7. Operational Mode in Startup

SSC1S310A Series
8.2. Constant Voltage Control Operation In the current-mode control method, the FB
comparator and/or the OCP comparator may respond to
The constant output voltage control function uses the the surge voltage resulting from the drain surge current
current mode control (peak current mode), which in turning-on the power MOSFET, and may turn off the
enhances response speed and provides stable operation. power MOSFET irregularly. Leading Edge Blanking,
This IC compares the voltage, VROCP, of a current tBW = 495 ns, is built-in to prevent these comparators
detection resistor with the target voltage, VSC, by the from malfunction caused by the surge voltage resulting
internal FB comparator, and controls the peak value of from turning-on the power MOSFET.
VROCP so that it gets close to VSC. VSC is internally As shown in Figure 8-10, when the power MOSFET
generated from the FB/OLP pin voltage (see Figure 8-8 turns on, if the drain current surge pulse width is large,
and Figure 8-9). the following adjustments are required so that the surge
pulse width falls within tBW.
● Light Load Conditions
When load conditions become lighter, the output
voltage, VOUT, rises, and the feedback current from the ● For the PCB trace layout of the current detection
error amplifier on the secondary side also increases. The resistor, ROCP, See Section 9.5.
feedback current is sunk at the FB/OLP pin, transferred ● Match the turn-on timing to a VDS bottom point.
through a photo-coupler, PC1, and the FB/OLP pin ● Lower the value of the voltage resonant capacitor, CV,
voltage decreases. Thus, VSC decreases and the peak and the value of the capacitor in the secondary side
value of VROCP are controlled to be low, and the peak snubber circuit.
drain current of ID decreases. This control prevents the ● Add a CR filter with R12 and C9 to the OCP pin as
output voltage from increasing. shown in Figure 8-8.
The CR filter should be determined according to the
● Heavy Load Conditions surge voltage level. It is necessary to check and adjust
When load conditions become greater, the control the CR filter values because they change the OCP
circuit performs the inverse operation to that described detection level and the load condition switched to
above. Thus, VSC increases and the peak drain current of burst oscillation mode at standby.
ID increases. This control prevents the output voltage When the CR filter is unnecessary, make R12 short
from decreasing. and C9 open.
When it is added, the target value of R12 is 100 to
330Ω, and that of C9 is 470pF to 680pF.
U1 VOCP(H)' of Figure 8-10 is the overcurrent detection
Q1 threshold voltage after input compensation in Section
OCP GND FB/OLP 8.8.
R12 6 8 1
tBW
PC1
ROCP C9 VOCP(H)'
VROCP IFB
C3
Figure 8-8. FB/OLP Peripheral Circuit
Target voltage Surge voltage width in

turning-on
+ VSC
- VROCP Figure 8-10. OCP Pin Voltage Waveform
FB comparator OCP pin voltage
Drain current,
ID
Figure 8-9. Drain Current, ID, and FB Comparator

Operation in Normal Operation

SSC1S310A Series
8.3. Quasi-Resonant Operation and

Bottom-On Timing tONDLY : Half cycle of free oscillation
8.3.1. Quasi-Resonant Operation

Figure 8-11 shows the circuit of a flyback converter. EFLY
A flyback converter is a system which transfers the
energy stored in the transformer to the secondary side EIN
when the primary side power MOSFET is turned off. VDS 0
After the energy is completely transferred to the Bottom point
secondary, when the MOSFET keeps turning off, the
MOSFET drain node begins free oscillation based on the
LP of the transformer and CV across the drain and source IOFF 0
pins. The quasi-resonant operation is the VDS bottom-on
operation that turns-on the MOSFET at the bottom point
of VDS free oscillation. Figure 8-12 shows an ideal VDS
waveform during bottom-on operation. Using bottom-on ID 0
operation, switching loss and switching noise are
reduced and it is possible to obtain converters with high tON
efficiency and low noise. This IC performs bottom-on
operation not only during normal quasi-resonant Figure 8-12. Ideal bottom-on operation waveform
operation, but also during bottom-skip quasi-resonant (Power MOSFET turn-on at a bottom point of a VDS
operation. This allows reduction of the operation waveform)
frequency during light load conditions, to improve
efficiency across the full range of loads.
8.3.2. Bottom-On Timing
VF
NP T1 NS D4 Figure 8-13 shows the voltage waveform of the BD
VOUT
LP pin peripheral circuit and auxiliary winding, D.
EFLY The following setup is required with the BD pin.
P S IOFF C6
ID
EIN ● Bottom-on timing setup (described here, below)
● OCP input compensation value setup (see Section 8.8)
C1
CV The components DZBD, RBD1, RBD2, and CBD, are
connected to the BD pin peripheral circuit as shown in
Figure 8-13, with values that are determined with the
above-mentioned steps 1) and 2).
This delay time, tONDLY, for bottom-on, from the start
of VDS free oscillation to the timing of turning-on the
Figure 8-11. Basic Flyback Converter Circuit power MOSFET, is created by exploiting the auxiliary
winding voltage, which synchronizes to the drain
In Figure 8-11, symbols means as follows: voltage VDS waveform.
EIN is input voltage, The voltage on either end of RBD1 and RBD2 is the
EFLY is flyback voltage, voltage subtracted the forward voltage drop, VF, of
NP DZBD from the flyback voltage, Erev1, of the auxiliary
EFLY = × (VOUT + VF ), winding, D. The quasi-resonant signal, Erev2, on the BD
NS
pin, is the voltage divided the former voltage by RBD1
NP is primary side number of turns, and RBD2. The delay time, tONDLY, is adjusted by Erev2
NS is secondary side number of turns, and CBD.
VOUT is output voltage, After the power MOSFET turns off, while the quasi-
VF is forward voltage drop of the secondary side resonant signal increases to the Quasi-Resonant
rectifier, Operation Threshold Voltage 1, VBD(TH1) = 0.24 V, the
ID is drain current of power MOSFET, power MOSFET remains off. After that, when Erev2
IOFF is secondary side rectifier flowing current while decreases enough to cross the Quasi-Resonant Operation
the power MOSFET is off, Threshold Voltage 2, VBD(TH2) = 0.17 V, the power
CV is voltage resonant capacitor, and MOSFET turns on again.
LP is primary side inductance. In addition, at this point, the threshold voltage

SSC1S310A Series
automatically increases to VBD(TH1) to prevent drain voltage, VDS, the drain current, ID, and the quasi-
malfunction of the quasi-resonant operation from noise resonant signal, under the maximum input voltage and
interference. the maximum output power. An initial reference value
for CBD is about 1000pF.
● RBD1 and RBD2 Setup The following show how to adjust the turn-on point:
RBD1 and RBD2 must set the range for the quasi-
● If the turn-on point precedes the bottom of the VDS
resonant signal, VBD(TH1) = 0.34 V(max.) or more under
signal (see Figure 8-14), it causes higher switching
input and output conditions where VCC becomes lowest,
losses. In that situation, after confirming the initial
but less than the absolute maximum rating of the BD pin,
turn-on point, delay the turn-on point by increasing
6.0 V, under conditions where VCC becomes highest.
the CBD value gradually, so that the turn-on will match
The target voltage of Erev2 is about 3.0 V, and the
the bottom point of VDS.
effective pulse width must be 1.0 µs or more between
● In the converse situation, if the turn-on point lags
the two points VBD(TH1) = 0.34 V (max.) and
behind the VDS bottom point (see Figure 8-15), it
VBD(TH2) = 0.27 V (max.)
causes higher switching losses also. After confirming
the initial turn-on point, advance the turn-on point by
● CBD Setup
decreasing the CBD value gradually, so that the turn-on
The delay time, tONDLY, after which the power
will match the bottom point of VDS.
MOSFET turns on, is adjusted by the value of CBD, so
that the power MOSFET turns on at the bottom-on of
VDS as shown in Figure 8-12, while the power MOSFET
Clamping Snubber
T1
P
EIN C1
Auxiliary Winding Voltage
RST EIN EFLY Waveform
Erev1
Flyback
D2 R2 voltage 0
D
Efw1
C2
Q1 4 7
CV Forward
ST VCC voltage
DZBD ｔON
U1 BD pin Voltage
R12 6 Waveform
OCP RBD1 About 3.0 V recommended,
2 but less than 6.0 V acceptable
BD
ROCP GND
C9 8 RBD2 Erev2 VBD(TH1)
CBD VBD(TH2)
Erev2 0
Figure 8-13. BD Pin Peripheral Circuit (Left) and Auxiliary Winding Voltage (Right)

SSC1S310A Series
Free oscillation, fR
Early turn-on point Delayed turn-on point
VDS 0 VDS 0
Bottom Bottom
point point
IOFF 0 IOFF 0
ID 0 ID 0
ｔON ｔON
VBD(TH1) VBD(TH1)
VBD(TH2) VBD 0 VBD(TH2)
VBD 0
Auxiliary Auxiliary
Winding Winding
voltage voltage
VD 0 VD 0
Figure 8-14. When the Turn-on of a VDS Waveform Figure 8-15. When the Turn-on of a VDS Waveform
Occurs before a Bottom Point Occurs after a Bottom Point
8.3.3. BD Pin Blanking Time ● The coupling of the primary winding and the auxiliary
winding must be good.
Figure 8-16 shows two different BD pin waveforms, ● The clamping snubber circuit (see Figure 8-13) must
comparing transformer coupling conditions between the be adjusted properly.
primary and secondary winding. The poor coupling
tends to happen in a low output voltage transformer
design with high NP/NS turns ratio (NP and NS indicate
the number of turns of the primary winding and VBD(TH1)= 0.24V
secondary winding, respectively), and it results in high VBD(TH2)= 0.17V
leakage inductance. The poor coupling causes high surge Erev2
voltage ringing at the power MOSFET drain pin when it
turns off. That high surge voltage ringing is coupled to Normal Waveform (Good Coupling)
the auxiliary winding and then the inappropriate quasi-

resonant signal occurs.
The BD pin has a blanking period of 250ns(max.) to VBD(TH1)= 0.24V
VBD(TH2)= 0.17V
avoid the IC reacting to it, but if the surge voltage period Erev2
continues that value or more, the IC responds to it and
repeatedly turns the power MOSFET on and off at high BD pin blanking time
250 ns (max.)
frequency. This result in an increase of the MOSFET
power dissipation and temperature, and the power Inappropriate Waveform (Poor Coupling)
MOSFET can be damaged.
The following adjustments are required when such
Figure 8-16. The Difference of BD Pin Voltage
high frequency operation occurs.
Waveform by the Coupling Condition of the
● CBD must be connected near the BD pin and the GND Transformer; Good Coupling Versus Inappropriate
pin. Coupling
● The circuit trace loop between the BD pin and the
GND pin must be separated from any traces carrying
high current.

SSC1S310A Series
8.3.4. Bottom Skip Quasi-Resonant ● The mode is changed from one bottom-skip quasi-
Operation resonant operation to normal quasi-resonant operation
(Figure 8-17), when load is increased from one
In order to reduce switching losses during light to bottom-skip operation, the MOSFET peak drain
medium load conditions, in addition to quasi-resonant current value increases, the on-time widens, and thus
operation, the bottom skip function is built in, to limit the peak value of the OCP pin voltage increases.
the rise of the power MOSFET operation frequency. When the load is increased further and the OCP pin
This function monitors the power MOSFET drain voltage increases to VOCP(BS1), the mode is changed to
current (in fact, the OCP pin voltage), it automatically normal quasi-resonant operation.
changes to normal quasi-resonant operation during ● The mode is changed from normal quasi-resonant
heavy load conditions, and it also changes to bottom operation to one bottom-skip quasi-resonant operation
skip quasi-resonant operation during light to medium (Figure 8-18), when load is reduced from normal
loads. quasi-resonant operation, the MOSFET peak drain
Figure 8-17 shows the operation state transition current value decreases, the on-time shortens, and
diagram of the output load from light load to heavy load. thus the peak value of the OCP pin voltage decreases.
Figure 8-18 shows that from heavy load to light load. As When the load is reduced further and the OCP pin
these are state change diagrams without input voltage decreases to VOCP(BS2), the mode is changed to
compensation of OCP, the overcurrent detection one bottom-skip quasi-resonant operation. This
threshold voltage shows just a VOCP(H) = 0.910 V. suppresses the rise of the operation frequency.
This IC has a built-in automatic multi-mode control
which changes among the following three operational
modes according to the output loading state: auto
standby mode, one bottom-skip quasi-resonant operation,
and normal quasi-resonant operation.
(Light load) One Bottom-Skip Quasi-Resonant Normal Quasi-Resonant (Heavy load)

VDS
OCP pin
voltage VOCP(H)= 0.910V
VOCP(BS1)= 0.572V
Figure 8-17. Operation State Transition Diagram from Light Load to Heavy Load Conditions
(Heavy load) Normal Quasi-Resonant One Bottom-Skip Quasi-Resonant (Light load)
VDS
OCP pin VOCP(H)= 0.910V

voltage
VOCP(BS2)= 0.289V
Figure 8-18. Operation State Transition Diagram from Heavy Load to Light Load Conditions

SSC1S310A Series
As shown in Figure 8-19, in the process of the Resonant Signal

increase and decrease of load current, hysteresis is
imposed at the time of each operational mode change.
For this reason, the switching waveform does not 8.4. Auto Standby Function
become unstable near the threshold voltage of a change,
and this enables the IC to switch in a stable operation. The auto standby function automatically changes the
IC operation mode to standby mode with burst
oscillation, when the MOSFET drain current, I D,
One Bottom-Skip Quasi-Resonant
VOCP(H)
decreases during light loads.
VOCP(BS1) The OCP pin circuit monitors ID. When the OCP pin
voltage decreases to the standby state threshold voltage
(about 9% compared to VOCP(H) = 0.910 V), the auto
Normal Quasi-Resonant standby function changes switching mode to standby
VOCP(BS2) mode (see Figure 8-21).
Load current The burst oscillation mode is controlled, so that when
the FB/OLP pin voltage decreases to VFB(STBOP), the IC
stops switching operation, and when it increases to that
Figure 8-19. Hysteresis at the Time of an Operational value or more, the IC starts switching operation.
Mode Change Because the burst oscillation mode has a certain interval
of off-time, switching losses are reduced and efficiency
Figure 8-20 shows the effective pulse width of quasi- is improved under light load conditions.
resonant signal waveform under light load condition. In
order to perform stable normal quasi-resonant operation Generally, a burst interval is set to several kilohertz or
and one bottom-skip operation, it is necessary to ensure less, in order to improve the efficiency during light loads.
that the pulse width of the quasi-resonant signal is 1.0 μs In this low frequency, audible noise may occur from the
or more under the conditions of minimum input voltage transformer. However, this IC keeps the peak drain
and minimum output power. The pulse width of the current low during burst oscillation mode, and
quasi-resonant signal, Erev2, is defined as the interval suppresses the audible noise of the transformer further
between VBD(TH1) = 0.34 V(max.) on the rising edge, and by enabling the step-on burst oscillation function, which
VBD(TH2) = 0.27 V(max.) on the falling edge of the pulse. expands the pulse width gradually.
During the transition stage to burst oscillation mode,

Erev2 if the VCC pin voltage decreases to the Startup Current
Supply Threshold Voltage, VCC(BIAS) = 11.0 V, the bias
assist function is activated. Because this function
VBD(TH1)= 0.34V(max.) provides the startup current, ICC(STARTUP) to the VCC pin,
VBD(TH2)= 0.27V(max.) in order to prevent the fall of the VCC pin voltage, it
enables stable standby operation. If the bias assist
Pulse width function operates during normal operation (which
OCP pin voltage 1.0µs or more includes burst oscillation mode periods), the power
consumption of the IC increases. Therefore, in order to
always keep the VCC pin voltage more than VCC(BIAS), it
is necessary to adjust the turn ratio between the auxiliary
(a) Normal Quasi-Resonant Operation winding and secondary winding of the transformer,
and/or minimize the value of R2 shown in Figure 8-5.
Erev2
VBD(TH1)= 0.34V(max.)
VBD(TH2)= 0.27V(max.)
Pulse width
OCP pin voltage 1.0µs or more
(b) One Bottom-Skip Quasi-Resonant Operation
Figure 8-20. Effective Pulse Width of a Quasi-

SSC1S310A Series
Output current, Burst oscillation

IOUT
Below several kHz
Drain current,
ID
Normal operation Standby operation Normal operation
Figure 8-21. Auto Standby Mode Timing
minimized because switching period is shorter than

oscillation stop period. When the fault condition is
8.5. Overvoltage Protection (OVP) removed, the IC returns to normal operation
automatically.
When the voltage between the VCC pin and GND pin
increases to the OVP Operation Threshold Voltage, ● Latched Shutdown Type: SSC1S312A
VCC(OVP) = 31.5 V, the overvoltage protection (OVP) is When the OVP is activated, the IC stops switching
activated, and switching operation is stopped. The IC operation in the latched state. For keeping the latched
has two operation types of the OVP. One is the auto state, the bias assist function is activated when VCC pin
restart. The other is latched shutdown. voltage decreases to VCC(BIAS). As a result, the VCC pin
When the auxiliary winding supplies the VCC pin voltage is kept to over the VCC(OFF). Releasing the
voltage, the VCC pin voltage is proportional to the latched state is done by turning off the input voltage and
output voltage. Thus, an excessive output voltage of the by dropping the VCC pin voltage below VCC(OFF).
secondary side when the output control circuit is open
can be detected by the OVP.
The output voltage of the secondary side at the OVP
activation, VOUT(OVP), is calculated approximately as
8.6. Overload Protection (OLP)
follows:
Figure 8-22 shows the FB/OLP pin peripheral circuit.
VOUT(NORMAL)
VOUT(OVP) = × 31.5 (V) (4)
VCC(NORMAL)
U1
Where, VOUT(NORMAL) is output voltage in normal GND FB/OLP
operation, and VCC(NORMAL) is VCC pin voltage in
normal operation 8 1
● Auto-restart Type: SSC1S311A IFB PC1

When the OVP is activated, the IC stops switching R1
operation. The VCC pin voltage decreases to
VCC(OFF) = 9.4 V, because the bias assist function is C3
C4
disabled during the OVP operation. Then, the control
circuit stops operation by the UVLO (undervoltage
lockout) circuit, and the IC reverts to the state before
startup. When the VCC pin voltage is increased to Figure 8-22. FB/OLP Pin Peripheral Circuit
VCC(ON) = 15.1 V by the startup current, the control
circuit returns to normal operation again. In this way, the
intermittent oscillation is repeated by the UVLO circuit When the drain peak current is limited by the OCP
during the excess voltage condition. The intermittent operation, the output voltage, VOUT, decreases, and then
oscillation reduces the stresses of a component such as the feedback current from the secondary photo-coupler,
the power MOSFET and the secondary rectifier diode. IFB, becomes zero. As a result, the capacitor, C4, is
Also, power consumption in the intermittent operation is charged, and the FB/OLP pin voltage increases. When

SSC1S310A Series
the FB/OLP pin voltage increase to VFB(MAX) = 4.05 V, latched state, the bias assist function is activated when
the capacitor C4 is charged by IFB(OLP) = −10 µA. When VCC pin voltage decreases to VCC(BIAS). As a result, the
the FB/OLP pin voltage increases to VFB(OLP) = 5.96 V, VCC pin voltage is kept to over the VCC(OFF).
the overload protection (OLP) is activated, and Releasing the latched state is done by turning off the
switching operation is stopped. input voltage and by dropping the VCC pin voltage
The time of the FB/OLP pin voltage from below VCC(OFF).
VFB(MAX) = 4.05 V to VFB(OLP) = 5.96 V is defined as the
OLP Delay Time, tDLY. Because the capacitor C3 for Off-line voltage is cut off
VCC Pin Voltage
phase compensation is small compared to C4, the
approximate value of tDLY is determined as follows: Latch release
VCC(BIAS)
VCC(OFF)
VFB(OLP) − VFB(MAX)
t DLY ≈ × C4 (5)
|IFB(OLP) |
FB/OLP Pin Voltage Charged by IFB(OLP)
If VFB(OLP) = 5.96 V, VFB(MAX) = 4.05 V, VFB(OLP)
IFB(OLP) = −10μA, and C4 = 4.7μF, the value of tDLY is VFB(MAX)
approximately 0.9s. The recommended value of R1 is 47
kΩ.
tDLY
The IC has two operation types of the OLP. One is the Drain Current,
auto restart. The other is latched shutdown. ID
● Auto-restart Type: SSC1S311A

Figure 8-23 shows the auto-restart OLP operation
waveforms. When the OLP is activated, the switching
operation is stopped, and the bias assist function is Figure 8-24. Latched Shutdown Type OLP Operation
disabled. Then an intermittent oscillation is repeated by Waveforms
the UVLO circuit (for more details, see Section 8.5).
When the fault condition is removed, the IC returns to
normal operation automatically. 8.7. Thermal Shutdown (TSD)
If the temperature of the IC reaches more than the
Thermal Shutdown Temperature Tj(TSD) = 135°C(min.),
VCC Pin Voltage
the Thermal Shutdown (TSD) is activated, and the IC
VCC(ON) stops switching operation.
VCC(OFF) The IC has two operation types of the TSD. One is the
auto restart. The other is latched shutdown.
Charged by IFB(OLP) ● Auto-restart Type: SSC1S311A

FB/OLP Pin Voltage
When the OLP is activated, the switching operation is
VFB(OLP) stopped, and the bias assist function is disabled. Then an
VFB(MAX) intermittent oscillation is repeated by the UVLO circuit
tDLY
(for more details, see Section 8.5). When the fault
condition is removed and the temperature of the internal
control circuit is decreases to Tj(TSD) or less, the IC
Drain Current,
ID returns to normal operation automatically.
● Latched Shutdown Type: SSC1S312A

When the TSD is activated, the IC stops switching
operation in the latched state. For keeping the latched
state, the bias assist function is activated when VCC pin
Figure 8-23. Auto-restart Type OLP Operation voltage decreases to VCC(BIAS). As a result, the VCC pin
Waveforms voltage is kept to over the VCC(OFF).
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
● Latched Shutdown Type: SSC1S312A below VCC(OFF).
Figure 8-24 shows the auto-restart OLP operation
waveforms. When the OLP is activated, the IC stops
switching operation in the latched state. For keeping the

SSC1S310A Series
8.8. Overcurrent Protection (OCP) through DZBD from Efw1 is biased by either end of RBD1
and RBD2, and thus the BD pin voltage is provided the
The overcurrent protection circuit (OCP) detects each voltage on RDB2 divided by the divider of RBD1 and RBD2.
peak drain current of the power MOSFET on pulse-by-
pulse basis, by the current detection resistor, ROCP. When Flyback voltage, Erev1
the OCP pin voltage reaches the OCP threshold, the IC D2 R2 T1
turns off the power MOSFET and limits the output
power. C2
7 D
VCC
Forward voltage,
DZBD
VDZBD Efw1
8.8.1. Overcurrent Input Compensation U1
Function R12
6 2
RBD1
The voltage
OCP BD
divided the
When using a quasi-resonant converter with universal GND
8
forward voltage
by resistors,
ROCP C9 RBD2
input (85 to 265 VAC), if the output power is set CBD Efw2
constant, then because higher input voltages have higher

frequency, the MOSFET peak drain current becomes
low. Because ROCP is fixed, the OCP point in the higher Figure 8-26. Overcurrent Input Compensation Circuit
input voltage will shift further into the overload area.
Thus, the output current at OCP point in the maximum
input voltage, IOUT(OCP), approximately doubles relative 100V 230V
to that in the minimum input voltage (see the curve of 0 AC
IOUT without input compensation of Figure 8-25). In VZ
order to suppress this phenomenon, this IC has the
overcurrent input compensation function. As for
determining an input compensation value, it is necessary Efw1
to avoid excessive input compensation for the output
0 AC
current specification, IOUT. When excessive input
compensation is applied, IOUT(OCP) may be below IOUT in
the situation where the input voltage is high. Therefore,
it is necessary to ensure that IOUT(OCP) remains more than Efw2 OCP input compensation starting point:
IOUT across the full range of input voltage, such as the the point matching, Efw1−VZ= 0V
curve of IOUT with appropriate input compensation in
Figure 8-25.
Figure 8-27. Efw1 and Efw2 Voltage Relative to AC
Input Voltage
Output current at OCP, IOUT(OCP) （A）
IOUT without input compensation
Figure 8-28 shows the relationship between the

IOUT with appropriate input compensation overcurrent detection threshold voltage after input
IOUT voltage compensation, VOCP(H)', and Efw2. Read the value
IOUT target output level
IOUT with excessive input compensation
of VOCP(H)' according to Efw2 in Figure 8-28.
● DZBD setting:
AC input voltage（V）
The starting voltage for input compensation is set by
85VAC 265VAC the Zener voltage, VZ, of DZBD. According to the
input voltage specification or transformer
Figure 8-25. OCP Circuit Input Compensation specification, it is required to be VZ = 6.8 to 30 V.
● RBD1 setting: see Section 8.3.2
● The recommended value of RBD2: 1.0 kΩ
Figure 8-26 shows an overcurrent input compensation
circuit, and Figure 8-27 shows Efw1 and Efw2 relative to Overcurrent input compensation should be adjusted so
the input voltage. Also, Figure 8-28 shows the that the variance of the output current, I OUT(OCP), at an
relationship between the overcurrent threshold voltages OCP point, is minimized at the high and low input
after input compensation, VOCP(H)', and the BD pin voltage. In addition, the input compensation must be
voltage, Efw2. The overcurrent input compensation adjusted so that IOUT(OCP) remains more than the output
function compensates the overcurrent detection current specification, IOUT, across the full range of input
threshold voltage (normal operation), VOCP(H), according voltage, such as the curve of IOUT with appropriate input
to the input voltage. The forward voltage, Efw1, is compensation in Figure 8-25.
proportional to the input voltage, the voltage passed If VOCP(H)' is compensated to the Bottom-Skip

SSC1S310A Series
Operation Threshold Voltage, VOCP(BS1), or less, the IC operation), VOCP(H).

will change from one bottom-skip operation to normal ● Point B to Point D: VDZBD < Efw1
quasi-resonant operation, and thus will raise the When the input voltage increases and Efw1 exceeds the
operation frequency and will provide output power. Zener voltage, VZ, of DZBD, Efw2 will be produced as a
Therefore, switching losses in normal quasi-resonant negative voltage to compensate the Overcurrent
operation is higher than that in bottom-skip operation. In Detection Threshold Voltage (normal operation),
this case, when the input compensation is compensated VOCP(H).
to VOCP(BS1) or less, the temperature of the power
Efw2 is generally adjusted to the BD pin voltage of
MOSFET should be checked in normal quasi-resonant
Efw2 = –3.0 V at the maximum input voltage. Adjustment
operation switched from bottom-skip operation, by
of Efw2 will change the overcurrent detection threshold
changing load condition. Efw2, which includes surge
voltage by an overcurrent input compensation function.
voltage, must be within the absolute maximum rating of
Therefore, Efw2 must be adjusted while checking the
the BD pin voltage (–6.0 V to 6.0 V) at the maximum
input compensation starting point and the amount of
input voltage. Figure 8-29 shows each voltage waveform
input compensation. Also, the variations of the
for the input voltage in normal quasi-resonant operation.
overcurrent detection threshold voltage after input
● Point A: VDZBD ≥ Efw1 compensation, VOCP(H)', can be calculated by the
Efw2 will be produced negative voltage, and the minimum and maximum values shown in Figure 8-28.
detection voltage for an overcurrent event is the
Overcurrent Detection Threshold Voltage (normal
1
VOCP(H)=0.910 : Recommended use range
0.8
0.6
VOCP(H)' (V)
Max.
0.4 Typ.
Min.
0.2
0
0 −1 −2 −3 −4 −5 −6
0 -1 -2 -3 -4 -5 -6
BD Pin Voltage, Efw2 (V)
Figure 8-28. Overcurrent Threshold Voltage after Input Compensation, VOCP(H)'

(Reference for Design Target Values)
Auxiliary winding voltage
Erev1
0
Efw1 tON
tON
tON
tON
0 Input voltage
VDZBD A B C D DZBD Zener voltage, Vz
100V 230V
0 Input voltage
Efw2
At the input voltage where Efw1 reaches VZ or more,

Efw2 goes negative.
Figure 8-29. Each Voltage Waveform for the Input Voltage in Normal Quasi-Resonant Operation

SSC1S310A Series
When RBD2 = 1 kΩ, RBD1 = 7.5 kΩ, VF = 0.7 V, and

Erev1 = 20 V, Erev2 of Figure 8-13 can be calculated as
8.8.2. Reference BD Pin Peripheral follows:
Components Setting R BD2
This example demonstrates the determination of Efw2 = × (Erev1 − VF ) (9)
R BD1 + R BD2
external component values for the BD pin peripheral
circuit. It assumes universal input (85 VAC to 265
VAC) is being used, and input compensation begins 1 kΩ
from the input voltage of 120 VAC. The transformer is = × (20 V − 0.7 V) = 2.27 V.
7.5 kΩ + 1 kΩ
assumed to have primary winding with NP = 40T, and an
auxiliary winding with ND = 5 (turn). In this case, the quasi-resonant voltage Erev2 meets the
To determine the Zener voltage, VZ, of DZBD, Efw1 at design guidelines: it is Quasi-Resonant Operation
120 VAC is calculated as follows: Threshold Voltage 1, VBD(TH1) = 0.24 V or more, and Efw2
and Erev2 are kept within the limits of the Absolute
ND Maximum Rating (–6.0 V to 6.0 V) of the BD pin.
Efw1 = × VIN(AC) × √2 (6)
NP
8.8.3. Reference Example of No

5 turn
= × 120 VAC × √2 = 21.2 V . Overcurrent Input Compensation
40 turn
Required
The Zener diode rating, VZ, is chosen to be 22 V, a When the input voltage is narrow range, or provided
standard value. from a pre-regulator such as PFC of active filter, the
RBD1 results in Efw2 = –3.0 V at the maximum input variation of the input voltage is small. Thus, the
voltage of 265 VAC, as follows: variation of OCP point may become less than that of the
universal input voltage specification. When overcurrent
R BD2 ND input compensation is not required, the input
R BD1 = × ( × VIN(AC) × √2 − ZBD − |Efw2 |)
|Efw1 | NP compensation function can be disabled by substituting a
high-speed diode for the Zener diode (DZBD), and by
(7) keeping the BD pin voltage from being negative
1 kΩ 5 turn voltage.
= ×( × 265 VAC × √2 − 22 V − |−3V|) In addition, the following formula shows the reverse
|−3V| 40 turn voltage of a high-speed diode. The high-speed selection
should take account of its derating.
= 7.28 kΩ .
The RBD1 rating is chosen to be 7.5 kΩ of the E series. ND
Efw1 = × Maximum input voltage (10)
Choosing RBD2 = 1.0kΩ, the |Efw2| value at 265 VAC NP
can be calculated as follows:
R BD2
Efw2 = × (|Efw1 | − ZBD ) (8)
R BD1 + R BD2 8.9. Maximum On-Time Limitation
Function
1 kΩ 5 turn When the input voltage is low or in a transient state
= ×( × 265 VAC × √2 − 22 V) such that the input voltage turns on or off, the on-time of
7.5 kΩ + 1 kΩ 40 turn
the power MOSFET is limited to the Maximum On-
Time, tON(MAX) = 40.0 μs (see Figure 8-30). Thus, the
= 2.92 kΩ. peak drain current is limited, and the audible noise of the
transformer is suppressed.
Referring to Figure 8-28, when compensated by In designing a power supply, the on-time must be less
Efw2 = –2.92 V, the overcurrent threshold voltage after than tON(MAX). If such a transformer is used that the on-
input compensation, VOCP(H)' , is set to about 0.66 V time is tON(MAX) or more, under the condition with the
(typ.). minimum input voltage and the maximum output power,
the output power would become low. In that case, the
transformer should be redesigned taking into
consideration the following:

SSC1S310A Series
● Inductance, LP, of the transformer should be lowered 9. Design Notes

in order to raise the operation frequency.
● Lower the primary and the secondary turns ratio,
NP/NS, to lower the duty cycle.
9.1. Peripheral Components
Take care to use properly rated and proper type of
ID components.
Maximum on time
● Input and output electrolytic capacitor
Apply proper design margin to ripple current, voltage,
and temperature rise. Use of high ripple current and
t low impedance types, designed for switch-mode
power supplies, is recommended, depending on their
VDS purposes.
● Transformer
Apply proper design margin to core temperature rise
by core loss and copper loss. Because switching
currents contain high frequency currents, the skin
t effect may become a consideration. In consideration
of the skin effect, choose a suitable wire gauge in
consideration of rms current and a current density of
Figure 8-30. Confirmation of Maximum On-time about 3 to 4A/mm2. If measures to further reduce
temperature are still necessary, the following should
be considered to increase the total surface area of the
8.10. DRV Pin Peripheral Components wiring:
Figure 8-31 shows the peripheral circuit around DRV - Increase the number of wires in parallel.
pin. The DRV pin is the gate drive pin for driving the - Use litz wires.
external power MOSFET. The output voltage, VDRV, is - Thicken the wire gauge.
7.5 V (min.), the peak source current and peak sink ● Current detection resistor, ROCP
current are −150 mA and 608 mA, respectively. It is A high frequency switching current flows to ROCP, and
necessary to choose the external power MOSFET of may cause poor operation if a high inductance resistor
which the gate threshold voltage, VGS(th) is less than is used. Choose a low inductance and high surge-
VDRV enough across the full temperature range in the tolerant type.
application.
R4, R5, and D3 should be adjusted considering power
losses of the power MOSFET, gate waveform (reduction
of ringing caused by pattern layout, and others), and 9.2. Transformer Design
EMI noise, based on actual operation in the application. The design of the transformer is fundamentally the
R3 prevents malfunctions caused by steep dv/dt at same as the power transformer of a Ringing Choke
turning off the power MOSFET. It is recommended to Converter (RCC) system: a self-excitation type flyback
place a resistor of 10kΩ to 100kΩ close to Gate and converter.
Source of the power MOSFET. However, because the duty cycle will change due to
the quasi-resonant operations delaying the turn-on, the
D3 R5 duty cycle needs to be compensated.
5 DRV VF
NP T1 NS D4
R4 VO
R3 LP
U1 EFLY
P S IOFF C6
ID
EIN
GND C1
ROCP
8 CV
Figure 8-31. DRV Pin Peripheral Circuit

Figure 9-1. Quasi-resonant Circuit

SSC1S310A Series
When the duty cycle, DON, is calculated by the ratio of

the primary turns, NP, and the secondary turns, NS, the NP × (VO + VF )
inductance, LP' on the primary side, taking into NS = (17)
EFRY
consideration the delay time, can be calculated by
Equation(11). where:
tONDLY is the delay time of quasi-resonant operation,
LP ′ IIN is the average input current,
2
(EIN(MIN) × DON ) η2 is the conversion efficiency of the power supply,
= 2 IDP is the peak drain current
2 × PO × f0 DON' is the duty cycle after compensation, and
(√ + EIN(MIN) × DON × f0 × π × √CV )
η1 VO is the secondary side output voltage
The minimum operation frequency of quasi-resonant

(11) operation, fO, can be calculated by Equation (18)
where:
PO is the maximum output power, In transformer design, AL-value and NP must be set in
fO is the minimum operation frequency of quasi- a way that the ferrite core does not saturate. Here, use
resonant operation, ampere turn value (AT), the result of IDP × NP and the
CV is the voltage resonance capacitor connected graph of NI-Limit (AT) versus AL-value (Figure 9-2 is
between the drain and source of the power MOSFET, an example of it). NI-Limit is the limit that the ampere
η1 is the transformer efficiency, turn value should not exceed; otherwise the core
DON is the duty cycle at the minimum input voltage: saturates.
When choosing a ferrite core to match the relationship
EFRY of NI-Limit (AT) versus AL-value, it is recommended to
DON = .
EIN(MIN) + EFRY set the calculated NI-Limit value below about 30% from
the NI-Limit curve of ferrite core data, as shown in the
EIN(MIN) is the C1 voltage of Figure 9-1 at the hatched area containing the design point in Figure 9-2,
minimum input voltage, to provide a design margin in consideration of
EFLY is the flyback voltage: temperature effects and other variations.
ND f0
EFRY = × (VO + VF ) , and 2
2
NP 4π(EIN(MIN) × DON ) × √CV
2P 2P
−√ O + √ O +
η1 η1 √LP ′
VF is the forward voltage drop of D4. =
2π√CV × EIN(MIN) × DON
Each parameter, such as the peak drain current, I DP, is
calculated as follows: ( )
t ONDLY = π√LP ′ × CV (12)

(18)
DON ′ = DON (1 − f0 × t ONDLY ) (13) Saturation region lower boundary

NI-limit (AT)
Saturation margin= below about 30%
PO 1
IIN = × (14)
η2 EIN(MIN)
NI-Limit design
2 × IIN point as example
IDP = (15)
DON ′
Al-value (nH/T2)
LP ′
NP = √ (16) Figure 9-2. Example of NI-limit vs. AL-value
AL − value Characteristics

SSC1S310A Series
9.3. Protection against Negative Input 9.4. Phase Compensation

Voltage at Start-up Pin A typical phase compensation circuit with a
If the ST pin voltage is applied more negative voltage secondary shunt regulator (U2) is shown in Figure 9-4.
than −0.3 V, the IC may be out of normal operation, and The value of C7 is recommended to be about 0.047 µF
thus either a diode or a resistor must be added, as shown to 0.47μF, and should be chosen based on actual
in Figure 9-3. The diode or resistor should be chosen in operation in the application. Place C3 between the
the following specification. In addition, it is necessary to FB/OLP pin and the GND pin, as shown in Figure 9-5,
check the operation based on actual operation across the to perform high frequency noise reduction and phase
full range of input voltage in the application. compensation. The value of C3 is recommended to be
about 470pF to 0.01μF, and should be chosen based on
actual operation in the application.
Add a resistor or a diode
T1 L1
D4 VOUT
T1
EIN C1 P
RST R9
PC1 R6
DRV C6 R10
S R7 C8
4
ST
7 D2 R2 C7 R8
VCC
U1 U2
C2 R11
D
8
GND
GND
Figure 9-3. ST Pin Countermeasure against Negative Figure 9-4. Peripheral Circuit around Secondary Shunt
Applied Voltage Regulator (U2)
● The recommended specification of additional diode

or resistor U1
- The case of resistor, RST
GND FB/OLP
type of resistors, such as metal oxide film.
The minimum value: 5.6 kΩ 8 1
The maximum value: Meet Equation (19).
PC1
|ICC(STARTUP) (min. )| × R ST + VSTART(ON) (max. ) IFB
(19) C3
≪ EIN (min. )
Where:
ICC(STARTUP)(min.) is −4.5 mA, Figure 9-5. FB/OLP Peripheral Circuit
VSTART(ON)(max.) is 24 V, and
EIN(min.) is the C1 voltage at the minimum input
voltage. 9.5. PCB trace layout and Component
placement
The value of RST in universal input range (85 VAC to
265 VAC) is 5.6 kΩ to 15 kΩ. PCB design and component layout significantly affect
operation, EMI noise, and power dissipation. Therefore,
- Diode characteristics pay extra attention to these designs. In general, where
high frequency current traces form a loop, as shown in
Peak reverse voltage, VRM: >35 V
Figure 9-6, wide, short traces, and small circuit loops are
Forward current, IF: >4.5 mA
important to reduce line impedance. In addition, earth
Reverse recovery time, trr: <27 μs
ground traces affect radiated EMI noise, and the same
Reverse current, IR: <100 μA

SSC1S310A Series
measures should be taken into account. Switch-mode and with proper voltage rating) near the IC or the
power supplies consist of current traces with high transformer is recommended to reduce impedance of
frequency and high voltage, and thus trace design and the high frequency current loop.
component layouts should be done to comply with all
safety guidelines. Furthermore, because the power (2) GND Trace Layout:
MOSFET has a positive thermal coefficient of RDS(ON), This trace also must be as wide and short as possible.
consider it when preparing a thermal design. If C2 and the IC are distant from each other, placing
a capacitor (approximately 0.1 µF to 1.0μF film
capacitor) close to the VCC pin and the GND pin is
recommended.
(3) ROCP Trace Layout

ROCP should be placed as close as possible to the
peripheral components of OCP pin. The connection
between the power ground of main trace and the
control circuit ground should be connected by a
single point ground (point A in Figure 9-7) to
remove common impedance, and to avoid
interference from switching currents to the control
Figure 9-6. High Frequency Current Loops circuit.
(Hatched Areas)
● Secondary Rectifier Trace Layout
This trace should be as wide as possible. If the loop
Figure 9-7 shows a circuit layout design example.
distance is lengthy, leakage inductance resulting from
the long loop may increase surge voltage at turning off
● IC Peripheral Circuit
the power MOSFET. Proper secondary trace layout
helps to increase margin against the power MOSFET
(1) Power MOSFET and OCP Trace Layout
breakdown voltage, and reduces stress on the clamp
This is the main trace containing switching currents, snubber circuit and losses in it.
and thus it should be as wide and short as possible.
If C1 and the IC are distant from each other, an
electrolytic capacitor or film capacitor (about 0.1μF
C5
D4
T1
C1 D3 R5
C6
CV RST
S
R4 D2 R2
R3
DRV
U1 ST C2 D
5 4
SSC1S310A
R12
6
OCP
C9 7 VCC 2 DZBD
BD
Main power circuit trace
ROCP 8 1
GND FB/OLP RBD1
GND trace for the IC
R1 Secondary rectifier trace

RBD2
A CBD
C4 C3
PC1
Figure 9-7. Peripheral Circuit Example around the IC

SSC1S310A Series
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Quasi-Resonant Off-Line Switching Control ICs

SSC1S310A Series Data Sheet

automatically changes the quasi-resonant mode to the FB/OLP BD

bottom-skip mode to improve efficiency. The IC is ROCP

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 1

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 2

1. Absolute Maximum Ratings

Power Supply Startup Operation

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 3

Parameter Symbol Conditions Pins Min. Typ. Max. Unit

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 4

4. Pin Configuration Definitions

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 5

VSTART(ON) ′ = VSTART(ON) + VZST (1)

Figure 5-1. Application Circuit Example 1

Figure 5-2. Application Circuit Example 2 (Adjustable Startup Voltage)

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 6

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 7

Figure 8-1 shows VCC pin peripheral circuit.

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 8

decrease of the VCC pin voltage is suppressed by D2 R2

VCC pin voltage IC startup Startup success

Target operating voltage

8.1.4. Auxiliary Winding

Output current, IOUT

Figure 8-4. VCC versus IOUT with/without resistor R2

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 9

Core Bobbin Core Bobbin

Barrier tape Barrier tape

Pin side Pin side

P1, P2: Primary winding

Figure 8-6. Winding Structure Example

8.1.5. Soft-Start Function 8.1.6. Operational Mode at Startup

Startup Steady operation

Time PWM operation Quasi-resonant operation

Time Pulse width 1.0µs(MIN)

Figure 8-7. Operational Mode in Startup

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 10

Figure 8-8. FB/OLP Peripheral Circuit

Target voltage Surge voltage width in

- VROCP Figure 8-10. OCP Pin Voltage Waveform

FB comparator OCP pin voltage

Figure 8-9. Drain Current, ID, and FB Comparator

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 11

8.3. Quasi-Resonant Operation and

8.3.1. Quasi-Resonant Operation

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 12

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 13

Early turn-on point Delayed turn-on point

the auxiliary winding and then the inappropriate quasi-

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 14

(Light load) One Bottom-Skip Quasi-Resonant Normal Quasi-Resonant (Heavy load)

(Heavy load) Normal Quasi-Resonant One Bottom-Skip Quasi-Resonant (Light load)

OCP pin VOCP(H)= 0.910V

SSC1S310A-DSE Rev.2.2 SANKEN ELECTRIC CO., LTD. 15

As shown in Figure 8-19, in the process of the Resonant Signal

During the transition stage to burst oscillation mode,

(b) One Bottom-Skip Quasi-Resonant Operation

Figure 8-20. Effective Pulse Width of a Quasi-