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    Datasheet 119

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    Tom Tom
    The SL74HCT04 is a hex inverter integrated circuit that operates with TTL, NMOS, and CMOS logic levels. It can interface TTL or NMOS outputs with high-speed CMOS inputs. Each inverter has an input and an output, inverting the input signal. The device operates from 4.5-5.5V and has low input current of 1uA maximum. It is available in plastic DIP and SOIC packages for operation from -55°C to 125°C.

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    Datasheet 119

    Uploaded by

    Tom Tom
    30 views4 pages
    The SL74HCT04 is a hex inverter integrated circuit that operates with TTL, NMOS, and CMOS logic levels. It can interface TTL or NMOS outputs with high-speed CMOS inputs. Each inverter has an input and an output, inverting the input signal. The device operates from 4.5-5.5V and has low input current of 1uA maximum. It is available in plastic DIP and SOIC packages for operation from -55°C to 125°C.

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    The SL74HCT04 is a hex inverter integrated circuit that operates with TTL, NMOS, and CMOS logic levels. It can interface TTL or NMOS outputs with high-speed CMOS inputs. Each inverter has an input and an output, inverting the input signal. The device operates from 4.5-5.5V and has low input current of 1uA maximum. It is available in plastic DIP and SOIC packages for operation from -55°C to 125°C.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    30 views4 pages

    Datasheet 119

    Uploaded by

    Tom Tom
    The SL74HCT04 is a hex inverter integrated circuit that operates with TTL, NMOS, and CMOS logic levels. It can interface TTL or NMOS outputs with high-speed CMOS inputs. Each inverter has an input and an output, inverting the input signal. The device operates from 4.5-5.5V and has low input current of 1uA maximum. It is available in plastic DIP and SOIC packages for operation from -55°C to 125°C.

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    SL74HCT04

    Hex Inverter

    High-Performance Silicon-Gate CMOS

    The SL74HCT04 may be used as a level converter for interfacing


    TTL or NMOS outputs to High-Speed CMOS inputs.
    The SL74HCT04 is identical in pinout to the LS/ALS04.
    • TTL/NMOS-Compatible Input Levels
    • Outputs Directly Interface to CMOS, NMOS, and TTL
    • Operating Voltage Range: 4.5 to 5.5 V
    • Low Input Current: 1.0 µA ORDERING INFORMATION
    SL74HCT04N Plastic
    SL74HCT04D SOIC
    TA = -55° to 125° C for all packages

    LOGIC DIAGRAM

    PIN ASSIGNMENT

    FUNCTION TABLE

    Inputs Output
    A Y
    L H
    H L

    PIN 14 =VCC
    PIN 7 = GND

    System Logic
    SLS Semiconductor
    SL74HCT04

    MAXIMUM RATINGS *

    Symbol Parameter Value Unit


    VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
    VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
    VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
    IIN DC Input Current, per Pin ±20 mA
    IOUT DC Output Current, per Pin ±25 mA
    ICC DC Supply Current, VCC and GND Pins ±50 mA
    PD Power Dissipation in Still Air, Plastic DIP+ 750 mW
    SOIC Package+ 500
    Tstg Storage Temperature -65 to +150 °C
    TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
    (Plastic DIP or SOIC Package)
    *
    Maximum Ratings are those values beyond which damage to the device may occur.
    Functional operation should be restricted to the Recommended Operating Conditions.
    +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
    SOIC Package: : - 7 mW/°C from 65° to 125°C

    RECOMMENDED OPERATING CONDITIONS


    Symbol Parameter Min Max Unit
    VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
    VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
    TA Operating Temperature, All Package Types -55 +125 °C
    tr, t f Input Rise and Fall Time (Figure 1) 0 500 ns

    This device contains protection circuitry to guard against damage due to high static voltages or electric
    fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
    voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
    GND≤(VIN or VOUT)≤VCC.
    Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
    Unused outputs must be left open.

    System Logic
    SLS Semiconductor
    SL74HCT04

    DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)


    VCC Guaranteed Limit
    Symbol Parameter Test Conditions V 25 °C ≤85 ≤125 Unit
    to °C °C
    -55°C
    VIH Minimum High-Level VOUT=0.1 V 4.5 2.0 2.0 2.0 V
    Input Voltage IOUT≤ 20 µA 5.5 2.0 2.0 2.0
    VIL Maximum Low -Level VOUT= VCC-0.1 V 4.5 0.8 0.8 0.8 V
    Input Voltage IOUT ≤ 20 µA 5.5 0.8 0.8 0.8
    VOH Minimum High-Level VIN=VIL 4.5 4.4 4.4 4.4 V
    Output Voltage IOUT ≤ 20 µA 5.5 5.4 5.4 5.4
    VIN=VIL
    IOUT ≤ 4.0 mA 4.5 3.98 3.84 3.7
    VOL Maximum Low-Level VIN=VIH 4.5 0.1 0.1 0.1 V
    Output Voltage IOUT ≤ 20 µA 5.5 0.1 0.1 0.1
    VIN=VIH
    IOUT ≤ 4.0 mA 4.5 0.26 0.33 0.4
    IIN Maximum Input VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
    Leakage Current
    ICC Maximum Quiescent VIN=VCC or GND 5.5 1.0 10 40 µA
    Supply Current IOUT=0µA
    (per Package)
    ∆ICC Quiescent Additional VIN=2.4 V,Any One Input ≥-55 °C 25 °C to mA
    Supply Current VIN=VCC or GND, Other -55°C
    Inputs
    IOUT=0µA 5.5 2.9 2.4

    NOTE: Total Supply Current=ICC+Σ∆ICC.

    System Logic
    SLS Semiconductor
    SL74HCT04

    AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ±10%,CL=50pF,Input t r=t f=6.0 ns)


    Guaranteed Limit
    Symbol Parameter 25 °C to ≤85°C ≤125°C Unit
    -55°C
    tPLH Maximum Propagation Delay, Input A 15 19 22 ns
    tPHL to Output Y (Figures 1 and 2) 17 21 26
    tTLH, t THL Maximum Output Transition Time, Any Output 15 19 22 ns
    (Figures 1 and 2)
    CIN Maximum Input Capacitance 10 10 10 pF

    Power Dissipation Capacitance (Per Inverter) Typical @25°C,VCC=5.0 V


    CPD Used to determine the no-load dynamic power 22 pF
    consumption:
    PD=CPDVCC2f+ICCVCC

    Figure 1. Switching Waveforms. Figure 2. Test Circuit

    EXPANDED LOGIC DIAGRAM


    (1/6 of the Device)

    System Logic
    SLS Semiconductor

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