A33003 Datasheet

A33003
- Precision Angle Sensor IC

with On-Chip Linearization, SENT, SPI, and PWM Output
FEATURES AND BENEFITS DESCRIPTION

• Contactless 0° to 360° angle sensor IC, for angular The A33003 is a 360° angle sensor IC that provides contactless
position, rotational speed, and direction measurement high-resolution angular position information based on magnetic
□ Capable of sensing magnet rotational speeds targeting circular vertical Hall (CVH) technology. It has a system-on-chip
12-bit effective resolution with 900 G field (SoC) architecture that includes: a CVH front end, digital signal
□ Circular vertical Hall (CVH) technology provides a processing to calculate the angular position data, and selectable
single-channel sensor system supporting operation output protocols (SPI, SENT, or PWM). It also includes on-chip
across a wide range of air gaps EEPROM technology, capable of supporting up to 100 read/
• On-chip 32-segment linearization to improve angle accuracy write cycles for flexible programming of calibration parameters.
□ Reduces the impact of magnet to sensor misalignment The A33003 is ideal for automotive applications requiring 0°
□ Reduces the impact of imperfect magnetization of to 360° angle measurements and high levels of redundancy,
target magnet such as electronic power steering (EPS), transmission actuators,
• Developed in accordance with ISO 26262 requirements and steer-by-wire (SBW) systems.
for hardware product development for use in safety-
The A33003 includes on-chip 32-segment linearization. This
critical applications
can be used to calibrate out errors due to misalignment between
□ Single-die version designed to meet ASIL B requirements
the magnet and the sensor or imperfect magnetization of the
when integrated and used in conjunction with the
target magnet (which can present as a misalignment of the
appropriate system-level control, in the manner prescribed
magnet to the sensor).
in the A33003 Safety Manual
□ Dual-die version designed to meet ASIL D requirements The A33003 supports customer integration into safety-critical
when integrated and used in conjunction with the applications.
appropriate system-level control, in the manner prescribed
The A33003 is available in a single- or dual-die 14-pin TSSOP
in the A33003 Safety Manual
package (suffix LU). The package is lead (Pb) free with 100%
• Programmable via Manchester encoding on the output
matte tin leadframe plating. The 1 mm thin package reduces
line to reduce external wiring and enable in-application
the minimum air gap between the CVH transducer and the
programming when in PWM or SENT mode
target magnet.
Continued on next page...
PACKAGE: 14-pin TSSOP
Not to scale (Suffix LU)
Package
Die 1
BYP
VCC Regulator To all internal circuits
Angle Detecon Temp

Sensor
PLL
CVH
ADC
ADC
GND ZCD
S
Manchester
Interface Digital Processing
SENT Harmonic Temp.
N Interface Linearizaon Compensaon Compensaon
TSSOP-14
VOUT
SPI
CS Interface
w/4 -bit Direct Serial EEPROM EEPROM
SCLK CRC Registers Controller Registers
MOSI
Die 2
Figure 1: A33003 Magnetic Circuit and IC Diagram
A33003-DS, Rev. 7 March 30, 2023

MCO-0000717
Precision Angle Sensor IC
A33003 with On-Chip Linearization, SENT, SPI, and PWM Output
FEATURES AND BENEFITS (continued)

• Digital output format selectable between SPI, SENT, or PWM enables multiple independent ICs to be connected to the same bus
• SENT output is SAE J2716 JAN2010-compliant with Allegro □ 4-bit CRC
proprietary enhancements • Multiple programming/configuration formats supported
□ Customer-programmable SENT tick times ranging from □ The system can be completely controlled and programmed
0.5 to 7.9 µs over SPI or Manchester protocol, including EEPROM writes
• On-chip EEPROM for storing factory and customer □ For system with limited pins available, writing and reading
calibration parameters can be performed over the VOUT pin
□ Integrated charge pump allows in-application programming □ 1 mm thin surface-mount TSSOP package to minimize air
without any requirement for high voltages to be supplied to gap from target magnet to the CVH transducer for improved
the device during programming field strength
□ Single-bit error correction, dual-bit error detection error
correction control (ECC)
• Supports operation in harsh conditions, required for
automotive and industrial applications
□ Operating temperature range from –40°C to 150°C
□ Operating supply voltage range from 4.5 to 5.5 V, absolute
maximum of 28 V
• Loss of power is indicated by reset flag
• 10 MHz SPI for low-latency angle and diagnostic information;
SELECTION GUIDE
Part Number Hot Trim Temperature Interface Voltage [1] System Die Package Packing
A33003LLUATR 150°C 3.3 V Single
14-pin TSSOP 4000 pieces per 13-inch reel
A33003LLUBTR-DD 150°C 3.3 V Dual
[1] Contact Allegro MicroSystems for 5 V interface availability.
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC Not sampling angles, respecting TJ(max) 28 V
Reverse Supply Voltage VRCC Not sampling angles –18 V
VOUT Pin VOUT 18 V
All Other Pins Forward Voltage VIN 5.5 V
All Other Pins Reverse Voltage VR 0.5 V
Operating Ambient Temperature TA L range –40 to 150 °C
Maximum Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C
THERMAL CHARACTERISTICS: May require derating at maximum conditions

Characteristic Symbol Test Conditions [1] Value Unit
Package Thermal Resistance RθJA LU-14 package; measured on JEDEC JESD51-7 2s2p board 82 °C/W
[1] Additional thermal information is available on the Allegro website.
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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table of Contents
Features and Benefits............................................................ 1 SPI Interface................................................................... 21
Description........................................................................... 1 Manchester Serial Interface............................................... 26
Package.............................................................................. 1 Manchester Message Structure......................................... 28
Simplified Block Diagram....................................................... 1 EEPROM and Shadow Memory Use..................................... 33
Selection Guide.................................................................... 2 Enabling EEPROM Access............................................... 34
Absolute Maximum Ratings.................................................... 2 EEPROM Write Lock........................................................ 34
Thermal Characteristics......................................................... 2 Read Transaction from EEPROM (or Shadow Memory)........ 35
Pinout Diagrams and Terminal Lists......................................... 4 Write Transaction to EEPROM (or Shadow Memory)............ 37
Operating Characteristics....................................................... 6 Shadow Memory Read and Write Transactions.................... 40
Performance Characteristics................................................... 9 Serial Interface Table........................................................... 41
Functional Description..........................................................11 Primary Serial Interface Registers Reference......................... 42
Overview.........................................................................11 EEPROM Table................................................................... 50
Angle Measurement..........................................................11 EEPROM Reference........................................................... 51
System Level Timing.........................................................11 Safety and Diagnostics........................................................ 59
Power-Up........................................................................11 Alive Counter.................................................................. 59
PWM Output................................................................... 12 Oscillator Watchdogs........................................................ 59
Linearization.................................................................... 15 Logic Built-In Self-Test (LBIST).......................................... 59
Angle Hysteresis.............................................................. 17 CVH Self-Test.................................................................. 59
Turns Counting................................................................ 18 I/O Structures..................................................................... 60
Turns Counting Behavior on Power-Up............................... 19 Package Outline Drawings................................................... 61
Setting the Turns Count Value........................................... 20 Appendix A: SENT Output Description..................................A-1
Device Programming Interface.............................................. 21 Appendix B: Angle Error and Drift Definition...........................B-1
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PINOUT DIAGRAMS AND TERMINAL LIST TABLES

Pinout Diagram Terminal List Table, Single Die
Pin Number Pin Name Function
LU 14-Pin TSSOP, Single Die
1 SCLK SPI: Clock input terminal.
SCLK 1 14 GND SPI: Controller-Out Peripheral-In.
MOSI/SA1 2 13 GND 2 MOSI/SA1 Manchester/SENT: Sets bit 1 of address field.
Tie to BYP for a logic 1, GND for a logic 0.
CS/SA0 3 12 GND
SPI Chip Select terminal, active low input.
VOUT 4 11 GND 3 CS/SA0 Manchester/SENT: Sets bit 0 of address field.
5 10 GND Tie to BYP for a logic 1, GND for a logic 0.
GND
SPI: Controller In/Peripheral Out, push-pull.
BYP 6 9 GND
4 VOUT SENT/PWM: Input/Output, open drain.
VCC 7 8 GND Manchester: Input/Output, push-pull.
Device ground terminal.
5, 8–14 GND
All GND pins should be connected together.
6 BYP External bypass capacitor terminal for internal regulator.
7 VCC Power supply.
Pinout Diagram Terminal List Table, Dual Die

Pin Number Pin Name Function
LU 14-Pin TSSOP, Dual Die
1 SCLK_1 SPI: Clock input terminal. (Die 1)
SCLK_1 1 14 VCC_2 SPI: Controller-Out/Peripheral-In.
MOSI/SA1_1 2 13 BYP_2 2 MOSI/SA1_1 Manchester/SENT: Sets bit 1 of address field.
Tie to BYP for a logic 1, GND for a logic 0. (Die 1)
CS/SA0_1 3 12 GND_2
SPI chip select terminal, active low input.
VOUT_1 4 11 VOUT_2 3 CS/SA0_1 Manchester/SENT: Sets bit 0 of address field.
Tie to BYP for a logic 1, GND for a logic 0. (Die 1)
GND_1 5 10 CS/SA0_2
SPI: Controller-In/Peripheral-Out, push-pull.
BYP_1 6 9 MOSI/SA1_2 SENT/PWM: Input/Output, open drain.
4 VOUT_1
Manchester: Input/Output, push-pull.
VCC_1 7 8 SCLK_2
(Die 1)
5 GND_1 Device ground terminal. (Die 1)
External bypass capacitor terminal for internal regulator.
6 BYP_1
(Die 1)
7 VCC_1 Power supply. (Die 1)
8 SCLK_2 SPI: Clock input terminal. (Die 2)
SPI: Controller-Out/Peripheral-In.
9 MOSI/SA1_2 Manchester/SENT: Sets bit 1 of address field. Tie to BYP
for a logic 1, GND for a logic 0. (Die 2)
SPI chip select terminal, active low input.
10 CS/SA0_2 Manchester/SENT: Sets bit 0 of address field. Tie to BYP
for a logic 1, GND for a logic 0. (Die 2)
SPI: Controller-In/Peripheral-Out, push-pull.
SENT/PWM: Input/Output, open drain.
11 VOUT_2
Manchester: Input/Output, push-pull.
(Die 2)
12 GND_2 Device ground terminal. (Die 2)
External bypass capacitor terminal for internal regulator.
13 BYP_2
(Die 2)
14 VCC_2 Power supply. (Die 2)
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VCC
0.1 µF
VCC
BYP
0.1 µF
A33003
Optional IO Pull-Ups
≈100 kΩ
VOUT
Host CS/SA0
Microcontroller MOSI/SA1
SCLK GND
Figure 2: A33003 Typical Setup
10 Ω [1] VS [2]
VCC
0.2 µF
4.7 kΩ
VCC
125 Ω
BYP VOUT Host
0.2 µF 1.2 nF Microcontroller
A33003
CS/SA0
MOSI/SA1
[1]
SCLK GND To prevent assertion of the undervoltage flag, power
supply tolerance must be taken into account when
sizing series resister value.
[2]
Ensure VS matches IO voltage level (3.3 V or 5 V).
For 5 V ordering information, contact Allegro.
Figure 3: A33003 Reference Design for Stringent EMC Requirements
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OPERATING CHARACTERISTICS: Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC Customer supply 4.5 – 5.5 V
Supply Current ICC Each die 11 13 16 mA
Undervoltage Flag Threshold VUVD dV/dt = 1 V/ms, A33003 sampling enabled 4.5 – 4.7 V
Supply Zener Clamp Voltage VZSUP ICC = ICC(max) + 3 mA, TA = 25°C 26.5 – – V
Reverse Battery Current IRCC VRCC = –18 V, TA = 25°C – – –5 mA
Power-On Time [1] tPO Power-on diagnostics disabled – 15 – ms
TA = 25°C, CBYP = 0.1 µF, 3.3 V interface 2.93 3.3 3.63 V
Bypass Pin Output Voltage [2] VBYP TA = 25°C, CBYP = 0.1 µF, 5.0 V interface,
4 – 5.5 V
VCC = 5 V
Digital Oscillator Frequency fOSC Main digital oscillator 28 32 36 MHz
SPI INTERFACE SPECIFICATIONS (for 3.3 V interface)
Digital Input High Voltage VIH MOSI, SCLK, CS pins 2.8 – 3.63 V
Digital Input Low Voltage VIL MOSI, SCLK, CS pins – – 0.5 V
SPI Output High Voltage VOH VOUT pins, CL = 20 pF 2.93 3.3 3.63 V
SPI Output Low Voltage VOL VOUT pins, CL = 20 pF – 0.3 – V
SPI INTERFACE SPECIFICATIONS (for 5.0 V interface) (Contact Allegro for 5 V SPI ordering information)
Digital Input High Voltage VIH MOSI, SCLK, CS pins 3.75 – 5.5 V
Digital Input Low Voltage VIL MOSI, SCLK, CS pins – – 0.5 V
SPI Output High Voltage VOH VOUT pins, CL = 20 pF 4 5 – V
SPI Output Low Voltage VOL VOUT pins, CL = 20 pF – 0.3 – V
SPI INTERFACE SPECIFICATIONS
SPI Clock Frequency [3] fSCLK VOUT pins, CL = 20 pF 0.1 – 10 MHz
SPI Clock Duty Cycle [3] DfSCLK SPICLKDC 40 - 60 %
SPI Frame Rate [3] tSPI Assuming a 16-bit SPI packet 5.8 – 588 kHz
Chip Select to First SCLK Edge [3] tCS Time from CS going low to SCLK falling edge 50 – – ns
Time CS must be high between SPI message
Chip Select Idle Time [3] tCS_IDLE 200 – – ns
frames
Data Output Valid Time [3] tDAV Data output valid after SCLK falling edge – – 50 ns
MOSI Setup Time [3] tSU Input setup time before SCLK rising edge 25 – – ns
MOSI Hold Time [3] tHD Input hold time after SCLK rising edge 50 – – ns
SCLK to CS Hold Time [3] tCHD Hold SCLK high time before C̄¯ S̄
¯ rising edge 5 – – ns
Load Capacitance [3] CL Loading on digital output (VOUT) pin – – 20 pF
Continued on the next page…
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OPERATING CHARACTERISTICS (continued): Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
MANCHESTER INTERFACE SPECIFICATIONS
Defined by the input message bit rate sent from
Bit Rate 4 – 40 kbps
the external controller
Data bit pulse width at 4 kbps 243 250 257 μs
Bit Time tBIT
Data bit pulse width at 100 kbps 9.5 10 10.5 μs
Bit Time Error errtBIT Deviation in tBIT during one command frame –11 – 11 %
Delay from the trailing edge of a read
Read Delay tSTART_READ command frame to the leading edge of the read 2 × tBIT – – μs
acknowledge frame
Bit Time Delay tb – 2 – tBIT
Access Code Timeout tmsgRX – – 300 µs
SSENT—Short F_AUX 56 – 70 ticks
SSENT—Long F_AUX 216 – 264 ticks
ASENT F_AUX 56 – 70 ticks
Interrupt Pulse Hold Time tHOLD SENT Aux. interrupt pulse 30 – – ticks
TSENT Aux. interrupt pulse 30 – – ticks
2 × PWM
PWM Aux. interrupt pulse – – µs
period [4]
Deglitch Gate Time tGATE 1.0 – – µs
INPUT SIGNAL VOLTAGE
Manchester Code High Voltage VMAN(H) Applied to PWM/MISO/SENT line 2.8 – VCC V
Manchester Code Low Voltage VMAN(L) Applied to PWM/MISO/SENT line 0.0 – 1.2 V
OUTPUT SIGNAL VOLTAGE
Minimum RPULLUP = 5 kΩ 0.9 × VS – – V
Manchester Code High Voltage VMAN(H)
Maximum RPULLUP = 50 kΩ 0.7 × VS – – V
Manchester Code Low Voltage VMAN(L) 5 kΩ < RPULLUP < 50 kΩ – – 0.1 V
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PWM INTERFACE SPECIFICATIONS
PWM frequency min. setting, TA in specification – 98 – Hz
PWM Carrier Frequency [3] fPWM PWM programmable options – 128 – codes
PWM frequency max. setting, TA in specification – 3.125 – kHz
PWM Output Low Clamp DPWM(min) Corresponding to digital angle of 0x000 – 5 – %
PWM Output High Clamp DPWM(max) Corresponding to digital angle of 0xFFF – 95 – %
PWM Output Resolution RESPWM – 12 – bit
PWM Output Saturation Voltage VSAT_LOW(PWM) Output current = –1 mA, VCC = 5 V, output FET on – – 0.25 V
PWM Current Limit ILIMIT(PWM) Output FET on, TA = 25°C 20 36 45 mA
PWM driver impedance when pulling to logic low;
PWM Output Impedance [3] RON(PWM) 40 – 250 Ω
TA = 25°C
SENT SPECIFICATIONS [3]
SENT Tick Time tTICK All SENT modes [5] 0.5 – 7.9375 µs
SENT Tick Time Tolerance TOLtTICK All SENT modes –15 – 15 %
VSENTtrig(L) VOUT falling, 3.3 V digital – – 1.2 V
SENT Output Trigger Thresholds
VSENTtrig(H) VOUT rising, 3.3 V digital 2.8 – – V
Output current = –4.7 mA, VCC = 5 V,
SENT Output Saturation Voltage VSAT(LOW) – – 0.45 V
output FET on
SENT Output Current Limit ILIMIT Output FET on, TA = 25°C 20 36 45 mA
SENT Output Load Resistance RL(PULLUP) Output current ≥ –10 mA 1.2 – – kΩ
From end of trigger pulse to beginning of SENT
Trigger Delay Time [6] tdSENT 7 – – ticks
message frame (TSENT and shared SENT)
SENT driver impedance when pulled to logic low;
SENT Output Impedance [3] RON(SENT) 40 – 250 Ω
TA = 25°C
BUILT-IN SELF TEST
Logic BIST Time tLBIST Configurable to run on power-up or on user request – 30 – ms
Circular Vertical Hall Self-Test Time tCVHST Configurable to run on power-up or on user request – 52 – ms
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MAGNETIC CHARACTERISTICS
Magnetic Field B Range of input field – – 900 G [7]
ANGLE CHARACTERISTICS
Both 12- and 15-bit angle values are available via
Output [8] RESANGLE – 12/15 – bit
SPI
Angle Refresh Rate [9] tANG No averaging – 2.0 – µs
Response Time [3] tRESPONSE Angular latency – 17 – µs
Effective Resolution [10] B = 300 G [7], TA = 25°C – 12.5 – bits
A33003LLUATR and A33003LLUBTR-DD PERFORMANCE CHARACTERISTICS:

Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristics Symbol Test Conditions [11] Min. Typ. Max. Unit
TA = 25°C, ideal magnet alignment, B = 300 G,
–1.2 ±0.4 1.2 degrees
target rpm = 0
Angle Error ERRANG
TA = 150°C, ideal magnet alignment, B = 300 G,
–1.5 ±0.5 1.5 degrees
target rpm = 0
TA = 150°C, B = 300 G –1.75 – 1.75 degrees
Temperature Drift ANGLEDRIFT
TA = –40°C, B = 300 G – ±1 – degrees
TA = 25°C, B = 300 G, no internal filtering,
– ±0.19 – degrees
target rpm = 0, 3 sigma noise
Angle Noise [12] NANG
TA = 150°C, no internal filtering, B = 300 G,
– ±0.25 – degrees
target rpm = 0, 3 sigma noise
B = 300 G, average maximum drift observed
Angle Drift Over Lifetime [13] AngleDrift_Life – 0.34 – degrees
following AEC-Q100 qualification testing
[1] During the power-on phase, the A33003 SPI transactions are valid within ≈ 300 µs of power on (with no self-tests). Angle reading requires full tPO to stabilize.
[2] The output voltage specification is to aid in PCB design. The pin is not intended to drive any external circuitry. The specifications indicate the peak capacitor charging and
discharging currents to be expected during normal operation.
[3] Parameter is not guaranteed at final test. Determined by design.
[4] The minimum hold time for the Auxiliary interrupt, when the output is set for PWM, is double the PWM period. If the PWM frequency increases as a result of a diagnostic
condition, the hold time is double the new PWM period at the diagnosis frequency.
[5] Tick times less than 0.5 µs are available, but not guaranteed.
[6] The synchronization pulse delay is a minimum of 7 ticks but can be extended to cover Slot Marking in SSENT.
[7] 1 G (gauss) = 0.1 mT (millitesla). Recommended minimum field is 300 G.
[8] RES
ANGLE represents the number of bits of data available for reading from the die registers.
[9] The rate at which a new angle reading becomes ready.
[10] Effective Resolution is calculated using the formula below:
Effective Resolution = log2(360) – log2 ( 1

n
×
n
i=1
i )
where σ is the Standard Deviation based on thirty measurements taken at each of the 32 angular positions, I = 11.25, 22.5, … 360.
[11] 1G (gauss) = 0.1 mT (millitesla).

[12] This value represents 3-sigma, or three times the standard deviation, of the measured samples.
[13] Maximum drift observed during AEC-Q100 testing was 1.076 degrees.
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TYPICAL PERFORMANCE CHARACTERISTICS

The figures below show performance data from 30 samples of A33003LLUBTR-DD devices.
Angle Error Angle Drift

2 2
Mean Angle Error Mean Angle Drift
1.8 Mean ±3 Sigma 1.8 Mean Drift ±3 Sigma
1.6 1.6
1.4 1.4
Angle Error [Degrees]
Angle Drift [Degrees]

1.2 1.2
1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
–40 –30–20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140150 –40 –30–20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140150
Temperature [Degrees Celsius] Temperature [Degrees Celsius]
Figure 4: Peak Angle Error over Temperature Figure 5: Maximum Absolute Drift over Temperature
(300 G) (300 G)
Angle Noise
0.3
Mean Noise
Mean Noise ±3 Sigma
0.25
Angle Noise [Degrees]
0.2
0.15
0.1
0.05
0
–40 –30–20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140150
Temperature [Degrees Celsius]
Figure 6: Noise Performance over Temperature

(3-Sigma, 300 G)
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FUNCTIONAL DESCRIPTION
Overview System-Level Timing

The A33003 is a rotary position Hall-sensor-based device in Internal registers are updated with a new angle value every tANG.
a surface-mount package, providing solid-state consistency Due to signal path delay, the angle is tRESPONSE old at each update.
and reliability, and supporting a wide variety of automotive In other words, tRESPONSE is the delay from time of magnet
applications. The Hall-sensor-based device measures the direction sampling until generation of a processed angle value. SPI, which
is asynchronously clocked, results in a varying latency depending
of the magnetic field vector through 360° in the x-y plane
on sampling frequency and SCLK speed. The values presented
(parallel to the branded face of the device) and computes an angle
to the user are latched to the output registers on the first SCLK
measurement based on the actual physical reading, as well as any edge of the SPI output frame. This means that, if the SPI clock
internal parameters that have been set by the user. The output is is 10 MHz, the data are clocked out after 1.6 µs. Because the
used by the host microcontroller to provide a single channel of data are sampled-in at the first clock edge at an age of maximum
target data. tRESPONSE, its age after the SPI transaction has finished is between
1.6 and 1.6 + tRESPONSE µs.
This device is an advanced, programmable system-on-chip (SoC).
The integrated circuit includes a circular-vertical-Hall (CVH) ana- Similar to SPI, when using the PWM output, the output packet is
log front end, a high-speed sampling analog-to-digital converter, not synchronized with the internal update rate of the sensor. The
digital filtering, and digital signal processing. angle is latched at the beginning of the carrier frequency period
(effectively at the rising edge of the PWM output). Because of
Advanced offset, gain, and linearization adjustment options are this, the age of the angle value, once read by the system micro-
available in the A33003. These options can be configured in controller, may be up to tresponse + 1/fPWM.
onboard EEPROM, providing a wide range of sensing solutions
The point within the SENT packet at which the angle value is
in the same device. latched varies with SENT configurations. However, in all config-
urations, the SENT transmission time is the dominant contributor
Angle Measurement
to the delay. For a detailed description, see Appendix A: SENT
The A33003 is capable of tracking magnet position at high speed. Output Description.
Performance up to 12,000 rpm has been verified by testing.
Power-Up
Operation up to 30,000 rpm has been verified via design simula-
tion. The A33003 has a typical output refresh rate of 2 µs. Upon applying power to the A33003, the device automatically
runs through an initialization routine. The purpose of this
Readout in SPI is possible with 12-bit resolution, with error initialization is to ensure that the device comes up in the
flags included in the same word, or in 15-bit resolution without same predictable operating condition every power cycle. This
included error flags. Reading out the angle requires a minimum initialization routine takes time to complete, which is referred to
of 16 SPI clock cycles. A 20-bit SPI packet with 4 bits of CRC is as power-on time, tPO. If diagnostics are enabled at power-up,
also supported. additional time is required for the device to complete the
programmed tests. Regardless of the state of the device before
PWM output is always resolved to a 12-bit angle value. a power cycle, the device repowers with EEPROM shadow
When using SENT output, a 12-bit or 16-bit angle packet may be bits copied from the EEPROM and with serial registers in their
selected via the DATA_MODE field in EEPROM. default states. For example, on every power-up, the device
powers up with the zero_offset that was stored in the EEPROM.
The sensor readout is processed and linearized in various steps. The extended write access field, WRITE_ADR, is set back to its
These are detailed in Figure 9. default value of zero.
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PWM Output PWM CARRIER FREQUENCY

The A33003 provides a pulse-width-modulated (PWM) open- The PWM carrier frequency is controlled via two EEPROM
drain output, with the duty cycle proportional to measured angle. fields, both of which are found in the PWS row.
The PWM duty cycle is clamped at 5% and 95% for diagnostic • PWM_FREQ
purposes. A 5% duty cycle corresponds to 0°; a 95% duty cycle
corresponds to 360°. • PWM_BAND
Together, these two fields allow 128 different PWM carrier fre-
D = 5% D = 50% D = 95%
quencies to be selected.
Magnetic Field Angle (°)
360
CLAMP_HIGH
Table 1: PWM Carrier Frequencies in Hz
CLAMP_LOW
0 PWM_BAND
0 1 2 3 4 5 6 7
D0T D1T D2T D3T D4T D5T D6T D7T D8T D9T D10T
PWM Waveform (V)
0 3125 2778 2273 1667 1087 641 352 185

D(x) = tpulse(x) / Tperiod 1 3101 2740 2222 1613 1042 610 333 175
tpulse(5) 2 3077 2703 2174 1563 1000 581 316 166
Tperiod
3 3053 2667 2128 1515 962 556 301 157
Time
0T 1T 2T 3T 4T 5T 6T 7T 8T 9T 10T 11T
4 3030 2632 2083 1471 926 532 287 150
Figure 7: PWM Mode Outputs a Duty Cycle 5 3008 2597 2041 1429 893 510 275 143
Proportional To Sensed Angle 6 2985 2564 2000 1389 862 490 263 137
PWM_FREQ
7 2963 2532 1961 1351 833 472 253 131

Within each cycle, the output is high for the first 5% and low
for the last 5% of each period. The middle 90% of the period is 8 2941 2500 1923 1316 806 455 243 126
a linear interpolation of the angle as sampled at the start of the 9 2920 2469 1887 1282 781 439 234 121
PWM period. 10 2899 2439 1852 1250 758 424 225 116
11 2878 2410 1818 1220 735 410 217 112
PWM Period PWM Period
12 2857 2381 1786 1190 714 397 210 108
13 2837 2353 1754 1163 694 385 203 105
5 % HIGH
5 % HIGH
5 % HIGH
14 2817 2326 1724 1136 676 373 197 101

5 % LOW
5 % LOW
5 % LOW
120 15 2797 2299 1695 1111 658 362 191 98

(0 Degrees) Degrees
PWM Period PWM Period

5 % HIGH
5 % HIGH
5 % HIGH
5 % LOW
5 % LOW
5 % LOW
360 Degrees 240 Degrees
Figure 8: Pulse-Width Modulation (PWM) Examples

The angle is represented in 12-bit resolution and can never reach
360°. The maximum duty cycle high period is:
DutyCycleMax (%) = (4095 / 4096) × 90 + 5 .
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ERROR REPORTING IN PWM Table 3: PWM Error Select (PES)

The PWM output can be configured to change state if certain Code Description
errors occur. There are three options: 0 PWM tristates on an error.
• No error reporting 1 PWM carrier frequency halved and highest
priority error output on PWM as selected duty
• Tristate the PWM cycle.
• Halve the carrier frequency and represent the error via The error priority and corresponding duty cycle are shown in
different duty cycles Table 4, with the high-priority error dictating the PWM duty
Two EEPROM bits, PEO and PES, control how errors are cycle.
reported in PWM mode. Both PEO and PES are in the PWS Each error is individually enabled for PWM reporting, so that
address row of EEPROM: only events of interest interrupt the device output. These enable
Table 2: PWM Error Output Enable Option (PEO) bits may be found within the PWE (0x18) EEPROM row.
Code Description
0 PWM does not respond to errors.
1 PWM output responds to errors as selected with
the PES field.
Table 4: PWM Error Duty Cycle and Priority

Error Priority Duty Cycle % Description / Persistence
WDE 1 (highest) 5 Watchdog error. Permanent.
EUE 2 10.625 EEPROM uncorrectable error.
STF 3 16.25 Self-test failure. Permanent.
PLK 4 21.875 PLL not locked. Persists until PLL locks.
ZIE 5 27.5 Zero-crossing integrity error. Persists until goes away.
AVG 6 33.125 Angle averaging error. Outputs once then clears.
Undervoltage (UVA and/or UVCC dependent on serial error masks).
UV 7 38.75
Persists until no unmasked undervoltage.
MSL 8 44.375 Persists until field strength higher than low threshold.
ESE 9 50 EEPROM correctable error. Outputs once then clears.
SAT 10 55.625 Persists until no saturation warnings.
MSH 11 61.25 Persists until field strength lower than high threshold.
TR 12 66.875 Persists until temperature within range.
TOV 13 72.5 Persists until cleared via the serial CTRL register.
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ZCD path
CVH
PLL path
Mixed-origin data
ΣΔ- ADC
Filter and ZCD angle Filter and PLL angle

measurement logic measurement logic
Angle averaging
(ORATE)
Field strength
measurement
Rotation direction Offset adjust

(RO) (ZERO_OFFSET)
Segmented
linearization
Offset adjust (ELI, LS, LIN##)
Rotation direction
(ZCD_TURNS_OFFSET) (RO)
Segmented
Offset adjust linearization
(ZERO_OFFSET) (ELI, LS, LIN##)
ZAL = 0
180° rotation
(RD)
GAUSS
output register
ANGLE_ZCD Angle hysteresis PWM pin

output register PEN, PWM_BAND, PWM_FREQ, PEO, PES
(HYSTERESIS) PHE = 0
H2T = 0 ANGLE and ANGLE_15

output register
Angle source
ANGLE_HYS output register
combination logic
TCP = 1 PLL_TURNS_ANGLE output register
Accumulate angle changes into 21-bit

value , resolution 4096 counts / 360° TURNS_DELTA output register
(initial value depends on TURNS_INIT)
Take 10 MSB of TURNS_DELTA TURNS output register

resolution 45° or 180°
Take 12 MSB of TURNS_DELTA T45 = 1
TURNS_OFFSET output register

Take 11 LSB of TURNS_DELTA T45 = 1
Take 9 LSB of TURNS_DELTA
Figure 9: Angle Measurement—Sensor Readout Steps
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Linearization
The A33003 contains linearization functionality. Linearization
Table 5: Linearization Coefficients
allows for conversion of the initially sensor-measured magnetic
Electrical Correction
field data into customer-desired linear output. This can be used Angle (°) Value Output Angle
to correct minor imperfections in the encoder signal, or to allow Measured by Written in Visible on Sensor Output
motor commutation in side-shaft measurement setups. Sensor EEPROM
0.00 LIN0 Output = 0.00 – LIN0
Linearization converts the electrical angles (the angle as mea-
sured by the sensor front end) into mechanical angles (the actual 11.25 LIN1 Output = 11.25 – LIN1
angle of the encoder signal). 22.50 LIN2 Output = 22.50 – LIN2
33.75 LIN3 Output = 33.75 – LIN3
To use the linearization feature, it is most convenient to use the
Allegro A33003 Samples Programmer Graphical User Interface 45.00 LIN4 Output = 45.00 – LIN4
(GUI). [1] It allows the user to measure points along the mechani- 56.25 LIN5 Output = 56.25 – LIN5
cal rotation, calculate all parameters that need to be written into 67.50 LIN6 Output = 67.50 – LIN6
the sensor, and write these values into the sensor. To use this 78.75 LIN7 Output = 78.75 – LIN7
function, the user must be able to read and control the mechanical 90.00 LIN8 Output = 90.00 – LIN8
angle.
101.25 LIN9 Output = 101.25 – LIN9
The sensor performs linearization by taking the measured electri- 112.50 LIN10 Output = 112.50 – LIN10
cal angles and, depending on the angle measured, subtracting 123.75 LIN11 Output = 123.75 – LIN11
a linearization coefficient stored in EEPROM. There are 32 of
135.00 LIN12 Output = 135.00 – LIN12
these linearization coefficients in the EEPROM. The angle value
146.25 LIN13 Output = 146.25 – LIN13
at a sensor angle reading of 0.00, 11.25, 22.50, … 348.75 electri-
cal degrees become modified by the values in EEPROM fields 157.50 LIN14 Output = 157.50 – LIN14
LIN0, LIN1, LIN2, … LIN31. The EEPROM LIN values are 168.75 LIN15 Output = 168.75 – LIN15
subtracted from the electrical sensor angles, as shown in Table 5. 180.00 LIN16 Output = 180.00 – LIN16
The LIN fields are 12-bit signed values. Each LIN coefficient has 191.25 LIN17 Output = 191.25 – LIN17
a range of –2048…+2047 LSB that corresponds to a correction of 202.50 LIN18 Output = 202.50 – LIN18
the electrical angle by +22.50…–22.49 degrees (EEPROM field 213.75 LIN19 Output = 213.75 – LIN19
LS = 0) or by +45.00…–44.98 degrees (EEPROM field LS = 1). 225.00 LIN20 Output = 225.00 – LIN20
When the electrical angle is between two of the linearization 236.25 LIN21 Output = 236.25 – LIN21
points, the sensor calculates the appropriate correction value for
247.50 LIN22 Output = 247.50 – LIN22
this angle by linear interpolation between the two coefficients
258.75 LIN23 Output = 258.75 – LIN23
next to the value. For example, if the sensor measures an angle of
5.625°, the output is 5.625 – (LIN0 + LIN1)/2. 270.00 LIN24 Output = 270.00 – LIN24
281.25 LIN25 Output = 281.25 – LIN25
An example of a nonlinear curve that is corrected by the sensor is
292.50 LIN26 Output = 292.50 – LIN26
shown in Figure 10. In this example, the values of LIN0 through
LIN4 are positive numbers, while LIN5 and LIN6 are negative 303.75 LIN27 Output = 303.75 – LIN27
numbers. The straight-line interpolation between LIN points typi- 315.00 LIN28 Output = 315.00 – LIN28
cally gives rise to some residual error because the device fits a line 326.25 LIN29 Output = 326.25 – LIN29
to a nonlinear error profile, as shown in Figure 11. 337.50 LIN30 Output = 337.50 – LIN30
The output delay of the A33003 is not affected by enabling or 348.75 LIN31 Output = 348.75 – LIN31
disabling linearization. If linearization is disabled, the EEPROM
LIN fields can be used for other customer purposes.
[1] Available for download via the Allegro Software Portal at https://registration.allegromicro.com/login
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90
Electrical Angle (not linearized)
Linearization Parameters
78.75 Ideal Output
LIN6
Sensor Angle (degrees)
67.5 LIN5
56.25 LIN4
45 LIN3
33.75 LIN2
22.5 LIN1
11.25 LIN0
0
0 11.25 22.5 33.75 45 56.25 67.5 78.75 90
Rotational Angle (degrees)
Figure 10: Linearization Example
Post-Linearization Performance
10
Prelinearization Angle
8 Linearization Segments
Residual Error
6
Angle Error (degrees)
-2
-4
-6
-8
-10
0 10 20 30 40 50 60 70 80 90
Electrical Angle (degrees)
Figure 11: Post-Linearization Error
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Angle Hysteresis direction, the output angle is held static until the sensor angle
exits the hysteresis window in either direction. If the exit is in
Hysteresis can be applied to the compensated angle to moderate the opposite direction of rotation where the “head” was, the
jitter in the angle output due to noise or mechanical vibration. In head flips to the opposite end of the hysteresis window and that
the A33003, the hysteresis field (ANG.HYSTERESIS) defines becomes the new reference direction. The current direction of
the width of an angle window at 14-bit resolution. Mathemati- rotation, or “head” for the purposes of hysteresis, is viewable via
cally, the width of this window is: the STA.ROT bit, where 0 is in the increasing angle direction,
ANG.HYSTERESIS × (360/16384) degrees, and 1 is in the decreasing angle direction.
giving a range of 0 to 1.384 degrees. This behavior has the following consequences:
On the SPI or Manchester interface, the hysteresis- 1. If the hysteresis window is greater than the output resolution,
compensated angle can be read via an alternate register the output angle skips consecutive resolution steps.
(HANG.ANGLE_HYS) at 12-bit resolution. 2. If there is jitter due to noise or mechanical vibration, especially
The effect of the hysteresis is shown in Figure 12. The current at a static angle position or very slow rotation, the angle tends
angle position as measured by the sensor is at the “head” of to bias to one side of the window, depending on the direction
the hysteresis window. As long as the sensor (electrical) angle of rotation as the angular velocity approaches zero (i.e., toward
advances in the same direction of rotation, the output angle is the current “head”), rather than to the average position of the
the sensor angle, minimizing latency. If the sensor angle reverses jitter.
Sensor angle posi�on

Output angle
Sensor angle and output angle the same
Hysteresis Window of hysteresis
Rota�on Direc�on of rota�on as observed by the hysteresis logic
Electrical Angle
1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1
Rota�on Hysteresis 2.7
Hysteresis 2.9
Hysteresis 2.9
Hysteresis 2.9
Hysteresis 2.9
OUTPUT ANGLE
Hysteresis 2.9
Hysteresis 3.0
TIME
Hysteresis 3.0
Hysteresis 3.0
Angle Jump
NOTE: The rotation direction resets to 0, or increasing angle direction. At power-up or after LBIST, the hysteresis window is always behind the initial angle posi-
tion; so, if hysteresis is enabled, a decreasing angle direction of rotation does not register until the hysteresis window has passed.
Figure 12: Effect of Hysteresis
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Turns Counting 360
270
Certain automotive angle-sensing applications involve the mag-
Angle [deg]
netic target rotating multiple times. Thus, tracking the turns of 180
the measured magnet becomes more important than knowing the 90

specific angle at which the target sits. Examples of such applica-
0 time
tions include:
8192
• Seat-belt passive safety systems
Turns_delta value
6144
• EPS motor position 4096
This implementation can also be used to measure exact angle 2048
in cases where the rotation is geared-up such that a slight angle
0 time
rotation of the device of interest results in multiple rotations of
a target magnet that the sensor is measuring. For this reason, 16
45 degree count
Turns_count value
the A33003 includes a circuit that counts the rotational turns of 12
180 degree count
a magnet. This feature also includes the ability to start up with 8

a preset value, allowing the turns counter to persist through
4
powered-down periods, when combined with adequate system-
level control. Traditionally, recovering the turns counter value 0 time
was achieved by a combination of relatively complex mechanical

Figure 13: Turns Counting
and electrical components. The A33003 can help reduce system-
level complexity and eliminate many system components by
performing both the absolute angle measurement and the tracking 360 Reset
of turns.
270
Angle [deg]
It is possible to use the zero-crossing diode (ZCD) signal path as

180
the turns-counter source. This is performed by setting the TCP
field in EEPROM to 0. 90
To read the total position of the magnetic encoder (angle in 0 time

12-bit resolution, as well as additional revolutions in 9 bits, sign- 5120
extended to 12 bits), a serial register TURNS_DELTA is pro- turns_init = 00, 01
turns_init = 10
vided. This 24-bit word accumulates the total changes in angle. 4096
turns_init = 11, t45 = 0
The initial value of the register (zero, current angle, or current
Turns_delta value
3072
angle with TURNS_COUNT zeroed) can be controlled using the
2048
EEPROM field TURNS_INIT, as detailed in Figure 14.
1024
0 time
-1024
Figure 14: EEPROM field TURNS_INIT
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Turns Counting Behavior on Power-Up register (address 0x2C) is simply the upper bits from the
TURNS_DELTA value. When configured in 180° turns mode
Turns tracking, as measured by the IC, is derived from the (i.e., T45 = 0), the upper 10 bits are used; if in 45° mode (i.e.,
TURNS_DELTA register. This is a 21-bit register that tracks T45 = 1), the upper 12 bits are used to indicate the turns. The
absolute angle across multiple magnetic rotations by tracking A33003 is capable of tracking up to –512/+511 turns in 180°
change in angle from a reference position. The actual TURNS mode and –2048/+2047 in 45° mode.
TURNS_DELTA register
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
11 10 9 8 7 6 5 4 3 2 1 0 TURNS register with T45 = 0

SE SE 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 SE = sign extended
TURNS_DELTA register
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
11 10 9 8 7 6 5 4 3 2 1 0
TURNS register with T45 = 1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Figure 15: Turns Register

The reference position from which the turns_delta is measured For a TURNS_INIT value of 002 or 012, the TURNS_DELTA
impacts the initial turns count value. The TURNS_INIT field has register measures the change in position relative to the observed
the following options controlling this: angle on power-up. As such, the value of the turn is initialized to 0
on sensor reset.
Table 6: turns_init (EEPROM 0x1D bits 19:18)
turns_init Description
When TURNS_INIT = 102, the turns_delta value represents the
difference in position relative to the sensor’s defined 0° position;
00 Turns counter is zeroed on power-up. Turns
are tracked relative to the angle observed on put more simply, the TURNS_DELTA is initialized to the angle
01 observed on power-up. As shown in Figure 14, once the reset
power-up.
TURNS_DELTA = 0 at power-up. occurs, the TURN_DELTA register is loaded with 3072 codes,
10 Turns counter is set relative to the defined 0 which is 270° in 12-bit resolution. Depending on the T45 setting,
position of the sensor, which may be a nonzero this is reflected as a turn value of 1 (in 180° mode) or 6 (in 45° mode).
number.
TURNS_DELTA is set to the angle observed on When TURNS_INIT = 112, the turns count is initialized to 0,
power-up. and the increment/decrement points for turns counting are fixed
11 Turns counter value initialized to zero, but to either the 0°/180° or the 0°/45°/90°/135°/180°/225°/270°/315°
increments on the 0°/180° or 45° boundaries as boundaries, based on the T45 field. The TURNS_DELTA regis-
observed by the IC (set via the T45 field).
TURNS_DELTA register is initialized with an offset ter becomes loaded with the angular distance between two adja-
based on the T45 register. cent boundaries (0°/180° or a multiple of 45°). For example, in
Figure 14, the T45 bit = 0, enabling 180° mode. The value of the
Control of the starting turns count value via the TURNS_INIT turn, in this case, is 0. The angle on power-up is 270°, which is
field is illustrated in Figure 14, where the angle constantly 50% between 180° and 360°; to reflect this, the TURNS_DELTA
increases up to 270°, after which a sensor reset occurs. register is loaded with 1024 codes indicating it is halfway
between one turn (i.e., 180° in 12-bit resolution, or 2048 codes).
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Setting the Turns Count Value B. Write the lower 16 bits into the EWDL register and the
upper 5 bits into the EWDH register, with leading zeroes
There are two ways to modify the value of the turns counter. to make the 16-bit value to write. This results in writing
• Using the turns counter reset function 0x0001 to EWDH (0x04:0x05) and 0xD00F to EWDL
(0x06:0x07).
• Writing the TURNS_DELTA value to register EWD and
loading it into TURNS_DELTA 3. Write the value 0x03 to the SPECIAL field, and write 0x46
to the INITIATE_SPECIAL field.
INVOKING A TURNS COUNTER RESET 4. The sensor behavior to process the setting depends on the set-
Resetting the turns counter is a command invoked using the ting of the TURNS_INIT EEPROM field:
SPECIAL field of the CTRL register. A. When TURNS_INIT = 002 or 012, the value is copied to
TURNS_DELTA, and subsequent angle changes accu-
CHANGING OR RESTORING TURNS_DELTA VALUE mulate on top of this value. Because small offset changes/
It is possible to load a desired value into the turns counter regis- noise errors accumulate every time such a write is
ter. This may be useful if a certain externally stored value should performed, this method is not recommended for scenarios
be set again following a power loss. The turns counter register where the saved value must be restored.
itself cannot be written directly. Instead, the writing action is an B. When TURNS_INIT = 102 or 112, the value is compared
indirect one using the following steps: to the currently sensed angle. The TURNS_DELTA field
1. Before writing, ensure the system is stable, as indicated by “snaps” to the closest value matching the sensed angle.
the STA.AOK bit field. Errors in position of <180° are removed this way. This
method is recommended if a saved turns count value must
2. Write the desired 21-bit value of TURNS_DELTA into the be restored, but the measured angle may have changed
EWDH and EWDL serial registers in little-endian format. slightly in the meantime.
Example:
A. To set the TURNS_DELTA to value 10441.32° (29 rota-
tions and 1.32° current angle), write (10441.32 / 360) ×
4096 = 118799 = 0x01D00F.
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DEVICE PROGRAMMING INTERFACE

The A33003 can be programmed in two ways: EEPROM writing requires additional procedures. For more infor-
mation, see the EEPROM and Shadow Memory Use section or
• Using the SPI interface for input and output
contact your Allegro representative.
• Using a Manchester protocol on the VOUT pin.
The A33003 features an internal charge pump and does not SPI Interface
require high-voltage pulses to write to EEPROM. The setup for programming using the SPI interface is given in
All setting fields and all data fields of the sensor can be read Figure 16.
and written using both protocols. Locking the EEPROM from Fixed supply
changes locks EEPROM write access from both protocols. voltage, e.g. 5 V
A separate setting to completely disable the Manchester interface VCC

is available in the PWS.DM field of the EEPROM. Using this
Host
setting causes the sensor to ignore any commands entered using
SPI
Manchester protocol. The SPI interface does not become disabled Sensor
by disabling the Manchester interface. R/W commands and
return data (SPI)
For details regarding the programming procedures, contact your
Allegro representative. GND GND
SWITCHING BETWEEN THE DIFFERENT Figure 16: SPI Interface Programming Setup
OUTPUT PROTOCOLS
SPI INTERFACE TIMING
The A33003 supports four output protocols (SPI, Manchester,
SENT, PWM), all of which overlap with the same pin. Below is The SPI interface operates in pure peripheral mode, with the con-
the hierarchy of precedence for control of the MISO pin. troller controlling the SCLK, MOSI, and CS lines. The control-
ler can maximize data throughput, up to fSCLK(max) of 10 MHz.
• SPI, when set with SPO bit within the serial register. The timing for read and write cycles is shown in Figure 17 and Fig-
• Manchester communication (when the auxiliary interrupt pulse ure 18.
is sent). tCS_IDLE
• PWM, when set via the PWS.PEN bit in EEPROM.

CSx
• SENT, when enabled via the SENT_MODE field in EEPROM. tCS tSCLKL tSCLKH tCHD
• Manchester, when neither PWM or SENT is enabled; SCLKx

SPI, when Manchester is disabled. tSU tHD
When the SPO bit is set, the SPI interface immediately overrides MOSIx R/W
all other output protocols—this includes Manchester. If this bit is

set via the Manchester interface, the device ends the Manchester Figure 17: A33003 SPI Interface Timings Input
interface and stops responding to Manchester communication tCS_IDLE
until SPO is cleared.

CSx
INTERFACE STRUCTURE
tCS tSCLKL tSCLKH tCHD
The primary serial interface registers are used for direct writes SCLKx
tDAV
and reads by the host controller for frequently required data. All
forms of communication operate through these registers, whether MISOx DO-15 DO-14 DO-x
it be via SPI or Manchester. These registers also provide a data Register Contents
and address location for accessing extended memory locations
under control of the onboard processor. Figure 18: A33003 SPI Interface Timings Output
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SPI MESSAGE FRAME SIZE typically performed in the case of long interface delays caused by
The SPI interface requires either 16-, 17-, or 20-bit packet large line capacitances or very long cables. Due to the sampling
lengths. The extended 20-bit SPI packet allows 4-bit CRC to on the falling edge, an additional 17th clock is required for the
accompany every data packet. The 17-bit packet is only allowed 16 bits of data.
when the EEPROM/shadow bit S17 = 1. If more or less clock pulses than expected are detected by the sen-
The purpose of the 17-bit SPI option is to allow a delayed reading sor during a SPI transaction, the interface warning, WARN.IER,
of the MISO line on the host side. Some hosts allow data to be becomes set. This occurs for anything other than 16 or 20 when
sampled from the peripheral on the falling edge of SCLK. This is S17 = 0, or anything other than 17 when S17 = 1.
CSx
SCLKx
MOSIx R/W A5 A4 A3 A2 A1 A0 DI-7 DI-6 DI-5 DI-4 DI-3 DI-2 DI-1 DI-0
MISOx DO-15 DO-14 DO-13 DO-12 DO-11 DO-10 DO-9 DO-8 DO-7 DO-6 DO-5 DO-4 DO-3 DO-2 DO-1 DO-0
Figure 19: Sixteen-Bit SPI Transaction
CSx
SCLKx
MOSIx R/W A5 A4 A3 A2 A1 A0 DI-7 DI-6 DI-5 DI-4 DI-3 DI-2 DI-1 DI-0 ICRC-3 ICRC-2 ICRC-1 ICRC-0
MISOx DO-15 DO-14 DO-13 DO-12 DO-11 DO-10 DO-9 DO-8 DO-7 DO-6 DO-5 DO-4 DO-3 DO-2 DO-1 DO-0 OCRC-3 OCRC-2 OCRC-1 OCRC-0
Figure 20: Twenty-Bit SPI Transaction
SPI OUTPUT VOLTAGE LEVELS

The A33003 can operate in either 3.3 or 5 V SPI mode. Contact
Allegro MicroSystems for more information.
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WRITE CYCLE OVERVIEW The simultaneous MISO signal output represents the contents
of the corresponding die SPI read packet, including 16 data bits
Write cycles consist of a 1-bit low, a 1-bit R/W asserted high, 6
and 4 optional CRC bits—automatically included if a 17th SCLK
address bits (corresponding to the primary serial register), 8 data
edge is detected. The data bits correspond to the register con-
bits, and 4 optional CRC bits. To write a full 16-bit serial register, tents selected during the previous read command. If the previous
two write commands are required (even and odd byte addresses). command was a write command, the device, by default, outputs
MOSI bits are clocked in on the rising edge of the controller- the angle register (0x20). If no previous command was sent, i.e.,
generated SCLK signal. The complete SPI packet is latched on the first SPI packet after POR, the data sent by the device is
the rising edge of the controller-generated (CS) signal. indeterminate.
CSx Input
latched
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLKx
MOSIx R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Register Contents (previous Read command selection, or Don’t Care)
Figure 21: SPI Write Example
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READ CYCLE OVERVIEW ing edge of the controller-generated (CS) signal. The MISO bits
are the contents of the register selected during the first stage, read
Read cycles have two stages: a read command to select a serial
16 bits at a time. The MISO bits transmit on the falling edge of
register address, followed by another read command to transmit
the SCLK signal, such that the controller can sample them on the
the data from the selected register. Both commands consist of a
SCLK rising edges.
1-bit low, a 1-bit R/W asserted low, 6 address bits identifying the
target register, and 8 data bits (all zeroes because no data is being Because a SPI read can transmit 16 data bits at one time and the
written). primary serial registers are built from one even and one odd byte,
the entire 16-bit contents of one serial register may be transmit-
In the first stage, as with the write command, read command ted with one SPI frame. This is accomplished by providing an
MOSI bits are clocked-in on the rising edge of the controller- even serial address value. If an odd value address is sent, only the
generated SCLK signal and data-latched on the rising edge of the contents of the single byte are returned, with the 8 MSBs within
(CS) signal. During the first read stage, the simultaneous MISO the SPI packet set to zero.
signal output is the content of the SPI read data from the previous
Example: To read all 16 bits of the error register (0x24:0x25),
read command.
send a SPI read request with the address bits set to 0x24. If only
In the second stage, the read command continues on the next fall- the 8 LSBs are desired, use the address 0x25.
Input
CSx
latched
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLKx
Figure 22: SPI Read Example, Register Selection

CSx
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLKx
Figure 23: SPI Read Example, Data Output

From Selected Register
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CRC The CRC can be calculated with the following C code:

To check the data coming from the sensor, 20-bit SPI frames can /*
be used. Without additional setting required, a 4-bit CRC is auto- * CalculateCRC
*
matically generated and placed on the MISO line if more than 16 * Take the 16-bit input and generate a 4-bit CRC
bits are read from the sensor. * Polynomial = x^4 + x + 1
* LFSR preset to all 1’s
The four additional CRC bits on the MOSI line coming from */
the host are ignored by the sensor, unless the PWS.SC bit is set uint8_t CalculateCRC(uint16_t input)
within EEPROM (0x1B, bit 0). When the incoming CRC check {
bool CRC0 = true;
is enabled, an incoming SPI packet with an incorrect CRC is bool CRC1 = true;
discarded, and the CRC error flag is set in the WARN.CRC serial bool CRC2 = true;
register. bool CRC3 = true;
int i;
The CRC is based on the polynomial x4 + x + 1 with the linear bool DoInvert;
feedback shift register preset to all ones. The 16-bit packet is uint16_t mask = 0x8000;
shifted through from bit 15 (MSB) to bit 0 (LSB). The CRC logic
for (i = 0; i < 16; ++i)
is shown in Figure 24. Data are fed into the CRC logic with MSB {
first. Output is sent as C3-C2-C1-C0. DoInvert = ((input & mask) != 0) ^ CRC3;
CRC3 = CRC2;
C0 C1 C2 C3 CRC2 = CRC1;
Input Data CRC1 = CRC0 ^ DoInvert;
CRC0 = DoInvert;
mask >>= 1;
}
Figure 24: SPI CRC return (CRC3 ? 8U : 0U) + (CRC2 ? 4U : 0U) + (CRC1 ? 2U
The CRC output by the sensor on the MISO pin is always : 0U) + (CRC0 ? 1U : 0U);
}
correct. The CRC from the host on the MOSI pin must be correct
if the CRC enable bit PWS.SC in the EEPROM was set.
NOTE: If the extended read data (ERD) register is read before the
ERCS.ERD bit indicates a read has completed, there is a pos-
sibility of a CRC error, because the data could change during the
read. Do not read the ERD register until it is known to be stable,
as evidenced by either an indication that the read is complete or
sufficient passage of time.
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Manchester Serial Interface ENTERING MANCHESTER COMMUNICATION MODE

The A33003 incorporates a serial interface shared with the Provided the disable Manchester bit is not set in EEPROM, there
standard output line (VOUT). (Note: The A33003 may be pro- are two ways to begin Manchester communication:
grammed via SPI, with additional wiring connections). This inter- 1. If PWM, SENT, and SPO are disabled, and if Manchester
face allows an external controller to read and write to registers in is the active communication protocol, only the Manchester
the A33003 EEPROM and volatile memory without the need for entry code on the VOUT pin is required to begin Manchester
the host controller to control VCC or to share the same VCC line. communication.
The device uses a point-to-point communication protocol, based
2. If PWM or SENT protocols are enabled, the Manchester
on Manchester encoding per G.E. Thomas (a rising edge indi-
auxiliary interrupt pulse or auxiliary function
cates a 0, and a falling edge indicates a 1), with address and data
(F_AUX) pulses must be used, followed by the
transmitted MSB first. The addressable Manchester code imple-
Manchester entry code. Once this has been completed,
mentation uses the logic states of the SA0/SA1 pins to set address
Manchester communication is enabled. If no entry
values for each die. In this way, individual communication with
code is received after an auxiliary interrupt pulse or F_AUX
up to four A33003 die is possible per line.
pulse for tmsgRX, the Manchester interface times out, and the
To prevent any undesired programming of the A33003, the serial device returns to its previous operating state.
interface can be disabled by setting the disable Manchester bit
(PWS.DM EEPROM address 0x1B, bit 3) to 1. With this bit set, NOTE: If the MEPE bit = 0, the auxiliary interrupt pulse
the A33003 ignores any Manchester input commands. and F_AUX pulses are disabled. Because of this, Manchester
VCC_1 VCC_2 communication is not possible when PWM or SENT are
active.
R/W Commands Once the Manchester communication mode is entered, the VOUT
(Manchester) pin ceases to provide angle data, interrupting any data trans-
Sensor mission in progress. After this, the Manchester interface only
MISO/SENT/PWM
Host
A33003 responds to two specific codes: the access and exit codes. If the
Return Data
(Manchester)
access code is sent, the Manchester interface becomes fully active
and responds to all commands. If the exit code is sent, the
Manchester interface closes all access and the previous protocol
resumes control of the PWM pin or SENT pin, as determined
Figure 25: Manchester Interface Programming Setup by EEPROM. Both the access and exit codes must be written to
address 0x3F (address field composed of all ones).
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MANCHESTER AUXILIARY INTERRUPT PULSE MANCHESTER AUXILIARY COMMAND

FOR PWM OUTPUT MODE FOR SENT AND TSENT OUTPUT MODE
To initialize communication using the Manchester auxiliary To initialize communication using the Manchester auxiliary com-
command when the A33003 is configured with PWM output, the mand when the A33003 is configured with SENT or TSENT out-
auxiliary interrupt pulse can be applied at any time. The auxil- put, the auxiliary interrupt pulse can begin at any time between
iary pulse must have a minimum width of tHOLD, after which the the start of the synchronization (sync) pulse and the end of the
pulse is released for tGATE plus the rise time to allow the line to last data nibble pulse. The pulse must have a minimum width of
pull high and the device to register a rising edge. After this, the tHOLD, after which the pulse must be released for tGATE plus the
controller must pull low for tGATE before beginning to send the rise time to allow the line to pull high, followed by a low period
Manchester access code. If the first rising edge of the Manchester of tGATE before sending the Manchester access code. Again, if the
access code is not observed by the device before tmsgRX after the first rising edge of the Manchester access code is not observed
hold time, the device times out, aborts Manchester initialization, before tmsgRX, the device times out, Manchester initializa-
and returns to PWM functionality. The Manchester auxiliary tion aborts, and the device returns to normal functionality. The
command for PWM output is shown Figure 26. Manchester auxiliary command for SENT and TSENT output is
shown Figure 27.
Device Output HIGH-Z SCN Data
Device Output Pause Pulse SYNC Pulse HIGH-Z
Nibble Nibble 1
Manchester
Controller Output HIGH-Z Aux. Interrupt Pulse Low HIGH-Z Trigger (TSENT) Manchester
Access Code Controller Output HIGH-Z Aux. Interrupt Pulse Low HIGH-Z
HIGH-Z (SENT) Access Code
Manchester
Line Voltage LOW (TSENT) Manchester
Access Code Line Voltage
HIGH (SENT) Access Code
tHOLD tGATE
tGATE + tRISE tHOLD tGATE
tGATE + tRISE
t msgRX
Figure 27: Interrupt Waveform for
t msgRX
Figure 26: Auxiliary Interrupt Pulse Waveform SENT and TSENT Output
OPERATING CHARACTERISTICS: Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
Access Code Timeout tmsgRX – – 300 µs
SSENT—Short F_AUX 50 – 83 ticks
SSENT—Long F_AUX 196 – 297 ticks
ASENT F_AUX 50 – 80 ticks
Interrupt Pulse Hold Time tHOLD SENT Aux. interrupt pulse 30 – – ticks
TSENT Aux. interrupt pulse 30 – – ticks
2 × PWM
PWM Aux. interrupt pulse – – µs
period [1]
Deglitch Gate Time tGATE 1.0 – – µs
[1] The minimum hold time for the auxiliary interrupt, when the output is set for PWM, is double the PWM period. If the PWM frequency increases as a result of a diagnostic
condition, the hold time is double the new PWM period at the diagnosis frequency.
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Manchester Message Structure When the A33003 is operating in I2C Mode (ISEL pin set to a
logic low), the die ID value is determined by the state of the SA0
The general format of a command message frame is shown in and SA1 pins.
Figure 28. Note that, in the Manchester coding used, a bit value
of 1 is indicated by a falling edge within the bit boundary, and a Table 8: Pin Values
bit value of 0 is indicated by a rising edge within the bit bound- SA1 SA0 ID Value
ary. 0 0 ID0
0 1 ID1
1 0 ID2
1 1 ID3
Using the 4 bits of the chip select field, die can be selected
via their ID value, allowing up to four die to be individually
addressed and providing for different group addressing schemes.
If the chip select field is composed of all zeroes, or if the A33003
is operating in SPI mode (ISEL pin set to a logic high), no ID
comparison is made, allowing all A33003 devices to be addressed
at once.
Figure 28: General Format for Serial Interface
Commands Example: If the chip select field is 1010, all die with ID3 or ID1
are selected.
A brief description of each bit is provided in Table 7.
Note: If sharing a SENT line with multiple chips/dies, reading
Table 7: Manchester Command General Format must be performed one die at a time.
Parameter
Bits Values Description Table 9: Chip Select
Name
Used to identify the beginning of Chip Select
2 Synchronization 00
a serial interface command
ID3 ID2 ID1 ID0
0 [As required] Write operation
1 Read/Write
1 [As required] Read operation
Used to select a set of target
4 Chip Select 0/1
chips/die, based on ID value.
6 Address 0/1 [Read/Write] Serial address
Requested serial register
16 Data 0/1
contents (write operation only)
3 CRC 0/1 Incorrect value indicates errors
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MANCHESTER AUXILIARY COMMAND Once the Manchester communication mode is exited, the
FOR SSENT AND ASENT OUTPUT MODE output pin returns to outputting angle data (provided no flag is
To initialize communication using the Manchester auxiliary com- asserted). This output data is taken directly from the transmis-
mand when the A33003 is configured with SSENT or ASENT sion in progress. The recommendation when exiting Manchester
output, the auxiliary function (F_AUX) pulse is applied as the communication is to disregard the first angle reading and to wait
frame request pulse. The auxiliary function pulse must have a for the start of the next PWM duty cycle or SENT packet, as
minimum width of tHOLD. After the pulse is released, the output applicable.
line is required to go HIGH-Z for tGATE plus the rise time. The
TRANSACTION TYPES
controller must then pull the output line low for tGATE before
sending the Manchester access code. If the first rising edge of the The A33003 never initiates communication. Four transactions
access code is not recognized before tmsgRX, a timeout occurs, the are recognized: write access, write to EEPROM, write to vola-
Manchester initialization aborts, and the output returns to normal tile, and read. Only the read transaction prompts the A33003 to
functionality. respond with data. When responding to a read command, the
A33003 does not check for line contention; it is the responsibility
Device Output
HIGH-Z
HIGH-Z of the controller to release the line in time and be ready to read
Wai�ng for addressing pulse
the data sent by the A33003.
Controller Output HIGH-Z F_AUX Pulse Low HIGH-Z
Manchester After a read command is received, there is a delay time between
Access Code
when the last bit of the command is sent to the device and when
Manchester
the device begins to respond on the line. This delay is divided
Line Voltage
Access Code into two times.
tHOLD tGATE • The first (td) is the delay between the last bit of the read
tGATE + tRISE command and when the device begins to pull the line low in
tmsgRX
preparation to send data.
Figure 29: Interrupt waveform for • The second (tb) is the delay between the time when the device
SSENT and ASENT output pulls the line low to when it begins outputting the data. While
the output is fully readable as long as the controller releases
ACCESS CODES control before td + tb, release of the line is recommended
before td.
Once the device is set up to recognize Manchester communica-
tion, there are two special Manchester codes used to activate or
LOW
Device Output High-Z DATA High-Z

deactivate the serial interface:
1. Manchester access code: This code (equivalent to perform- Controller Output High-Z Read Command High-Z
ing a write to register: 0x3F with data: 0x62D2) must be
sent to fully begin Manchester communication. Once this is
High-Z
LOW
Line Voltage High-Z Read Command DATA High-Z

performed, the Manchester interface responds to all available
Manchester commands. td
tb
2. Manchester exit code: This code (equivalent to writing to
register: 0x3F with data: 0x0000), when sent, exits Manchester Figure 30: Transaction Types
communication and returns the device to its previous state.
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READING DATA USING MANCHESTER ENCODING The following command messages can be exchanged between the
A read command with the desired register number is sent from device and the external controller:
the controller to the A33003. The device responds with a read • Manchester access code
response frame using the Manchester protocol. • Manchester exit code
In addition to the contents of the requested memory location, a • Read
return status field is included with every read response. This field • Read response
provides the ID used to communicate with the part and any errors • Write
that may have occurred during the transaction. These bits are: For EEPROM address information, refer to the EEPROM Refer-
• ID: ID (SA1, SA0) unless BC = 1 (ID is 00). ence section. For serial address locations, refer to the Primary
Serial Interface Registers Reference section.
• BC: Broadcast; ID field was zero.
• AE: Abort error; edge detection failure after sync detect. ERROR CHECKING
• OR: Overrun error; a new Manchester command has been The serial Manchester interface uses a cyclic redundancy check
received before the previous request could be completed. (CRC) for data bit error checking (synchronization bits are
ignored during the check).
• CS: Checksum error; a prior command had a checksum error.
Table 10: Return Status Bits The CRC algorithm is based on the polynomial:
Return Status Bits (6 bits) g(x) = x3 + x + 1,
5 4 3 2 1 0 and the calculation is represented graphically in Figure 32.
ID BC AE OR CS
The trailing 3 bits of a message frame comprise the CRC token.
The CRC is initialized at 111.
Synchronize Return Status Data (16 Bits) CRC C0 C1 C2 C3
Input Data
0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ... 0/1 0/1 0/1 0/1 0/1
MSB
Figure 31: Manchester Read Response Figure 32: Manchester CRC Calculation
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Table 11: Manchester Access Code

Function Transmits the access code to the A33003. Enters serial communication mode with the desired output protocol.
Syntax Sent by the external controller on the A33003 output pin.
Related Commands Related command: Serial exit code
Access Code
Synchronize Target ID (16 bits) CRC
Pulse Sequence
0 0 0 0/1 0/1 0/1 0/1 1 1 1 1 1 1 0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1 0/1
MSB
Access Codes:
Options Manchester access code = 0x62D2
Selects Manchester output on the PWM pin.
The Manchester access code operates as a broadcast pulse, meaning the target ID field is inconsequential. For
Examples example, if two A33003s configured with ID0 and ID2 respectively are sharing a common SENT line, a Manchester
access code with a target ID value of 0x1 results in both sensors entering Manchester serial communication mode.
Table 12: Manchester Exit Code

Function Returns the A33003 to normal operation.
Sent by the external controller on the A33003 output pin.
Syntax
Manchester exit code = Any value other than 0x62d2
Related Commands Manchester access codes
Serial Register Exit Code

Synchronize Target ID Address (16 bits) CRC
Pulse Sequence
0 0 0 0/1 0/1 0/1 0/1 1 1 1 1 1 1 0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1 0/1
MSB
Options None
Similiar to the Manchester access code, the Manchester exit code acts as a broadcast pulse. To exit the serial
Examples
communication mode, the exit code can be any value besides the access code (such as 0x0000).
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Table 13: Manchester Read

Determines the serial address within the A33003, from which the next read response transmits data.
Function
The A33003 must first receive a Manchester access code before responding to a read command.
Related Commands Read response
Read/Write
Serial Register
Synchronize Target ID Address CRC
Pulse Sequence
0 0 1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
MSB
Options None
Examples
Table 14: Manchester Read Response

Transmits to the external controller data retrieved from the A33003 serial register in response to the most recent read
Function
command.
Sent by the A33003 on the output pin.
Syntax
Sent after a read command.
Related Commands Read
Read response with Manchester output.
Synchronize ID BC AE OR CS Data (16 Bits) CRC

Pulse Sequence
0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ... 0/1 0/1 0/1 0/1 0/1
MSB
See “Return Data using Manchester Encoding” for bit definitions.
Read from an even address, returns even byte [15:8] and odd byte [7:0].
Options Since the Manchester format will only respond to a valid Read command,
Read from an odd address, returns odd byte [7:0] only. Data bits [15:8] are zeroes.
the NR bit is not applicable.
Examples –
Table 15: Manchester Write

Function Transmits to the A33003 data prepared by the external controller.
Related Commands
Read/Write
Serial Register Data
Synchronize Target ID Address (16 bits) CRC
Pulse Sequence
0 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1
MSB MSB
If the address is even, the 16 bits of the data field are written to the addressed byte and the addressed byte + 1.
Options
If the address is odd, only 8 bits are written (LSB of 16-bit data field).
Examples
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EEPROM AND SHADOW MEMORY USE

The device uses EEPROM to permanently store configura- as the EEPROM and are accessed at extended addresses 0x40
tion parameters for operation. EEPROM is user-programmable higher than the equivalent EEPROM address. Unused bits in the
and permanently stores operation parameter values or customer EEPROM do not exist in the related shadow register and return
information. The operation parameters are downloaded to shadow 0 when read. Shadow registers do not contain the ECC bits. All
(volatile) memory at power-up. Shadow fields are initially loaded EEPROM and shadow locations may be read without unlock-
from corresponding fields in EEPROM, but can be overwritten, ing. The mapping of bits from register addresses in EEPROM to
either by performing an extended write to the shadow addresses, or their corresponding register addresses in shadow is shown in the
by reprogramming the corresponding EEPROM fields and power EEPROM table (See EEPROM Table section).
cycling the IC. Use of shadow memory is substantially faster than
Extended access is provided to additional memory space via
accessing EEPROM. In situations where many parameters need
the direct registers. This access includes the EEPROM, shadow
to be tested quickly, shadow memory is recommended for try-
registers, and registers for additional status and diagnostics. All
ing parameter values before permanently programming them into
extended registers are up to 32 bits wide.
EEPROM. The shadow memory registers have the same format
Primary Serial Interface Extended Locations
Address Function Shadow EEPROM

Name
02:03 Extended Write Address Address Address
User SPI/MANCHESTER
04:05 Extended Write Data High – 0x17 CU2
Write
06:07 Extended Write Data Low 0x58 0x18 PWE
08:09 Extended Write Control/Status 0x59 0x19 SEN
0A:0B Extended Read Address 0x5A 0x1A MSK
0C:0D Extended Read Data High 0x5B 0x1B PWS
Read
0E:0F Extended Read Data Low ... ... ...
10:11 Extended Read Control/Status ... ... ...
1E:1F Device Control

20:21 Angle
... ...
... ...
Figure 33: Serial Interface to Extended Memory

(EEPROM and Shadow)
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Enabling EEPROM Access EEPROM Write Lock

To enable EEPROM write access after a power-on reset, an It is possible to protect the EEPROM against accidental writes:
unlock code needs to be written to the KEYCODE serial register. • Setting the LOCK field in the EEPROM to the value 0xC
This involves five write commands, executed as follows: (1100 in binary) blocks any writes to the EEPROM, so that
1. Write 0x00 to register 0x3C[15:8] permanent changes are not possible anymore. Temporary
2. Write 0x27 to register 0x3C[15:8] changes to the setting are still possible by writing to the
shadow memory, but these changes are lost after a power
3. Write 0x81 to register 0x3C[15:8] cycle.
4. Write 0x1F to register 0x3C[15:8]
This lock is permanent and cannot be reversed. Reading of the
5. Write 0x77 to register 0x3C[15:8] settings is still possible.
Setting the LOCK field in the EEPROM to the value 0x3 (0011 in
This needs to be performed once after power-on reset to enable
binary) locks both EEPROM writes and shadow memory writes.
writing to the EEPROM.
This means none of the sensor settings can be changed anymore.
Writing to serial registers and reading from serial registers does This lock is permanent and cannot be reversed. Reading of the
not require special treatment after power-up. settings is still possible.
Reading all EEPROM cells is always possible.
The device must be unlocked when performing EEPROM margin
checking.
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Read Transaction from EEPROM (or Shadow

Memory)
Invoking an extended read access is a three-step process:
1. Load the ERA register (using SPI or Manchester direct
access) with the target extended address. ERA is the 8-bit
extended address that determines which extended memory
address is to be accessed.
2. Invoke the extended access by writing the direct ERCS reg-
ister EXR bit with a 1. The ERA address is then read and the
data are loaded into the ERD registers.
3. Read the ERD registers (using SPI or Manchester direct ac-
cess) to get the extended data. Multiple packets are required
to obtain all 32 bits.
EEPROM read accesses may take up to 2 µs to complete. The
RDN bit in the ERCS register can be polled to determine if the
read access is complete before reading the data. Shadow and
AUX register reads complete in one system clock cycle after
synchronization. Do not attempt to read the ERD registers if the
read access is potentially in process, because it could change dur-
ing the serial access and the data would be inconsistent. It is also
possible that a SPI CRC error would be detected if the data were
to change during the serial read via the SPI interface.
For example, to read location 0x1F in the EEPROM:
• Write 0x1F to the lower 8 bits of ERA (0x1F to ERA+1,
address 0x0B)
• Write 0x80 to ERCS
• Read ERCS+1 until bit 0 (RDN) is set (or wait enough time)
• Read ERD (upper 16 bits of read data)
• Read ERD+2 (lower 16 bits of read data)
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For example, to read location 0x1F in the EEPROM:

1. Write 0x1F to lower 8 bits of ERA (0x1F to “ERA+1”, address 0x0B).
0x4B 0x1F
2. Write 0x80 to ERCS.
0x4C 0x80
3. Read ERCS+1 until bit 0 (RDN) is set, or wait enough time.

In the example, register 0x0C is read, so that the last bit of the second output byte contains the RDN bit.
0x0C 0x00 0x00 0x00
0x52 0x7B 0x00 0x01
4. Read ERDH (upper 16 bits of read data).

5. Read ERDL (lower 16 bits of read data).
In the example below, the result for the data at address 0x1F is 0x58A45678. In this value:
□ Bits [31:26] are the EEPROM CRC.
□ Bits [25:24] are unused and zero.
□ Bits [23:0] are the EEPROM values that can be used. These are the 24 bits containing the data 0xA45678 that was written in the
EEPROM write example.
0x0E 0x00 0x00 0x00 0x10 0x00 0x00 0x00
0x00 0x00 0x58 0xA4 0x00 0x00 0x56 0x78
NOTE: It is possible to pipeline transactions in this example, i.e., to send a new command while reading return data from the old
command. If pipelined, the example transaction would be performed in eight SPI frames instead of the five shown.
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Write Transaction to EEPROM (or Shadow

Memory)
Invoking an extended write access is a three-step process:
1. Load the EWA register (using SPI or Manchester direct ac-
cess) with the target extended address.
2. Load the EWD registers (using SPI or Manchester direct access)
with the data to be written to the target. Four SPI writes or two
Manchester packets are needed to load all 32 bits of data.
3. Invoke the extended access by writing the direct EWCS reg-
ister EXW bit with the value 1.
The EWA address is then written with the 32-bit EWD data.
The WDN bit in the EWCS register can be polled to determine
when the write completes. This is only necessary for EEPROM
writes, which can take up to 24 ms to complete. Shadow and
AUX register writes complete immediately in one system clock
cycle after synchronization.
For example, to write location 0x1F in the EEPROM with
0x00A45678:
1. Write 0x1F to the lower 8 bits of the EWA register (0x1F to
EWA+1 address 0x03).
2. Write 0x00A45678 to EWD (0x00 to EWD, 0xA4 to
EWD+1, 0x56 to EWD+2, and 0x78 to EWD+3).
3. Write 0x80 to EWCS.
4. Read EWCS+1 until bit 0 (WDN) is set (or wait enough
time).
If an access violation occurs (address not unlocked), the transac-
tion terminates, the corresponding RDN or WDN bit becomes set,
and the XEE warning bit asserts. The XEE bit in the ERR register
also sets if the EEPROM write aborts.
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For example, to write location 0x1F in the EEPROM with 0x00A45678:

1. Write 0x1F to the lower 8 bits of the EWA register (0x1F to EWA+1, address 0x03).
0x43 0x1F
2. Write 0x00A45678 to EWD (0x00 to EWD, 0xA4 to EWD+1, 0x56 to EWD+2, and 0x78 to EWD+3).
0x44 0x00 0x45 0xA4 0x46 0x56 0x47 0x78
3. Write 0x80 to EWCS.
0x48 0x80
4. Read EWCS+1 until bit 0 (WDN) is set, or wait enough time.
In the example, register 0x08 is read, so that the second output byte is from register 0x09, and a wait occurs for bit 0 to become 1,
which happens in the last read.
0x08 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x08 0x00 0x00 0x00
0x00 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01
If an access violation occurs (address not unlocked), the transaction terminates and the corresponding RDN or WDN bit becomes
set, and the XEE warning bit asserts. The XEE bit in the ERR register also becomes set if the EEPROM write aborts.
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After writing to the EEPROM, verify that the write was success- In the figure below, VNOM(H) represents the nominal voltage
ful by performing an EEPROM margin check. programmed into EEPROM cells containing a one, and VNOM(L)
represents the nominal voltage programmed into EEPROM cells
EEPROM Margin Check containing a zero. The red and blue lines represent the actual
Due to nonidealities in transistors, current slowly leaks into or voltage levels in the programmed cells for “1” and “0” values,
out of EEPROM cells and can, over time, cause small changes respectively. As can be observed, at time 0 when the margin test
in the stored voltage level. Variances in voltage levels of the is run, both high and low levels still appear to be the correct value
charge pump can result in a variety of stored EEPROM cell when the threshold is moved to the margin testing levels.
voltages when programming. If this value is marginally close to EEP voltage
the threshold, the small drift over lifetime can cause this value to
move across the threshold. This results in a corrupted EEPROM VNOM(H)
value. Because this drift happens slowly over time, if there is an
issue, it may not become apparent for years. For this reason, it Margin Test [H]
is important to perform margin testing (margining) to verify the

internal voltage levels of EEPROM cells after programming, to
ensure issues do not present in the future. VTHRESH
Margining is performed by Allegro on all registers at final test.

Margin Test [L]
Because EEPROM cell voltages are only modified when writing
to the cell, margining is not required on registers that have not
VNOM(L)
been modified.
Margining is performed in two steps: the first checks the validity
of the voltage stored on digital “1” cells, and the second checks �me
the voltage stored on digital “0” cells. It is important to perform
both steps to ensure there are no issues. Figure 34: Example of Passing Programming Voltages
To perform margining, write the value 0b0001 to the SPECIAL In the figure below, the high and low voltage levels at the time
field of the CTRL register. This reduces the internal threshold of programming are farther from their target. The drift over time
value. Once this value is written, an EEPROM read uses this results in these values crossing VTHRESH and becoming corrupted.
lower threshold when reading EEPROM values. Perform a read At time 0 when the margin test is run, these values fail and are
on all EEPROM registers that are being tested, and confirm they reported as errors to be reprogrammed.
read correctly. If a stored voltage is marginal to the normal oper-
EEP voltage
ating threshold, it appears as a one when it should be a zero.
To raise the threshold value above normal operation, repeat this VNOM(H)
test with the value 0b0010 in the SPECIAL register. Again, read
Margin Test [H]
all EEPROM registers being tested. In this test, any stored high
voltage that is marginal to the normal threshold appears as a zero
when it should be a one. VTHRESH
During either test, if a bit is read incorrectly, perform another
EEPROM write of the desired values to the register, and retest the Margin Test [L]
margins.
Unlike other values in the SPECIAL field, these values persist VNOM(L)
and can be read to confirm the write was successful. As a result,
the SPECIAL register must be cleared (or power cycled) to return
the threshold value to its normal level. �me
Figure 35: Example of Failing Programming Voltages
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Margining is shown below as a list of high-level steps. For details Shadow Memory Read and Write Transactions
on performing individual steps, see the associated sections.
Shadow memory read and write transactions are identical to
1. Clear the ERR and WARN registers. those for EEPROM. Instead of addressing to the EEPROM
2. Write new data to EEPROM as desired. extended address, the shadow extended addresses must be
3. Check the following flags for communication errors: ESE, addressed, which are located at an offset of 0x40 above the
EUE, XEE, IER, CRC, and BSY. EEPROM. For all addresses, refer to the EEPROM Table section.
4. Set CTRL.SPECIAL to the value 0001.
5. Check the following flags for communication errors: ESE,
EUE, XEE, IER, CRC, and BSY.
6. Read all EEPROM registers changed in step 1 and verify the
contents.
7. Set CTRL.SPECIAL to the binary value 0010.
8. Check the following flags for communication errors: ESE,
EUE, XEE, IER, CRC, and BSY.
9. Read all EEPROM registers changed in step 1 and verify the
contents.
10. If any value read in steps 3 or 5 is not the same as was set in
step 1, repeat steps 1through 6 for erroneous registers.
11. Set CTRL.special to the value 0000, or power cycle the part.
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SERIAL INTERFACE TABLE
Table 16: Primary Serial Interface Registers Bits Map

Address [1] Register Read/ Addressed Byte (MSB) Addressed Byte + 1 (LSB) LSB
(0x00) Symbol Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address
0x00 NOP RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x01

0x02 EWA RW 0 0 0 0 0 0 0 0 WRITE_ADR 0x03
0x04 EWDH RW WRITE_DATA_HI 0x05
0x06 EWDL RW WRITE_DATA_LO 0x07
0x08 EWCS WO/RO EXW 0 0 0 0 0 0 WIP 0 0 0 0 0 0 0 WDN 0x09
0x0A ERA RW 0 0 0 0 0 0 0 0 READ_ADR 0x0B
0x0C ERCS WO/RO EXR 0 0 0 0 0 0 RIP 0 0 0 0 0 0 0 RDN 0x0D
0x0E ERDH RO READ_DATA_HI 0x0F
0x10 ERDL RO READ_DATA_LO 0x11
0x12 0x13
0x14 0x15
0x16 0x17
UNUSED RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18 0x19
0x1A 0x1B
0x1C 0x1D
0x1E CTRL RW/WO SPECIAL SPO CLS CLW CLE INITIATE_SPECIAL 0x1F
0x20 ANG RO 0 EF UV P ANGLE 0x21
0x22 STA RO 1 0 0 0 EPTR 0 DIEID ROT 0 SDN BDN LBR CSTR BIP AOK 0x23
0x24 ERR RO 1 0 1 0 WAR STF AVG 0 PLK ZIE EUE OFE UVD UVA MSL RST 0x25
0x26 WARN RO 1 0 1 1 IER CRC SEN 0 XEE TR ESE SAT TCW BSY MSH TOV 0x27
0x28 TSEN RO 1 1 1 1 TEMPERATURE 0x29
0x2A SFIELD RO 1 1 1 0 GAUSS 0x2B
0x2C TURNS RO 1 1 TSRC P TURNS 0x2D
0x2E TOFF RO 1 LAT 0 P 0 TURNS_OFFSET 0x2F
0x30 HANG RO 0 EF UV P ANGLE_HYS 0x31
0x32 ANG15 RO 0 ANGLE_15 0x33
0x34 ZANG RO 0 EF UV P ANGLE_ZCD 0x35
0x36 TD_HIGH RO 0 EF TSRC P TURNS_DELTA[23:12] 0x37
0x38 TD_LOW RO 0 EF LAT P TURNS_DELTA[11:0] 0x39
0x3A PTANG RO 0 EF UV P PLL_TURNS_ANGLE 0x3B
0x3C IKEY WO/RO KEYCODE 0 0 0 0 0 0 0 CUL 0x3D
0x3E UNUSED RO UNUSED 0x3F
[1] Addresses that span multiple bytes are addressed by the most significant byte.
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PRIMARY SERIAL INTERFACE REGISTERS REFERENCE
Location 0x02:0x03 (EWA) Location 0x0A:0x0B (ERA)

EWA.WRITE_ADR ERA.READ_ADR
The field WRITE_ADR is a bit field located at address The field READ_ADR is a bit field located at address
0x02[7:0]. This bit field is part of the location EWA. 0x0A[7:0]. This bit field is part of the location ERA.
8-bit address for extended writes. Writes require unlock. 8-bit address for extended reads.
0x00:0x1F—EEPROM (takes approximately 24 ms) 0x00:0x1F—EEPROM (takes approximately 2 µs)
0x40:0x5F—Shadow memory 0x40:0x5F—Shadow memory
Location 0x04:0x05 (EWDH) NOTE: After LBIST or a reload of EEPROM values, the value of
READ_ADR changes.
EWDH.WRITE_DATA_HI
Location 0x0C:0x0D (ERCS)
The field WRITE_DATA_HI is a bit field located at address
0x04[15:0]. This bit field is part of the location EWDH. ERCS.RDN
Upper 16 bits of data for an extended write operation. The field RDN is a bit located at address 0x0C[0]. This bit is part
of the location ERCS.
Location 0x06:0x07 (EWDL)
Read is complete when value is 1, clears when EXR is set to 1.
EWDL.WRITE_DATA_LO
ERCS.RIP
The field WRITE_DATA_LO is a bit field located at address
0x06[15:0]. This bit field is part of the location EWDL. The field RIP is a bit located at address 0x0C[8]. This bit is part
of the location ERCS.
Lower 16 bits of data for an extended write operation.
Read in progress when value is 1.
Location 0x08:0x09 (EWCS)
ERCS.EXR
EWCS.WDN
The field EXR is a bit located at address 0x0C[15]. This bit is
The field WDN is a bit located at address 0x08[0]. This bit is part part of the location ERCS.
of the location EWCS.
Initiate extended read by writing with the value 1. Sets RIP and
Write is complete when wdn = 1; WDN clears when EXW is set clears RDN. Write-only, always reads back the value 0.
to 1.
Location 0x0E:0x0F (ERDH)
EWCS.WIP
ERDH.READ_DATA_HI
The field WIP is a bit located at address 0x08[8]. This bit is part
of the location EWCS. The field READ_DATA_HI is a bit field located at address
0x0E[15:0]. This bit field is part of the location ERDH.
Write in progress when 1.
Upper 16 bits of data from extended read operation, valid when
EWCS.EXW RDN is set to 1.
The field EXW is a bit located at address 0x08[15]. This bit is
part of the location EWCS.
Initiate extended write by writing with 1. Sets WIP and clears
WDN. Write-only, always reads back 0.
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Location 0x10:0x11 (ERDL) CTRL.CLS

The field CLS is a bit located at address 0x1E[10]. This bit is part
ERDL.READ_DATA_LO of the location CTRL.
The field READ_DATA_LO is a bit field located at address
Clears bits SDN and BDN from STATUS register when set to 1.
0x10[15:0]. This bit field is part of the location ERDL.
Write-only, returns 0 when read.
Lower 16 bits of data from extended read operation, valid when
RDN is set to 1. CTRL.SPECIAL
The field SPECIAL is a bit field located at address 0x1E[15:12].
Location 0x1E:0x1F (CTRL)
This bit field is part of the location CTRL.
CTRL.INITIATE_SPECIAL Special actions. Some of the actions are only invoked after the
The field INITIATE_SPECIAL is a bit field located at address INITIATE_SPECIAL field is written with the correct value.
0x1E[7:0]. This bit field is part of the location CTRL. This field returns 0x00 on completion.
For certain actions from the SPECIAL bit field, a code must be 0000 No action.
sent to INITIATE_SPECIAL. The following actions may be
0001 Enable EEPROM low-voltage margin. IC
triggered by writing this field (the code must be written after the
must be unlocked.
CTRL.SPECIAL field is written):
0x46 Initiates turns counter reset. 0010 Enable EEPROM high-voltage margin. IC
0x5A Initiates hard reset. must be unlocked.
0xA5 Initiates EEPROM reload. 0011 Turns counter load from EWD. Starts after
0xB9 Initiates CVH self-test or functional BIST. writing 0x46 to INITIATE_SPECIAL.
Read always returns 0x00.
0100 Turns counter reset. Starts after writing 0x46
to INITIATE_SPECIAL.
CTRL.SPO
0101 Reload EEPROM. Requires unlock
The SPO bit is bit 11 of the CTRL row. It is the SPI override bit.
of part. Starts after writing 0xA5 to
If set to 1, MISO is forced to be SPI output. This overrides PWM INITIATE_SPECIAL.
and SENT. 0111 Hard reset. Requires unlock of part. Starts
after writing 0x5A to INITIATE_SPECIAL.
CTRL.CLE
1001 Run CVH self-test. Starts after writing 0xB9
The field CLE is a bit located at address 0x1E[8]. This bit is part
to INITIATE_SPECIAL.
of the location CTRL.
1010 Run logic BIST (on PLL logic). Starts after
Clears error register ERR when written with the value 1. Clears
writing 0xB9 to INITIATE_SPECIAL.
bits that were previously read from ERR. Bits that have not been
read are not cleared, so ERR should be read first. Write-only, 1011 Run both the CVH self-test and Logic BIST
always returns 0. in parallel. Starts after writing 0xB9 to the
CTRL.INITIATE_SPECIAL field.
CTRL.CLW
1101 Resample PWM errors (errors must have
The field CLW is a bit located at address 0x1E[9]. This bit is part cleared for this to have an effect).
of the location CTRL.
1110 Clear fatal PWM errors (EUE, WDE, STE).
Clears warning (WARN) register when set to 1. Bits that have not
been read are not cleared, so WARN should be read first. Write- 1111 Clear fatal and resample all PWM errors.
only, always returns 0.
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Location 0x20:0x21 (ANG) STA.CSTR

The field CSTR is a bit located at address 0x22[2]. This bit is
ANG.ANGLE part of the location STA.
The field ANGLE is a bit field located at address 0x20[11:0].
CVH self-test running.
This bit field is part of the location ANG.
Angle from PLL after processing. Angle in degrees = unsigned STA.LBR
12-bit value × (360/4096). The field LBR is a bit located at address 0x22[3]. This bit is part
of the location STA.
ANG.P
LBIST running.
The field P is a bit located at address 0x20[12]. This bit is part of
the location ANG. STA.BDN
Odd parity computed across all bits of this register. Value is cho- The field BDN is a bit located at address 0x22[4]. This bit is part
sen in such a way that there should always be an odd number of of the location STA.
ones in the 16-bit word.
Boot complete. EEPROM loaded and any startup self-tests are
ANG.UV complete.
The field UV is a bit located at address 0x20[13]. This bit is part STA.SDN
of the location ANG.
The field SDN is a bit located at address 0x22[5]. This bit is part
Undervoltage flag (real time). OR of analog and digital UV flags. of the location STA.
Conditions are real time, but are masked by the shadow mask bits.
Special access (from ctrl register) done. Clears to 0 when
ANG.EF SPECIAL triggered, set to 1 when complete.
The field EF is a bit located at address 0x20[14]. This bit is part STA.ROT
The field ROT is a bit located at address 0x22[7]. This bit is part
Error flag. If 1, at least one unmasked bit is set in ERR or WARN. of the location STA.
Location 0x22:0x23 (STA) Rotation direction based on hysteresis (0 = increasing angles,
1 = decreasing angles).
STA.AOK
The field AOK is a bit located at address 0x22[0]. This bit is part STA.DIEID
of the location STA. The field DIEID is a bit field located at address 0x22[9:8]. This
bit field is part of the location STA.
Angle output OK. PLL is in lock.
Die ID from EEPROM. Programmed by Allegro at factory.
STA.BIP
The field BIP is a bit located at address 0x22[1]. This bit is part
of the location STA.
Boot in progress.
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Location 0x24:0x25 (ERR) ERR.EUE
This is the error register. All errors are latched, meaning they The field EUE is a bit located at address 0x24[5]. This bit is part
remain high after they have occurred just once. Errors need to of the location ERR.
be read, then cleared to remove them. It is important to clear
EEPROM uncorrectable error. A multi-bit EEPROM read
errors during operation, so that subsequent errors become visible.
This is especially important for the RST error flag (reset), which occurred.
is always enabled after power-up. Failure to remove an error flag
ERR.ZIE
prevents discovery of any later unexpected reset.
The field ZIE is a bit located at address 0x24[6]. This bit is part
ERR.RST of the location ERR.
The field RST is a bit located at address 0x24[0]. This bit is part
Zero-crossing integrity error. A zero-crossing did not occur within
of the location ERR.
the maximum time expected, likely indicating a missing magnet
Reset condition. Sets on power-on reset or on hard reset. Does or extreme rotation speed.
not set on LBIST.
ERR.PLK
ERR.MSL
The field PLK is a bit located at address 0x24[7]. This bit is part
The field MSL is a bit located at address 0x24[1]. This bit is part
Magnetic sense low fault. Magnetic sense was below the low PLL lost lock.
limit (MagSenseLow).
ERR.AVG
ERR.UVA The field AVG is a bit located at address 0x24[9]. This bit is part
The field UVA is a bit located at address 0x24[2]. This bit is part of the location ERR.
Angle averaging error. The ORATE is too high for the velocity
Undervoltage detector tripped. Becomes set again after clearing if and the averaging is corrupted.
the undervoltage situation persists. Based on analog regulator.
ERR.STF
ERR.UVD
The field STF is a bit located at address 0x24[10]. This bit is part
The field UVD is a bit located at address 0x24[3]. This bit is part
Self-test failure.
Undervoltage detector tripped. Becomes set again after clearing if
the undervoltage situation persists. Based on digital regulator.
ERR.WAR
ERR.WDE The field WAR is a bit located at address 0x24[11]. This bit is
The field WDE is a bit located at address 0x24[4]. This bit is part part of the location ERR.
of the location ERR. Warning. Some unmasked error bits are set in the WARN register.
Oscillator watchdog tripped. If WAR in mask register MSK is set, ERR.WAR is forced to 0.
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Location 0x26:0x27 (WARN) WARN.XEE

The field XEE is a bit located at address 0x26[7]. This bit is part
WARN.TOV of the location WARN.
The field TOV is a bit located at address 0x26[0]. This bit is part
Extended execute error. A command intiated by an extended
of the location WARN.
write failed. Write failed due to access error (not unlocked) or
Turns counter overflow error. The turns counter surpassed its EEPROM write failure.
maximum value of ±256 full rotation. This is not dependent on
the resolution of TURNS (45 or 180 degrees). WARN.SEN
The field SEN is a bit located at address 0x26[9]. This bit is part
WARN.MSH of the location WARN.
The field MSH is a bit located at address 0x26[1]. This bit is part
SENT contention error.
Magnetic sense high fault. Magnetic sense has exceeded the high WARN.CRC
limit (MagSenseHigh). The field CRC is a bit located at address 0x26[10]. This bit is
part of the location WARN.
WARN.BSY
Incoming SPI CRC error. Packet was discarded.
The field BSY is a bit located at address 0x26[2]. This bit is part
of the location WARN. WARN.IER
Extended access overflow. An EXW or EXR was initiated while The field IER is a bit located at address 0x26[11]. This bit is part
previous extended read or write was in progress. of the location WARN.
WARN.TCW Interface error. Invalid number of bits in SPI packet, or bit 15 of

MOSI data = 1. Packet was discarded.
The field TCW is a bit located at address 0x26[3]. This bit is part
of the location WARN. Also Manchester error or SENT contention.
Turns counter warning (over ±135 degrees delta). Location 0x28:0x29 (TSEN)
WARN.SAT TSEN.TEMPERATURE
The field SAT is a bit located at address 0x26[4]. This bit is part The field TEMPERATURE is a bit field located at address
of the location WARN. 0x28[11:0]. This bit field is part of the location TSEN.
Aggregate saturation flag. Shows that any internal signals have Current junction temperature from internal temperature sensor
saturated, likely to have been cause by extremely strong or weak relative to room temperature (signed value). Value is in 1/8 of a
fields. degree. Temperature °C ≈ (TSEN.TEMPERATURE / 8) + 25.
WARN.ESE Location 0x2A:0x2B (FIELD)

The field ESE is a bit located at address 0x26[5]. This bit is part FIELD.GAUSS
The field GAUSS is a bit field located at address 0x2A[11:0].
EEPROM soft error. A correctable (single-bit) EEPROM read This bit field is part of the location FIELD.
occurred.
Field strength in gauss. Field level is used for gross correction,
WARN.TR and should not be used for accurate field readings. Value is typi-
cally ~10% low.
The field TR is a bit located at address 0x26[6]. This bit is part of
the location WARN.
Temperature out of range. The temperature sensor calculated a
temperature below –60°C or above 180°C. Temperature saturates
at those limits.
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Location 0x2C:0x2D (TRNS) TOFF.LAT

The field LAT is a bit located at address 0x2E[14]. This bit is part
TRNS.TURNS of the location TOFF.
The field TURNS is a bit field located at address 0x2C[11:0].
Indicates that the TURNS_OFFSET field is latched. If 1,
This bit field is part of the location TRNS.
indicates that the word TOFF was latched on a prior read of the
Turns counter. Signed 45- or 180-degree increments. TURNS register and is consistent with that reading. Returns to 0
after reading.
Reading this field automatically latches the TOFF.TURNS_
OFFSET value and sets TOFF.LAT. Allows all 21 bits of the Location 0x30:0x31 (HANG)
TURNS_DELTA field to be read with the same timestamp.
HANG.ANGLE_HYS
TRNS.P
The field ANGLE_HYS is a bit field located at address
The field P is a bit located at address 0x2C[12]. This bit is part of 0x30[11:0]. This bit field is part of the location HANG.
the location TRNS.
Angle from PLL after processing and application of hysteresis.
Odd parity computed across all bits of this register. Value is cho- Angle in degrees = unsigned 12-bit value × (360 / 4096).
sen in such a way that there should always be an odd number of
ones in the 16-bit word. HANG.P
TRNS.TSRE
the location HANG.
The field TSRE is a bit located at address 0x2C[13]. This bit is
part of the location TRNS. Odd parity computed across all bits of this register. Value is cho-
Turns source. Set to 1 to use the more accurate PLL as the turns ones in the 16-bit word.
counter source (recommended). Set to 0 to use ZCD angle as
turns counter (not recommended). HANG.UV
Location 0x2E:0x2F (TOFF) The field UV is a bit located at address 0x30[13]. This bit is part
of the location HANG.
TOFF.TURNS_OFFSET Undervoltage flag (real time). OR of analog and digital UV flags.
The field TURNS_OFFSET is a bit field located at address Conditions are real time, but are masked by the shadow mask bits.
0x2E[10:0]. This bit field is part of the location TOFF.
HANG.EF
This is either the 11 or 9 LSBs of the TURNS_DELTA register,
depending on a 180- or 45-degree turns configuration. This field The field EF is a bit located at address 0x30[14]. This bit is part
is latched whenever the turns address is read. of the location HANG.
Error flag. Becomes 1 if any unmasked bit in ERR or WARN is set.
TOFF.P
The field P is a bit located at address 0x2E[12]. This bit is part of Location 0x32:0x33 (ANG15)
the location TOFF.
ANG15.ANGLE_15
Odd parity computed across all bits of this register. Value is cho-
The field ANGLE_15 is a bit field located at address 0x32[14:0].
This bit field is part of the location ANG15.
15-bit compensated angle (not rounded).
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Location 0x34:0x35 (ZANG) Location 0x36:0x37 (TD_HIGH)

ZANG.ANGLE_ZCD TD_HIGH.TURNS_DELTA_HIGH
The field ANGLE_ZCD is a bit field located at address The field TURNS_DELTA_HIGH is a bit field located
0x34[11:0]. This bit field is part of the location ZANG. at address 0x36[11:0]. This bit field is part of the location
TD_HIGH.
Angle from ZCD.
Angle in degrees = unsigned 12-bit value × (360 / 4096). Upper 9 bits (sign extended to 12) of the turns delta counter.
ZANG.P When read, the contents of TD_LOW (address 0x38:0x39) are

latched and the TD_LOW.LAT bit is set. This allows all 25 bits
The field P is a bit located at address 0x34[12]. This bit is part of (sign extended) of the TURNS_DELTA value to be read at the
the location ZANG. same timestamp.
sen in such a way that there should always be an odd number of TD_HIGH.P
ones in the 16-bit word. The field P is a bit located at address 0x36[12]. This bit is part of
the location TD_HIGH.
ZANG.UV
The field UV is a bit located at address 0x34[13]. This bit is part sen in such a way that there should always be an odd number of
of the location ZANG. ones in the 16-bit word.
Undervoltage flag (real time). OR of analog and digital UV flags.
Conditions are real time, but are masked by the shadow mask TD_HIGH.TSRC
bits. The field TSRC is a bit located at address 0x36[14]. This bit is a
part of the location TD_HIGH.
ZANG.EF
Turns source. When 1, indicates the PLL is the turns counter
The field EF is a bit located at address 0x34[14]. This bit is part source. When 0, the ZCD signal path (uncompensated) is the
of the location ZANG. source.
Error flag. Becomes 1 if any unmasked bit in ERR or WARN is
set. TD_HIGH.EF
The field EF is a bit located at address 0x36[14]. This bit is part
of the location TD_HIGH.
set.
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Location 0x38:0x39 (TD_LOW) Location 0x3A:0x3B (PTANG)

TD_LOW.TURNS_DELTA_LOW PTANG.PLL_TURNS_ANGLE
The field TURNS_DELTA_LOW is a bit field located at address The field PLL_TURNS_ANGLE is a bit field located at address
0x38[11:0]. This bit field is part of the location TD_LOW. 0x3A[11:0]. This bit field is part of the location PTANG.
Lower 12 bits of the turns delta. This is the angle offset at 12-bit Angle from PLL after processing, as used for the turns counter.
resolution.
May have hysteresis based on H2A configuration in EEPROM.
This value is latched when reading the td_high register, allow-
Angle in degrees = unsigned 12-bit value × (360 / 4096).
ing the entirety of TURNS_DELTA to be read with the same
timestamp. PTANG.P
TD_LOW.P The field P is a bit located at address 0x3A[12]. This bit is part of
the location PTANG.
the location TD_LOW. Odd parity computed across all bits of this register. Value is cho-
Odd parity computed across all bits in this register. Value is cho-
ones in the 16-bit word. PTANG.UV
TD_LOW.LAT The field UV is a bit located at address 0x3A[13]. This bit is part
of the location PTANG.
The filed LAT is a bit located at address 0x38[13]. This bit is part
of the location TD_LOW. Undervoltage flag (real time). OR of analog and digital UV flags.
Conditions are real time, but are masked by the shadow mask
Inidicates that the TD_LOW field is latched. If 1, indicates that
bits.
TD_LOW was latched on a prior read of the TD_HIGH register
and is consistent with that reading. Returns to 0 after reading. PTANG.EF
TD_LOW.EF The field EF is a bit located at address 0x3A[14]. This bit is part
of the location PTANG.
The field EF is a bit located at address 0x38[14]. This bit is part
of the location TD_LOW. Error flag. Becomes 1 if any unmasked bit in ERR or WARN is
set.
set. Location 0x3C:0x3D (KEY)
KEY.CUL
The field CUL is a bit located at address 0x3C[0]. This bit is part
of the location KEY.
Customer unlocked if 1.
KEY.KEYCODE
The field KEYCODE is a bit field located at address 0x3C[15:8].
This bit field is part of the location KEY.
Customer access keycode is entered here; value is
0x27_81_1F_77.
Always reads back 0.
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EEPROM TABLE
The EEPROM register bitmap is shown below.

All EEPROM content can be read by the user. The EEPROM
ECC field in bits [31:26] of each word are not shown here.
Table 17: EEPROM / Shadow Memory Map

Shadow Bits
EEPROM Register
Address
Memory Name
Address 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x17 0x57 CU2 -X- -X- CUSTOMER 2

0x18 0x58 PWE -X- -X- ZCD_TURNS_OFFSET TOV TR MSH SAT ESE MSL UV AVG ZIE PLK STF EUE WDE
0x19 0x59 SEN MAXID SS SENT_TICK SM SENT_MODE DATA_MODE CIS SCN_MODE NS ZS XA FA
0x1A 0x5A MSK -X- -X- IERM CRCM SENM -X- XEEM TRM ESEM SATM TCWM BSYM MSHM TOVM WARM STFM AVGM -X- PLKM ZIEM EUEM WDEM UVCCM UVAM MSLM RSTM
0x1B 0x5B PWS FP_ADJ PEN PWM_BAND PWM_FREQ MEPE PHE PEO PES ELI LS ZAL IS PO SPDRV DM H2T S17 SC
0x1C 0x5C ANG -X- -X- ORATE RD RO HYSTERESIS ZERO_OFFSET
0x1D 0x5D LPC -X- -X- T45 TCP -X- -X- TURNS_INIT -X- -X- -X-
0x1E 0x5E COM -X- -X- LOCK LBE CSE DUR DEL -X- CUD DST DHR MAG_THRES_HI MAG_THRES_LO
0x1F 0x5F CUS -X- -X- CUSTOMER
0x20 0x60 LIN -X- -X- LINEARIZATION ERROR SEGMENT 1 LINEARIZATION ERROR SEGMENT 0
0x21 0x61 LIN -X- -X- LINEARIZATION ERROR SEGMENT 3 LINEARIZATION ERROR SEGMENT 2
… … … -X- -X- … ---
0x2E 0x6E LIN -X- -X- LINEARIZATION ERROR SEGMENT 29 LINEARIZATION ERROR SEGMENT 28
0x2F 0x6F LIN -X- -X- LINEARIZATION ERROR SEGMENT 31 LINEARIZATION ERROR SEGMENT 30
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EEPROM REFERENCE
Location 0x17 (CU2) PWE.AVG

Customer-usable field, intended for storing data or turns counter. The field AVG is a bit located at address 0x18[5]. This bit is part
of the location PWE.
This word can be written even if EEPROM is locked. Write may
be allowed without the unlock code based on COM.DUR and PWM angle averaging error enable. Duty cycle is 33.125% at
COM.DEL settings (see word 0x1E). half the selected PWM frequency.
CU2.CUSTOMER 2 PWE.UV
The field CUSTOMER 2 is a bit field located at address The field UV is a bit located at address 0x18[6]. This bit is part
0x17 [23:0]. This bit field is part of the location CU2. of the location PWE.
PWM undervoltage fault enable (analog or digital). Duty cycle
Location 0x18 (PWE) 38.75% at half the selected PWM frequency.
PWE.WDE
PWE.MSL
The field WDE is a bit located at address 0x18[0]. This bit is part
The field MSL is a bit located at address 0x18[7]. This bit is part
of the location PWE. of the location PWE.
PWM watchdog error enable. Duty cycle output 5% at half the PWM magnetic sense low fault enable. Duty cycle 44.375% at
selected PWM frequency. half the selected PWM frequency.
PWE.EUE PWE.ESE
The field EUE is a bit located at address 0x18[1]. This bit is part The field ESE is a bit located at address 0x18[8]. This bit is part
PWM EEPROM uncorrectable error enable. Duty cycle 10.625% PWM EEPROM soft error enable. Duty cycle 50% at half the
at half the selected PWM frequency. selected PWM frequency.
PWE.STF PWE.SAT
The field STF is a bit located at address 0x18[2]. This bit is part The field SAT is a bit located at address 0x18[9]. This bit is part
PWM self-test failure error enable. Duty cycle 16.25% at half the PWM saturation warning enable. Duty cycle 55.625% at half the
selected PWM frequency. selected PWM frequency.
PWE.PLK PWE.MSH
The field PLK is a bit located at address 0x18[3]. This bit is part The field MSH is a bit located at address 0x18[10]. This bit is
of the location PWE. part of the location PWE.
PWM PLL lost lock error enable. Duty cycle 21.875% at half the PWM magnetic sense high fault enable. Duty cycle 61.25% at
selected PWM frequency. half the selected PWM frequency.
PWE.ZIE PWE.TR
The field ZIE is a bit located at address 0x18[4]. This bit is part The field TR is a bit located at address 0x18[11]. This bit is part
PWM zero-crossing integrity error enable. Duty cycle 27.5% at PWM temperature sensor out of range error enable. Duty cycle
half the selected PWM frequency. 66.875% at half the selected PWM frequency.
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PWE.TOV SEN.SCN_MODE
The field TOV is a bit located at address 0x18[12]. This bit is The field SCN_MODE is a bit field located at address 0x19 [6:4].
part of the location PWE. This bit field is part of the location SEN.
PWM turns counter overflow error enable. Duty cycle 72.5% at SCN contents by mode:
half the selected PWM frequency.
0 {0, 0, SOFT_FLAG, HARD_FLAG}
PWE.ZCD_TURNS_OFFSET 1 {SERIAL MSG SYNC, SERIAL MSG DATA,
The field ZCD_TURNS_OFFSET is a bit field located at SOFT_FLAG, HARD_FLAG}
address 0x18[23:13]. This bit field is part of the location PWE. 2 {ID[1], ID[0], SOFT_FLAG, HARD_FLAG}
Offset to ZCD angle for purposes of aligning for turns counting. 3 {0, 0, 0, SOFT_FLAG | HARD_FLAG}
This is 11-bit angle resolution and is added to the ZCD angle for 4 {0, 0, ID[1], ID[0]}
turns purposes. If turns is configured to use the PLL (TCP = 1), it 5 {SERIAL MSG SYNC, SERIAL MSG DATA,
is important to use this to align the ZCD close to the PLL angle. ID[1], ID[0]}
Location 0x19 (SEN) 6 {SOFT_FLAG, HARD_FLAG, ID[1], ID[0]}
7 {SERIAL MSG SYNC, SERIAL MSG DATA, 0,
For further details, see Appendix A: SENT Output Description.
SOFT_FLAG | HARD_FLAG}
SEN.FA SEN.CIS
The field FA is a bit located at address 0x19 [0]. This bit field is The field CIS is a bit located at address 0x19 [7]. This bit field is
part of the location SEN. part of the location SEN.
F_SAMPLE is an addressing pulse. If 0, it is a broadcast pulse. If 1, CRC includes the status and communication nibble.
SEN.XA SEN.DATA_MODE
The field XA is a bit field located at address 0x19 [1]. This bit The field DATA_MODE is a bit field located at address 0x19
field is part of the location SEN. [11:8]. This bit field is part of the location SEN.
Allows the F_AUX pulse to be treated as an addressing pulse. If SENT data nibble content mode:
0, F_AUX is a broadcast pulse.
0 Angle only (3 nibbles)
SEN.ZS 1 Angle (3) + rotating status (2)
The field ZS is a bit located at address 0x19 [2]. This bit field is 2 Angle (3) + rotating data (3)
part of the location SEN. 3 Unused
Sample-and-hold is to be performed in slot 0. 4 Angle (3) + rotating status (2) + alive (1)
5 Angle (3) + alive (2) + ~first nibble (1) (secure sensor
SEN.NS format)
The field NS is a bit located at address 0x19 [3]. This bit field is 6 Angle16 (4)
part of the location SEN. 7 Angle16 (4) + rotating status (1) + alive (1)
No sample. If 1, the F_SAMPLE pulse does not perform a 8 Angle only (3 nibbles) + ID (1)
sample-and-hold. 9 Angle (3) + rotating status (2) + ID (1)
10 Angle (3) + rotating data (2) + ID (1)
11 Unused
12 Angle (3) + rotating status (1) + alive (1) + ID (1)
13 Angle (3) + alive(1) + ~first nibble (1) + ID (1)
14 Angle16 (4) + ID (1)
15 Angle16 (4) + alive (1) + ID (1)
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SEN.SENT_MODE Location 0x1A (“MSK”)

The field SENT_MODE is a bit field located at address 0x19
[14:12]. This bit field is part of the location SEN. MSK.RSTM
The field RSTM is a bit located at address 0x1A[0]. This bit is
0 Disabled part of the location MSK.
1 Streaming (no pause pulses)
Reset mask. Set to 1 to hide the error bit.
2 Streaming but aligned to angle update (pause pulses)
3 TSENT, data sampled just before data nibbles MSK.MSLM
4 TSENT, data sampled at falling edge of trigger (after The field MSLM is a bit located at address 0x1A[1]. This bit is
minimum width) part of the location MSK.
5 ASENT Magnetic sense low fault mask. Set to 1 to hide the error bit.
6 SSENT
7 Long SSENT MSK.UVAM
NOTE: If PEN = 1, then PWM has precedence, and SENT The field UVAM is a bit located at address 0x1A[2]. This bit is
becomes disabled. part of the location MSK.
NOTE: If both PWM and SENT are disabled, Manchester is Analog undervoltage fault mask. Set to 1 to hide the error bit.
active (unless it is disabled or CTRL.SPO is 1).
MSK.UVDM
SEN.SM The field UVDM is a bit located at address 0x1A[3]. This bit is
The field SM is a bit located at address 0x19 [15]. This bit field is part of the location MSK.
part of the location SEN. Digital undervoltage fault mask. Set to 1 to hide the error bit.
Slot marking. SSENT only. If 1, SSENT outputs a bus high delay
after an addressing pulse based on slot ID. MSK.WDEM
The field WDEM is a bit located at address 0x1A[4]. This bit is
SEN.SENT_TICK part of the location MSK.
The field SENT_TICK is a bit field located at address 0x19 Watchdog error mask. Set to 1 to hide the error bit.
[22:16]. This bit field is part of the location SEN.
SENT tick time, N × period of 16 MHz clock (forced to mini- MSK.EUEM
mum of 2 clocks internally). The field EUEM is a bit located at address 0x1A[5]. This bit is
part of the location MSK.
SEN.SS
EEPROM uncorrectable error mask. Set to 1 to hide the error bit.
The field SS is a bit located at address 0x19 [23]. This bit field is
part of the location SEN. MSK.ZIEM
Slot sync. SSENT only. If 1, then SSENT synchronizes to the bus The field ZIEM is a bit located at address 0x1A[6]. This bit is
after a reset based on the slot marking of the other sensor. Only part of the location MSK.
valid if SM = 1.
Zero-crossing integrity error mask. Set to 1 to hide the error bit.
SEN.MAXID
MSK.PLKM
The field MAXID is a bit field located at address 0x19 [25:24].
The field PLKM is a bit located at address 0x1A[7]. This bit is
This bit field is part of the location SEN.
Max sensor ID on bus, for SSENT. Defines highest sensor ID on
PLL lost lock error mask. Set to 1 to hide the error bit.
bus, after which the slot counting wraps back to 0.
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MSK.AVGM EEPROM soft error mask. Set to 1 to hide the error bit.
The field AVGM is a bit located at address 0x1A[9]. This bit is
MSK.TRM
The field TRM is a bit located at address 0x1A[18]. This bit is
Angle averaging fault mask. Set to 1 to hide the error bit. part of the location MSK.
MSK.STFM Temperature sensor out of range error mask. Set to 1 to hide the
error bit.
The field STFM is a bit located at address 0x1A[10]. This bit is
part of the location MSK. MSK.XEEM
Self-test failure error mask. Set to 1 to hide the error bit. The field XEEM is a bit located at address 0x1A[19]. This bit is
MSK.WARM
Execute error mask. Set to 1 to hide the error bit.
The field WARM is a bit located at address 0x1A[11]. This bit is
part of the location MSK. MSK.SEN
If set to 1, the WAR bit in the ERR register does not become set MSK.SEN is located at address 0x1A[21].
when unmasked warnings are present. SENT error mask. Set to 1 to prevent a SENT contention error
from asserting the EF flag within serial space and the soft error
MSK.TOVM flag within the SCN of the SENT frame.
The field TOVM is a bit located at address 0x1A[12]. This is part
of the location MSK. MSK.CRCM
Turns counter overflow error mask. Set to 1 to hide the error bit. The field CRCM is a bit located at address 0x1A[22]. This bit is
MSK.MSHM CRC error mask (SPI). Set to 1 to hide the error bit.
The field MSHM is a bit located at address 0x1A[13]. This bit is
MSK.IERM
The field IERM is a bit located at address 0x1A[23]. This bit is
Magnetic sense high fault mask. Set to 1 to hide the error bit. part of the location MSK.
MSK.BSYM Interface error mask. Set to 1 to hide the error bit.
The field BSYM is a bit located at address 0x1A[14]. This bit is Location 0x1B (PWS)
PWS.SC
Indirect access busy error mask. Set to 1 to hide the error bit. The field SC is a bit located at address 0x1B[0]. This bit is part of
the location PWS.
MSK.TCWM
SPI CRC (incoming) validated if SC = 1, ignored if SC = 0.
The field TCWM is a bit located at address 0x1A[15]. This bit is
part of the location MSK. PWS.S17
Turns counter warning mask. Set to 1 to hide the error bit. The field S17 is a bit located at address 0x1B[1]. This bit is part
of the location PWS.
MSK.SATM SPI ignore 17th clock to allow negative edge host sampling.
The field SATM is a bit located at address 0x1A[16]. This bit is
part of the location MSK. PWS.H2T
The field H2T is a bit located at address 0x1B[2]. This bit is part
Aggregate saturation flag mask. Set to 1 to hide the error bit.
of the location PWS. Turns uses hysteresis if 1.
MSK.ESEM 0 = Use nonhysteresis angle for turns counter
The field ESEM is a bit located at address 0x1A[17]. This bit is 1 = Use hysteresis angle for turns counter
part of the location MSK. This affects special register PTANG (0x3A).
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PWS.DM PWS.PES
The field DM is a bit located at address 0x1B[3]. This bit is part The field PES is a bit located at address 0x1B[12]. This bit is part
of the location PWS. of the location PWS.
Disable Manchester interface. PWM error select (if PEO = 1).
If 1, any Manchester input. 0 = PWM tristated, must reset (or set PEO back to 0 in
shadow) to release the PWM output.
PWS.SPDRV
1 = PWM carrier frequency halved and highest priority error
SENT and PWM pin drive strength. output on PWM as selected duty cycle.
PWS.ZAL PWS.PEO
The field ZAL is a bit located at address 0x1B[9]. This bit is part The field PEO is a bit located at address 0x1B[13]. This bit is
of the location PWS. part of the location PWS.
Zero offset after linearization: PWM error output enable. If 1, PES selects the response to an
0 = Before linearization and rotation enabled error.
1 = After linearization
PWS.PHE
PWS.PO The field PHE is a bit located at address 0x1B[14]. This bit is
POR offline. SSENT only. If 1, SSENT is offline at POR. If 0, part of the location PWS.
SSENT goes online with slot counter 0. PWM hysteresis enable. If 1, use hysteresis on angle going to PWM.
PWS.LS PWS.MEPE
The field LS is a bit located at address 0x1B[10]. This bit is part The field MEPE is a bit located at address 0x1B[15]. This bit is
of the location PWS. part of the location PWS.
Linearization scale: If 1, the Manchester auxiliary interrupt pulse and the F_AUX pulse
0 = ±22.5 degrees are enabled; else, the auxiliary interrupt pulse and the F_AUX
1 = ±45 degrees pulse are ignored, and Manchester communication is only acces-
sible when PWM and SENT are deactivated.
PWS.IS
PWS.PWM_FREQ
Idle sync (SSENT only). If 1, an idle SENT bus > 511 ticks resets
the slot counter to 0. The field PWM_FREQ is a bit field located at address
0x1B[19:16]. This bit field is part of the location PWS.
PWS.ELI PWM frequency select. Together with the PWS.PWM_BAND
The field ELI is a bit located at address 0x1B[11]. This bit is part field, defines the PWM carrier frequency. See the PWM Output
of the location PWS. section for more details.
Enable linearization: PWS.PWM_BAND
0 = Disabled The field PWM_BAND is a bit field located at address
1 = Enabled 0x1B[22:20]. This bit field is part of the location PWS.
PWM frequency band. Together with the PWS.PWM_FREQ
field, defines the PWM carrier frequency. See tthe PWM Output
section for more details.
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PWS.PEN ANG.ORATE
The field PEN is a bit located at address 0x1B[23]. This bit is The field ORATE is a bit field located at address 0x1C[23:20].
part of the location PWS. This bit field is part of the location ANG.
When set to 1, PWM is enabled and overrides any SENT setting. Reduces the output rate by averaging samples. 2ORATE samples
are averaged. ORATE values greater than 12 are reduced to 12
If 0, SENT_MODE field determines state of PWM/SENT pin.
in the logic, meaning that up to 4096 samples = 4 ms can be
PWS.FP_ADJ selected as averaging time.
Function pulse adjust. Long SSENT (SENT_MODE 7) only. Location 0x1D (LPC)
Increases the lower threshold of the F_OUTPUT pulse by the
number of ticks in this field (0 through 3). LPC.TCP
The field TCP is a bit located at address 0x1D[11]. This bit is
Location 0x1C (ANG) part of the location LPC.
ANG.ZERO_OFFSET Turns counter PLL:
The field ZERO_OFFSET is a bit field located at address 0 Turns uses ZCD angle.
0x1C[11:0]. This bit field is part of the location ANG.
1 Turns uses PLL angle, except if PLL lock is lost.
Post-compensation zero offset (or DC adjust) at angle resolution. Ensure the ZCD_TURNS_OFFSET aligns the ZCD
This value is subtracted from the measured angle. PWS.ZAL bit angle near the PLL angle.
determines if ZERO_OFFSET is applied before or after linear-
ization. LPC.TURNS_INIT
ZAL = 0 ZERO_OFFSET precedes linearization. The field TURNS_INIT is a bit field located at address
0x1D[19:18]. This bit field is part of the location LPC.
ZAL = 1 ZERO_OFFSET follows linearization.
Turns initialization at power-up.
ANG.HYSTERESIS
00, 01 Turns counter zeroed at power-up.
The field HYSTERESIS is a bit field located at address
0x1C[17:12]. This bit field is part of the location ANG. 10 Turns counter set to full settings angle (turns register
may be non-zero).
Angle hysteresis threshold, angle resolution × 4 (14 bit). Range is
approximately 0 degrees to 1.384 degrees. 11 Turns counter set to settled angle offset from 180- or
45-degree configuration (MSB 10 or 12 bits zeroed),
ANG.RO turns register starts at zero.
The field RO is a bit located at address 0x1C[18]. This bit is part LPC.T45
The field T45 is a bit located at address 0x1D[23]. This bit is part
Rotation direction (pre-linearization). If set to 0, increasing angle of the location LPC.
movement is in the clockwise direction when looking down on
the top of the die. If set to 1, increasing angle movement is in the Turns counter resolution is 45° if set to a 1, and 180° if set to a 0.
counter-clockwise direction.
Location 0x1E (COM)
ANG.RD
COM.MAG_THRES_LO
The field RD is a bit located at address 0x1C[19]. This bit is part
The field MAG_THRES_LO is a bit field located at address
0x1E[5:0]. This bit field is part of the location COM.
Rotate die. Rotates final angle by 180 degrees. This is the last
Magnetic field low comparator value. Field value equals low
step in the angle processing algorithm. This is a convenient set-
field error threshold in gauss divided by 16.
ting to adjust one die in a dual-die package for conformance to
the other die.
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COM.MAG_THRES_HI COM.LBE
The field MAG_THRES_HI is a bit field located at address The field LBE is a bit located at address 0x1E[19]. This bit is
0x1E[11:6]. This bit field is part of the location COM. part of the location COM.
Magnetic field high comparator value. Field value equals maxi- Power-up logic BIST enable.
mum field threshold in gauss divided by 32. If set to 0, high
threshold is disabled. COM.LOCK
The field LOCK is a bit field located at address 0x1E[23:20].
COM.DHR This bit field is part of the location COM.
The field DHR is a bit located at address 0x1E[12]. This bit is
Lock options:
part of the location COM.
1100 Lock EEPROM writes.
Disable hard reset. Initiates in serial CTRL register special if 1.
0011 Lock EEPROM writes and shadow register writes.
COM.DST
Location 0x1F (CUS)
The field DST is a bit located at address 0x1E[13]. This bit is
part of the location COM. CUS.CUSTOMER
Disable self-test. Initiates in serial CTRL register special if 1. The field CUSTOMER is a bit field located at address
0x1F[23:0]. This bit field is part of the location CUS. This field
COM.CUD may be written with customer tracking, ID, or any other pertinent
The field CUD is a bit located at address 0x1E[14]. This bit is data.
Location 0x20 (LIN00)
If 1, the CUSTOMER word 0x1F uses the DUR and DEL con-
figuration in addition to the CUSTOMER2 word 0x17. LIN00.LINEARIZATION ERROR SEGMENT 0
The field LINEARIZATION ERROR SEGMENT 0 is a bit
COM.DEL
field located at address 0x20[11:0]. This bit field is part of the
The field DEL is a bit located at address 0x1E[16]. This bit is location LIN00.
Correction value at segment boundary. Signed, resolution is based
Disable EEPROM lock for CUST2 (EEPROM word 0x17) and, on LS bit. Is subtracted from sensor angle to produce linearized
if CUD = 1, CUST word 0x1F. EEPROM lock does not affect the angle.
ability to write to word 0x17 (and 0x1F if enabled).
LS = 0 Range is ±22.5 degrees.
COM.DUR LS = 1 Range is ±45 degrees.
The field DUR is a bit located at address 0x1E[17]. This bit is
part of the location COM. LIN00.LINEARIZATION ERROR SEGMENT 1
Disable unlock requirement for CUST2 (EEPROM word 0x17) The field LINEARIZATION ERROR SEGMENT 1 is a bit
and, if CUD = 1, CUST word 0x1F. field located at address 0x20[23:12]. This bit field is part of the
location LIN00.
COM.CSE Correction value at segment boundary. Signed, resolution is based
The field CSE is a bit located at address 0x1E[18]. This bit is part on LS bit. Is subtracted from sensor angle to produce linearized
of the location COM. angle.
Enable CVH self-test at power-up. LS = 0 Range is ±22.5 degrees.
LS = 1 Range is ±45 degrees.
NOTE: Linearization segments 2 through 29 have been omitted
from the datasheet for reasons of brevity.
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Location 0x2F (LIN15)

LIN15.LINEARIZATION ERROR SEGMENT 30
field located at address 0x2F[11:0]. This bit field is part of the
location LIN15.
on LS bit. Is subtracted from sensor angle to produce linearized
angle.
LIN15.LINEARIZATION ERROR SEGMENT 31

field located at address 0x2F[23:12]. This bit field is part of the
location LIN15.
on LS bit. Is subtracted from sensor angle to produce linearized
angle.
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SAFETY AND DIAGNOSTICS
The A33003 was developed in accordance to the ASIL design The test is complete following initialization when either:
flow. It incorporates several diagnostics.
• STA.SDN = 1 (special done) or
Alive Counter • STA.LBR = 0 (LBIST not running).
A 32-bit counter increments periodically from zero after a power- A failure is indicated by ERR.STF = 1.
on reset or a hard reset. It is read via AUX.ALV. The alive incre-
ment period is 8.192 ms. CVH Self-Test
The alive counter can overflow. The overflow period of the coun- CVH self-test is a method of verifying the operation of the CVH
ter is [232 × 8.192] ms. This period is approximately 400 days. transducer without applying an external magnetic field. This
Oscillator Watchdogs feature is useful for both manufacturing test and for integration
debug. The CVH self-test is implemented by changing the switch
The watchdogs run constantly when in full-power or “wake” configuration from the normal operating mode into a test configu-
modes. They are disabled during sleep mode and are reset when ration, allowing a test current to drive the CVH in place of the
waking up to ensure there is not a false positive due to a partial
magnetic field. By changing the direction of the test current and
clock count. These watchdogs are intended to detect gross fail-
by changing the elements in the CVH that are driven, the self-test
ures of either oscillator. Logic running on clocks based on each
oscillator effectively counts clock periods produced in the other circuit emulates a changing angle of magnetic field. The mea-
clock domain and compares to expected limits. sured angle is monitored to determine a passing or failing device.
CVH self-test typically takes 52 ms to verify.
Logic Built-In Self-Test (LBIST)
Logic BIST is implemented to verify the integrity of the A33003 Self-test can be run on power-up, by setting the EEPROM field
logic. It can be executed in parallel with the CVH self-test. COM.CSE = 1.
LBIST is effectively a form of auto-driven scan. The logic to be Self-test can also be invoked via the serial control register by
tested is broken into 31 scan chains. The chains are fed in parallel issuing the corresponding SPECIAL command.
by a 31-bit linear feedback shift register (LFSR) to generate pseu-
dorandom data. The output of the scan chains are fed back into a The test is complete when either:
multiple-input shift register (MISR) that accumulates the shifted
• STA.SDN = 1 (special done) or
bits into a 31-bit signature.
• STA.CSTR = 0 (CVH self-test not running).
LBIST takes approximately 30 ms to complete.
Failure is indicated by:
LBIST can be enabled to run on power-up by setting COM.LBE
bit in EEPROM (0x1E bit 19). • ERR.STF = 1 (assuming it was cleared before test was run).
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I/O STRUCTURES
CS, MOSI, SCK
1 kΩ
VOUT Passive Components (Always on the line)
Always Ac�ve (Push-Pull and Open Drain)
Ac�ve Durring SPI (Push-Pull)
33 Ω
50 Ω
1 pF
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PACKAGE OUTLINE DRAWINGS

For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000381, Rev. 1 and JEDEC MO-153 AB-1)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.00 ±0.10
8º
D 0º
2.50 ±0.05
14
0.20
0.09
D D1 0.427 E E1
6.40 BSC
4.40 ±0.10
D D1 +0.15
0.60
A D 2.20 ±0.05 –0.10
1.00 REF
1 2
Branded Face 0.25 BSC
SEATING PLANE
16X C GAUGE PLANE
0.95
0.85 1.10 MAX
0.10 C SEATING
PLANE
0.15
0.30 0.05
0.19
0.65 BSC
XXXXXXX
Date Code
Lot Number
0.45 0.65
14
1
C Standard Branding Reference View
1.70
Lines 1, 2 = 7 characters, right align
Line 3 = 5 characters, right align
Line 1: Part Number

Line 2: Logo A, 4-digit Date Code
Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number
6.00
A Terminal #1 mark area
B Reference land pattern layout (reference IPC7351 TSOP65P640X120-14M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
C Branding scale and appearance at supplier discretion
1 2 D Hall element (D1); not to scale
B PCB Layout Reference View E Active area depth (E1)
Figure 36: Package LU, 14-Pin TSSOP, Single Die
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For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000381, Rev. 1 and JEDEC MO-153 AB-1)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.00 ±0.10
8º
D 0º
2.50
14
0.20
0.09
0.427 E E2
D1 0.274 E E1
D D2 6.40 BSC
4.40 ±0.10
D D2 D D1
+0.15
2.20 D 0.60
A –0.10
1.00 REF
1 2
Branded Face 0.25 BSC
SEATING PLANE
16X C GAUGE PLANE
0.95
0.85 1.10 MAX
0.10 C SEATING
PLANE
0.15
0.30 0.05
0.19
0.65 BSC
XXXXXXX
Date Code
Lot Number
0.45 0.65
14
1
C Standard Branding Reference View
1.70
Lines 1, 2 = 7 characters, right align
Line 3 = 5 characters, right align
Line 1: Part Number

Line 2: Logo A, 4-digit Date Code
Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number
6.00
A Terminal #1 mark area
B Reference land pattern layout (reference IPC7351 TSOP65P640X120-14M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
C Branding scale and appearance at supplier discretion
1 2 D Hall elements (D1, D2); not to scale
B PCB Layout Reference View

E Active area depth (E1, E2)
Figure 37: Package LU, 14-Pin TSSOP, Dual Die
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APPENDIX A: SENT OUTPUT DESCRIPTION
SENT Output Mode

The SENT output converts the measured magnetic field angle to • SENT_MODE
a binary value mapped to the full-scale output (FSO) range of 0 • SENT_DRIVER
to 4095, shown in Figure 36. This data is inserted into a binary • DATA_MODE
pulse message, referred to as a frame, that conforms to the SENT • SCN_MODE
data transmission specification (SAE J2716 JAN2010). • SENT_ENABLE
• SENT_TICK
The SENT frame can be configured by setting the following
parameters in EEPROM (shown in Figure 36):
4095 (1111 1111 1111)
SENT Data Value

Angle (°)
(LSB)
2048 (1000 0000 0000)
0000 (0000 0000 0000)
Figure 38: Angle is Represented as a 12-bit Digital Value
Table 18: Main SENT Parameter Location [1]

Address Bits Parameter Name Description
22:16 SENT_TICK Sets tick rate coefficient.
14:12 SENT_MODE Sets frame update rate, enables TSENT, SSENT, ASENT.
0x19 11:8 DATA_MODE Set data nibble format.
7 CIS CRC nibble includes the status and communication nibble data.
6:4 SCN_MODE Configure status and communication nibble contents.
23 PEN PWM enable. When 1, this overrides the SENT_MODE setting.
0x1B
6:4 SENT_DRIVER SENT pin drive strength.
For information about the SSENT and ASENT configuration bits, see the SSENT Specific Fields section and the ASENT/SSENT Specific Fields
[1]
section, respectively.
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MESSAGE STRUCTURE The duration of a nibble is denominated in ticks. The period of

Data within a SENT message frame is represented as a series of a tick is set by the SENT_TICK parameter. The duration of the
nibbles, with the following characteristics: nibble is the sum of the low-voltage interval plus the high-voltage
interval.
• Each nibble is an ordered pair of a low-voltage interval
followed by a high-voltage interval. The parts of a SENT message are arranged in the following
required sequence (see Table 18):
• The low-voltage interval acts as the delimiting state, which
acts as a boundary between each nibble. The length of this 1. Synchronization and Calibration: Flags the start of the
low-voltage interval is fixed at 5 ticks. SENT message.
• The high-voltage interval performs the job of the information 2. Status and Communication Nibble: Provides A33003 status
state and is variable in duration in order to contain the data and the optional serial data determined by the setting of the
payload of the nibble. SCN_MODE parameter.
3. Data: Angle information and optional data.
• The slew rate of the falling edge may be adjusted using the
SENT_DRIVER parameter. 4. CRC: Error checking.
5. Pause Pulse (optional): Fill pulse between SENT message
frames.
0 5 12 0 5 27 Table 19: Nibble Composition and Value

Ticks Ticks
Quantity of Ticks
Binary Decimal
Low- High- (4-bit) Equivalent
Message Message Voltage Voltage Total Value Value
Signal Signal Interval Interval
Voltage Voltage
5 7 12 0000 0
Low High Low High 5 8 13 0001 1
Interval Interval Interval Interval
5 9 14 0010 2
Nibble Data Value = 0000 Nibble Data Value = 1111
Figure 39: General Value Formation for SENT 5 21 26 1110 14

0000 (left), 1111 (right) 5 22 27 1111 15
SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED
12 to 27 12 to 27 12 to 27 12 to 27
56 ticks ticks ticks ticks ticks
Status and Pause

Nibble Name Synchronization Data 1 Data 6 CRC Pulse
and Calibration Commun-
ication (MSB) (optional)
tSENT
Figure 40: General Format for SENT Message Frame
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Synchronization and Calibration Pulse Hard Error Flag:

Hard error flags cannot be masked and asserts independent of
EEPROM mask bits.
56 ticks 12 to 27 ticks 12 to 27 ticks 12 to 27 ticks 12 to 27 ticks

• Latched indefinitely if any of the following occur:
□ Watchdog timeout
Synchronization Status Data 1 Pause
Nibble Name (MSB) Data 6 CRC Pulse
and and
Calibration Communication (optional)
□ EEPROM hard error (multi-bit fault)

tSENT
□ Self-test error
Figure 41: Synchronization and Calibration Pulse • Temporarily sets but clears after the following conditions
within the SENT Message Frame pass:
The synchronization and calibration pulse is 56 ticks wide, mea- □ Reset/POR
sured from falling edge to falling edge, and delineates the start of □ ZCD integrity error
a new message frame. The host microcontroller uses this pulse to □ Angle averaging error
rescale the subsequent nibble values to correct for clock variation □ Temperature sensor out of range
between the controller and the sensor.
□ PLL not in lock
Status and Communication Nibble Soft Error Flag:
SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED Soft error flags may be masked by setting the appropriate
mask bit in EEPROM address 0x1A.
56 ticks 12 to 27 ticks 12 to 27 ticks 12 to 27 ticks 12 to 27 ticks • Latched temporarily, clears on next SENT frame unless
condition is still asserted.
and and
tSENT
□ Any unmasked errors asserted
b) ID Data: Die ID bits set via SA0 (SCLK) and SA1 (MOSI) pins.
Figure 42: Status and Communication Nibble
within the SENT Message Frame • ID[0]: Value set by the logic level of the SA0 pin.
• ID[1]: Value set by the logic level of the SA1 pin.
The status and communication nibble (SCN) provides diagnos-
c) Serial Data: Two bits, consisting of the SERIALSYNC and
tic information along with other status and environmental data.
SERIALDATA bits. Together they form the “Short Serial
Nibble contents are controlled via the SCN_MODE field within
Message” (per SAE J2716, paragraph 5.2.4.1).
EEPROM. By default, contents of the SCN are not included in
the 4-bit CRC at the end of each SENT frame. The CIS bit within • SERIALSYNC: Indicates the start of a 16-bit serial
EEPROM enables CRC coverage of the SCN contents. It should message.
be noted that this option is not specified in the SAE J2716 SENT • SERIALDATA: Serial data, transmitted one bit at a time,
standard. With the CIS bit set, the CRC is no longer compliant MSB first.
with that outlined in the SENT specification.
Table 20: SCN Bit Contents
The SCN has three different types of bit values that may be pres-
ent, depending on the SCN_MODE setting. These are: SCN_
Bit 3 Bit 2 Bit 1 Bit 0
MODE
a) Soft/Hard Error: Overall condition of the A33003, separated 000 0 0 SOFT HARD
into soft and hard error flags. Detailed error information can 001 SERIALSYNC SERIALDATA SOFT HARD
be obtained via the expanded data nibbles, set via DATA_
010 ID[1] ID[0] SOFT HARD
MODE, or through the slow serial communication.
011 0 0 0 SOFT+HARD
100 0 0 ID[1] ID[0]
101 SERIALSYNC SERIALDATA ID[1] ID[0]
110 SOFT HARD ID[1] ID[0]
111 SERIALSYNC SERIALDATA 0 SOFT+HARD
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Short Serial Message Format Table 22: Serial Output Data

The SENT specification allows additional data transfer via spe- Message ID
Data (8 bits)
(4 bits)
cific bits within the SCN. This data stream is also referred to as
the “slow channel”. 8-bit alive counter (increments by one, every
0 (8)
0-through-15 rotation of the message ID field).
The A33003 implements “Short Serial Message Format” as Temperature in degrees Celsius, offset by +64 (subtract
1 (9)
described in paragraph 5.2.4.1 of the SAE J2716 specification. 64 to get measured temperature).
A 16-bit data packet is transmitted one bit at a time over con- 2 (10) Status, bits [15:8]. See Table 23.
secutive SENT message frames, starting with the MSB. The 3 (11) Status, bits [7:0]. See Table 23.
beginning of each 16-bit packet is indicated by a 1 in the SERI-
Magnetic field reading in gauss, divided by 8 (multiply
ALSYNC bit. The message data is transmitted bit-by-bit via the 4 (12)
by 8 to obtain gauss rating).
SERIALDATA bit. The 16-bit message packet is separated into
5 (13) CUSTOMER [23:16] from EEPROM 0x1F.
three different fields:
6 (14) CUSTOMER [15:8] from EEPROM 0x1F.
a) MESSAGE ID (4 bits): 7 (15) CUSTOMER [7:0] from EEPROM 0x1F.
Four leading bits of the serial data packet, used to identify
data contents. Data rotates through the 16 message IDs as
SENT Data Nibbles
shown in Table 21. The message ID may be considered the
4 LSBs of a 12-bit alive counter that increments every 16 The angle value is embedded within the first three (if using a
SENT frames 12-bit angle value) or four (if using a 16-bit angle value) nibbles
b) Message DATA (8 bits): of every SENT frame and transmitted MSB first. Additional
Eight bits of data. information may be transmitted by extending the number of data
nibbles, up to 6. The contents and number of data nibbles in
c) CRC (4 bits):
every SENT frame are configured using the DATA_MODE field
CRC checksum, used to validate the message ID nibble and
in EEPROM.
the two data nibbles. Same CRC algorithm as that used for the
SENT message frame. SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED SENT_FIXED
Sixteen separate SENT frames are needed to construct a com-

plete 16-bit serial message. To transmit all 8 unique serial data 56 ticks 12 to 27 ticks 12 to 27 ticks
messages (MESSAGE ID 0:7), a total of 128 SENT transmis-
12 to 27 ticks 12 to 27 ticks
and and
sions are necessary. 256 SENT transmissions are required for a Calibration Communication (optional)
complete rotation of the 16 MESSAGE ID fields. tSENT
Figure 43: SENT Data Nibbles

within the SENT Message Frame
Table 21: Short Serial Message Format in SENT Status and

Communication Nibble
SNC Bit Nibble #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SERIALSYNC 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SERIALDATA MESSAGE ID DATA CRC
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SENT Data Mode Options

DATA_MODE = 0
Data Nibbles:
Sync = Synchronization Pulse
SC = Status and Communication Nibble
1,2,3 = Angle Data
CRC = Cyclical Redundancy Check
DATA_MODE = 1
Data Nibbles:
1,2,3 = Angle Data
4,5 = Rotating Status Bits Status[0] = 0: Status[7:1] = Upper 7 bits of SENT status flags
CRC = Cyclical Redundancy Check Status[0] = 1: Status [7:1] = Lower 7 bits of SENT status flags
See Table 23 for details of each status flag.
DATA_MODE = 2
Data Nibbles:
1,2,3 = Angle Data
4 = Message ID Rotating Extended Data (Nibbles 5 and 6) follow the serial message format.
5,6 = Rotating Extended Data Message ID (Nibble 4) indicates the ID for each 8-bit packet of the serial message.
CRC = Cyclical Redundancy Check See Table 21 and Table 22.
DATA_MODE = 3
Data Nibbles:
1,2,3 = Angle Data
4,5,6 = Turns Counter
DATA_MODE = 4
Data Nibbles:
1,2,3 = Angle Data
4,5 = Rotating Status
6 = Alive Counter Status[0] = 0: Status[7:1] = Upper 7 bits of SENT status flags
CRC = Cyclical Redundancy Check Status[0] = 1: Status [7:1] = Lower 7 bits of SENT status flags
DATA_MODE = 5
Data Nibbles:
1,2,3 = Angle Data
4,5 = Alive Counter
When combined with SCN_MODE = 3, this implements the “Single Secure Sensor” requirement
6 = 1’s Complement of Data Nibble 1
outlined in SAE J2716, Appendix A.
DATA_MODE = 6
Data Nibbles:
1,2,3,4 = Angle Data
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DATA_MODE = 7
Data Nibbles:
5 = Rotating Status
Status rotates through the status register. The alive counter [1:0] can be used to
6 = Alive Counter
identify the quadrant of the status register data.
DATA_MODE = 8
Data Nibbles:
1,2,3 = Angle Data
4 = Self-Test and ID
DATA_MODE = 9
Data Nibbles:
1,2,3 = Angle Data
4,5 = Rotating Status
Status[0] = 0: Status[7:1] = Upper 7 bits of SENT status flags
Status[0] = 1: Status [7:1] = Lower 7 bits of SENT status flags
DATA_MODE = 10
Data Nibbles:
1,2,3 = Angle Data Rotating extended data (Nibble 5) follow the serial message format.
4 = Nibble ID Message ID = 0 indicates rotating data is 4 MSBs of first packet.
5 = Rotating Extended Data Message ID = 1 indicates rotating data is 4 LSBs of first packet.
6 = Self-Test Flag and ID See Table 21 and Table 22.
CRC = Cyclical Redundancy Check For a detailed data mode description, refer to the Rotating Data Information for SENT DATA_MODE 10
(rotation spanning 16 SENT frames) section.
DATA_MODE = 11
Data Nibbles:
1,2,3 = Angle Data
4,5 = Rotating Turns Counter Rotating turns [7] = 0: Rotating turns [6:0] = Upper half of turns register.
CRC = Cyclical Redundancy Check Rotating turns [7] = 1: Rotating turns [6:0] = Lower half of turns register.
DATA_MODE = 12
Data Nibbles:
1,2,3 = Angle Data
4 = Rotating Status
5 = Alive Counter Status rotates through the status register. The alive counter [1:0] can be used to
6 = Self-Test and ID identify the quadrant of the status register data.
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DATA_MODE = 13
Data Nibbles:
1,2,3 = Angle Data
4 = Alive Counter
5 = 1’s Compliment of Nibble 1
Modified version of the “Single Secure Sensor” implementation as outlined in Appendix A of SAE J2716.
DATA_MODE = 14
Data Nibbles:
DATA_MODE = 15
Data Nibbles:
5 = Alive Counter
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955 Perimeter Road
Self-Test and ID Nibble This nibble is particularly useful when sharing SENT lines,
The self-test and ID (ST&ID) nibble is optional. It is included because it allows the self-test diagnostic results and correspond-
as one of the extended nibbles when using DATA_MODE = 4:7. ing sensor ID to be quickly determined without a significant
This nibble consists of the following three data bits (MSB is latency penalty (only one nibble to the SENT frame).
always 0):
SENT Status Bit Description
Bit 3 Bit 2 Bit 1 Bit 0
The extensive status and error flags of the A33003 may be read
0 ST ID[1] ID[0]
at any time via SPI or by entering Manchester communication
Figure 44: ST&ID Nibble mode. To facilitate error/status flag reporting by way of the unidi-
rectional SENT protocol, a selection of these flags are communi-
The ST bit indicates a failure of one of the three internal self-tests cated via extra data nibbles when using DATA_MODE = 1, 4, 7,
(CVH self-test and logic BIST). If set, this indicates significant 9, or 12. These status flags are also transmitted via the slow serial
failure of the sensor, and a reset should be initiated. protocol through the SCN.
ID[0] and ID[1] provide the sensor ID value as determined via The flags are 0 if the condition is clear and 1 if the condition is
the logic values of the SA0 and SA1 pins. true. For transient conditions, the flag clears after the bit is pre-
sented on the SENT output.
Table 23: SENT Status Flag Definitions

Bit Symbol Definition
15 SF15 PLL not in lock.
14 SF14 Angle averaging (ORATE) or zero-crossing integrity error.
13 SF13 POR (power-on reset) occurred.
12 SF12 Temperature sensor out of range.
11 SF11 Self-test error (CVH self-test or LBIST).
10 SF10 EEPROM hard error.
9 SF9 Oscillator watchdog error.
8 R Always 0. Indicates MSB byte.
7 SF7 Magnetic sense low.
6 SF6 Undervoltage, on VCC line or analog regulator output.
5 SF5 EEPROM soft error.
4 SF4 Saturation in math computations.
3 SF3 SENT contention.
2 SF2 Magnetic sense high.
1 SF1 Turns counter overflow.
0 R Always 1. Indicates LSB byte.
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Status Flag Locations for SENT DATA_MODE 1, 4, and 9 (spanning 2 SENT frames)
Nibble 4 Nibble 5
SF15 SF14 SF13 SF12 SF11 SF10 SF9 R (0)
Nibble 4 Nibble 5
SF7 SF6 SF5 SF4 SF3 SF2 SF1 R (1)
Status Flag Locations for SENT DATA_MODE 7 and 12 (spanning 4 SENT frames)
Nibble 4 (Status Nibble) Nibble 5 (Alive Counter)
SF15 SF14 SF13 SF12 X X 0 0

SF11 SF10 SF9 R(0) X X 0 1

SF7 SF6 SF5 SF4 X X 1 0

SF3 SF2 SF1 R(1) X X 1 1
Turns Count Information for SENT DATA_MODE 11 (spanning 2 SENT frames)

Nibble 4 Nibble 5
0 0 TURNS[11:10] TURNS[9:6]
Nibble 4 Nibble 5
1 0 TURNS[5:4] TURNS[3:0]
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Rotating Data Information for SENT DATA_MODE 10 (rotation spanning 16 SENT frames)
Nibble 4 (Rotating Data) Nibble 5 (Rotating Data)

NibID NibData
0 0 0 0 8-bit Alive counter MSBs [7:4]
0 0 0 1 8-bit Alive counter LSBs [3:0]
0 0 1 0 Temperature MSBs [7:4]
0 0 1 1 Temperature LSBs [3:0]
0 1 0 0 SF15 SF14 SF13 SF12
0 1 0 1 SF11 SF10 SF9 0
0 1 1 0 SF7 SF6 SF5 SF4
0 1 1 1 SF3 SF2 R 1
1 0 0 0 Magnetic Field [7:4]
1 0 0 1 Magnetic Field [3:0]
1 0 1 0 CUSTOMER [23:20]
1 0 1 1 CUSTOMER [19:16]
1 1 0 0 CUSTOMER [15:12]
1 1 0 1 CUSTOMER [11:8]
1 1 1 0 CUSTOMER [7:4]
1 1 1 1 CUSTOMER [3:0]
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SENT CRC Nibble SENT Pause Pulse (Optional)

The CRC nibble is a 4-bit error checking code, implemented per The pause pulse is an optional addition to the SENT message
the SAE J2716 SENT recommended specification. frame, transmitted following the CRC nibble. It acts to “fill in”
the frame until the beginning of the next SENT transmission.
The CRC is calculated using the polynomial x4 + x3 + x2 + 1,
The pulse may behave in one of two ways, based on the SENT_
initialized to 0101.
MODE setting.
By default, the checksum covers only the contents of the data
With SENT_MODE set to 2, a pause pulse is inserted until
nibbles (nibbles 3:6). By setting the CIS bit within EEPROM, the
new angle data is available. The inserted pause pulse is a mini-
contents of the SCN are included within the CRC nibble, which
mum of 12 ticks in length. If a pause longer than 768 ticks is
deviates from the SENT standard.
required, the pulse restarts, requiring a minimum of 12 more
ticks.
For SENT_MODE values 3 through 7, the sensor operates in
56 ticks
Synchronization
12 to 27 ticks
Status
12 to 27 ticks
Data 1
12 to 27 ticks 12 to 27 ticks
Pause
either triggered or addressable/sequential SENT mode. In these
modes the sensor outputs a SENT message frame in response
and and
to host action (either a trigger or a function pulse). When not

tSENT
responding to the host, the sensor outputs a pause pulse of indefi-
nite length (i.e., remains high until a host request).
Figure 45: CRC Nibble within the SENT Message Frame
56 ticks 12 to 27 ticks 12 to 27 ticks 12 to 27 ticks 12 to 27 ticks

and and
tSENT
Figure 46: Pause Pulse within

the SENT Message Frame
Low High Low High

SENT_MODE 2
5 Ticks 7 to 763 Ticks 5 Ticks 7 to 763 Ticks
SENT_MODEs Low High Low (host)

3 through 7 5 Ticks Infinite (until pulled low by host) Trigger (Min of 1.8 µs) or Function Pulse
Figure 47: SENT Pause Pulse
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SENT OUTPUT MODE

The timing and method of SENT transmission may be configured • Triggered SENT (TSENT)
using the SENT_MODE field within EEPROM. The method of A SENT message frame occurs only when initiated by the
SENT transmission falls within the following three categories: host. The A33003 sensor outputs a continuous pause pulse,
during which the host triggers a SENT frame by pulling the
• Free-Running SENT
SENT line low for a minimum of TTrig(MIN). Once released, the
Angle data is automatically placed on the SENT line with
sensor responds with a SENT message frame.
no prompting from the host. Depending on settings, the
• Shared SENT
SENT message frames may be transmitted back-to-back or
Two distinct formats—sequential SENT (SSENT) and
synchronized with each update of the angle value.
addressable SENT (ASENT)—allow four compatible devices
to share a single SENT line.
SENT_MODE Visual Description

0002 (0) – SENT disabled.
Streaming output with variable message duration and
CRC
CRC
SCN
SCN
sync
sync
data
data
no pause pulse. Angle data is sampled near the end
of the status and communication nibble. Maximum
0012 (1) SENT age at time of sampling is 2ORATE × 2 µs. Depending
message SENT message 1 SENT message 2 on tick time and ORATE setting, the same data may
TSENT1 TSENT2
be transmitted multiple times. This mode provides the
quickest data delivery rate.
SENT message frames are synchronized with

pause
pause
CRC
SCN
SCN
sync
sync
data
data
the device internal update rate. Pause pulse is

inserted until fresh data becomes available. Angle
0102 (2) SENT data is sampled between 1 to 2 tick times of the
12
message ticks synchronization pulse. Pause pulse varies in length
min. between 12 and 2ORATE × 2 µs. (Pulse restarts after
SENT message 1 SENT message 2 768 ticks).
Controller pulls OUT low Controller releases OUT TSENT SCN sampling:
tdSENT (7 ticks) Controller initiates a SENT transmission by pulling the
Sensor IC starts message line low during a pause pulse. After a delay of tdSENT,
Angle data latched the controller releases the output, then the SENT
0112 (3) message begins. Angle data is latched at the end
pause
pause
Waiting
CRC
sync
SCN
sync
data
period, twait of the SCN. When latched, the data age may be up
to (2ORATE + 2 µs) + tRESPONSE. This option is useful
when the controller requires a prompt with a minimum
(previous message) SENT message “age” for the angle data.
Controller pulls OUT low; Controller releases OUT

angle data latched TSENT falling-edge sampling:
tdSENT (7 ticks) Similar to SENT_MODE = 3, except angle data is
Sensor IC starts message latched once the output line is pulled low.
Useful when multiple ICs are connected to a single
1002 (4)
pause
pause
Waiting controller. Allows synchronous sampled data to be

CRC
SCN
sync
data
period, twait retrieved one device at a time, by releasing the trigger

for each individual sensor. When latched, data age
may vary by up to (2ORATE + 2 µs) + tRESPONSE.
(previous message) SENT message
Addressable SENT (ASENT). See Shared SENT

1012 (5) –
Protocol section.
Sequential SENT (SSENT). See Shared SENT
1102 (6) –
Protocol section.
Long sequential SENT. See Shared SENT Protocol
1112 (7) –
section.
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SHARED SENT PROTOCOL

Addressable SENT (ASENT) and sequential SENT (SSENT) defined number of ticks greater than a normal SENT pulse low
are extensions of the Allegro triggered SENT (TSENT) protocol. period. The duration of the low time is measured by the sensors
ASENT and SSENT allow multiple Allegro sensors with SENT and interpreted as a designated function.
output capability to coexist on a single shared SENT bus. The
host (ECU) is able to select one sensor at a time, addressing that
sensor to respond with a SENT output packet, thus polling each
sensor on the bus over some period of time.
Like TSENT, the ASENT and SSENT protocols require an
open-drain system configuration in which any sensor or the host
can pull the SENT line low. The SENT line is pulled high by an
external resistor to a known VCC. A high level is attainable on the FunctionPulse
bus only when no device is actively pulling the line low.
In ASENT and SSENT, each sensor on the bus is assigned a Greater than 7 Ticks Low
unique sensor ID number between 0 and 3, allowing up to four Width Defines Function
sensors to coexist on the bus. This sensor ID number is assigned
by the logic state of the SA0 and SA1 pins. Figure 49: Function Pulse (Output by Host)
Function Pulses Functions that are acted upon by all sensors simultaneously are
VCC 5 V Max designated broadcast pulses. Functions that are acted upon by
Sensor Sensor Sensor Sensor Host only one sensor are designated addressing pulses and are associ-
ated with a target sensor ID. A function pulse may be defined as
ID = 0 ID = 1 ID = 2 ID = 3 (ECU)
both a broadcast pulse and an addressing pulse. For instance, all

R
sensors sample and hold data, but only one transmits a SENT
packet.
C
Bus Capacitance A sensor that does not support a specific function does not
respond to the function pulse.
Figure 48: Shared SENT Bus Example Function pulses must be greater in duration than the SENT pulse
low time (5 ticks on the A33003), not to be mistaken as a part of
This section describes the different function pulses that are a normal SENT transmission
referenced in the Addressable SENT (ASENT) section and the
The duration of function pulses are defined in SENT ticks in
Sequential SENT (SSENT) section.
order to scale with the SENT frame itself. Minimum and maxi-
The host sends communications to a sensor or sensors via differ- mum pulse durations are set such that they satisfy electrical and
ent function pulses, which are equivalent in nature to a TSENT timing characteristics.
trigger pulse, but with defined widths. A function pulse is placed
The various function pulses with their expected tick ranges are
on the SENT bus by the host pulling the SENT line low for a
shown in Table 24 through Table 26.
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Table 24: ASENT Functional Pulses

Function Type Related Options Min Tick Nom Tick Max Tick Description
Addressed sensor responds with SENT frame,
Addressing/
F_OUTPUT NO_SAMPLE 15 17 19 containing either held data (from F_SAMPLE) or
Broadcast
current data.
Except sensors configured with NO_FSAMPLE
= 1, all sensors sample and hold their magnetic
Addressing/ NO_FSAMPLE
F_SAMPLE 31 35 39 data. If SAMPLE_ADR = 1, this is also an
Broadcast SAMPLE_ADR
addressing pulse, and addressed sensor
responds with SENT frame.
Addressing/ Manchester If MEPE = 1, device enables Manchester
F_AUX 56 63 70
Broadcast Communication communication. Otherwise, ignored.
Table 25: SSENT Functional Pulses. SENT_MODE = 6

containing either held data (from slot 0 sampling
Addressing/ NO_SAMPLE
F_OUTPUT 15 17 19 or F_SAMPLE) or current data.
Broadcast ZERO_SAMPLE
If ZERO_SAMPLING = 1 and SLOT = 0, sensors
sample and hold their magnetic data.
Except sensors configured for NO_FSAMPLE
= 1, all sensors sample and hold their magnetic
Addressing/ NO_FSAMPLE
F_SAMPLE 31 35 39 data. If SAMPLE_ADR = 1, this is also an
Broadcast SAMPLE_ADR
addressing pulse, and addressed sensor
responds with SENT frame.
F_AUX 56 63 70
All sensors synchronize their slot counters such
F_SYNC Broadcast 93 104 115
that the next slot is for sensor ID 0.
Table 26: Long SSENT Functional Pulses. SENT_MODE = 7

Per micro- containing either held data (from slot 0 sampling)
Addressing/ NO_SAMPLE
F_OUTPUT 9 [1] controller 81 or current data.
Broadcast ZERO_SAMPLE
spec If ZERO_SAMPLING = 1 and SLOT = 0, sensors
sample and hold their magnetic data.
All sensors synchronize their slot counters such
F_SYNC Broadcast 105 140 171
that the next slot is for sensor ID 0.
F_AUX 216 240 264
[1] At
tick times less than 1.5 µs, the nominal 5-tick low portion of a SENT pulse within the SENT frame may overlap with F_OUTPUT range, resulting in contention. The low
side of the F_OUTPUT pulse may be increased via the PWS.FP_ADJ EEPROM field. All sensors sharing a bus must have the same FP_ADJ setting.
Sensor Measurement Range Sensor Measurement Range Sensor Measurement Range

Function
ASENT or SSENT SSENT Long
Sensors measure function pulses to a wider range of tick times to F_OUTPUT 13:27 7:94
allow for variance in falling/rising threshold and oscillator vari-
F_SAMPLE 28:49 N/A
ance from sensor to sensor. Sensor measurement ranges for each
F_AUX 50:83 196:297
type of function pulse are:
F_SYNC 84:133 (SSENT only) 95:195
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SEQUENTIAL SENT (SSENT) protocol has a broadcast F_SYNC pulse that is used by the host
to force all sensors to reset their slot counter to 0.
SSENT Addressing Protocol
Long SSENT (SENT_MODE = 7) allows the A33003 to work
The SSENT protocol requires sensors on the bus to be polled in with existing shared SENT methodologies. The added overhead
sequential order, meaning increasing, consecutive, and rotating decreases the rate at which messages may be transmitted.
order by sensor ID starting with sensor ID 0. The slot for a sen-
sor is the time at which that sensor is expected to respond to an In order to reduce the burden on the host, and also to improve
addressing pulse and other sensors are expected to not respond. detection and recovery from bus contention or system errors
affecting the SENT bus, the SSENT protocol has the following
Each sensor independently maintains a slot counter that is configuration options that can be selected.
incremented each time the sensor detects an addressing pulse.
This slot counter becomes the slot number, which is used by the • SLOT_MARKING. When enabled, each sensor waits a
sensor to decide which sensor is being polled by the host. The different length of time following an addressing pulse, based
slot counter is compared to the sensor ID and, if they match, that on their sensor ID. This leaves the SENT bus in a high state
sensor responds with the SENT frame, and all other sensors do for a varying duration before the sensor pulls the line low to
not respond, although they increment their own slot counter. begin the SENT frame. All sensors on the bus (including the
addressed sensor) measure this time to interpret the sensor
If the slot counter is incremented past the total number of sensors ID of the transmitting sensor. By comparing this to the slot
on the bus (MAX_SENSOR option), the slot counter is returned counter, each sensor can recognize if an unexpected sensor
to 0. Each sensor must be programmed consistently with the total responded to the addressing pulse. By default, the sensor
number of sensors so they all roll over to 0 at the same count. would then drop offline, because it cannot be known which
Sensors do not increment their slot counter on a broadcast pulse. sensor is out-of-sync. This option increases the overhead on
The SSENT protocol relies on each sensor maintaining the exact the bus and therefore reduces the maximum rate at which
same slot number by counting the addressing pulses. In order sensors can be polled. Slot marking increases the polling time
to synchronize all sensors to the same slot number, the SSENT of a sensor by the slot marking time for that sensor. All sensors
on a bus must be configured with the same choice for this
option.
FrameReq Pulse (Host) Delay (Sensor) SENT Frame (Sensor) BusIdle
Slot Number N
Width Defines Function Delay Sensor Responds if

Sensors Increment Slot Counter 7 Ticks or Sensor ID = Slot Number
Slot Marking
Figure 50: SSENT Sensor Addressing
F_SYNC (Host) BusIdle FrameReq Dly SENT Frame SensorID 0 (Slot 0) BusIdle
BusIdle FrameReq Dly SENT Frame SensorID 1 (Slot 1) BusIdle
Figure 51: SSENT Sensor Addressing—No Slot Marking (Three Sensors on Bus)
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F_SYNC (Host) BusIdle FrameReq Dly SENT Frame SensorID 0 (Slot 0) BusIdle
BusIdle FrameReq DlySlot1 SENT Frame SensorID 1 (Slot 1) BusIdle
Figure 52: SSENT Sensor Addressing—With Slot Marking (Four Sensors on Bus)
Table 27: Slot Marking Delay Time

Sensor ID Delay Time in Ticks (Nominal) [1]
0 7
1 18
2 36
3 62
[1] Delay time not intended for use by host. Tick values are approximate and differ
from part to part due to oscillator variance.
• POR_OFFLINE. When enabled, a sensor remains offline until ♦ If configured with C_ZERO_SAMPLE = 1, the sensor
the host issues F_SYNC, or one of the other synchronization performs a sample-and-hold on the rising edge of the
options takes effect (C_IDLE_SYNC). If disabled, a sensor F_OUTPUT pulse for slot 0.
powers up with its slot counter set to 0 and goes directly ♦ If configured with C_NO_SAMPLE = 1 and C_ZERO_
online. This allows the sensors to initialize without any host SAMPLE = 0, the sensor never performs a sample-and-
interaction. However, if a sensor gets a power-on reset after hold, so it always returns current data in response to
the bus is in operation, its counter may be out of sync with F_OUTPUT.
other sensors, and this could result in bus contention.
• F_SAMPLE: Except for sensors configured with
• IDLE_SYNC. When enabled, a sensor monitors the bus NO_SAMPLE = 1, all sensors sample and hold their data at
for a long high (bus idle) period greater than 510 ticks and the rising edge of the pulse:
resets its slot counter to 0. This option can be used if sensor
polling is expected to always be periodic and continuous, such □ If SAMPLE_ADR = 0, this is a broadcast pulse to a sensor,
that the only extended bus idle time occurs after power-up. and that sensor does not respond.
□ If SAMPLE_ ADR = 1, this is also an addressing pulse to a
SSENT Function Pulses sensor, and the addressed sensor returns a SENT frame with
• F_OUTPUT: The addressed sensor returns a SENT frame either the sampled or current data.
with sampled magnetic data: SAMPLE_ADR must be configured the same for all parts on
□ If data from a sample-and-hold operation is available the bus.
(F_SAMPLE or via C_ZERO_ SAMPLE = 1), that data is • F_SYNC: All sensors synchronize their slot numbers by
returned. setting their slot counters such that the next addressing pulse is
□ If data from a sample-and-hold operation is not available, for slot 0.
current data is sampled and returned:
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ADDRESSABLE SENT (ASENT) • F_SAMPLE: Except for sensors configured with

NO_ SAMPLE = 1, all sensors sample and hold their data at
ASENT Addressing Protocol the rising edge of the pulse:
The ASENT protocol allows sensors to be polled in an arbitrary □ If SAMPLE_ADR = 0, this is a broadcast pulse to a sensor,
order. The sensor ID is transmitted by the host following any and that sensor does not respond.
addressing pulse as a series of 0, 1, 2, or 3 incremental address
(IncAdr) pulses. After this sequence, the SENT line is left in a □ If SAMPLE_ADR = 1, this is also an addressing pulse to a
high state. After a time period of about 18 nominal ticks, each sensor, and the addressed sensor returns a SENT frame with
sensor recognizes that there are no more incoming IncAdr pulses. either the sampled or current data.
The sensor whose ID matches the number of IncAdr pulses The SAMPLE_ADR must be configured the same for all parts
received responds. on the bus.
ASENT Function Pulses • F_AUX: Sensor(s) output becomes disabled, pending a

Manchester access or exit code:
• F_OUTPUT: Addressed sensor returns a SENT frame with
sampled magnetic data: □ If an incorrect access or exit code is sent to the device,
SENT operation resumes.
□ If data from a sample-and-hold operation (F_SAMPLE) is
available, that data is returned □ To return to SENT functionality and ignore incorrect
Manchester messages after the access code has been sent, an
□ If data from a sample-and-hold operation is not available, exit code must be sent.
current data is sampled and returned.
□ If configured with NO_SAMPLE = 1, the sensor does ASENT Host Requirements:
not sample and hold, so it always returns current data in • The host must initiate SENT frame output by selecting
response to F_OUTPUT. appropriate function pulses.
• Following any function pulse, the host must detect timeouts or
SENT frame contention and take appropriate recovery action.
7 ticks high 5 ticks low

IncAdr Pulse
Figure 53: ASENT IncAdr Pulse (Output by Host)
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FrameReq Pulse (Host) IncAdr Pulses (0 – 3)(Host) EndAddress > 18 Ticks High SENT Frame (Sensor)
Width defines function Host adds pulses for Sensor recognizes the end Addressed sensor
SensorID 0 selected SensorID 1, 2, or 3 of the addressing phrase responds
SensorID 0 FrameReq (Host) EndAddress SENT Frame (Sensor) BusIdle
SensorID 1 FrameReq (Host) IncAdr EndAddress SENT Frame (Sensor) BusIdle
SensorID 2 FrameReq (Host) IncAdr IncAdr EndAddress SENT Frame (Sensor) BusIdle
SensorID 3 FrameReq (Host) IncAdr IncAdr IncAdr EndAddress SENT Frame (Sensor) BusIdle
Figure 54: ASENT Sensor Addressing
SENSOR MAGNETIC DATA SAMPLING Sample-and-Hold

Sensors sample their magnetic data based on a combination of Sample-and-hold is when the sensor samples magnetic data on
function pulse and configuration options. Two types of sampling the rising edge of a specific function pulse and holds it for output
are supported: sample-on-output and sample-and-hold. in a SENT frame later in time, when addressed. This allows the
data sampling from multiple sensors to be synchronized, with the
Sample-on-Output: tradeoff in latency. The sensor performs a sample-and-hold of its
Sample-on-output is when the sensor samples magnetic data magnetic data in the following cases:
within a short time period preceding the transmission of that data • An F_SAMPLE function is broadcast, unless the sensor is
in the SENT frame. This provides the host with a minimal latency configured with NO_FSAMPLE = 1.
between the data sample and its reception at the host. The sensor
uses sample-on-output in the following cases: • The host initiates an F_OUTPUT function in SSENT
mode, the slot number is for sensor ID 0, and the sensor is
• An F_OUTPUT function is addressed to that sensor and no configured with ZERO_SAMPLE = 1.
held data is present.
Once the sensor has data held from a sample-and-hold, it trans-
mits it in the SENT frame the next time it is addressed. If the
re sensor is again polled before another sample-and-hold, then that
d He
m ple sensor returns the same data unless certain events intervene,
Sa in which case the sample-and-hold data is discarded. These
le
A ng events are:
• A diagnostic is executed that prevents the SENT interface
Sync Pulse SCN Nibble Data Nibble
F_OUTPUT + Addressing
from obtaining valid magnetic data from the sensor logic
Figure 55: Sample-on-Output Example (CVH_SELFTEST).
• The SENT interface is disabled; for instance, the SENT line is
taken over by the receipt of a Manchester access code.
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If a sensor is polled and no sample-and-hold data is available (for The sensor exits the offline state and enters the BusSync state
instance, if the part comes online after a sample-and-hold has once its SENT logic becomes functional, after it monitors the
been issued), it samples current data. It is not required that SENT bus long enough to flush any internal synchronization or
all sensors on a shared bus be configured the same for sampling. filtering pipelines and sees the SENT bus high. This is necessary
This allows a subset of the sensors on a shared bus to be synchro- to guarantee that any subsequent low pulses are measured as their
nized for data sample, while others always perform sample-on- full duration.
output.
Bus Synchronization (BusSync)
SENSOR STATES: OFFLINE, BUS SYNC, AND ONLINE BusSync is the state in which the sensor determines to which
addressing pulse it should respond. For ASENT, this state is
unnecessary, and it immediately transitions from offline to
online. For SSENT, the sensor first monitors the SENT bus
until it can synchronize its slot counter to the other sensors on
All
Co the bus before responding to any addressing pulse, but always
n responds to broadcast pulses, even in the BusSync state.
Sa figur
mp ed
F_SAMPLE le Se A sensor configured for SSENT sets its slot counter and exits
He ns BusSync to online when:
re ors
• The host issues an F_SYNC pulse. The sensor immediately
Figure 56: Sample-and-Hold (SSENT or ASENT) knows the next slot is for sensor ID 0, and can then respond
correctly.
• IDLE_SYNC is enabled and the bus is high (BusIdle) for at
All
Co
n least a fixed (greater than 510 ticks) period of time.
Sa figur
mp ed
le Se
He ns • POR_OFFLINE = 0, and the sensor exits the power-on-reset
re ors
state.
Online
F_OUTPUT Slot 0 Sync Pulse SCN Nibble Data Nibble
In the online state, the sensor is actively interpreting the shared
bus, looking for and responding to function pulses. From online,
Figure 57: Sample-and-Hold a sensor goes offline when:
SSENT with ZERO_SAMPLE = 1
• It is powered down or reset.
Offline • In response to a Manchester activation (F_AUX).
Offline is when the sensor is not actively interpreting the state of • It detects a bus contention (SSENT mode).
a shared SENT bus. In the offline state, the sensor does not drive
the SENT bus. A sensor is offline:
• During Manchester.
• When unpowered.
• After power-up.
• After a reset that would reset the SENT logic (POR).
• During CVH self-test.
• After a bus contention is detected (unless stated otherwise).
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SENT Message Frame Descriptions

The general format of a SENT message frame is shown in
Figure 38. The individual sections of a SENT message are
described in Table 28.
Table 28: SENT Message Frame Section Definitions

Section Description
Synchronization and Calibration
Provide the external controller with a detectable start of the message frame. The large quantity of ticks
Function
distinguishes this section, for ease of distinction by the external controller.
Syntax Tick count: 56
Status and Communication
Provides the external controller with the status of the A33003 and indicates the format and contents of the DATA
Function
section.
Nibbles: 1
Tick count: 12 to 27
Syntax Field width: 4 bits
1:0 Device status (indicates either a hard or soft error condition)
3:2 Message serial data protocol (set by SCN_MODE parameter)
Data
Function Provides the external controller with data selected by the SENT_DATA parameter.
Nibbles: 3 to 6
Syntax Tick count: 12 to 27 (each nibble)
Field width: 4 bits (each nibble)
CRC
Provides the external controller with cyclic redundancy check (CRC) data for certain error detection routines
Function
applied to the data nibbles.
Nibbles: 1
Syntax Tick count: 12 to 27 (each nibble)
Field width: 4 bits
Pause Pulse
Additional time can be added at the end of a SENT message frame to synchronize each SENT message with the
Function
internal angle measurement updates, determined by the SENT_UPDATE parameter.
Quantity of ticks: 12 tick minimum and 768 tick maximum (length determined by SENT_UPDATE option and by the
individual structure of each SENT message. If a pause pulse reaches 768 ticks, it restarts with a minimum length
Syntax
of 12 ticks)
Quantity of bits: n/a
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SENT Data Programming Parameters

Table 29: SCN_MODE (Register Address: 0x19, bits 6:4)
Status and Communication Nibble Format
Function
Defines role of bits within the status and communication nibble
Related Commands –
SCN_MODE Bit 3 Bit 2 Bit 1 Bit 0

000 0 0 SOFT HARD
001 SERIALSYNC SERIALDATA SOFT HARD
010 ID[1] ID[0] SOFT HARD
Values 011 0 0 0 SOFT+HARD
100 0 0 ID[1] ID[0]
101 SERIALSYNC SERIALDATA ID[1] ID[0]
110 SOFT HARD ID[1] ID[0]
111 SERIALSYNC SERIALDATA 0 SOFT+HARD
Options –
The SERIALSYNC and SERIALDATA bits form a 16-bit message, transmitted over 16 consecutive SENT frames.
The message contents are arranged as follows:
Short Serial Message
SCN Bit Nibble #
Examples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SERIALSYNC 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SERIALDATA MESSAGE ID DATA CRC
Table 30: SENT_DRIVER (Register Address: 0x1B, bits 6:4)

Output Signal Configuration
Function Sets configuration of the output signal slew-rate control. Sets the ramp rate on the gate of the output driver,
thereby changing slew rate at the output.
Fall Time (80% to 20% Typical Values) (µs)
Code
CLOAD = 100 pF CLOAD = 1 nF
000 (Default) 0.031 0.102
001 0.075 0.105
010 0.130 0.226
Values
011 0.180 0.296
100 0.460 0.622
101 0.930 1.100
110 1.900 1.900
111 2.900 2.700
Options –
Examples –
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Table 31: DATA_MODE (Register Address: 0x19, bits 11:8)

Data Nibble Format
Function Quantity and contents of data nibbles in message. (Does not relate to data contained in the status and
communication nibble.)
0: Nibbles 1,2,3: Angle data (nibbles 4,5,6 skipped)
1: Nibbles 1,2,3: Angle data
Nibbles 4,5: Status bits, alternates between two 8-bit words
Nibbles 4,5,6: Rotating extended data (see the Short Serial Message Format section)
Nibbles 4,5,6: Turns count data
Nibble 6: Alive counter
Nibbles 4,5: 8-bit alive counter
Nibble 6: 1’s complement of nibble 1
6: Nibbles 1,2,3,4: Angle data
Nibble 5: Status bits, alternates between four 4-bit words
Nibble 4: Self-test and ID
Values
Nibbles 4,5: Status bits, alternates between two 8-bits words
Nibbles 4,5: Rotating extended data (see the Short Serial Message Format section)
Nibbles 4,5: 8-bit turns counter
Nibble 5: 1’s complement of Nibble 1
Options –
Examples –
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Table 32: SENT_MODE (Register Address: 0x19, bits 14:12)

Function Selects between the various SENT update rates. Also used to select various modes of triggerable SENT.
000: Disable, no SENT output.
001: No pause pulse; new frame immediately follows previous frame.
010: SENT message frame synchronized to internal angle update rate. Pause pulse inserted to ensure each
new SENT transmission corresponds to a fresh angle sample.
011: Triggered SENT mode (TSENT). Pause pulse held indefinitely until receipt of trigger pulse (OUT pulled
low) from the controller, SENT message begins once output is released. Data latched near end of SCN.
Values
100: Triggered SENT mode (TSENT). Pause pulse held indefinitely until receipt of trigger pulse (OUT pulled
low) from the controller, SENT message begins once output is released. Data latched on falling edge of
trigger.
101: Addressable SENT mode (ASENT). See Shared SENT Protocol section.
110: Sequential SENT mode (SSENT). See Shared SENT Protocol section.
111: Long SSENT. Supports alternative SENT line sharing protocol. See Shared SENT Protocol section.
Options –
Examples –
Table 33: SENT_TICK (Register Address: 0x19, bits 22:16)

Tick Duration
Function
Sets the SENT tick time: SENT_TICK/16 MHz = tick (µs)
Field width: 7 bits
Syntax
Any value from 0 to 127 can be used (although an internal limit of one clock period is forced)
Code Tick Time (µs) Coefficient
000 0000 [1] 0.0625 1/16 (a minimum of one clock period is forced internally)
000 0001 [1] 0.0625 1/16
000 0010 [1] 0.125 2/16
000 0011 [1] 0.1875 3/16
000 0100 [1] 0.25 4/16
Values 000 1000 0.5 8/16
001 0000 1 16/16
001 1000 1.5 24/16
011 0000 3 48/16
110 0000 6 96/16
111 1110 7.875 126/16
111 1111 7.9375 127/16
Options –
Examples –
[1] Tick times shorter than 0.5 µs are not guaranteed.
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Table 34: CIS (Register Address: 0x19, bit 7)

Function SENT CRC includes the status and communication nibble (SCN)
Syntax Field width: 1 bit
0: SCN is not included in the CRC nibble.
Values
1: SCN bits are included via the CRC nibble (does not conform to the J2716 SENT standard)
Options –
Examples –
ASENT/SSENT SPECIFIC FIELDS

Table 35: MAXID (Register Address: 0x19, bits 25:24)
Function Specifies highest sensor ID number on the shared SENT bus
00: Highest ID value is 0. Sensor is not sharing the SENT line
01: Highest ID value is 1. Two sensors are sharing the SENT line
Values
10: Highest ID value is 2. Three sensors are sharing the SENT line
11: Highest ID value is 3. Four sensors are sharing the SENT line
Options –
Examples –
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Table 36: NS (Register Address: 0x19, bit 3)

Function No Sample. Sensor does not sample angle on receipt of an F_SAMPLE pulse
0: On receipt of an F_SAMPLE pulse, sensor samples and holds angle data
Values
1: Sensor does not sample and hold data on receipt of an F_SAMPLE pulse
Options –
Examples –
Table 37: FA (Register Address: 0x19, bit 0)

Function F_SAMPLE addressing. Sensor treats the F_SAMPLE pulse as an addressing pulse
0: F_SAMPLE is treated as a broadcast pulse. If NS ≠ 1, sensors sample and hold angle data on any F_
SAMPLE pulse.
Values
1: F_SAMPLE is treated as an addressing pulse. If NS ≠ 1, sensors only sample and hold angle data on an
F_SAMPLE pulse if properly addressed.
Options –
Examples –
SSENT SPECIFIC FIELDS

Table 38: IS (Register Address: 0x1B, bit 8)
Function IDLE_SYNC. If SENT bus idle for more than 510 ticks, sensor resets its slot counter (SSENT only).
0: Sensor takes no action for an idle SENT line
Values 1: If SENT line is idle for greater than 510 ticks, internal slot counter is reset to 0. All sensors sharing a SENT
line should have matching IS settings
Options –
Examples –
Table 39: PO (Register Address: 0x1B, bit 7)

Function POR_OFFLINE. After power-on reset, sensor remains offline (SSENT only).
0: After a power-on reset, sensor goes online with a slot counter of 0
Values 1: After a power-on reset, sensor remains offline; after slot counter synchronization via an F_SYNC pulse or
IDLE_SYNC, sensor goes online
Options –
Examples –
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Table 40: SM (Register Address: 0x19, bit 15)

Function SLOT_MARKING enable (SSENT only).
0: No slot marking pulses
Values
1: Sensor outputs a bus high delay after an addressing pulse, based on sensor ID
Options –
Examples –
Table 41: ZS (Register Address: 0x19, bit 2)

Function ZERO_SAMPLING. Sensor samples and holds data at Slot 0 (SSENT only)
0: When sensor sloct counter resets to 0, no special action is performed
Values
1: When sensor slot counter resets to 0, sensor performs a sample and hold
Options –
Examples –
Table 42: FP_ADJ (Register Address: 0x1B, bits 25:24)

Function Pulse Adjust. Only for long SSENT (SENT_MODE = 7). Increases the lower threshold of F_OUTPUT
Function
pulse by 0 to 3 ticks. Reduces possible misinterpretation of F_OUTPUT pulses at sub-1.5 µs tick times
00: No Change to F_OUTPUT pulse width. Minimum width = 9 ticks
01: Minimum width of F_OUTPUT increased by 1 tick. Min = 10 ticks
Values
10: Minimum width of F_OUTPUT increased by 2 ticks. Min = 11 ticks
11: Minimum width of F_OUTPUT increased by 3 ticks. Min = 12 ticks
Options –
Examples –
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APPENDIX B: ANGLE ERROR AND DRIFT DEFINITION
Angle error is the difference between the actual positon of the Angle Drift
magnet and the position of the magnet as measured by the angle
sensor IC (without noise). This measurement is performed by Angle drift is the change in the observed angular position over
reading the angle sensor IC output and comparing it with a high- temperature, relative to 25°C.
resolution encoder. See Figure 56. During Allegro factory trim, drift is measured at 150°C. The
Angle Error value is calculated using the following formula:
E [º]
AngleDrift = Angle25°C – Angle150°C
Emax where each angle value is an array corresponding to 16 angular
positions around a circle.
0º
E = α Sensor – α Real Reference Angle

36
α Real
1.5
0º
Error 25°C
Error 150°C
Eminl 1 No Error
Angle Drift
Figure 58: Angle Error Definition Angle Error
0.5
0
Angle Error Definition
–0.5
Throughout this document, the term “angle error” is used exten-
sively. Thus, it is necessary to introduce a single angle error –1
definition for a full magnetic rotation. The term “angle error” is
calculated according to the following formula: –1.5
0 60 120 180 240 300 360
AngleError = max( |Emax| , |Emin| ) Input Angle
In other words, it is the maximum deviation from a perfect NOTE: This data is a simple representation of angle drift and not
straight line between 0 degrees and 360 degrees. For the pur- real data. Also, the error at 25°C and 150°C are often out of phase.
pose of a generic definition, the offset of the IC angle profile is This can cause a drift larger than the maximum error specification
removed prior to the error calculation, as shown in Figure 56. of the part, as shown.
The offset itself depends on the starting IC angle position relative
Figure 59: Angle Drift of 150°C in Reference to 25°C
to the encoder 0° and thus can differ anywhere from 0° to 360°.
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REVISION HISTORY
Number Date Description
– September 30, 2019 Initial release
1 November 22, 2019 Added footnote to Selection Guide table (page 2); updated footnote 4 (page 10)
Updated Interrupt Pulse Hold Time values (page 7); changed PWI to PWS (pages 23, 27, 50); corrected
package drawing Hall element labels (page 62); updated Hard Error Flag and Soft Error Flag descriptions
2 October 6, 2020
(page A-3); updated Sent Output Mode table (page A-12), tables 24-26 (page A-14); added Sensor
Measurement Range section (page A-14).
Added footnote to Figure 3 (page 5); updated SEN.SENT_MODE description (page 53) and FWS.FP_ADJ
3 October 14, 2020
description (page 56).
Updated ASIL status (page 1), Selection Guide (page 2), Bypass Pin Output Voltage (page 6), footnote 1
4 January 13, 2021 (page 9), Linearization section (pages 17-18), Package Drawing reference numbers (pages 62-63),
Figure 46 (page A-11); added CRC section (page 27).
Updated “ISO 26262:2011” to “ISO 26262” (page 1), Features and Benefits (page 1-2), Angle Measurement
5 April 20, 2021 section (page 13), Table 10 (page 32), Figure 29 (page 29), Figure 32 (page 31), and SENT Output Mode
table (page A-12)
Removed 125°C version and corrected part number of 150°C version in selection guide (page 2); removed
125°C performance characteristics table (page 10); corrected part number (page 11); removed performance
characteristics charts for 125°C version (page 12; entire page removed); In EEPROM Table, swapped the
order of columns 1 and 2 (Shadow Memory Address and EEPROM Address), changed Register Names
6 November 29, 2021
MPWS and PLPC to PWS and LPC respectively, changed Bit 1 “da” to “xa” (page 50, formerly page 51);
clarified definition of SEN.XA (page 52, formerly page 53); corrected rotation direction parenthetical in
ANG.ro definition (page 56, formerly page 57); In Table 22, corrected references to other table (was Table 19,
now Table 23) (page A-4).
Updated reference design (page 5), updated SPI interface specifications (page 6), corrected footnote
numbering (pages 6 through 9), added EEPROM Margin Check section (pages 39 and 40), added SENT
error mask description and corrected typo in H2T bit name (page 54), updated product outline drawings
(pages 61 and 62), clarified reference to data mode descriptions (page A-6), and made minor branding,
7 March 30, 2023
editorial, and formatting corrections (all pages), including removal of archaic language (e.g., MOSI redefined
as controller-out/peripheral in), addition of cross-references and hyperlinks, minimization of the use of
capitalization and quotation marks, use of capitalization for bit addresses, and recreation of low-resolution
images.
Copyright 2023, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

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A33003

- Precision Angle Sensor IC

FEATURES AND BENEFITS DESCRIPTION

VCC Regulator To all internal circuits

Angle Detecon Temp

Figure 1: A33003 Magnetic Circuit and IC Diagram

A33003-DS, Rev. 7 March 30, 2023

FEATURES AND BENEFITS (continued)

[1] Contact Allegro MicroSystems for 5 V interface availability.

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS: May require derating at maximum conditions

PINOUT DIAGRAMS AND TERMINAL LIST TABLES

Pinout Diagram Terminal List Table, Dual Die

Figure 2: A33003 Typical Setup

Figure 3: A33003 Reference Design for Stringent EMC Requirements

Continued on the next page…

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A33003LLUATR and A33003LLUBTR-DD PERFORMANCE CHARACTERISTICS:

Effective Resolution = log2(360) – log2 ( 1

[11] 1G (gauss) = 0.1 mT (millitesla).

TYPICAL PERFORMANCE CHARACTERISTICS

Angle Error Angle Drift

Angle Drift [Degrees]

Figure 6: Noise Performance over Temperature

Overview System-Level Timing

PWM Output PWM CARRIER FREQUENCY

Table 1: PWM Carrier Frequencies in Hz

0 3125 2778 2273 1667 1087 641 352 185

7 2963 2532 1961 1351 833 472 253 131

14 2817 2326 1724 1136 676 373 197 101

120 15 2797 2299 1695 1111 658 362 191 98

PWM Period PWM Period

360 Degrees 240 Degrees

Figure 8: Pulse-Width Modulation (PWM) Examples

ERROR REPORTING IN PWM Table 3: PWM Error Select (PES)

Table 4: PWM Error Duty Cycle and Priority

Filter and ZCD angle Filter and PLL angle

Rotation direction Offset adjust

ANGLE_ZCD Angle hysteresis PWM pin

H2T = 0 ANGLE and ANGLE_15

TCP = 1 PLL_TURNS_ANGLE output register

Accumulate angle changes into 21-bit

Take 10 MSB of TURNS_DELTA TURNS output register

TURNS_OFFSET output register

Take 9 LSB of TURNS_DELTA

Figure 9: Angle Measurement—Sensor Readout Steps

Figure 10: Linearization Example

Figure 11: Post-Linearization Error

Sensor angle posi�on

Figure 12: Effect of Hysteresis

Turns Counting 360

the measured magnet becomes more important than knowing the 90

a magnet. This feature also includes the ability to start up with 8

was achieved by a combination of relatively complex mechanical

It is possible to use the zero-crossing diode (ZCD) signal path as

To read the total position of the magnetic encoder (angle in 0 time

Figure 14: EEPROM field TURNS_INIT

11 10 9 8 7 6 5 4 3 2 1 0 TURNS register with T45 = 0

Angle Detecon Temp