This article has been accepted for inclusion in a future issue of this journal.

Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON ELECTRON DEVICES 1

A Charge Transfer Model for CMOS Image Sensors

Liqiang Han, Student Member, IEEE, Suying Yao, Member, IEEE, and Albert J. P. Theuwissen, Fellow, IEEE

Abstract— Based on the thermionic emission theory, a charge

transfer model has been developed which describes the charge
transfer process between a pinned photodiode and floating
diffusion (FD) node for CMOS image sensors. To simulate
the model, an iterative method is used. The model shows that
the charge transfer time, barrier height, and reset voltage of the
FD node affect the charge transfer process. The corresponding
measurement results obtained from two different test chips are
presented in this paper. The model also predicts that other
physical parameters, such as the capacitance of the FD node
and the area of the photodiode, will affect the charge transfer.
Furthermore, the model can be extended to explain the pinning
voltage measurement method and the feedforward effect.
Index Terms— CMOS image sensors (CISs), pinned Fig. 1. 4T pixel architecture.
photodiode (PPD), thermionic emission theory.

I. I NTRODUCTION with a small signal level [11]. In [12], subthreshold current,

also called emission current, is used to explain charge transfer
C MOS image sensors (CISs) are widely used nowadays in
the fields of electronic imaging, such as consumer, scien-
tific, and military applications. The pinned photodiode (PPD)
noise and image lag. The emission current originates from the
thermal motion phenomenon of electrons, where the electrons
is the most important component in a CIS. The implants of the which have enough thermal velocity in the transfer direction
PPD and the transfer gate (TG) must be accurately controlled will cross the barrier on the charge transfer path [13].
and optimized for the purpose of low image lag, low dark In [6], [14], and [15], methods are shown for the ideal charge
current, and large full well capacity (FWC) [1]–[3]. Small transfer path without a barrier, which needs a very precise
implant adjustments in implant energy, dose, tilt, and mask doping control. In actual manufacturing, both the increased
position will affect the performance dramatically [4], [5]. surface boron implant dose for sufficient surface pinning and
It is popular to utilize TCAD tools to study the performance dark current reduction, and the out-diffusion phenomena of
of a CIS [6]–[8]. However, implant adjustments are still boron itself may result in a barrier on the charge transfer
required in actual manufacturing. path [16], which affects the charge transfer efficiency
Since the doping profile under the TG is so complicated, dramatically.
it is difficult to describe the charge transfer process using a In standard 4T pixels, the typical charge transfer time
drift diffusion (DD) model without TCAD tools. Self-induced is 1 μs. For some high speed applications, the charge transfer
drift, thermal diffusion, and fringing field effects are common time should be much shorter, e.g., 40 ns [17]. In many
views for charge transfer in charge coupled devices (CCD) [9]. papers, see [5], [18], [19], a nonlinear photoresponse with low
A similar viewpoint for CIS can be found in [10]. exposure levels is observed if the charge transfer time is not
In standard 4T CIS pixels, the PPD and floating diffusion (FD) long enough. This leads to a low charge transfer efficiency
node are separated, which is very different from a CCD and may result in serious image lag.
where the electrodes are adjacent. For the PPD structure, the In this paper, we establish a charge transfer model to
subthreshold current is used to explain the charge transfer describe the charge transfer process between the PPD and the
FD node based on the thermionic emission theory. Section II
Manuscript received March 20, 2015; revised June 13, 2015; accepted describes the model in detail. Section III shows some
June 23, 2015. The review of this paper was arranged by Editor J. R. Tower.
L. Han is with the School of Electronic Information Engineering, measurement results corresponding to the model prediction.
Tianjin University, Tianjin 300072, China, and also with the Electronic Section IV gives two examples of the model extension. Finally,
Instrumentation Laboratory, Delft University of Technology, Delft 2628CD, the conclusion is drawn in Section V.
The Netherlands (e-mail: h.liqiang@tudelft.nl and hlq@tju.edu.cn).
S. Yao is with the School of Electronic Information Engineering, Tianjin
University, Tianjin 300072, China (e-mail: syyao@tju.edu.cn). II. C HARGE T RANSFER M ODEL IN A CIS
A. J. P. Theuwissen is with Harvest Imaging, Bree 3960, Belgium, and also
with the Electronic Instrumentation Laboratory, Delft University of Technol- A typical 4T pixel is shown in Fig. 1. The BB is the charge
ogy, Delft 2628CD, The Netherlands (e-mail: a.j.p.theuwissen@tudelft.nl). transfer path when a high voltage is applied to the TG. Several
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. implants, at least including p+ for the pinned layer and n− for
Digital Object Identifier 10.1109/TED.2015.2451593 the PPD, affect the potential distribution in region A, where a
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

2 IEEE TRANSACTIONS ON ELECTRON DEVICES

where A is the Richardson constant [13], and S A is the area

of the cross section on the charge transfer path at the barrier
position.
The number of electrons in the PPD Ne can be obtained by
the famous equation
Ne /V = n e = NC exp(q(VC − Vbf )/kT ) (3)
where V is the volume of the PPD, n e is the electron density,
and NC is the conduction band effective density of states.
From (3), we can obtain
Vbf = VC − kT /q × ln (Ne /NC V ) . (4)
Fig. 2. Potential diagram along BB .
Substituting (4) with (1), and using d Q = −qd N e
−Ne−1 d Ne = I0 / (q NC V ) × exp (−q VC /kT ) dt (5)
barrier may occur. Because of this potential barrier, we have  Ne  t
developed a charge transfer model based on the thermionic − Ne−1 d Ne = I0 / (q NC V ) exp (−q VC /kT )dt (6)
emission theory in Section II-A. In Section II-B, we prove Ne0 0
that this emission theory-based model is also applicable for where Ne0 is the initial number of electrons in the PPD, and
pixels without barriers. In Sections II-C and II-D, the effect of t is the charge transfer time. Then, we can obtain
conduction band variation and the FD potential is considered,    
respectively. I0 q VC
Ne = Ne0 exp − exp − t (7)
q NC V kT

A. Level-1 Model: Thermionic Emission Theory in Pixel where Ne also represents the number of residual electrons after
the charge transfer phase. Therefore, the number of transferred
Fig. 2 shows the potential diagram along the cross section electrons from the PPD to the FD node in the given transfer
of BB when the TG is open, where E C , E f , and E V represent time is
the energy levels of the conduction band, Fermi level, and     
I0 q VC
valence band, respectively; q is the electron charge; q VC is Ntransfer = Ne0 1 − exp − exp − ×t .
the barrier height on the charge transfer path; q Vbf is the q NC V kT
difference between the conduction band barrier in region A (8)
and the Fermi level in the n− PPD region; and |Eff | is the Equation (8) is the level-1 charge transfer model. The
fringing field intensity. In this paper, the electrostatic potential relationship between Ntransfer and Ne0 is linear for a given t.
in a semiconductor is defined as the potential of the middle Fig. 3(a) shows an example of the photoresponse curve
of the bandgap. based on the level-1 model, where Ne0 and Ntransfer correspond
There are six assumptions for this level-1 model. to the exposure and output, respectively. If t is long enough,
1) qVbf is much larger than kT, where k is the Boltzmann the exponential term in (8) approximates to zero, and the
constant, and T is the absolute temperature. charge transfer is complete. With a certain Ne0 as shown
2) Region A and the fringing field region are fully depleted. in Fig. 3(b), the relationship between Ntransfer and t is
3) The conduction band is fixed. exponential, and the charge transfer process is mainly
4) |Eff | is large enough, and the electrons will quickly drift completed during the beginning of the charge transfer phase.
to the FD node if they can cross the barrier. The total
current flow is limited by the emission current.
5) During the charge transfer phase, the Fermi level in the B. Supplement for the Level-1 Model: Diffusion Theory
n− region is balanced, and the charge transfer process As mentioned in Section I, it is hard to say that all pixels
in the PPD is neglected. This is suitable for pixels with have a potential barrier on the transfer path, even though
a small PPD area and large pixels with a special design a monotonic potential distribution is difficult to implement.
for a built-in electric field [1], [8], [17], [20]. For those pixels which have an ideal transfer path as shown
6) The number of transferred electrons is small and the in Fig. 4, the emission theory is also applicable. A simple
potential of the FD node is high enough so that the derivation is given below.
effect of the electrons in the flat region of the tunnel The emission theory is established by calculating the
as shown in Fig. 2 is neglected, and the charge transfer number of electrons that have enough thermal velocity in
process is unidirectional. the transfer direction to cross the barrier per time unit. The
The emission current from the PPD to the FD node is written thermal motion phenomenon of a particle is the physical basis.
as follows: For a typical PPD structure, the order of magnitude of the
n− region doping concentration is 1015–1016 cm−3 , which
IPPD−FD = d Q/dt = I0 exp(−q Vbf /kT ) (1) means that assumption 1) in the level-1 model is also valid.
I0 = A · S A · T 2 (2) Thus, the derivation of the emission current which is based
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

HAN et al.: CHARGE TRANSFER MODEL FOR CISs 3

Fig. 5. Gradient concentration.

where n e (l) and n e (−l) are the charge density at x = l

and x = −l, respectively. Using the degraded emission theory,
the current at x = 0 due to electrons that originate at x = −l
and move from left to right is
Ir→l = −q × n e (−l) × (kT /2πm ∗ )1/2 . (12)
The current at x = 0 due to charges that originate at x = l
and move from right to left is
Il→r = −q × n e (l) × (kT /2πm ∗ )1/2 . (13)
Then, the total current at x = 0 is
Ix=0 = Ir→l − Il→r = q(kT /2πm ∗ )1/2 × (n e (l) − n e (−l)).
Fig. 3. Photoresponse in the level-1 model. (a) Ntransfer versus Ne0 and
(b) Ntransfer versus t, where T = 300 K, Ne0 = 10 000, q VC = 0.05 eV, (14)
A = 120 A/T2 cm2 , S A = 0.4 μm2 , and V = 8 μm2 .
It should be noted that the collision effect is neglected in the
thermionic emission theory. Therefore, we consider l in (14)
to be equal to the mean free path
(n e (l) − n e (−l))
Ix=0 = q(kT /2πm ∗ )1/2 × 2l (15)
2l
∗ 1/2 dn e (x)
Ix=0 = ql(2kT /πm ) (16)
dx
where (2kT/πm ∗ )1/2 is equal to the thermal velocity vth , which
is well known as the mean of the magnitude of the velocity
in any one dimension. Equation (16) can be written as
dn e (x) dn e (x)
Ix=0 = qlvth = q Dn (17)
dx dx
Fig. 4. Charge transfer path without a barrier. where lvth is equal to the diffusion constant Dn [21]. This is
the thermal diffusion theory.
From (12)–(17), we know that the diffusion theory is
on the Boltzmann distribution is applicable for this condition. bidirectional. However, the degraded emission current is
Without a barrier, (1) can be written as unidirectional, which means an external force is needed to
 
I = 4πqm ∗ k 2 / h 3 · T 2 exp((q E Cfn − q E Cn )/kT ) (9) keep this unidirectional transfer, otherwise the transfer will
become bidirectional again. We consider assumption 4) in
where 4πqm∗ k2 / h 3 is the extended form of the Richardson the level-1 model to be valid for well-designed pixels. For
constant A, h is the Planck constant, m∗ is the effective mass example, the band bending in the fringing field region is 1 eV
of the electron, and E Cfn and E Cn are the Fermi level and at a depth (width) of 0.15 μm with a linear distribution, where
conduction band in the n− region, respectively. Substituting |E ff | is ∼66 667 V/cm. As a result, μ|E ff | is much larger
NC = 2(2πm∗ kT)3/2 /h 3 with (9), we can achieve than vth , where μ is the electron mobility. The charge transfer
I = q(kT /2πm ∗ )1/2 NC exp((q E Cfn − q E Cn )/kT ) (10) is limited by the current flow in region A.
∗ 1/2 In conclusion, both the diffusion theory and emission theory
I = q(kT /2πm ) ne . (11)
originate from the thermal motion of electrons. For pixels with
We call (11) the degraded emission current. an ideal charge transfer path, the degraded emission current
Assume there is a piece of semiconductor with a charge and diffusion current originate from the same physical process
density gradient in the x-axis direction as shown in Fig. 5, in region A. We use this degraded emission theory instead
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

4 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 8. Example of conduction band potential variation.

Fig. 6. Conduction band correction. potential. Multiplying both sides by dϕC gives
d (dϕC /d x) q
dϕC = − (N D + n e ) dϕC (20)
 dϕC /d x d x   ε  ϕC
dϕC dϕC q ND q NC
d =− dϕC +
0 d x d x ε
 ϕC 0  ε
qϕC − qϕ f
× exp dϕC
0 kT
(21)
where ϕ f is the Fermi level potential, resulting in
Fig. 7. PPD structure with a uniform doping concentration.  
2q N D kT n e kT NC −qϕ f
E2 = − ϕC + − exp . (22)
ε ε ε kT
of DD model in region A, so that the level-1 model is also From (19), we can also obtain the following equation:
applicable because of the existence of |E ff |. 
dϕC q ND q x
E =− = x− n e d x. (23)
dx ε ε 0
C. Level-2 Model: Conduction Band Correction At two specific positions, the middle of the PPD x = 0 and
The PPD is a finite well for electrons which is fully depleted the edge of depleted region x = d, the respective electrical
after a complete charge transfer. As the number of electrons in field intensities are
the PPD decreases, there are more fixed positive charges which E x=0 = 0 (24)
lead to a stronger electrical field from the inside of the PPD to E x=d = q N D d/ε − q Ne / (2εSPPD ) (25)
region A. Therefore, the effect of conduction band variation is
considered in the level-2 model. Assumption 3) in the where SPPD is the area of the PPD. Substituting (24) and (25)
level-1 model should be modified as follows: the conduction with (22) results in
 
band profile in region A should be fixed under a certain 2q N D kT n e (0) kT NC −qϕ f
0=− ϕC (0) + − exp
voltage applied to the TG, but the conduction band inside the ε ε ε kT
PPD varies with the number of electrons as shown in Fig. 6. (26)
We expect to obtain the following corrected equation for (q N D d/ε − q Ne / (2εSPPD ))2
the conduction band potential:  
2q N D kT n e (d) kT NC −qϕ f
=− ϕC (d) + − exp .
VC = VC0 + VCnwell (18) ε ε ε kT
(27)
where VCnwell reflects the variation of the conduction band
Assuming the PPD has a square well and combining
potential in the n− region, and VC0 is defined as the barrier
(26) and (27), VCnwell is approximately expressed as
height when the number of electrons in the PPD is equal to
the FWC with a certain high voltage applied to the TG. VCnwell ≈ ϕC (0) − ϕC (d)
 2
As shown in Fig. 7, we assume that the doping concentration q Ne kT (n e (0) − n e (d))
= ND d − +
is uniform. The x-axis represents the depth direction, the depth 2ε N D 2SPPD q 2N D
of the undepleted PPD region is 2d under full well condition (28)
for a horizontal PPD structure. Solving the Poisson equation
where the first term is much larger than the second term.
to get the relationship between the Ne and VCnwell
Substituting (28) with (18) leads to
d 2 ϕC /d x 2 = −q (N D + n e ) /ε (19) VC ≈ VC0 + q/ (2ε N D ) × (N D d − Ne / (2SPPD ))2 . (29)
where N D is the doping concentration of the n− region, ε is There is a parabolic relationship between Ne and VC as
the permittivity of silicon, and ϕC is the conduction band shown in Fig. 8. It should be noted that the electron density
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

HAN et al.: CHARGE TRANSFER MODEL FOR CISs 5

Fig. 9. Simulation flow of the level-2 model.

Ne /V (n e ) is lower than the doping concentration N D in a

working PPD.
Equation (29) is the corrected term for (8). Nevertheless,
it is still difficult to achieve an analytical solution. An iterative
method is used for the level-2 model simulation shown
in Fig. 9, which requires the following equation, derived
from (7), to calculate the transfer time of each electron:
ti = q NC V /I0 × exp (q VC / (kT )) × ln (Ne / (Ne − n))
(30)
where n represents the simulation step size.
An example of the simulation results is shown in Fig. 10,
where the Richardson constant A is 120 A/T2 cm2 ,
S A = 2 μm × 0.2 μm, N D = 3 × 1015 cm−3 , d = 0.25 μm,
and SPPD = 4 μm × 4 μm. Ne0 and Ntransfer correspond to the
exposure and the output, respectively. With a certain barrier
height, as shown in Fig. 10(a), if the charge transfer time is not Fig. 10. Simulation results: photoresponse curves (a) with different transfer
long enough, e.g., 100 or 300 ns, the transfer is incomplete and time, (b) with different barrier heights, and (c) CTI curves with different
a nonlinear response is observed at the very beginning of the barrier heights.
curve. Fig. 10(b) shows that the charge transfer speed becomes
slower with a greater barrier height. The corresponding charge
transfer inefficiency (CTI) curves are shown in Fig. 10(c),
where the initial number of electrons is 10 000 e− .
In [3], [11], and [12], the capacitor of the PPD CPPD is
used to represent the charge holding capacity, and the potential
variation is described by the differential form of CPPD .
In addition, we can obtain the expression of CPPD from (28).
However, for [3], [11], and [12], the effect of Fermi level
variation is neglected.

D. Level-3 Model: Effect of FD Potential

In the level-1 and level-2 models, the effect of FD potential
ϕFD is neglected. In fact, ϕFD decreases with an increase in Fig. 11. TG tunnel and FD potential profile (a) for a small signal, the flat
region is depleted and (b) for a large signal, the flat region is inversed.
number of transferred electrons. Electrons will transfer from
the FD node back to the PPD through the thermionic emission
process if ϕFD is low enough. is fixed with a certain voltage applied to the TG; ϕfFD is
Fig. 11 shows the potential profile of the TG tunnel and the Fermi level potential of the TG tunnel and FD node;
FD node, where ϕpin is the lowest potential in region A and and ϕfrst is the value of ϕfFD after the FD node reset.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

6 IEEE TRANSACTIONS ON ELECTRON DEVICES

1) If the number of transferred electrons from the PPD to

the FD node is small, all the electrons are stored in the
FD node and the TG tunnel is depleted. In this condition,
ϕfFD − ϕpin is high enough so that the emission current
from the FD node back to the PPD can be neglected.
2) As the number of transferred electrons is increased, the
potential of the FD and ϕfFD will become lower
simultaneously. Finally, the TG tunnel becomes
inversed; the emission current from the tunnel back to
the PPD should be taken into consideration if the value
of ϕfFD − ϕpin is low enough.
In the level-3 model, the effect of the FD potential is
considered. Emission current from the TG tunnel to the
PPD is

Iback = I0 exp(−q(ϕfFD − ϕpin + E g /2q)/kT ) (31)

where E g is the bandgap width, and we assume the charge

transfer path from the FD node back to the PPD in region A is
the same as the charge transfer path from the PPD to the
FD node, so that I0 need not to be corrected as it equals the Fig. 12. Simulation flow of the level-3 model.
value in (1). In the level-1 and level-2 models, we calculate
the variation of the PPD Fermi level and conduction band,
respectively. For the FD node, only the conduction band
potential variation is considered, since the doping concentra-
tion of the FD node is much higher than that of the PPD, and
the difference between the Fermi level and the conduction
band is almost fixed, e.g., 0.05 eV. Thus, the relationship
between the number of transferred electrons and the potential
variation is

VFD = ϕfrst − ϕfFD = q Ntransfer / (CFD + CTG ) (32)

where VFD is the variation of the FD potential, CFD is the

capacitance of the FD, and CTG is the equivalent capacitance
of the TG. From the famous C–V curve of a MOS capacitor,
we know that CTG is not a constant. For small signal and large
signal conditions, CTG is approximately equal to zero and to
the oxide capacitance, respectively. In order to simplify the
discussion, we only consider the large signal condition, thus
CTG is equal to the oxide capacitance.
Fig. 12 shows the simulation flow of the level-3 model.
An example of the simulation results is shown in Fig. 13,
where ϕpin = 1.2 V, VC0 = 0.03 V, CFD = 1 fF,
CTG = 1 fF, and the other physical parameters are the same as
the simulation of the level-2 model. As shown in Fig. 13(a),
where t = 1 μs, a higher reset voltage can improve the charge
transfer capacity, and a small slope of the transfer curve α Fig. 13. Simulation results (a) level-2 versus level-3 model and (b) with
in the large signal region is observed. With a certain Ne0 , different transfer time.
the charge transfer process on the macrolevel will stop when
IPPD−FD = Iback . On the other hand, IPPD−FD will become
larger with an increase in the residual electrons in the PPD. transfer case is shown in Fig. 13(b). The difference between
The saturated output level (Ntransfer ) will become slightly the charge transfer curves with a different t becomes narrow in
higher with the increase in exposure level (Ne0 ), since a larger the saturation region, meaning that they will finally intersect
Iback is needed for the balance, which also means a larger with each other.
Ntransfer is required. This is the reason for the presence of The level-3 model describes the bidirectional emission
the small slope α in the saturation region. However, in the process. Both the FWC of the PPD and the FD node will
small signal region, the change in reset voltage has almost no affect the slope α in the saturation region, since both of them
effect on the charge transfer efficiency. The incomplete charge affect the balance between IPPD−FD and Iback . For example,
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

HAN et al.: CHARGE TRANSFER MODEL FOR CISs 7

Fig. 16. Measurement results of chip A: photoresponse curves with different

Fig. 14. Simulation results: slope α in the saturation region. barrier heights.

Fig. 15. (a) Test pixel in chip A. (b) Test pixel in chip B.

if the FWC of the PPD is fixed, we can achieve a larger α

with a larger CFD . Conversely, if CFD is fixed, we can
reach a larger α with a smaller FWC of the PPD, as shown
in Fig. 14. Furthermore, the area of the PPD will affect the
charge transfer efficiency without even considering the thermal
diffusion inside the PPD.

III. M EASUREMENT R ESULTS

In this section, some measurement results obtained from
two different test chips will be shown. Chip A was fabricated
in a technology for which we could adjust the pixel implants.
Chip B was fabricated in a standard 180-nm CIS process, and
the source follower (SF) and row select transistor (SEL) were
implemented by pMOS transistors. Both of the test pixels have
a large area but also a special design for a built-in electric field Fig. 17. Measurement results of chip B (a) with different reset voltages of
inside the PPD, as shown in Fig. 15. The performance of the the FD and (b) with different transfer times.
W-shaped pixel in chip B has been published in [1].

A. Measurement Results of Chip A with longer t (1.2 μs for Fig. 16 and 2 μs for Fig. 17). The
The test pixel in chip A is L-shaped as shown in Fig. 15(a), black curves and red curves correspond to the pixels with
and CFD is ∼8 fF. We changed the doping concentration for lower barrier height and greater barrier height, respectively.
the TG by several special p-type implants, and two pixels with As the model predicts, the charge transfer process has a strong
a high barrier height on the same wafer were selected for this correlation with barrier height. Normally, a lower doping
discussion. In chip A, all the transistors in the pixel were concentration in the tunnel region improves the charge transfer
implemented by nMOS, the voltage applied to the TG was performance, but the FWC of the PPD will decrease because
3.3 V, the reset voltage of the FD node was ∼2.7 V. of the feedforward effect [3].
Fig. 16 shows the measurement results, which correspond Since the pixel transistors in chip A were implemented by
to the simulation results in Fig. 10. In the linear response nMOS, the readout of a large signal is limited by the SF.
region, we consider all the electrons to be transferred from In order to observe the large signal region of the response
the PPD to the FD node if t is long enough. Then, Ne0 is curves, the measurement results obtained from the pixel with
obtained by multiplying the exposure by the average sensitivity the pMOS SF and SEL will be shown in Section III-B.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 18. Timing for pinning voltage measurement.

B. Measurement Results of Chip B Fig. 19. Simulation results for the pinning voltage.
The test pixel in chip B is W-shaped as shown in Fig. 15(b),
where CFD is ∼4 fF, the width of the TG is 0.9 μm, and the
FWC is limited by the FD node rather than the PPD. Fig. 17
shows the measurement results of the test pixel in chip B,
where Fig. 17(a) and (b) corresponds to the simulation results
in Fig. 13(a) and (b), respectively.
As shown in Fig. 17(a), the reset voltage of the FD node
is varied, and the transfer time is fixed at 2 μs. In the small
signal region, the variation of the FD reset voltage has almost
no effect on the charge transfer. In fact, a small difference
between the various curves is observed due to the nonlinearity Fig. 20. Simulation method for the feedforward effect.
of the SF. In the large signal region, the curve with the lowest
FD reset voltage 1.8 V enters saturation first, and the curve
with the highest FD reset voltage 2.2 V has the largest output
range. The improvement in the output range (e− ) is equal
to CFD Vrst /q, where Vrst is the reset voltage difference.
As shown in Fig. 17(b), the transfer time is varied, and
the reset voltage of the FD is fixed at 2.2 V. The difference
between the two curves with a different t becomes narrow
in the saturation region. Yet a small difference still exists
between them which originates from the thermal diffusion
process inside the PPD; this is not considered in our model.
In addition, a small slope is observed in the saturation region Fig. 21. Charge transfer path when the TG is OFF.
as the model predicts.

IV. M ODEL E XTENSION obtain the potential inside the PPD ϕppd , and ϕppd = ϕpin +
VC = 1.37 V.
A. Explanation for the Pinning Voltage Measurement
The method for measuring the pinning voltage was first
reported in [22], and later explained in [23]. The measurement B. Feedforward Effect During Exposure Phase
timing is shown in Fig. 18. During the injection phase, the TG The feedforward effect, which is explained by the
and the reset transistor are open, and the number of electrons thermionic emission theory, is reported in [3]. This effect
injected from the FD node to the PPD is controlled by varying influences the FWC of the PPD. During the exposure phase,
Vinj , where Vinj is the voltage of VDDRST during the injection both the photogenerated current inside the PPD and the emis-
phase. sion current from the PPD to the FD node exist if the barrier
We use the level-3 model to describe the charge injection height is not high enough. Therefore, these two processes
process during the injection phase. The only difference is that should be simulated simultaneously during the exposure phase;
ϕfFD is fixed, and ϕfFD = Vinj. Fig. 19 shows the simulation the simulation method is shown in Fig. 20. The entire exposure
results for the method used to measure the pinning voltage, phase consists of m interval periods. The photoinduced elec-
where ϕpin = 1.2 V, VC0 = 0.03 V, and all other physical trons generate at the very beginning of each interval period,
parameters are the same as the simulation of the level-2 model. and the emission current is simulated by the level-2 model
In the transition region, the shape of the curve has a correlation during the rest of this period (using the level-3 model if ϕfrst is
with injection time ting ; similar measurement results can be very low).
found in [23]. When the PPD is empty, VC = 0.14 V+VC0, Fig. 21 shows the charge transfer path when the TG is OFF,
which can be extracted from (29) and Fig. 8. Then, we can and the position depends on the doping profile between the
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

HAN et al.: CHARGE TRANSFER MODEL FOR CISs 9

finally intersect with each other, which was not observed in

the measurement results. In fact, a small difference still exists
between them which originates from the thermal diffusion
process inside the PPD; this is not considered in our model.
The model also predicts that the width of the TG, the
capacitance of the FD node, the equivalent capacitance of
the TG, and even the area ratio between the PPD and the
FD node, which can be controlled by the pixel designer, will
affect the charge transfer efficiency. Furthermore, the model
can be extended to explain the pinning voltage measurement
method and the feedforward effect. We hope this model can
help the readers to understand more about the charge transfer
process between the PPD and the FD node, thus allowing
better pixel design.

ACKNOWLEDGMENT
The authors would like to thank Y. Xu and X. Ge for
providing test chip B and helping with the measurement.

R EFERENCES
[1] Y. Xu and A. J. P. Theuwissen, “Image lag analysis and photodiode
shape optimization of 4T CMOS pixels,” in Proc. Int. Image Sensor
Workshop, Jun. 2013, pp. 153–157.
[2] J. P. Carrère, S. Place, J. P. Oddou, D. Benoit, and F. Roy, “CMOS
Fig. 22. Simulation results. (a) Feedforward effect. (b) Photoresponse curves image sensor: Process impact on dark current,” in Proc. IEEE Int. Rel.
limited by the FWC of the PPD. Phys. Symp., 2014, pp. 3C.1.1–3C.1.6.
[3] M. Sarkar, B. Büttgen, and A. J. P. Theuwissen, “Feedforward effect
in standard CMOS pinned photodiodes,” IEEE Trans. Electron Devices,
vol. 60, no. 3, pp. 1154–1161, Mar. 2013.
PPD and the FD node. In the simulation for the feedforward [4] Y. Li, B. Li, J. Xu, Z. Gao, C. Xu, and Y. Sun, “Charge transfer
effect, m = 1000, and the physical parameters are the same as efficiency improvement of a 4-T pixel by the optimization of electrical
potential distribution under the transfer gate,” J. Semicond., vol. 33,
in the simulation of the level-2 model. As shown in Fig. 22(a), no. 12, p. 124004, Dec. 2012.
a greater barrier height and shorter exposure time texp will [5] Z. Cao et al., “Process techniques of charge transfer time reduction
increase the equivalent FWC of the PPD during the exposure for high speed CMOS image sensors,” J. Semicond., vol. 35, no. 11,
p. 114010, Nov. 2014.
phase. The same conclusion can be found in [3]. Fig. 22(b) [6] H. Mutoh, “3-D optical and electrical simulation for CMOS image
shows the photoresponse curves limited by the FWC of sensors,” IEEE Trans. Electron Devices, vol. 50, no. 1, pp. 19–25,
the PPD, which is very different from the curves limited by the Jan. 2003.
[7] J. Michelot et al., “Back illuminated vertically pinned photodiode with in
FWC of the FD node as shown in Fig. 13(b). The difference depth charge storage,” in Proc. Int. Image Sensor Workshop, Jun. 2011,
between the two curves with a different t does not become pp. 24–27.
smaller in the large signal region. A similar measurement [8] B. Shin, S. Park, and H. Shin, “The effect of photodiode shape on charge
transfer in CMOS image sensors,” Solid-State Electron., vol. 54, no. 11,
result can be found in [5]. pp. 1416–1420, Nov. 2010.
[9] A. J. P. Theuwissen, Solid-State Imaging With Charge Coupled Devices.
V. C ONCLUSION Boston, MA, USA: Kluwer, 1995, pp. 27–35.
[10] E. R. Fossum and D. B. Hondongwa, “A review of the pinned photodiode
Based on the thermionic emission theory, we established a for CCD and CMOS image sensors,” IEEE J. Electron Devices Soc.,
charge transfer model to describe the charge transfer process vol. 2, no. 3, pp. 33–43, May 2014.
[11] N. Teranishi, A. Kohono, Y. Ishihara, E. Oda, and K. Arai, “No image
between the PPD and the FD node. The model is suitable for lag photodiode structure in the interline CCD image sensor,” in Proc.
small pixels and large pixels with a special design for an extra IEDM, Dec. 1982, pp. 324–327.
built-in electric field. [12] E. R. Fossum, “Charge transfer noise and lag in CMOS active pixel
sensors,” in Proc. IEEE Workshop Charge-Coupled Devices Adv. Image
For a small signal, both a short charge transfer time and a Sensors, May 2003, pp. 149–154.
high potential barrier on the charge transfer path will result [13] S. M. Sze, Physics of Semiconductors, 2nd ed. New York, NY, USA:
in a nonlinear photoresponse, and the reset voltage of the FD Wiley, 1981, pp. 255–258.
[14] I. Inoue, N. Tanaka, H. Yamashita, T. Yamaguchi, H. Ishiwata, and
has almost no effect on the charge transfer, the measurement H. Ihara, “Low leakage current and low operating voltage buried
results of which are consistent with the model prediction. For photodiode for a CMOS imager,” IEEE Trans. Electron Devices, vol. 50,
a large signal, both the model prediction and the measurement no. 1, pp. 43–47, Jan. 2003.
[15] J. Yu, B. Li, P. Yu, J. Xu, and M. Cun, “Two-dimensional pixel image lag
results show that the output level is limited by the reset simulation and optimization in a 4-T CMOS image sensor,” J. Semicond.,
voltage of the FD if the FWC is limited by the FD node, and vol. 31, no. 9, p. 094011, Sep. 2010.
a small slope in the saturation region of the photoresponse [16] B. Mheen, Y.-J. Song, and A. J. P. Theuwissen, “Negative offset
operation of four-transistor CMOS image pixels for increased well
curve is observed. However, the level-3 model predicts that capacity and suppressed dark current,” IEEE Electron Device Lett.,
the photoresponse curves with a different transfer time will vol. 29, no. 4, pp. 347–349, Apr. 2008.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON ELECTRON DEVICES

[17] Z. Cao, Y. Zhou, Q. Li, L. Liu, and N. Wu, “Design of pixel for high Suying Yao (M’11) received the B.E. degree from
speed CMOS image sensors,” in Proc. Int. Image Sensor Workshop, Tianjin University, Tianjin, China, in 1970.
Jun. 2013, pp. 229–232. She is currently a Professor and Ph.D. Candidate
[18] L. Bonjour, N. Blanc, and M. Kayal, “Experimental analysis of lag Supervisor with the School of Electronic Infor-
sources in pinned photodiodes,” IEEE Electron Device Lett., vol. 33, mation and Engineering, Tianjin University, and
no. 12, pp. 1735–1737, Dec. 2012. the Director of the Tianjin University Application
[19] L. Han, S. Yao, J. Xu, C. Xu, and Z. Gao, “Analysis of incomplete Specific Integrated Circuit (ASIC) Design Center.
charge transfer effects in a CMOS image sensor,” J. Semicond., vol. 34, Her current research interests include CMOS image
no. 5, p. 054009, May 2013. sensors, ASICs, and device modeling.
[20] K. Yasutomi, S. Itoh, S. Kawahito, and T. Tamura, “Two-stage charge
transfer pixel using pinned diodes for low-noise global shutter imaging,”
in Proc. Int. Image Sensor Workshop, Jun. 2009, pp. 333–336.
[21] B. Van Zeghbroeck, Principles of Semiconductor Devices. Boulder, CO,
USA: Univ. Colorado, 2004, chs. 2–7. [Online]. Available: http://ece-
www.colorado.edu/~bart/book/
[22] J. Tan, B. Büttgen, and A. J. P. Theuwissen, “Analyzing the radiation
degradation of 4-transistor deep submicron technology CMOS image
sensors,” IEEE Sensors J., vol. 12, no. 6, pp. 2278–2286, Jun. 2012.
[23] V. Goiffon et al., “Pixel level characterization of pinned photodiode and
transfer gate physical parameters in CMOS image sensors,” IEEE J.
Electron Devices Soc., vol. 2, no. 4, pp. 65–76, Jul. 2014.

Liqiang Han (S’13) received the B.E. degree from Albert J. P. Theuwissen (M’82–SM’95–F’02)
the School of Electronic Information Engineering, received the Ph.D. degree in electrical engineering
Tianjin University, Tianjin, China, in 2010, where from the Catholic University of Leuven, Leuven,
he is currently pursuing the Ph.D. degree in micro- Belgium, in 1983.
electronics and solid electronics. He started Harvest Imaging, Bree, Belgium, where
He has been a Visiting Student with the he focuses on consulting, training, and teaching in
Electronic Instrumentation Laboratory, Delft Uni- solid-state imaging technology, after he left DALSA.
versity of Technology, Delft, The Netherlands, He is currently a part-time Professor with the Delft
since Oct. 2014. University of Technology, Delft, The Netherlands.