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7 August 2023 1445 ‫ محرم‬21
ً ‫َو َما أُوتِيت ُ ْم مِ نَ ْالع ِْل ِم إِ اَّل قَل‬

‫ِيل‬
Dr. Hesham Omran
Ain Shams University – Master Micro LLC
Analog IC Design – Cadence Tools & SA

Lab 05
Simple vs Wide Swing (Low Compliance) Cascode Current Mirror
Intended Learning Objectives

In this lab you will:
• Explore current mirror sizing trade-offs using Sizing Assistant (SA).
• Bias a cascode device using a series resistance.
• Design and simulate simple and wide swing (low-voltage) current mirrors.
• Compare simple and low-voltage current mirrors.
NOTE: To get access to the Sizing Assistant (SA) please register at https://adt.master-micro.com/ and
create a support ticket from your dashboard. Verified instructors may also request access to an editable
MS Word version of the labs and the model answers.
NOTE: The values and charts used in the lab document assume the provided 180 nm educational device
models and 1.8 V supply. Other models/technologies can be used by applying reasonable adjustments to
the lab values.
Part 1: Exploring Sizing Tradeoffs Using SA

1) We want to design a simple current mirror with the following specs.
Parameter
Input Current 10𝜇𝐴
Output Current 20𝜇𝐴
% Change in Current for 𝚫𝑽𝒐𝒖𝒕 = 1𝑉 < 10%
Current direction (source/sink) Sink
Answer the following:

2) The % Change in current translates to a spec on the 𝜆 = 1/𝑉𝐴 of the device. How much is the
required 𝜆?
3) Sinking current means which device type? NMOS or PMOS?
4) The higher the 𝑔𝑚 /𝐼𝐷 (the lower the 𝑉 ∗) the higher the headroom (the available swing), but the
larger the area. Examine this trade-off using SA as shown below. Report L and W vs Vstar.
5) Another related tradeoff is the random mismatch, which is inversely proportional to the device area.
Assume Pelgrom’s coefficient for 𝑉𝑇𝐻 random mismatch is 5𝑚𝑉 ⋅ 𝜇𝑚. Plot the % rms (standard
deviation, i.e., sigma) change in current vs Vstar using this expression in SA:
idmis_% = 5m/sqrt(W*L*1e12)*gm/ID*100
➔ ADT Hint: If the LUT contains mismatch data, we can directly use the parameter idmis in SA to
get the standard deviation of the current random variations. The mismatch data can be added to
any LUT using ADT by using an appropriate Monte Carlo mismatch model file.
Page 2 of 6
6) Pick a bias point (Vstar) that gives idmis < 3%. Determine 𝑊 and 𝐿. We will use these sizing
parameters for the cascode current mirror as well.
7) Can we do the previous design trade-offs exploration sweeps using a standard SPICE simulator, i.e.,
sweep Vstar at a constant 𝜆? Why?
Part 2: Current Mirror Simulation

1) Create a new schematic. Construct the circuit shown below. or using the toolbar.
➔ Cadence Hint: You can add labels (names) to nets (wires) using the hotkey “l” and create ports
using the hotkey “p”.
➔ Cadence Hint: You can put the circuit under test in a schematic, create a symbol, then create a
new schematic for the testbench. For design variables (e.g., WN and LN), you can use
pPar(“VariableName”), which passes the variable to the upper level of hierarchy. The variables
will appear when you instantiate the cell in the upper level schematic.
2) The current mirror takes input current IB and generates output current = 2*IB (note the multiplier
setting in the output branch).
3) Instead of using a wide-swing bias transistor (a magic battery) to generate VB, we use a resistor RB in
series with the input branch.
4) Unless otherwise stated, set VOUT = VDD/2 and VMIS1 = VMIS2 = 0.
Page 3 of 6
1. Design and OP (Operating Point) Analysis
1) Assume we want to set a 50𝑚𝑉 saturation margin for M2 and M3, i.e., 𝑉𝐷𝑆2 ≈ 𝑉𝐷𝑆3 ≈ 𝑉 ∗ + 50𝑚𝑉.
Ignore the body effect and calculate a rough value for RB.
𝑉𝐺𝑆4 +𝑉𝐷𝑆2 −𝑉𝐺𝑆2 𝑉𝐷𝑆2
Hint: 𝑅𝐵 = ≈
𝐼𝐵 𝐼𝐵
Hint: The purpose of doing rough analysis is not to reach a final design point, but to calculate a value
that makes sense and can be used to determine a reasonable range for a simulator sweep.
2) Perform DC sweep (not parametric sweep) for RB. Choose a reasonable sweep range given the rough
value computed in the previous step. Report 𝑉𝐷𝑆3 vs 𝑅𝐵 . Choose 𝑅𝐵 to satisfy the 50𝑚𝑉 saturation
margin requirement. Is the selected 𝑅𝐵 value larger or smaller than the rough analytical value?
Why?
➔ Cadence Hint: The DC sweep is performed in a simulator inner loop, so it is very fast and takes
small disk space. The parametric sweep is an outer loop repetitive calling of the simulator, so it is
much slower and takes much larger disk space.
3) Simulate the OP point. Report a snapshot clearly showing the following parameters.
➔ Cadence Hint: You can use Info Balloons (View -> Info Balloons) to show the device parameters.
Use (View -> Annotations -> Setup) to customize the Info Balloons.
➔ Cadence Hint: You can add expressions to the Info Balloons, e.g., Vstar = 2/(gm/ID).
ID
VGS
VDS
VTH
VDSAT
Vstar = 2/(gm/ID)
gm/ID
GM
GDS
GMB
Region
Page 4 of 6
4) Do all transistors operate in saturation?
2. DC Sweep (𝐼𝑜𝑢𝑡 vs VOUT)

1) Perform DC sweep (not parametric sweep) using VOUT = 0:10m:VDD. Report 𝐼𝑜𝑢𝑡 vs VOUT for the
two CMs overlaid in the same plot.
o Comment on the difference between the two circuits.
o From the plot, find an estimate for the compliance voltage of each current mirror.
o 𝐼𝑜𝑢𝑡 of the simple CM is exactly equal to IB*2 at a specific value of VOUT. Why?
2) For the simple current mirror, calculate the percent change in 𝐼𝑜𝑢𝑡 when VOUT changes from 0.5V to
1.5V (i.e., 1V change). Compare the result to the value expected from Part 1.
3) Report the percent of error in 𝐼𝑜𝑢𝑡 vs VOUT (ideal 𝐼𝑜𝑢𝑡 should be IB*2) for the two CMs in the current
mirror operating region (VOUT ≈ 𝑉 ∗to VDD) overlaid in the same plot.
Hint: Calculate percent of error as (simulated – ideal)/ideal * 100
4) Report Rout vs VOUT (take the inverse of the derivative of 𝐼𝑜𝑢𝑡 plot) for the two CMs in the current
mirror operating region (VOUT ≈ 𝑉 ∗to VDD) overlaid in the same plot. Use log scale on the y-axis.
Add a cursor at VOUT = VDD/2.
o Does Rout change with VOUT? Why?
➔ Cadence Hint: Rout can be also simulated using AC analysis. The value we used here should be
the same as the AC analysis result at low frequencies.
5) Analytically calculate Rout of both circuits at VOUT = VDD/2. Compare with simulation results in a
table.
3. Mismatch
NOTE: Practically, we study the mismatch using Monte Carlo simulation. However, since the
educational device model we are using does not include a mismatch model, we will manually add
mismatch in the circuit.
1) Set VMIS1 = 5m/sqrt(W*L) and VMIS2 = 0. This models the standard deviation of the mismatch in
𝑉𝑇𝐻 for the current mirror devices. Run OP simulation. Find the percent change in 𝐼𝑜𝑢𝑡 .
2) Analytically calculate the percent change in 𝐼𝑜𝑢𝑡 and compare it to the simulation result.
Hint: The voltage change at the gate can be considered as a small signal. Thus, the change in the
current can be calculated using the 𝐺𝑚 of the circuit. In this case, the circuit can be considered as a
cascode amplifier.
3) Set VMIS1 = 0 and VMIS2 = 5m/sqrt(W*L). This models the standard deviation of the mismatch in
𝑉𝑇𝐻 for the cascode devices. Run OP simulation. Find the percent change in 𝐼𝑜𝑢𝑡 .
4) Analytically calculate the percent change in 𝐼𝑜𝑢𝑡 and compare it to the simulation result.
Hint: The voltage change at the gate can be considered as a small signal. Thus, the change in the
current can be calculated using the 𝐺𝑚 of the circuit. In this case, the circuit can be considered as a
degenerated common source amplifier.
5) Which mismatch contribution is more pronounced? Why?
6) Which design decision is better: setting the same W and L for the mirror and cascode devices? Or
using larger W and L for the current mirror devices? Why?
Page 5 of 6
Lab Summary
In Part 1 you learned:
• How to use SA to examine current mirror design trade-offs.
• How to design a simple current mirror.
In Part 2 you learned:

• How to design a wide swing (low-voltage) current mirror.
• How the behavior of a simple current mirror changes with the output voltage.
• How the behavior of a low-voltage current mirror changes with the output voltage.
Acknowledgements
Thanks to all who contributed to these labs. Special thanks to Dr. Sameh A. Ibrahim for reviewing and editing
the labs. If you find any errors or have suggestions concerning these labs, please contact
Hesham.omran@eng.asu.edu.eg.
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7 August 2023 1445 ‫ محرم‬21

ً ‫َو َما أُوتِيت ُ ْم مِ نَ ْالع ِْل ِم إِ اَّل قَل‬

Analog IC Design – Cadence Tools & SA

Intended Learning Objectives

Part 1: Exploring Sizing Tradeoffs Using SA

Input Current 10𝜇𝐴

Output Current 20𝜇𝐴

% Change in Current for 𝚫𝑽𝒐𝒖𝒕 = 1𝑉 < 10%

Current direction (source/sink) Sink

Answer the following:

Part 2: Current Mirror Simulation

2. DC Sweep (𝐼𝑜𝑢𝑡 vs VOUT)

In Part 2 you learned:

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