Birzeit University

Faculty of Engineering and Technology

Electrical and Computer Engineering Department
Digital Electronics and Computer Organization Lab
ENCS211

EXP. No. 10. Simple Computer Simulation

10.1 Objectives
In this experiment we are going to design the Verilog HDL control sequence for a simple
computer (SIMCOMP). The SIMCOMP is a very small computer to give the students practice in
the ideas of designing a simple CPU with the Verilog HDL notation.

10.2 Equipment Required

❖ A computer with Quartus II

10.3 Pre Lab

❖ Read the experiment to find the prelab.

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10.4 Theory
10.4.1 Basic Computer Model - Von Neumann Model
Von Neumann computer systems contain three main building blocks: the central
processing unit (CPU), memory, and input/output devices (I/O). These three
components are connected together using the system bus. The most prominent items
within the CPU are the registers: they can be manipulated directly by a computer
program, see Figure 1:
Function of the Von Neumann Component:
Memory: Storage of information (data/program)
Processing Unit: Computation/Processing of Information
Input: Means of getting information into the computer. e.g., keyboard, mouse
Output: Means of getting information out of the computer. e.g., printer, monitor
Control Unit: Makes sure that all the other parts perform their tasks correctly and at
the correct time.

Figure (1): Von Neumann computer systems.

10.4.2 General Registers

1) One of the CPU registers is called as an accumulator AC or 'A' register. It is the
main operand register of the ALU it is used to store the result generated by ALU.

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 2) The data register (MDR) acts as a buffer between the CPU and main memory. It
is used as an input operand register with the accumulator.
3) The instruction register (IR) holds the opcode of the current instruction.
4) The address register (MAR) holds the address of the memory in which the
operand resides.
5) The program counter (PC) holds the address of the next instruction to be
fetched/execution.
Additional addressable registers can be provided for storing operands and address.
This can be viewed as replacing the single accumulator by a set of registers. If the
registers are used for many purposes, the resulting computer is said to have general
register organization. In the case of processor registers, a register is selected by the
multiplexers that form the buses.

10.4.3 Communication Between Memory and Processing Unit

Communication between memory and processing unit consists of two registers:
Memory Address Register (MAR). Memory Data Register (MDR).
To read,
1- The address of the location is put in MAR.
2- The memory is enabled for a read.
3- The value is put in MDR by the memory.
To write,
1- The address of the location is put in MAR.
2- The data is put in MDR.
3- The Write Enable signal is asserted.
4- The value in MDR is written to the location specified.
10.4.4 Generic CPU Instruction Cycle
The generic instruction cycle for an unspecified CPU consists of the following stages:
1) Fetch instruction:
Read instruction code from address in PC and place in IR. (IR ← Memory [PC])
2) Decode instruction:
Hardware determines what the opcode/function is and determines which registers

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 or memory addresses contain the operands.
3) Fetch operands from memory if necessary:
If any operands are memory addresses, initiate memory read cycles to read them
into CPU registers. If an operand is in memory, not a register, then the memory
address of the operand is known as the effective address, or EA for short. The
fetching of an operand can therefore be denoted as Register ← Memory [EA]. On
today's computers, CPUs are much faster than memory, so operand fetching
usually takes multiple CPU clock cycles to complete.
4) Execute:
Perform the function of the instruction. If arithmetic or logic instruction, utilize
the ALU circuits to carry out the operation on data in registers. This is the only
stage of the instruction cycle that is useful from the perspective of the end user.
Everything else is overhead required to make the execute stage happen. One of
the major goals of CPU design is to eliminate overhead and spend a higher
percentage of the time in the execute stage.
5) Store result in memory if necessary:
If destination is a memory address, initiate a memory write cycle to transfer the
result from the CPU to memory. Depending on the situation, the CPU may or may
not have to wait until this operation completes. If the next instruction does not
need to access the memory chip where the result is stored, it can proceed with the
next instruction while the memory unit is carrying out the write operation.
Below is an example of a full instruction cycle which uses memory addresses
for all three operands:
1- Mull product, x, y
2- Fetch the instruction code from Memory [PC]
3- Decode the instruction. This reveals that it's a multiply instruction, and that
the operands are memory locations x, y, and product.
4- Fetch x and y from memory.
5- Multiply x and y, storing the result in a CPU register.
6- Save the result from the CPU to memory location product.

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 10.4.5 Addressing Modes
The term addressing modes refers to the way in which the operand of an instruction is
specified. Information contained in the instruction code is the value of the operand or
the address of the result/operand.

Figure (2): connection between memory and registers.

10.5 Our Simple Computer

SIMCOMP has a two byte-addressable memory with size of 128byte. The memory is
synchronous to the CPU, and the CPU can read or write a word (or cell) in single clock period.
The memory can only be accessed through the memory address register (MAR) and the memory
buffer register (MBR). To read from memory, you use:
- MBR <= Memory [MAR];
And to write to memory, you use:
- Memory [MAR] <= MBR;
1. The CPU has three registers: an accumulator (AC), a program counter (PC) and an
instruction register (IR).
2. The SIMCOMP has only three instructions: Load, Store, and Add.
3. The size of all instructions is 16 bits; all the instructions are single address instructions
and access a word in memory.

Figure (3): Instruction format.

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The opcodes are:

Op-code Instruction Description

Loads the contents of memory location M into the
0011 Load M
accumulator.
Stores the contents of the accumulator in memory location
1011 Store M
M.
Adds the contents of memory location M to the contents of
0111 Add M
the accumulator.
Table 1
Prelab:

1) You must write the basic code shown in Figure 4 at the last page of this experiment in your own
Quartus II file.
2) You have to trace the basic code manually so that you can understand what does the code do. Use
the following table:
Line # Code Description of what is done
6 reg [15:0] Memory [0:63]
7 reg [2:0] state
13 Memory [10] = 16’h3020
14 Memory [11] = 16’h7021
15 Memory [12] = 16’hB014
18 Memory [32] = 16’d7
19 Memory [32] = 16’d7
22 PC = 10; state = 0
29 MAR <= PC
30 state = 1
33 IR <= Memory [MAR]
34 PC <= PC + 1
35 state = 2
38 MAR <= IR [11:0]
39 state = 3
42 state = 4
43 case (IR [15:12])
load: MBR <= Memory
44
[MAR]

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 45 add: MBR <= Memory [MAR]
46 store: MBR <= AC
52 AC <= AC + MBR
56 AC <= MBR
60 Memory [MAR] <= MBR
Table 2

3) You have to summarize the objective of Program#1 above, then repeat for Program #2

10.6 Accumulator Based Simple Computer

The Verilog program described by the following table is shown in Figure 4, study, and simulate
the code.

Instructions
Memory location Instruction assembly Instruction machine code in Hex
10 Load [32] 0011-0000-0010-0000b 16'h3020
11 Add [33] 0111-0000-0010-0001b 16'h7021h
12 Store [20] 1011-0000-0001-0100b 16'hB014h
Data
32 Data 7 Memory [32] 16'h7
33 Data 5 Memory [32] 16'd5
Table 3

Task1: Modify the code to include the jump instruction

Choose any opcode e.g., jump=4'b0001, you have to include the execution of jump which changes
the PC to the specified address in the instruction.
Instructions
Memory location Instruction assembly Instruction machine code in Hex
10 Load [32] 0011-0000-0010-0000b 16'h3020
11 Add [33] 0111-0000-0010-0001b 16'h7021h
12 Store [20] 1011-0000-0001-0100b 16'hB014h
13 Jump 11 0001-0000-0000-1011b 16'hB014h
Data
32 Data 7 Memory [32] 16'h7
33 Data 5 Memory [32] 16'd5
Table 4

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 Task 2: Write the General form of the instruction set for Prog #1
Task 3: Trace the Modified code as was done in the prelab but this time using
the waveforms

10.7 Register Based Simple Computer [SIMCOMP2]

Modify the instruction format so that SIMCOMP can handle four addressing modes and four
registers. This new SIMCOMP2 has four 16-bit general purpose registers, R[0], R[1], R[2] and
R[3] which replace the AC. In Verilog, you declare R as a bank of registers much like we do
Memory.
reg [15:0] R [0:3]; // declaration of registers bank
Since registers are usually on the CPU chip, we have no modeling limitations as we do with
Memory - with Memory we have to use the MAR and MBR registers to access the memory.
Therefore, in a load you could use R as follows:
R [IR [9:8]] <= MBR; //where the 2 bits in the IR specify which R register to set.

Task 4: Modify the four instructions of the old SIMCOMP

The new instruction should follow the new form:
1. LOAD R[i], M loads the contents of memory location M into R[i].
2. STORE R[i], M stores the contents of R[i] in memory location M.
3. ADD R[i], R [j], R[k] adds contents of R[j] and R[k] and places result inR[i].
To test your SIMCOMP2 design, perform the following program where:
1. PC starts at 10,
2. Suppose IR [9:8] is used to specify the register number.
3. In the “add instruction” IR [11:10] destination register, IR [9:8], IR [7:6] source1,
source2 respectively.

Instructions
Memory Destination Source
Instruction Instruction set code in binary in Hex
location register Register/Memory
10 Load R1 3 0011-0001-0000-0011b 16'h3103
11 Load R2 4 0011-0010-0000-0100b 16'h3204
12 Add R1 R1, R2 0111-0101-1000-0000b 16'h7580
13 Store R1 5 1011-0001-0000-0101b 16'hB105

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 Data
3 Data A Memory [3] 16'hA
4 Data 6 Memory [4] 16'd6
Table 5

Task 5: Write the General form of the instruction set for SIMCOMP2.
Task 6: Trace SIMCOMP2 code using the waveforms.
Task 7: Add immediate addressing to the SIMCOMP2:
If bit (IR [11]) is a one in a Load, the last eight bits are not an address but an operand. The
operand is in the range -128 to 127.
If immediate addressing is used in a LOAD, the operand is loaded into the register.
Load R1, 8
R1 ← 8
Simulate the following test with handwritten comments explaining what you are doing.
PC = 10
Memory [10]: Load R1,3 // Load immediate
Memory [11]: Load R2, -4 //Use 2's complement to represent (-4) Memory [12] Add R1, R1, R1
Memory [13]: Store R1,5

Instructions
Memory Destination Source
Instruction Instruction set code in binary in Hex
location register Register/Memory
Load
10 R1 3 0011-1001-0000-0011b 16'h3903
Immediate
Load
11 R2 -4 0011-1010-1111-1100b 16'h3AFC
Immediate
12 Add R1 R1, R2 0111-0101-1000-0000b 16'h7580
13 Store R1 5 1011-0001-0000-0101b 16'hB105
Data
3 Data A Memory [3] 16'hA
4 Data 6 Memory [4] 16'd6
Table 6

Hint: How to read the 2's complement (8 bit) in Verilog:

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 MBR <= - (~ (IR [7:0]) + 1)
Task 8: Write the General form of the instruction set for Prog #2 with
immediate load

Figure (4): Basic code.

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 At the end of this experiment, you should have two files:
1- An Accumulator Based Simple Computer with 4 instructions as in program 1.
2- A register based simple computer with 3 opcodes (noting that the load opcode can be
immediate or normal) as in program 2.

10.8 Post Lab

1. Modify Program #2 so that it finds the sum of three elements and then traces the
process (using waveform).

2. Modify the program in the first part of the post-lab to include the jump instruction
with opcode (jump=4'b1001) and change code to run this code below. (Write the
instruction format)

3. Modify the previous program making it sum 10 elements using a jump (loop)
opcode to sum the 10 elements.

Instructions
Memory Destination Source
Instruction Instruction set code in binary in Hex
location register Register/Memory
10 Load R1 3
11 Load R2 4
12 Load R3 -9
13 Add R1 R1, R2, R3
14 Store R1 5
Table 7

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