Lec 4

Embedded
System Design
Lecture-4
Dr. Nalin Kumar Sharma

Objectives of this lecture
• ARM Architecture
1. Buses
2. Memory
3. Peripherals
4. Software
So far in ESD
• What is ESD?
• Design aspects of ESD
• Architecture of general-purpose microprocessor
• Microprocessors vs Micro-controllers
• Operation of an instruction
Recap: Four major design rules of
ARM
• Instruction
• Pipeline
• Register
• Load-store architecture
Benefit of more Stages in
pipeline?
• Non pipelined system takes 130ns to process an instruction . A
program of 1000 instructions is executed in non pipelined
system. Then same program is processed with processor with 5
segment pipeline with clock cycle of 30 ns/stage.
Determine speed up ratio of pipeline.

Stages, Clock and Latches
ARM-based embedded microcontroller
• AHB Arbiter arbitrates for the AHB bus

among as many as four AHB master
components.
• The AHB to APB bridge is an AHB slave,
providing an interface between the high-
speed AHB and the low-power APB
Bus technology in embedded systems
• ES use an on-chip bus that is internal to the chip.
• There are two different classes of devices attached to the bus.
• The ARM processor core is a bus master—a logical device capable
of initiating a data transfer with another device across the same bus.
• Peripherals tend to be bus slaves—logical devices capable only of
responding to a transfer request from a bus master device.
AMBA Bus Protocol
• Advanced Microcontroller Bus Architecture (AMBA) was introduced in

1996. The major buses in this architectures are:
1. ARM High Performance Bus (AHB): Bus for High-speed peripheral
components, such as external memory.
2. ARM Peripheral Bus (APB): Bus for slow-speed peripheral
components, such as counters/times.
Memory
Memory: Hierarchy
• The cache is placed between main memory and the core. It is used to speed
up data transfer between the processor and main memory.
• A cache provides an overall increase in performance but with a loss of
predictable execution time. Note that many small embedded systems do not
require the performance benefits of a cache.
• The main memory is large and is generally stored in separate chips. Load and
store instructions access the main memory unless the values have been stored
in the cache for fast access.
• Secondary storage is the largest and slowest form of memory. Hard disk drives
are examples of secondary storage.
Memory: Width
• The memory width is the number of bits the memory returns on
each access—typically 8, 16, 32, or 64 bits.
• The memory width has a direct effect on the overall performance
and cost ratio.
• If you have an uncached system using 32-bit ARM instructions and
16-bit-wide memory chips, then the processor will have to make two
memory fetches per instruction.
• Each fetch requires two 16-bit loads. This obviously has the effect
of reducing system performance, but the benefit is that 16-bit
memory is less expensive.
Memory Types: ROM
• Read-only memory (ROM) is the least flexible of all memory

types because it contains an image that is permanently set
at production time and cannot be reprogrammed.
• ROMs are used in high-volume devices that require no
updates or corrections.
• Many devices also use a ROM to hold boot code.
Memory Types: Flash ROM
• Flash ROM can be written to as well as read, but it is slow to write

so one shouldn’t use it for holding dynamic data.
• Its main use is for holding the device firmware or storing longterm
data that needs to be preserved after power is off.
• The erasing and writing of flash ROM are completely software
controlled with no additional hardware circuity required, which
reduces the manufacturing costs.
• Flash ROM has become the most popular of the read-only
memory.
Memory Types: DRAM
• Dynamic random access memory (DRAM) is the most

commonly used RAM for devices.
• It has the lowest cost per megabyte compared with other
types of RAM.
• DRAM is dynamic— it needs to have its storage cells
refreshed and given a new electronic charge every few
milliseconds.
Memory Types: SRAM
• Static random access memory (SRAM) is faster than the more

traditional DRAM, but requires more silicon area.
• SRAM is static—the RAM does not require refreshing.
• The access time for SRAM is considerably shorter than the
equivalent DRAM because SRAM does not require a pause
between data accesses.
• Because of its higher cost, it is used mostly for smaller
high-speed tasks, such as fast memory and caches.
Memory Types: SDRAM
• Synchronous dynamic random access memory (SDRAM) is a

subcategory of DRAM.
• It can run at much higher clock speeds than conventional memory.
• SDRAM synchronizes itself with the processor bus because it is
clocked.
• Internally the data is fetched from memory cells, pipelined, and finally
brought out on the bus in a burst.
• The old-style DRAM is asynchronous, so does not burst as efficiently as
SDRAM.
Thanks

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Embedded

Dr. Nalin Kumar Sharma

Determine speed up ratio of pipeline.

• AHB Arbiter arbitrates for the AHB bus

• Advanced Microcontroller Bus Architecture (AMBA) was introduced in

• Read-only memory (ROM) is the least flexible of all memory

• Flash ROM can be written to as well as read, but it is slow to write

• Dynamic random access memory (DRAM) is the most

• Static random access memory (SRAM) is faster than the more

• Synchronous dynamic random access memory (SDRAM) is a

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