Scribd Logo
Upload

Welcome to Scribd!

  • 7 views

    Lec 6

    Uploaded by

    Prateek Goyal
    The document discusses ARM registers including the classification of registers, the current processor status register (CPSR), saved processor status register (SPSR), and general purpose registers. It describes that ARM has 37 registers which are 32-bit and can be classified into dedicated program counter, current program status, saved program status, and general purpose registers. It provides details on the fields and functions of CPSR and SPSR registers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Lec 6

    Uploaded by

    Prateek Goyal
    7 views15 pages
    The document discusses ARM registers including the classification of registers, the current processor status register (CPSR), saved processor status register (SPSR), and general purpose registers. It describes that ARM has 37 registers which are 32-bit and can be classified into dedicated program counter, current program status, saved program status, and general purpose registers. It provides details on the fields and functions of CPSR and SPSR registers.

    Original Title

    Lec-6

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document discusses ARM registers including the classification of registers, the current processor status register (CPSR), saved processor status register (SPSR), and general purpose registers. It describes that ARM has 37 registers which are 32-bit and can be classified into dedicated program counter, current program status, saved program status, and general purpose registers. It provides details on the fields and functions of CPSR and SPSR registers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    7 views15 pages

    Lec 6

    Uploaded by

    Prateek Goyal
    The document discusses ARM registers including the classification of registers, the current processor status register (CPSR), saved processor status register (SPSR), and general purpose registers. It describes that ARM has 37 registers which are 32-bit and can be classified into dedicated program counter, current program status, saved program status, and general purpose registers. It provides details on the fields and functions of CPSR and SPSR registers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 15

    Lecture-6

    EMBEDDED SYSTEM DESIGN


    DR. NALIN KUMAR SHARMA
    OBJECTIVE OF THE LECTURE

    • ARM registers
    SO FAR

    • Embedded System Design: Introduction


    • ARM architecture: Introduction
    REGISTERS

    • Registers are used to save data for the processing.


    • The data may be an instruction to execute or a data item.
    • The ARM processor uses a load-store architecture. Load instructions copy data from
    memory to registers in the core, and the store instructions copy data from registers to
    memory.
    • Data processing is carried out solely in registers.
    REGISTERS CLASSIFICATIONS

    • ARM has 37 registers.


    • All the registers are 32 bit long.
    • These registers are can be classified as :
    • 1- dedicated programme counter
    • 1-dedicated current program status register
    • 5-dedicated saved program status register
    • 30-general purpose registers
    The processor can operate in seven different modes
    CPSR ( CURRENT PROCESSOR STATUS
    REGISTER )
    • It contains the current status of the
    processor.
    • This includes:
    1. Conditional code flags, such as
    • N – Negative result from ALU.
    • Z – Zero result from ALU.
    • C – ALU operation Carry out.
    • V – ALU operation overflowed.
    CPSR ( CURRENT PROCESSOR STATUS
    REGISTER )
    2. Status
    3. Exception
    4. Control
    • I bit disables IRQ.
    • F bit disables FIQ.
    • T bit – indicates whether the core is in
    Thumb state.
    • M[4:0] – specifies the processor mode
    MODES AND ADDRESSES
    SPSR ( SAVED PROCESSOR STATUS REGISTER
    )
    • In the exception modes there is an additional Saved Processor
    Status register (SPSR) which holds information on the processor’s
    state before the system changed into this mode i.e. the processor
    status just before an exception.
    GENERAL-PURPOSE REGISTERS

    • It holds either data or an address.


    • They are identified with the letter r prefixed to the
    register number. For example, register 4 is given the
    label r4.
    • There are 16 data registers visible to the programmer
    as r0 to r15.
    GENERAL-PURPOSE REGISTERS

    • The ARM processor contains three registers: r13, r14, and r15, each of which is
    allocated to a specific duty or unique function.
    • Register 13 is traditionally used as the stack pointer (SP) and stores the head of
    the stack in the current processor mode.
    • Register r14 is called the link register (LR) and is where the core puts the return
    address whenever it calls a subroutine.
    • Register 15 is the program counter (PC) and contains the address of the next
    instruction to be fetched by the processor.
    CHANGING MODES

    You might also like