The document discusses different types of addressing modes used in computer architectures. It describes immediate, direct, indirect, register, register indirect, displacement (indexed), and stack addressing modes. Each mode trades off between addressing flexibility, memory references, and complexity. Different architectures use different subsets of these addressing modes depending on their design. The document also specifically outlines the various addressing modes supported by Intel x86 processors.
The document discusses different types of addressing modes used in computer architectures. It describes immediate, direct, indirect, register, register indirect, displacement (indexed), and stack addressing modes. Each mode trades off between addressing flexibility, memory references, and complexity. Different architectures use different subsets of these addressing modes depending on their design. The document also specifically outlines the various addressing modes supported by Intel x86 processors.
The document discusses different types of addressing modes used in computer architectures. It describes immediate, direct, indirect, register, register indirect, displacement (indexed), and stack addressing modes. Each mode trades off between addressing flexibility, memory references, and complexity. Different architectures use different subsets of these addressing modes depending on their design. The document also specifically outlines the various addressing modes supported by Intel x86 processors.
The document discusses different types of addressing modes used in computer architectures. It describes immediate, direct, indirect, register, register indirect, displacement (indexed), and stack addressing modes. Each mode trades off between addressing flexibility, memory references, and complexity. Different architectures use different subsets of these addressing modes depending on their design. The document also specifically outlines the various addressing modes supported by Intel x86 processors.
Reference: Computer Organization and Architecture by William Stallings 8th Edition Addressing Modes • How the operands are specified in an instruction • The trade-off deals with —Address range and/or addressing flexibility —number of memory references —complexity in address calculation
Different architectures use different addressing modes
• Operand = address field • e.g. ADD 5 —Add 5 to contents of accumulator —5 is an operand • No memory reference to fetch data Immediate Addressing
• Operand is part of instruction
• Operand = address field • e.g. ADD 5 —Add 5 to contents of accumulator —5 is an operand • No memory reference to fetch data • Fast • Limited range of values Direct Addressing
• Address field contains address of operand
• Effective address (EA) = operand value • e.g. ADD Addr —Add contents of cell Addr to accumulator —Look in memory at address Addr for operand Direct Addressing
• Address field contains address of operand
• Effective address (EA) = operand value • e.g. ADD Addr —Add contents of cell Addr to accumulator —Look in memory at address Addr for operand • Single memory reference to access data • No additional calculations to work out effective address • Limited address space Direct Addressing Diagram
Instruction Opcode Address A Memory
Operand Indirect Addressing • Memory cell pointed to by the address field of instruction contains the address of the operand • EA = (A) —Look in A, find address (A) and look there for operand • e.g. ADD (A) —Add contents of cell pointed by the contents of A to accumulator Indirect Addressing contd.
• Large address space
• May be nested, multilevel, cascaded —e.g. EA = (((A))) • Multiple memory accesses to find operand • Slower Indirect Addressing Diagram
Instruction Opcode Address A Memory
Pointer to operand
Operand Register Addressing
• Operand is held in register named in
address filed • EA = R Register Addressing contd.
• Similar to Direct addressing
• No memory access • Very fast execution • Very limited address space (register options) Register Addressing Diagram Instruction Opcode Register Address R Registers
Operand Register Indirect Addressing
• Similar to indirect addressing
• EA = (R) • Operand is in memory cell pointed to by contents of register R Register Indirect Addressing
• Similar to indirect addressing
• EA = (R) • Operand is in memory cell pointed to by contents of register R • Large address space • One fewer memory access than indirect addressing Register Indirect Addressing Diagram
Instruction Opcode Register Address R Memory
Registers
Pointer to Operand Operand
Displacement Addressing
• EA = A + (R) • Address field holds two values —A = base value —R = register that holds displacement —or vice versa
• R = Program counter, PC • EA = A + (PC) • i.e. get operand from A cells from current location pointed to by PC Indexed Addressing • A = base • R = displacement • EA = A + R • Then, increments (or decrements) R • Good for accessing arrays —EA = A + R —R++ Stack Addressing
• Operand is (implicitly) on top of stack
• e.g. —ADD Pop top two items from stack and add Intel x86 Addressing Modes • Virtual or effective address is offset into segment — Starting address plus offset gives linear address — This goes through page translation if paging is enabled • Addressing modes available — Immediate — Register operand — Displacement — Base — Base with displacement — Scaled index with displacement — Base with index and displacement — Base scaled index with displacement — Relative Intel x86 Addressing Modes Intel x86 Addressing Modes
Mode Algorithm Immediate Operand = A Register Operand LA = R Displacement LA = (SR) + A Base LA = (SR) + (B) Base with Displacement LA = (SR) + (B) + A Scaled Index with Displacement LA = (SR) + (I) ´ S + A Base with Index and Displacement LA = (SR) + (B) + (I) + A Base with Scaled Index and Displacement LA = (SR) + (I) ´ S + (B) + A Relative LA = (PC) + A
LA = linear address (X) = contents of X SR = segment register PC = program counter A = contents of an address field in the instruction R = register B = base register I = index register S = scaling factor
