‫قسم البرامج الفنيه ( القوي و التكييف )‬

‫‪UPS and Inverters‬‬

‫‪TS03PW16En‬‬
UPS&Inverter

UPS&Inverter

Aim of study

By the end of this course, the trainee should be acquainted with:

– UPS Theory and operations

– Free scale Semiconductor’s Solution
– Advantages and Features of Freescale’s Controller
– Online UPS Theory and Description
– Control Loops In The Online UPS
– Program Loop Timing
– Battery Charger Control Loop
– Rectifier Soft Start Routine

Contents Pages

1.1 Introduction 2
1.2 Freescale Semiconductor’s Solution 2
1.3 Advantages and Features of Freescale’s Controller 5
1.4 Online UPS Theory and Description 8
1.5 Control Loops In The Online UPS 36
1.6 Battery Temperature Reading 47
1.7 Program Loop Timing 48
1.8 Inverter Control Loop 49
1.9 PFC Control Loop 51
1.10 Battery Booster Control Loop 52
1.11 Battery Charger Control Loop 53
1.12 Rectifier Soft Start Routine 54

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UPS&Inverter

1.1 Introduction

The main purpose of an Uninterruptible Power Supply (UPS) is to provide

clean and stable power to a load, regardless of power grid conditions such as
black-outs. Uninterruptible Power Supplies have been widely used for office
equipment, computers, communication systems, medical/life support and many
other critical systems. Recent market requirements include a target expectation
for UPS reliability of 99.999% power availability, performance demands of
zero switch over time, and complex network connectivity and control methods,
such as Simple Network Management Protocol (SNMP).

Presently, a UPS is often implemented with an MCU. But MCUs have

significant price/performance limitations that can be rectified by implementing
the UPS using a hybrid MCU with efficient digital signal processing capability.
This has not been possible until recently, due to performance and the cost of
the processors required to do the job. The 56F8300 series of digital signal
controllers has the required performance, peripherals, and price targets to
enable UPS designs to implement advanced features..

1.2 Freescale Semiconductor’s Solution

The digital 56800/E network-enabled high-performance UPS reduces system

component count, increases system reliability, and enables advanced functions
while reducing cost. Key advantages of this digitally-controlled UPS include:
• Single-device solution which combines MCU functionality and DSP
processing power.
• Bidirectional AC/DC conversion.
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• High input power factor with Direct PFC and lower power pollution to
the power grid.
• Extended battery life and lower maintenance costs.
• Power source and load conditioning can be monitored in real time.
• Network communication for remote control and monitoring.
• Expedites time-to-market using out-of-the-box software components.
The functional blocks of the on-line triple conversion UPS are shown in
Figure 1.

Figure1 on-line Triple Conversion UPS Block Diagram

During normal operation, the AC input voltage is rectified by an AC/DC

converter that rectifies the input voltage and regulates the input power factor.
The output of the AC/DC converter is a DCBus voltage that is used as the
source for both the battery charger and DC/AC inverter. The battery charger is

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a boost/buck DC/DC converter. When the system is charging the batteries, the
DC/DC converter works in buck mode, which steps the high DCBus voltage
down to the batteries’ acceptable voltage level and charges the batteries. When
the battery pack is fully charged, the converter switches to stand-by mode. If an
input power failure occurs, the DC/DC converter works in boost mode, which
supplies power to the DCBus from the batteries. The DC/AC inverter is used to
convert the DC voltage to approximated sinusoidal output voltage pulses. The
pulse string is input to an LC filter, which generates a true sinusoidal output
voltage that is supplied to the load. The user can select the frequency of the
sinusoidal output voltage and the frequency can either be synchronized to the
input voltage frequency or any other desired independent stable frequency.

When any failures or faults are generated or maintenance is needed in the UPS
system, the bypass switch will be engaged, which turns the UPS system off and
connects the load directly to the input power source. All necessary control
functions are implemented within the controller, such as:
• Power on/off control
• DCBus voltage regulation
• Input power factor correction
• Battery management
• AC output voltage regulation
• Frequency synchronization of input and output
• Power source monitoring
• System self diagnostics and self protection
• Emergency event processing
• Real-time multi-tasking system operation
• Communication protocols

1.3 Advantages and Features of Freescale’s Controller

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The Freescale 56F8300 (56800E core) family is well suited for UPS design,
combining the DSP’s calculation capability with an MCU’s controller features
on a single chip. These controllers offer many dedicated peripherals, including
Pulse Width Modulation (PWM) units, Analog-to-Digital Converters (ADC),
timers, communication peripherals (SCI, SPI, CAN), on-board Flash and
RAM. Generally, all the family members are appropriate for use in UPS
design.

The following section uses a specific device to describe the family’s features.

1.3.1 56F8346, 56800E Core Family

The 56F8346 provides the following peripheral blocks:

• Two Pulse Width Modulator units (PWMA and PWMB), each with six
PWM outputs, three Current Sense inputs, and three Fault inputs for
PWMA/PWMB; fault-tolerant design with dead time insertion,
supporting both center-aligned and edge-aligned modes
• Two 12-bit Analog-to-Digital Converters (ADCs), supporting two
simultaneous conversions with dual 4-pin multiplexed inputs; the ADC
can be synchronized by PWM modules
• Two Quadrature Decoders (Quad Dec0 and Quad Dec1), each with four
inputs, or two additional Quad Timers, A & B
• Two dedicated general purpose Quad Timers totaling three pins: Timer C,
with one pin and Timer D, with two pins
• CAN 2.0 B-compatible module with 2-pin ports used to transmit and
receive.
• Two Serial Communication Interfaces (SCI0 and SCI1), each with two
pins, or four additional GPIO lines.

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• Serial Peripheral Interface (SPI), with a configurable 4-pin port, or four

additional GPIO lines.
• Computer Operating Properly (COP) / Watchdog timer.
• Two dedicated external interrupt pins.
• 61 multiplexed General Purpose I/O (GPIO) pins.
• External reset pin for hardware reset.
• JTAG/On-Chip Emulation (OnCE).
• Software-programmable, Phase Lock Loop-based frequency synthesizer
for the controller core clock.
• Temperature Sensor system.

1.3.2 Peripheral Description

PWM modules are the controller’s key features enabling UPS control. Each
PWM is double-buffered and includes interrupt controls. The PWM module
provides a reference output to synchronize the Analog-to-Digital Converters.
The PWM has the following features:
•Three complementary PWM signal pairs, or six independent PWM signals
• Features of complementary channel operation
• Dead time insertion
• Separate top and bottom pulse width correction via current status inputs
or software
• Separate top and bottom polarity control
• Edge-aligned or center-aligned PWM signals
• 15-bit resolution
• Half-cycle reload capability
• Integral reload rates from 1 to 16
• Individual software-controlled PWM outputs
• Mask and swap of PWM outputs

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• Programmable fault protection

• Polarity control
• 20mA current sink capability on PWM pins
• Write-protectable registers
The UPS utilizes the PWM block set in the complementary PWM mode,
permitting generation of control signals for all switches of the power stage
with dead time insertion.

The Analog-to-Digital Converter (ADC) consists of a digital control

module and two analog Sample and Hold (S/H) circuits. The ADC features:
• 12-bit resolution
• Maximum ADC clock frequency is 5MHz with 200ns period
• Single conversion time of 8.5 ADC clock cycles (8.5 x 200ns = 1.7µs)
• Additional conversion time of 6 ADC clock cycles (6 x 200ns = 1.2µs)
• Eight conversions in 26.5 ADC clock cycles (26.5 x 200ns = 5.3µs) using
simultaneous mode
• ADC can be synchronized to the PWM via the sync signal
• Simultaneous or sequential sampling
• Internal multiplexer to select two of eight inputs
• Ability to sequentially scan and store up to eight measurements
• Ability to simultaneously sample and hold two inputs
• Optional interrupts at end of scan, if an out-of-range limit is exceeded, or
at zero crossing
• Optional sample correction by subtracting a preprogrammed offset value
• Signed or unsigned result
• Single-ended or differential inputs The Quad Timer is an extremely
flexible module, providing all required services relating to time events. It
has the following features:
• Each timer module consists of four 16-bit counters/timers

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• Counts up/down
• Counters are cascadable
• Programmable count modulo
• Maximum count rate equals peripheral clock/2 when counting external
events
• Maximum count rate equals peripheral clock when using internal clocks
• Counts once or repeatedly
• Counters are preloadable
• Counters can share available input pins
• Each counter has a separate prescaler
• Each counter has capture and compare capability

1.4 Online UPS Theory and Description

1.4.1 Introduction

Uninterruptible Power Supplies (UPS) are electronic devices designed to

provide power to critical mission systems.
An Online UPS (OUPS) provides continuous power to the load during power
outage or glitches caused by power source switching.

1.4.1.1 The Concept of an Online UPS

The minimum components needed to design an Online UPS are the rectifier,
the battery bank and the inverter. The rectifier converts the distribution line’s
AC (Alternating Current) power to DC (Direct Current) power, The Form of
current suitable to store energy in a battery bank. At all times, this DC is also
fed to an inverter, which reconverts the DC power to an AC waveform
connected to any equipment utilizing AC that a user considers as mission

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critical. If the AC supply fails for any reason, the inverter will continue to draw
power from the batteries.

Figure2 A Basic Online UPS

1.4.1.2 Input Power Factor Control (PFC)

When a sinusoidal input signal is connected to a full wave rectifier, conduction

will occur only during the peaks of the signal. This causes a two-fold
inconvenience to the electricity distribution line:
• Insertion of harmonics to the lines
• High current peaks, which imply greater losses on the distribution.
These effects are aggravated by the long distances the electric
distribution networks usually span. From the electrical utility’s point of
view, the best possible load is the pure resistive: The current waveform
should be a pure sinusoidal waveform identical to the voltage
waveform and of the same frequency and phase. In order to show a
resistive load to the utility lines, the input current to the UPS is
controlled (i.e., modulated) to make it match a set point.
This set point depends on the input voltage waveform, and its
amplitude is dependent on the equipment’s power consumption.

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1.4.1.3 DC/DC Converters

If a rectifier is connected to the AC line supply, then the DC voltage will be

equal to the peak voltage of the line. (i.e., in a 120 VRMS line, the peak will be
120•ã2, 170V). If the battery bank is configured for 12 or 24 VDC, the UPS
works by using DC/DC converters.

For an online UPS, two power DC/DC converters are required. One converter
operates as the battery charger, and the other boosts the battery voltage in the
absence of line input and generates the appropriate DC required by the inverter.

Figure3 Prototype UPS

1.4.2 System Actuators

A simplified schematic of the controller’s relationship with actuators is shown

in Figure 4 where all switches represent MOSFETs or IGBTs.

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Figure 4. Relationship between a 56800E and Power Actuators

Figure 5. Simplified Schematic Diagram of the UPS

1.4.3 Input Rectifier Theory of Operation

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The input rectifier is implemented as a four-diode bridge (X1, X2, D24, and
D23). A soft start system implemented with SCRs can prevent a huge in-rush
current when the system starts, while the system’s internal capacitors get
charged to the line’s peak voltage.

Figure6 Input Rectifier

1.4.3.1 Rectifier Soft Start

If a high voltage is applied to a discharged capacitor, its low impedance will
result in a very high inrush current across the circuit, reducing the components’
longevity. A soft start circuit is designed to avoid that circumstance. Figure 7
shows a full wave-controlled rectifier bridge.

If the trigger angle of X1 and X2 is gradually decreased from the zero crossing
towards the peak voltage, as demonstrated in Figure 8, the capacitor voltage
will then increase slowly. As the current on a capacitor equals the capacitance
value times the voltage derivative with respect to time, the input current will be
proportional to the slope of the voltage applied to the capacitor.

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Figure 7. Full Wave-Controlled Rectifier Bridge

Figure8 Relationship between Rectifier Soft Start Operation / Actuator Signals and the AC
Main Line Voltage

1.4.4 Power Factor Corrector (PFC) Theory of Operation

After the rectifier soft start finishes, X1 and X2 must act as diodes with
continuous triggers. When no PFC is implemented, the line current will be
similar to that shown in Figure 9, due to the diode–capacitor nature of a
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rectifier.

The objective of the PFC circuit is to simulate a resistive load to the power
line; in other words, to obtain a unity power factor and low harmonic content in
the current waveform. A fast control must be

implemented in order to make the current waveform follow the AC voltage,

while elevating and controlling the rail voltage and supplying the average
power required to the load. Figure 10 shows how the PFC works, illustrating a
current signal waveform similar in form to the voltage waveform. The ripple in
the figure is a consequence of the IGBT high frequency switching.

Figure 9 Typical Rectifier Current vs. AC Line Voltage

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Figure10. PFC Current and Voltage Waveforms

Once the voltage on capacitors C3, C7, and C8, shown in Figure 11, reach the
AC main supply peak after the rectifier soft start, the PFC is turned on,
correcting the power factor presented to the line and generating the rail DC
voltages VP and VN at a value higher than the line peak.

Figure11 PFC Schematic

In order to work as a PFC, U1 and U2 in Figure 11 turn on and off in

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complementary mode. When U1 is on, U2 is off, and vice versa. The

switching frequency of operation is 20 kHz. The line nominal frequencies are

50Hz or 60Hz, so it is a valid approximation to consider the line voltage as a
constant during a switching period. For positive values of the line, when U2 is
on (closed) and U1 is off (open), the circuit reduces to that shown in Figure12,
where C3 is connected in parallel to C8, causing the voltages on these
capacitors to be the same, thus reducing the ripple voltage on C8.

Figure 12 Partial PFC Schematic when U1 Is Open and U2 Is Closed

For positive values of the line, when U1 is closed and U2 is open, the circuit
reduces as shown in Figure 13. C3 is now connected in parallel to C7, thus
reducing its ripple voltage. The line is applied directly to L1, increasing the
current across it with a constant slope, because line voltage could be
considered constant, and the inductor current, which corresponds to the current
in the line (ILINE), depends on the voltage across its terminals.

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Figure 13 Partial PFC Schematic when U1 Is Closed and U2 Is Open

Inductor current is calculated by the equation:

Where:
VL1 is the voltage across the inductor terminals
The peak current across the inductor at time t2 depends, among other factors,
on the instant value of the line voltage and the time difference t2 – t1, which is
the time that U1 remains closed.

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Figure 14 Resulting Parallel Connection between C3 and C7

The voltage-boosting characteristic of the PFC is accomplished by increasing

the voltage across C3 (and consequently, across C7 and C8). Given that a
current is circulating in the inductor L1, when U1 opens, the voltage across L1
adds to the line voltage as shown in Figure 15. This forces D24 into a
conduction state and C3 and C8 to charge to the addition of the line and the
inductor terminal voltage, VL1. This is a typical boost configuration.

Figure 15 Voltage Boost across Capacitors C3 and C8

Due to symmetry, this circuit works in the same way for negative values in line
voltage.
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1.4.5 Battery Charger Theory of Operation

Figure 16 has been extracted from the UPS schematic shown in Figure 5. Using
the high DC voltages VPrail positive and VN rail negative as its power sources,
this circuit provides the charge conditions for a battery bank formed by two
12V batteries connected in series, which must be charged with constant
current. When the float condition is reached, the charger must preserve a
constant voltage while providing the battery bank’s self-discharge current.

Figure 16 Battery Charger Schematic

The battery charger is an application of a two-transistor fly back configuration

using a coupling inductor rather than a transformer. Because this operating
mode implies no flow of current in the secondary when the primary has a non-
zero current, and vice versa, it means that no current flows simultaneously in
both windings.
Figure 16 shows a two-transistor version of a fly back converter, where U5 and
U6 are simultaneously turned on and off. The advantage of such a topology

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over a single-transistor fly back converter is that the switches’ voltage rating is
VP - VN. Moreover, since a current path exists through the diodes D18 and
D19, which are connected to the primary winding, a dissipative snubber across
the primary winding is not needed to dissipate the energy associated with the
transformer primary-winding leakage inductance. The design, calculations and
construction of TX1 are critical in order to prevent the reflected voltage from
secondary to primary ising higher than VP - VN when D22 is on.

1.4.6 Battery Booster Theory of Operation

The battery booster is a DC/DC converter and transforms the battery voltage of
24VDC to the required differential 440VDC between rails. The rails are
symmetric, implying VP = 220VDC at the positive rail, and VN = -220VDC at
the negative rail, as shown in Figure 17.
Although the topology of Figure 17 is usually called “booster” because its
output voltage is higher than input voltage, it is actually a push-pull converter
with an arrangement of two forward converters working alternatively and a
transformer to increase the output voltage

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Figure 17 Battery Booster Schematic

The switches U9 and U10 cannot be closed at the same time. Typical drive
signals are illustrated in Figure 18.

Figure 18 Drive Signals for Battery Booster Switches

Using a control signal like the one shown in Figure 18, the waveforms at the
transformer secondary over L10 and L9 are illustrated with positive and

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negative values of voltage in Figure 19.

Figure 19 Signals at Transformer Secondary Windings L10 and L9

C9 remains charged to VBAT and is added because the coupling factor is not
equal to one, implying that a leakage inductor must be considered. C9 acts as a
snubber, creating a current path to avoid an controlled voltage peak at the
primary windings of the transformer.
The four diodes D25, D26, D27 and D28 form a conventional full-wave
rectifier bridge and generate only positive values in the cathodes of D25 and
D27 and negative values at the anodes of D26 and D28, as shown in Figure 20.

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Figure 20 Signals at the Cathode of D25 and Anode of D26

The objective of DC/DC converters is to generate a DC voltage. In order to

filter any undesirable AC components, two LC filters are added:
• L7 - C7 for the negative rail
• L6 - C8 for the positive rail

1.4.7 Inverter Theory of Operation

Figure 21 Inverter Schematic Diagram

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The chosen inverter configuration is a half-bridge monophasic circuit. It must

generate a low-distortion sinusoidal waveform in the output terminals from the
VP and VN DC rail voltages. To produce such a signal, VP and VN must be
higher than the AC positive and negative peak voltages, respectively.
Consider a switching period of T seconds. Assume that U8 is closed during TP
seconds, while U7 is open.
During the remaining T – TP seconds, U7 is closed and U8 open. If the cutoff
frequency of the low-pass filter composed by inductor L5 and C6 is low
enough to reject the 1/T Hz switching frequency, then the output approximates
to:

Where:
tp/T is the duty cycle of the control signal
The expression simplifies to:

As 1/T = 20kHz is much higher than 50Hz or 60Hz, then the output voltage
will result proportional to TP, and the sinusoidal signal can be considered
constant during T seconds.

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1.4.8 Pulse Width Modulation

If a sinusoidal reference signal is compared to a symmetric triangle wave, the
resulting signal is pulse width modulated, as shown in Figure 22. The triangle
waveform frequency corresponds to the PWM switching frequency.

Figure 22 Generation of a PWM Signal

1.4.9 Auxiliary Circuits

Additional circuits are required to make the complete system operational and
include:
• Power supplies
• Signal sensing circuitry
• Limiters
• Isolation circuits
• Driver circuits for SCRs, NMOSFETs and IGBTs

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1.4.9.1 Power Supplies and Isolation Circuitry

This system requires multiple power supplies with floating references. The
typical configuration is shown in Figure 23, and consists of a fly back
converter similar to the one used in the battery charger. A 100 kHz switching
signal with a duty cycle of 35% is provided by the 56800E controller and
applied to an NMOS technology H bridge.

Figure 23 H Bridge Configuration Providing Multiple Floating Power Supplies

The output of the isolating transformer is half-wave rectified and applied to the
load. Positive and negative voltages are generated. The 39. Resistor limits the
current of the transformer’s secondary when M1 and M2 are on. Resistors RL1
and RL2 represent the load.

All isolated power supplies are connected in parallel to the rail voltage,
depicted as nodes A and B in Figure 23.

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Figure 24 Waveforms at A and B

While M1 and M2 are on, VCC is connected directly to the primary, increasing
the current linearly, as shown in Figure 25. Cn is simultaneously charging
across Dn.The 39. resistor acts as a current limiter. M1, M2, Dp, Cp, and the
transformer shape a traditional fly back power supply.

Figure 25 Current Waveforms

When M1 and M2 are off, an inverted voltage is induced in the primary and

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D1, D2 which limit that voltage to 15V plus 1.2 from two diode junctures,
turning Dp on and charging Cp.

There are several transformers connected to the rails A and B which generate
isolated power supplies to drive SCRs, IGBTs, and MOSFETs used in the
rectifier, inverter, battery charger, and battery booster.

Figure 26 shows the control power supply, which uses a LM2576 step-down
voltage regulator, to generate +VCC = 15V fed by the redundant DC voltage
coming from 18VAC or +VBAT or an additional power supply VDCR coming
from the battery charger. This circuit also generates the Control Board Power
Supply, which is isolated from +VCC.

Figure 26 Control Power Supply

1.4.9.2 Sensing Circuits and Reference Voltage Generator

All signals that require sensing as voltages, currents, and temperature at the
Analog-to-Digital Converters are converted to the appropriate input levels and
diode-limited to avoid damage to the ADCs; this process uses differential

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amplifiers as seen in Figure 28, because of the different ground references

shown in Figure 27.

Figure 27 Partial View of the Auxiliary Power Supply and Optoisolation Network

Figure 28 A/D Sensing Circuitry

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Figure 29 General Design of the Sensing Circuits

The value of the resistors required to sense every signal is calculated in order to
guarantee full swing, minimizing analog and quantization noise at the ADCs.
The reference level of the ADC is used to shift the AC input signal to swing
from 0 to VRH (i.e., 0 volts in the input signal are mapped to VRH/2). If the
output of the operational amplifier tends to go out of limits for any reason, the
diodes protect the ADC inputs.

1.4.9.3 Voltage Reference Supply

The voltage reference, VRH, is generated by the circuit shown in Figure 29.
This circuit acts as a buffer to the reference voltage VREFH from the
controller. This circuit also generates two auxiliary voltage outputs:
• VA equal to one diode voltage Vã
• VB with value VRH-Vã
These voltages will be used to limit the values of voltage applied to A/D
modules.

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Figure 30 Voltage Reference Generator

1.4.9.4 Silicon Controlled Rectifier (SCR) Gate Drivers

The circuit in Figure 30 shows the basic driver which handles the SCRs’ gates
using an 4N35 optocoupler to generate an isolated current supply to trigger the
rectifier’s SCRs.

Figure 31 SCR Gate Driver

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1.4.9.5 IGBT and MOSFET Gate Drivers Circuit

Figure 32 illustrates the basic isolated circuit implemented to drive the IGBT’s
and MOSFET’s gates. It is based in an HCPL 3101 gate drive optocoupler.

Figure 32 IGBT and MOSFET Gate Driver

1.4.10 Power Transfer Circuits (Bypass) Theory of Operation

Under normal conditions, the UPS inverter feeds all power to the load.
However, in order to ensure that the load is supported in the event of a failure,
or during maintenance, the equipment must also allow for direct connection to
the AC main line. A switching relay is connected as shown in Figure 33.

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Figure 33 Bypass Relay Configuration

The relay’s transfer time must be shorter than a period of the AC line. A
transfer time of less than 20ms is fast enough to comply with this constraint.
The transfer is allowed if phase and voltage conditions are satisfied.
Figure 34 shows the circuit implemented to turn the bypass relay on and off
using the BP1 signal. Please note the three different grounds used in the
system.

Figure 34 Relay Driver

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1.4.11 Overcurrent Protection

Figure 35 shows the rectifier and inverter current sensing circuit. Figure 36
shows the circuits implemented to sense the battery charger and battery booster
currents. These circuits generate overcurrent signals when the current value
reaches a defined level. These two signals are connected directly to the
controller’s FAULT 0 and FAULT 1 pins.

Figure 35 over current Protection for Rectifier and Inverter

Figure 36 over current Protection for Charger and Push-Pull

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The battery charger over current protection generates a fault signal, named
“SIC”, which turns off the charger PWM signal. Likewise, the battery booster’s
over current protection circuit generates the FPP signal, which turns off the
drive signal for the MOSFETs.

1.4.12 Battery Temperature Sensing

The battery temperature sensing circuit is shown in Figure 37; it uses an LM-
35-CZ, which is a precision centigrade temperature sensor.

The output of this circuit is a voltage that is proportional to the temperature.

This sensor must be located near the battery.

Figure 37 Battery Temperature Sensing Circuitry

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Figure 38 Battery Temperature Sensor

1.5 Control Loops In The Online UPS

The UPS’ control algorithms are digitally implemented. The topology chosen
for the compensators is the PID (Proportional-Integral-Derivative) and the PI
(Proportional-Integral), with a 3-bit resolution. All gain constants are 16-bit
implemented. The accumulators are all 32-bit, unless otherwise specified.

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1.5.1 Control Algorithms Discrete Equivalents

An ideal PID analog controller is expressed as follows:

An appropriate technique to discretize this transfer function is the backward

difference method, which is based on numerical integration theory and has the
following equivalence rule:

Where:

Ts is the sampling period

The PID transfer function in discrete time domain is:

It is implemented as follows:

where:

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is the discrete time integrator gain and

is the discrete time differential gain. The proportional gain constant, KP,
remains unmodified.

1.5.2 PFC and Rail Control

Figure 39 shows a simplified PFC control loop, valid only for positive AC line
voltages. The PFC is a current loop with a set point calculated as the product of
the rail voltage control output times the AC line voltage.
The voltage control must keep a constant DC rail. V. Positive Rail is sensed
and compared to Voltage Setpoint.
The error signal then passes through a PI control network, which outputs one of
the operands used to calculate the current set point. The other operand is the
AC Line Voltage, VLINE. This signal is then used as the set point of a second
PI control, which forms the current control loop.

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Figure 39 PFC and Rail Control Loops (Positive Semicycle)

The goal of the rectifier stage is to maintain the rail DC voltage at ± 220V and
to control the input current to mimic the voltage waveform (and thus to make
the complete system appear as a resistive load to the AC main line). In order to
achieve these two goals, two control loops are required:

A current control loop, implemented with a PI controller, generates a current as

required by the input inductor. The circuit symmetry makes it possible to
implement a control using the line voltage

absolute value to control the signal, regardless of its sign. A suitable controller
for this pplication is a PI compensator with the following parameters:

Using the backward difference method yields the following discrete time
equivalent:

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with:
KP = 6.4 and KI = 1.6
The second controller keeps the rail voltage constant and uses a low pass filter
to reject the 60Hz and 120Hz ripple. The process is much slower than any of
these frequencies, and therefore should not attempt to correct higher harmonic
disturbances. The chosen controller is a PI. The output of this controller
modulates the AC main line voltage to obtain the reference for the current loop.
The low-pass filter is a first-order Infinite Impulse Response (IIR) filter with a
3dB cutoff frequency of 5Hz, implemented with the following transfer
function:

with:
b0 = 0.01
a1 = 0.9984
The following is the proper PI controller:

Using the backward difference method yields the following discrete time
equivalent:

with:
KP = 0.9 and KI = 0.0008

1.5.3 Battery Charger Control

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The circuit in Figure 40 shows a schematic battery charger control loop,

consisting of an inner voltage loop and an outer current loop. The sensed
battery voltage determines the charging current (limited to 1 Ampere). This
current is a function of the PWM duty cycle.

Figure 40 Battery Charger Control Loop

Given that the battery voltage is a slow signal, the sampling frequency for this
control is decimated by 16 relative to the 20kHz (20kHz/16 = 1250Hz)
sampling frequency used elsewhere in the system. The PWM switching
frequency is preserved at 20kHz.

To avoid saturation of the voltage compensating network’s integrator, its input

is deactivated if the control output is above a predefined threshold.
The batteries are charged using the constant current–constant voltage approach.
While the battery voltage is lower than the floating voltage (in this case, 28V),
a constant current of 1A is applied. When the battery-

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terminal voltage reaches 28V, the voltage is kept constant, decreasing the
charge current. The battery charger system is implemented by two nested
loops. The inner loop controls the charging current and uses a PI control.
The reference for this control is delivered by a voltage control loop, whose
output is limited from 0 to 1/3, where 1/3 (in Frac16 notation) represents 1A.
When the batteries are discharged, the voltage control

increases the current reference, looking for a 28V voltage. However, when the
voltage control loop reaches 1/3, the integral action is disconnected and the
output is limited, forcing the current loop to set a 1A charging current to the
battery. When floating voltage is reached, the voltage control loop reduces its
output, reducing the current applied to the batteries.
The controller chosen for the current control loop is a PI compensator with the
following parameters:

Using the backward difference method results in the following discrete time
equivalent system:

with:
KP = 0.7 and KI = 0.035

The controller chosen for the voltage control loop is a PI compensator with the
following parameters:

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Using the backward difference method results in the following discrete time
equivalent system:

with:
KP = 0.02 and KI = 0.0005

1.5.4 Inverter Control

The objective of the inverter control loop is to supply the load with a voltage
defined by the reference signal.
This reference signal is generated by the PLL system, at a sampling frequency
of 20 kHz, high above the 50/60Hz nominal frequency. For this reason, it is
reasonable to consider the set point a constant.

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Figure 41 Inverter Control Loop

The inverter control is implemented with a nested topology. The outer loop
controls the output voltage and the inner loop controls the inductor current.
This configuration allows better stability of the feedback system and an
implicit limitation of the current delivered to the load. The inner control loop
stabilizes the system, acting as a damper for the LC output circuit.
The controller chosen for the current control loop is a PI compensator with the
following parameters:

Using the backward difference method results in the following discrete time
equivalent system:

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with:
KP = 0.84 and KI = 0.0024

The outer loop is the voltage control. The goal of this loop is to keep a
sinusoidal voltage waveform, regardless of the load characteristics. When
nonlinear loads (as a full wave rectifier) are connected, a high current is drawn
at the peaks of the signal. The action taken to

overcome this condition is to inhibit the integral action by disconnecting the

integrator input when the current draw is high. This action reduces the output
distortion and enhances the controller response when the load requires high
currents.

The controller chosen for the current control loop is a PI compensator with the
following parameters:

Using the backward difference method results in the following discrete time
equivalent system:

with:
KP = 3.42
KI = 0.475
and
KD = 11.75

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1.5.5 Battery Booster Control Loop

The function of this controller is to keep the rail DC voltage at ±220V while
the system is supported by the battery.

Figure 42 Battery Booster Control Loop

Given that the rail voltage is a slow signal, the sampling frequency for this
control is decimated by 16 relative to the 20kHz (20kHz/16 = 1250Hz)
sampling frequency used in other sections of the system. The PWM switching
frequency is preserved at 20 kHz.

The system is implemented with a PID compensator in order to regulate the rail
DC voltage. The control output modulates the duty cycle of a push-pull power
supply. The following are the parameters of such a controller:

Using the backward difference method yields the following discrete time
equivalent system:

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with:
KP = 16
KI = 0.2
and
KD = 0.1

1.5.6 Minimizing Delay in the Control Loops

The triangular signal used as a carrier wave for the PWM is created from a
counter that accumulates at the controller’s clock speed (60MHz). The pulse
width of the PWM is updated at a rate of 20 kHz. This implies that in order to
obtain both the 20kHz sampling frequency and a symmetric triangle wave, this
counter must count from zero to 1500, then count back from 1500 to zero:

Given that the PWM(s) update their value when the PWM load command is
given to the PWM peripheral, the delay from the time elapsed between the
sampling of the signal and the update of the PWM compare values should be
minimized, enhancing the system’s stability. The implementation of this delay
and the relationship between the PWM reference and the ADC conversion is
fully explained in Section 7..

1.6 Battery Temperature Reading

The interrupt service routine AD2_OnEnd reads and stores the battery
temperature to a variable. The execution of the ISR is shown in Figure 43

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Figure 43 Battery Temperature Reading

1.6.1 Delay_Timer_OnInterrupt

This routine merely counts 21 times 140ms (the time interval of the timer) in
order to generate a time delay of 3 seconds following the controller’s core
start-up. This is a wait time to allow the auxiliary power supplies to stabilize.

1.7 Program Loop Timing

The timing of the program originates at the PWM, configured for one complete
cycle reload, and center-aligned. The modulo of the PWM is set to 1500,
generating a 20 kHz triangle wave from the 60MHz internal bus clock.
The SYNC signal of the PWM is passed to Timer C2 to provide the sync signal
to the ADCA peripheral. At Timer C2, the SYNC signal is delayed in order to
reduce the time between the sampling and the updating of the values at the

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PWM, enhancing the stability of the discrete time control algorithms.

Figure 44 Program Loop Timing

After the configured delay, Timer C2 signals the ADCs to start conversion. At
the end of the conversion, the ADC module interrupts the core processor. All
control loops are executed in this interruption.

1.8 Inverter Control Loop

The control network for the inverter is constructed with an inner current PI
control loop and an outer PID control loop as shown in Figure 45
The outer control loop receives the sinusoidal wave synthesized by the PLL
module as a reference and compares it with the inverter output voltage. The
error signal passes through a PID compensator whose output constitutes the set
point for the inner PI control loop. This current set point is compared with the
load current.

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The transfer function of a discrete time PID control loop is calculated by this
equation:

The transfer function of a discrete time PI control loop is calculated by the

following equation:

The sine wave generated is used as the set point of the inverter control. The
inverter uses the output voltage and current as sensing inputs to the control,
which have a double control loop topology, inner PI current control and outer
PID voltage control. Figure 45 shows the details of the inverter loop as
implemented in the source code. Signal names are the actual variable names in
the C code.

Figure 45 Inverter Control Loop Diagram

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1.9 PFC Control Loop

Figure 46 shows the actual function implementation of the PFC control loop. It
consists of two controls, one to control the rail-to-rail voltage and another to
control the current drawn to the AC main line. The current set point for the
inner loop is the AC line voltage times a factor linearly proportional to the
error signal at the rails (and finally dependent on the UPS load current). The
hardware implementation in this UPS (please refer to Figure 46) requires the
inner control to work with the absolute values of the signals in order to avoid
discontinuities at the current control output. Both control loops use
Proportional–Integral (PI) compensators, implemented with 32-bit integrators.
The Z domain transfer function of a PI compensator is:

Where:
KP is the proportional gain
KI is the integral gain A total gain, KT, is implemented in order to

allow flexibility when tuning the control; i.e., varying the total loop gain
without the necessity of modifying the individual gains.

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Figure 46 PFC Control Loop Diagram

1.10 Battery Booster Control Loop

The battery booster control signals for the switches are not complementary but
180° phase shifted. This is implemented at PWMA channels 2 and 3, defining
the compare value of channel 3 as 1500 (the full scale of the PWM) minus the
compare value of channel 2, and inverting its output. A protection time of 4ms
is implemented between the active state of these signals at maximum duty
cycle.
Decimation by 16 is implemented for a routine sample frequency of 1250Hz.
Figure 47shows the battery booster system.

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Figure 47 Battery Booster Control Loop

1.11 Battery Charger Control Loop

The battery charger is a constant current power supply. The control loop uses
the measured battery current to calculate the appropriate voltage set point.
Decimation of the sampling rate by 16 allows for better precision for the
battery voltage variable. The variables are sensed at 20 kHz, but the battery
voltage routine is executed at 20 kHz/16 = 1250Hz. Moving averaging of the
samples is implemented for noise filtering.
Due to the slow speed of the system, the integrator input of the voltage control
is disabled when the output of the controls reaches a defined limit.
Please see Figure 48 for a detailed diagram of the battery charger system

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Figure 48 Battery Charger Control Loop

1.12 Rectifier Soft Start Routine

In order to implement the rectifier soft start, a software synchronized ramp is

generated and compared with the rectifier trigger level signal, which starts at a
value higher than the peak of the ramp, then decrements towards zero. The
result of the compare operation generates a PWM signal that is set at the zero
crossing time minus time T, and is always reset at the zero crossing. As the
trigger level decrements, the time ô increases from zero to a half period. This
signal can drive the input SCRs that form the full wave rectifier at the input of
the UPS.

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Figure 49 SCR Control Signal Generation at the Beginning and End of the Rectifier Soft Start

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