SE ETC Digital Logic Design (BTEXC305) SEM III

6 7 D C A 3
E E76 137 CD EF D5C 57 0EA B3 B7 415

EE E761 137 CD EFDD5C 570 0EA B3B B74 415F F8A
76 3 CD EF 5 57 E B3 7 15 8A 8C
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7C E D C 0 A 3B 4 F A A E 61 7 D
Q. 6
Q. 5
Q. 3
Q. 2
Q. 4
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E D C5 0E AB 3B 41 F8 8 A E 61 7C E D C5 0
DE FD 5C 70 A 3B 74 5F A CA EE 761 37C DE FD 5C 70 EA
5 5 E B 1 8 8 7 5 E B
EF FD5 C57 70E AB 3B7 7415 5F8 A8C CAE EE7 613 37CDDEF FD5 5C57 70E AB 3B7
D C5 0E AB 3B 41 F8 A8 A E 61 7C E D C5 0 AB 3B 41
flipflop.
FD 5C 70 A 3B 74 5F A CA EE 761 37 D FD 5C 70 EA 3 74 5F
Max Marks: 60
5C 570 EA B3 74 15F 8A 8C EE 76 37 CD EFD 5C 57 EA B3 B74 15 8A
57 EA B3 B7 15 8A 8C AE 76 137 CD EF 5C 57 0EA B3 B7 15 F8A 8C
0E B B7 41 F8 8 AE E7 13 C E D5 5 0E B B 41 F8 8 A
AB 3B 41 5F A8 CA E 61 7C DE FD C5 70 AB 3B 741 5F A8 CA EE
3B 741 5F 8A8 CA EE 761 37C DE FD 5C5 70 EAB 3B 74 5F 8A8 CA EE 761
74 5F 8A CA EE 761 37 D FD 5C 70 EA 3B 74 15F 8A CA EE 76 37
15 8A 8C E 76 37 CD EF 5C 57 EA B3 7 15 8A 8C E 76 13 CD
F8 8C AE E7 13 C E D5 5 0E B B 41 F8 8 A E7 13 7C E
A8 A E 61 7C DE FD C 70 A 3B 74 5F A8 CA EE 61 7C DE FD
Instructions to the Students:

CA EE 761 37 DE FD 5C 570 EA B3B 74 15F 8A CA EE 76 37 D FD 5C
EE 761 37 CD FD 5C 570 EA B3B 74 15F 8A 8CA EE 76 137 CD EFD 5C 570
76 37 CD EFD 5C 57 EA B3 74 15 8A 8C E 76 137 CD EF 5C 57 EA
13 CD EF 5 57 0E B B7 15 F8 8C AE E7 13 C EF D5 5 0E B
7C E D C5 0E AB 3B 41 F8 A8 A E 61 7C DE D C5 70 AB 3B
DE FD 5C 70 A 3B 74 5F A CA EE 761 37C DE FD 5C 70 EA 3B 74
FD 5C 570 EA B3B 74 15F 8A 8CA EE 761 37 D FD 5C 570 EA B3 74 15F
A) Explain two input TTL NAND Gate

based is mentioned in ( ) in front of the question.
A) Design 4 : 16 decoder using 2: 4 decoder.

0 --- 2 --- 5 --- 4 --- 7 --- 3.
1. Solve ANY FIVE questions out of the following.
A) Implement Full Adder Circuit Using PLA.

EE 761 37 CD FD 5C 570 EA B3B 74 15F 8A 8CA EE 76 137 CD EFD 5C 570
B) Design the circuit to generate the sequence :

Q. 1 A) Design a 4-bit binary to Gray code converter.

Date: 01/06/2019
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3. Use of non-programmable scientific calculators is allowed.
B) Explain VHDL three modelling styles with example.

B) Give comparison between TTL and CMOS logic family

4. Assume suitable data wherever necessary and mention it clearly.
A) Draw and explain the Serial In Parallel Out Shift Register.
************* The End *************

Subject Name and Subject Code: Digital Logic design(BTEXC305)
F (A, B, C, D) = m (0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)

15F8A8CAEE76137CDEFD5C570EAB3B74
Course: B. Tech. in Electronics and Telecommunication Engineering

EE 761 37 CD FD 5C 570 EA B3B 74 15F 8A 8CA EE 76 137 CD EFD 5C 570 A) Give comparison between Combinational and Sequential Circuit
B) Implement 3 bit Asynchronous Up Counter. Draw clock waveform.

B) Minimize the given Boolean expression using Quine-McCluskey method

Supplementary Semester Examination – Summer 2019

Sem: III
B) Write down Next state equation and excitation table for SR, JK, T and D

74 5F 8A CA EE 761 37 D FD 5C 70 EA 3B 74 15F 8A CA EE 76
15 8A 8C E 76 37 CD EF 5C 57 EA B3 7 15 8A 8C E 76 13
F8 8C AE E7 13 C E D5 5 0E B B 41 F8 8 A E7 13
A8 A E 61 7C DE FD C 70 A 3B 74 5F A8 CA EE 61 7
Duration: 3 Hr.
l/
CA EE 761 37 DE FD 5C 570 EA B3B 74 15F 8A CA EE 76 37
(3)
(4)
(4)
(2)
(3)
(2)
(3)
CO)
(1,2)
(2,3)
(2,3)
(2,3)
DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
EE 761 37 CD FD 5C 570 EA B3B 74 15F 8A 8CA EE 76 137 C

76 37 CD EFD 5C 57 EA B3 74 15 8A 8C E 76 137 CD
13 CD EF 5 57 0E B B7 15 F8 8C AE E7 13 C
7C E D C5 0E AB 3B 41 F8 A8 A E 61 7C DE
06
06
06
06
06
06
06
06
06
06
(2,3) 06
06
DE FD 5C 70 A 3B 74 5F A CA EE 761 37C DE F
FD 5C 570 EA B3B 74 15F 8A 8CA EE 761 37 D FD
2. The level question/expected answer as per OBE or the Course Outcome (CO) on which the question is
5C 570 EA B3 74 15F 8A 8C EE 76 37 CD EFD

(Leve Marks
57 EA B3 B7 15 8A 8C AE 76 137 CD EF 5
0E B B7 41 F8 8 AE E7 13 C E D5
AB 3B 41 5F A8 CA E 61 7C DE FD C
3B 741 5F 8A8 CA EE 761 37C DE FD 5C5
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15 8A 8C E 76 37 CD EF 5C 57
F8 8 A E7 13 C E D5 5 0

SE ETC Digital Logic Design (BTEXC305) SEM III

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6 7 D C A 3

E E76 137 CD EF D5C 57 0EA B3 B7 415

Instructions to the Students:

A) Explain two input TTL NAND Gate

A) Design 4 : 16 decoder using 2: 4 decoder.

CA EE 761 37 DE FD 5C 570 EA B3B 74 15F 8A CA EE 76 37 D FD 5C

A) Implement Full Adder Circuit Using PLA.

B) Design the circuit to generate the sequence :

Q. 1 A) Design a 4-bit binary to Gray code converter.

B) Explain VHDL three modelling styles with example.

B) Give comparison between TTL and CMOS logic family

A) Draw and explain the Serial In Parallel Out Shift Register.

************* The End *************

F (A, B, C, D) = m (0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)

CA EE 761 37 DE FD 5C 570 EA B3B 74 15F 8A CA EE 76 37 D FD 5C

B) Implement 3 bit Asynchronous Up Counter. Draw clock waveform.

FD 5C 570 EA B3B 74 15F 8A 8CA EE 761 37 D FD 5C 570 EA B3 74 15F

5C 570 EA B3 74 15F 8A 8C EE 76 37 CD EFD 5C 57 EA B3 B74 15 8A

3B 741 5F 8A8 CA EE 761 37C DE FD 5C5 70 EAB 3B 74 5F 8A8 CA EE 761

CA EE 761 37 DE FD 5C 570 EA B3B 74 15F 8A CA EE 76 37

EE 761 37 CD FD 5C 570 EA B3B 74 15F 8A 8CA EE 76 137 C

5C 570 EA B3 74 15F 8A 8C EE 76 37 CD EFD

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