Building a Data path

Data path element : A unit used to operate on or hold data within a

processor
• MIPS implementation, the data path elements include
– The instruction and data
memories, the register file, the ALU, and adders
▪ Data path design start by examining the major components
▪ Required to execute each class of MIPS instructions
▪ Two state elements are needed to store and access
instructions
▪ Instruction memory and the program counter
▪ Adder is needed to compute the next instruction address
▪ Instruction memory provide only read access because the data
path does not write instructions
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Building a Data path
▪ Instruction memory
▪ Output at any time reflects the contents of the location specified by the address input
▪ Require no read control signal
▪ The program counter
▪ 32-bit register written at the end of every clock cycle
▪ Does not need a write control signal
▪ The adder is an ALU wired to always add its two 32-bit inputs and place the sum on its
output
▪ To execute any instruction, we must start by fetching the instruction from memory
▪ To prepare for executing the next instruction, program counter is incremented so that it
points at the next instruction, 4 bytes later

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Building a Data path
▪ A portion of the data path used for fetching instructions and incrementing the
program counter

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R-format Instructions (or) Arithmetic- logical instructions

• Read two registers

• Perform an ALU operation on the contents of the registers
• Write the result to a register
• This instruction class includes add, sub, AND, OR, and slt
• add $t1,$t2,$t3, which reads $t2 and $t3 and writes $t1
• The processor’s 32 general-purpose registers (MIPS) are stored in a structure called a
register file
• Register file
– Collection of registers
– Any register can be read or written by specifying the number of the register in the file
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R-format Instructions
▪ The register file contains the register state of the computer
▪ ALU is needed to operate on the values read from the registers
▪ R-format instructions have three register operands
▪ For each instruction
▪ Need to read two data words from the register file
▪ Write one data word into the register file
▪ For each data word to be read from the registers, we need
▪ An input to the register file that specifies the register number to be read
▪ And an output from the register file carrying the value that has been read from the
registers

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R-format Instructions
• To write a data word, we will need two inputs:
– one to specify the register number to be written and
– one to supply the data to be written into the register
• Two elements needed to implement R-format ALU operations

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R-format Instructions
• The register file always outputs the contents of whatever register
numbers on the Read register inputs
• Writes, controlled by the write control signal, which must be asserted
for a write to occur at the clock edge
• Need a total of 4 inputs - 3 for register numbers and one for data
• And two outputs (both for data)
• The register number inputs are 5 bits wide to specify one of 32
registers (32 = 25)
• Data input and two data output buses are each 32 bits wide
• The ALU, which takes two 32-bit inputs and produces a 32-bit result,
as well as a 1-bit signal if the result is 0
• The operation performed by ALU is controlled with the ALU operation
signal, which will be 4 bits wide

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Load Word and Store Word Instructions
• The data memory must be written on store instructions
• Data memory has
– Read and write control signals,
– An address input,
– An input for the data to be written into memory

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 Load Word and Store Word Instructions
• lw $t1,offset_value($t2)
• sw $t1,offset_value ($t2)
• These instructions compute a memory address by adding
the base register ($t2), to the 16-bit signed offset field
• If the instruction is a store, the value to be stored must also
be read from the register file resides in $t1
• If the instruction is a load, the value read from memory must
be written into the register file ($t1)
• Need both the register file and the ALU
• Sign extension unit
– To sign-extend the 16-bit offset field in the instruction
to a 32-bit signed value
• Data memory unit - to read from or write to

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Data path for Branch Instructions
• The beq instruction has three operands
– Two registers that are compared for equality
– 16-bit offset used to compute the branch target address
relative to the branch instruction address
• beq $t1,$t2,offset
• Branch target address is computed by adding the sign-extended
offset field of the instruction to the PC
• Base for the branch address calculation is the address of the
instruction following the branch
• PC + 4 (next instruction address) in the instruction fetch
datapath, is the base for computing the branch target address
• The offset field is shifted left 2 bits
• Shift increases the effective range of offset field by a factor of 4
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Branch Instructions
• The datapath for a branch uses
– ALU - To evaluate the branch condition
– Adder - To compute the branch target as the sum of the incremented PC and the sign-
extended, lower 16 bits of the instruction shifted left 2 bits
• branch datapath must do two operations:
– compute the branch target address
– compare the register contents
• branch is taken
– When the condition is true (the operands are equal)
– the branch target address becomes the new PC
• branch is not taken
– If the operands are not equal
– the incremented PC should replace the current PC
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Delayed branch
▪ Instruction immediately following the branch is always executed,
independent of whether the branch condition is true or false

▪ Condition is false, the execution looks like a normal branch

▪ Condition is true,

▪ a delayed branch first executes the instruction immediately following

the branch in sequential instruction order before jumping to the
specified branch target address

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Building a Data path

• The operations of arithmetic-logical (or R-type) instructions and the memory

instructions data path are quite similar

• The key differences are the following:

– The arithmetic-logical instructions use the ALU, with the inputs coming from the
two registers

– The memory instructions can also use the ALU for address calculation

– Second input is sign-extended 16-bit offset field from the instruction

– The value stored into a destination register comes from the ALU (for an R-type
instruction) or the memory (for a load)
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The data path for the memory instructions and the R-type Instructions

• Data path for the operational portion of the memory-reference and

arithmetic-logical instructions that uses a single register file and a
single ALU

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The simple data path for the MIPS architecture combines the
elements required by different Instruction classes

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