EE2255 Microelectronic Circuits

Midterm Exam 11/17/2022

1. Plot the Thevenin and Norton equivalent circuits in the dashed-line box (clearly
indicate the polarity and direction of the calculated VTHEV and INOR). (20/100)

(a) (b)

1 k 3 k
+ +
+ 2 k vout
5V - 2 mA 5 k vout
- -

(c) Assume the overdrive voltage is 0.1 V, drain current is 2 mA, = 0.04 V-1, RL= 12.5
k, and vin= 5 mV.

+ +
vin + gmvgs
- vgs ro RL vout
- -

(d) Same parameters as (c).

+ +
vgs gmvgs ro RL vout
- -

vin +
-

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2. Determine the small-signal input or output impedances in the following circuits.
Assume that the diode is on, BJT is in the active mode (VBE,on= 0.8 V), and the
MOSFET is in the saturation region. (20/100)

(a) (b) VCC= 5 V

Rin RC
RD= 10  D1 2 mA RB= 10 k

= 50

Rin

(c) (d)

VDD= 2.5 V
VDD

RG1= 3 k RD= 600 

+
VGS -
Rout
RG2= 2 k 5 mA
Rout

W/L= 200, nCox= 100 A/V2, VGS = 1 V and VTH = 0.5 V

VTH= 0.5 V, = 0.1 V-1

3. A PNP common-emitter amplifier is designed to amplifier a weak AC signal with an

internal source resistance of RS = 200 ohm. Assume the transistor ( = 100 and VA = )
is biased in the active mode. The collector current IC is 2 mA and RC = 1 k.

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 (a) What is the main carrier transport mechanism in a BJT? What is the main carrier
for conducting current in a PNP transistor? Name one disadvantage comparing
with using NPN for amplifier design. (5/100)
(b) Plot the small-signal model of the amplifier and determine the small-signal gain
vout/vin. (10/100)
(c) Determine the minimum allowed bias voltage VCC to still have the amplifier
functioning properly. If the input signal has an amplitude of 1 mV, plot the output
waveform under this condition. Indicate the DC level and relative phase of the
output signal. (5/100)
VCC

vin
RS vout
1 mV VB
vin 
t RC 2 mA
VB

4. A MOSFET has the following technology dependent parameters and L is fixed as 20

nm.
(a) If the transistor is biased in the triode region and used as a resistor, design the
transistor width W to have a resistor of 200 ohm if VG= 0.7 V. (5/100)
(b) The transistor is also biased in the saturation region to design a common-source
amplifier. If VDD is fixed at 2 V and the power budget is 1 mW. Assume RD is 500
ohm, design W to have a voltage gain of 20 dB. (5/100)
(c) Based on the W calculated from (a) and (b), and assume M1 and M2 are operated
in the triode and saturation regions respectively. Plot the small-signal model of the
circuit and determine the range of |gain| when VG varies from 0.65 to 0.75 V. Also,
briefly explain what is the purpose of using a very large CB in the circuit. (10/100)

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5. (a) What types of capacitances exist under a forward-biased PN junction? How about
a reverse-biased PN junction? (5/100)
(b) A silicon sample (cross section is 500 m  500 m) is uniformly doped by Boron
of 21018 cm-3. Determine the total current at T= 300 K. Assuming n= 1200 cm2/Vs
and p= 500 cm2/Vs. (5/100)
(c) Design a limiter circuit using two diodes (VD, 0n= 0.8 V) and two voltage sources
to have the transfer function shown below. Also, plot the output waveform in time
domain based on the provided vin. (5/100)
(d) What should be the small-signal input and output impedance for an ideal voltage
amplifier? What would be the ideal input impedance of the amplifier if the input
signal is current? (5/100)

(b) (c)
Vout
1.8 V
vin
Boron-doped Si 2V
-1.3 V
15 mm
mm t Vin
1.8 V
-2 V
-1.3 V
1 VV
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