Course Plan Digital Electronics

COURSE PLAN
For
(20EC104) DIGITAL ELECTRONICS
Course Coordinator : Dr.L.M.I.Leo Joseph
Course Instructors :
1. Dr. L.M.I. Leo Joseph

2. Mr.Chakradhar
3. Dr.Syed Nageena Parveen
4. Mr.Sagar
Course Type : Professional Core
Semester and Year : III Semester and II Year
L-T-P : 3-0-2
Credits :4
School : School of Engineering
Department : Department of Electronics and Communication

Engineering
Course Level : UG
School of Engineering
SR University,
Warangal
Page 1 of 14
1.COURSE CONTEXT
DEPARTMENT ECE
SCHOOL Engineering
DATE THIS COURSE

DEGREE B.Tech. WILL BE EFFECTIVE 10-07-2023
FROM
2.COURSE BRIEF
DIGITAL
COURSE TITLE ELECTRONICS PRE-REQUISITES NA
COURSE CODE (20EC104) TOTAL CREDITS 4
COURSE TYPE Program Core L-T-P FORMAT 3-0-2
3.COURSE SUMMARY
This course provides a comprehensive understanding of digital electronics, covering both theoretical
concepts and practical implementations. Students will learn about number systems, logic gates,
Boolean algebra, combinational and sequential circuit design, and programmable logic devices.
4.COURSE-SPECIFIC LEARNING OUTCOMES (CO)
By the end of this program, students should have the following knowledge, skills and values:
CO1: Understand digital logic gates, Boolean algebra, and the fundamental principles of digital
circuits, analyze and design basic digital circuits utilizing logic gates.
CO2: Implement digital circuits by effectively utilizing a range of electronic components, including
logic gates, flip-flops, multiplexers, and decoders.
CO3: Cultivate skills in designing and analyzing combinational and sequential circuits, as well as gain
proficiency in working with various Programmable Logic Devices (PLDs).
Course Articulation Matrix
PO/
PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO
PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2
CO
CO1 3 3 3
CO2 3 3 3 2
CO3 3 3 3 3
Mapping
Target Level
Page 2 of 14
Course Outcome 1 (CO1): Understand digital logic gates, Boolean algebra, and the fundamental
principles of digital circuits, analyze and design basic digital circuits utilizing logic gates.
Program Outcome 1 (PO1): Demonstrate a strong foundation in the principles and theories of
electrical and electronic engineering.
Program Outcome 2 (PO2): Apply mathematical and scientific principles to analyze and solve
engineering problems.
Course Outcome 2 (CO2): Implement digital circuits by effectively utilizing a range of electronic
components, including logic gates, flip-flops, multiplexers, and decoders.
Program Outcome 3 (PO3): Demonstrate proficiency in using modern tools and equipment to design,
simulate, and implement electronic systems.
Program Outcome 4 (PO4): Develop the ability to work effectively in teams and communicate
engineering concepts clearly.
Course Outcome 3 (CO3): Cultivate skills in designing and analyzing combinational and sequential
circuits, as well as gain proficiency in working with various Programmable Logic Devices (PLDs).
Program Outcome 5 (PO5): Demonstrate the ability to design and analyze complex electronic systems
using appropriate methodologies and tools.
Program Outcome 6 (PO6): Exhibit an understanding of ethical and professional responsibilities in the
field of electrical and electronic engineering.
5.DETAILED SYLLABUS
UNIT I (Contact hours: 7)
Number systems and Logic Gates
Review on number systems, digital logic gates: AND, OR, NOT, NAND, NOR, Ex-OR and Exclusive
- NOR, Realization of gates using Universal Gates, Implementations of Logic Functions using basic
gates, NAND –NOR implementation.
UNIT II (Contact hours: 8)
Boolean Algebra and Minimization of Switching Functions
Boolean postulates and laws –De-Morgan’s Theorem- Boolean function- Minimization of Boolean
expressions – Sum of Products (SOP) –Product of Sums (POS)-Canonical forms – Karnaugh map
Minimization – Don’t care conditions – Quine Mc’Clusky method of minimization, simplification
rules.
UNIT III (Contact hours:8)
Combinational Logic Design:
Definition, Design procedure – Adders-Subtractors -Serial adder / Subtractor - Parallel adder /

Subtractor - Carry look ahead adder, BCD adder , Magnitude Comparator- Multiplexer/ Demultiplexer
- encoder / decoder, parity checker - code converters: Binary to Gray, Gray to Binary, BCD to excess
3 code , Implementation of combinational logic using MUX, Decoder.
Page 3 of 14
UNIT IV (Contact hours:8)
Sequential Circuits
Flip-Flops, and latches - SR Flip flop, JK Flip flop, T Flip flop, D Flip flop and Master slave Flip flops
– Excitation table - Realization of one flip flop using other flip flops.
Counters (Asynchronous and Synchronous counters: Modulo-n counter – Shift Register- Universal
Shift Register, Applications of Shift Register: Ring counter, Johnson counter.
Finite state machine-capabilities and limitations, Mealy and Moore models-minimization of
completely specified and incompletely specified sequential machines, Introduction to ASM.
UNIT V (Contact hours: 5)
Programmable Logic Devices
Basic PLD’s –ROM, PROM, PLA, PAL. Realization of switching function using PLD’s –
Introduction to FPGA, CPLD.
TEXT BOOKS
REFERENCES
1. Digital Design: Principles and Practices,,Wakerly,4th edition, Pearson Education
2. Fundamentals of Logic Design, C. H. Roth, L. L. Kinney, 7th edition, Cengage Learning.
6.STUDIO WORK / LABORATORY EXPERIMENTS:
1. Realization of Logic gates

2. Minimization of Boolean functions and realization using logic gates
3. Realization of logic gates using universal gates
4. Verification of Demorgan’s theorem
5. Design of Half adder, Full adder, Half subtractor and Full subtractor
6. Design of Multiplexer, Demultiplexer
7. Design of Comparators
8. Design of Encoder, Decoder
9. Design of Code converters
10. Conversion of one flip to another flip and its realization.
11. Design of 2-bit counters
12. Design of Up/ Down Counters
13. Realization of memory read write operation
14. Design of shift registers
7.TEXTBOOKS/LEARNING RESOURCES:
1. Digital Design, M. Morris Mano, M.D.Ciletti, , Pearson Pearson Education; Sixth edition
2. Digital Logic and Computer Design by M. Morris Mano, Pearson Pearson Education; Fifth edition
Page 4 of 14
8.REFERENCE BOOKS/LEARNING RESOURCES:
1. Digital Design: Principles and Practices,,Wakerly,4th edition, Pearson Education
2. Fundamentals of Logic Design, C. H. Roth, L. L. Kinney, 7th edition, Cengage Learning.
9.MOOC COURSES (Reference to the Course):

1. Coursera: Coursera offers various digital electronics courses, such as "Introduction to Electronics" by
Georgia Institute of Technology and "Digital Systems: From Logic Gates to Processors" by Universität
Autònoma de Barcelona.
2. edX: edX provides courses like "Digital Electronics" by Purdue University and "Introduction to
Electronics" by Massachusetts Institute of Technology (MIT).
3. Udemy: Udemy offers a wide range of digital electronics courses, including "Digital Electronics:
Introduction to Digital Electronics" and "Digital Electronics: Combinational Logic Circuits."
4. NPTEL: NPTEL (National Programme on Technology Enhanced Learning) offers digital electronics
courses in collaboration with various Indian Institutes of Technology (IITs), such as "Digital
Electronics" by IIT Madras.
10.Lecture Wise Plan
No. Content Planned
Review of number system (10 minutes),

Conversion between decimal and binary numbers (10 minutes)
1 Conversion between binary numbers and octal numbers(10 minutes)
Conversion between binary numbers ,octal numbers and hexadecimal numbers(10 minutes)
Sample problems on number system (10 minutes)
Problems on decimal to binary, binary to decimal (10 minutes)
Problems on decimal to binary, binary to octal (10 minutes)
octal to binary, binary to decimal (10 minutes)
2
Problems on decimal to binary, binary to octal (10 minutes)
octal to hexadecimal and viceversa (10 minutes)
Introduction to logic gates (10 minutes)

Logical AND and its truthtable ( 5 minutes)
Logical OR and its truthtable ( 5 minutes)
Logical NOT and its truthtable ( 5 minutes)
3 Logical NAND and its truthtable ( 5 minutes)
Logical NOR and its truthtable ( 5 minutes)
Logical XOR and its truthtable ( 5 minutes)
Logical XNOR and its truthtable ( 5 minutes)
Summary of logic gates( 5 minutes)
4 Realization of AND logic using NAND and NOR
Page 5 of 14
Conversion steps (10 minutes)
Sample circuit and its conversion (30 minutes)
Realization of simple circuit using universal gates(10 minutes)
Realization of OR logic using NAND
Sample circuit and its conversion
Basic circuit (5 minutes)
5
Conversion (10 minutes)
Truth table( 10 minutes)
Comparison of basic with converted circuit (5 minutes)
Realization of OR logic using NOR
6
Concept to circuit conversion and its realization
7
8 Buffer Lecture - Unit 1
Introduction to Boolean Algebra
Boolean Postulates ( 25 minutes)
basic postulates( 10 minutes)
postulates necessary for minimization ( 10 minutes)
9 simple example (5 minutes)
Boolean laws
basic laws( 10 minutes)
laws necessary for minimization ( 10 minutes)
simple example (5 minutes)
De-Morgan's Theorem and its realization
Theorem and Boolean expression (10 minutes)
10
Theorem and its proof (10 minutes)
Boolean Functions (30 minutes)
Minimization of Boolean Expressions (20 minutes)
11
2 level literals based minimization (30 minutes) contd….
12 Minimization of Boolean Expressions (20 minutes)
Page 6 of 14
higher level literals and its minimization(30 minutes)
Sum of Products (SOP) (12 minutes) ,
13 Product of Sums (POS) (12 minutes)
Realization using truthtable (26 minutes)
2 variable Karnaugh Map Minimization (15 minutes)
14 3 variable Karnaugh Map Minimization (25 minutes)
Don't Care Conditions (10 minutes)
15 Quine McCluskey Method of Minimization (50 minutes) contd…
16 Quine McCluskey Method of Minimization (50 minutes)
17 Buffer Lecture – unit 2
Design procedure for Adders and Subtractors (20 minutes)
18 Design of half adder and full adder (15 minutes)
Design of half subtractor and full subtractor (15 minutes)
Serial Adder/Subtractor
Logic explanation (5 minutes)
Realization (10 minutes)
Parallel Adder/Subtractor
19 Logic explanation (5 minutes)
Realization (10 minutes)
Carry Look Ahead Adder
Logic diagram (10 minutes)
Logical realization (10 minutes)
BCD Adder
Magnitude Comparator
20
Truth Table (5 minutes)
Kmap formation (10 minutes)
boolean expression realization (5 minutes)
Logic realization (10 minutes)
Multiplexer/Demultiplexer
21 Logic diagram (10 minutes)
Encoder/Decoder (30 minutes)
22 Kmap formation (10 minutes)
boolean expression realization (5 minutes)
Parity Checker
23
boolean expression realization (10minutes)
Page 7 of 14
Code Converters: Binary to Gray (35 minutes)
24
Gray to Binary, BCD to Excess 3 Code
25
26 Buffer Lecture – Unit 3
Introduction to sequential logic and the need for memory elements
Definition (2minutes)
About the need of memory elements ( 3 minutes)
Basic concept of a latch and its operation (5 minutes)
27 Introduction to flip-flops and their characteristics
Types of flip-flop (10 minutes)
Truth table of all flip flops (10 minutes)
Characteristic table(10 minutes)
Excitation table(10 minutes)
Implementing flip-flops using NAND and NOR gates
Truth table of SR flip flops (5minutes)
28 Excitation table(10 minutes)
Truth table of JK flip flops (5 minutes)
Truth table of D flip flops (5 minutes)
29
Truth table of T flip flops (5 minutes)
Realization of flip-flops
procedure to convert one flip to another (10 minutes)
truth table , excitation table identification( 10 minutes)
30
conversion table formation and realization (10 minutes)
logic diagram formation (20 minutes)
31 Introduction to counters and their applications (5 minutes)
Asynchronous counters: definition, operation, and timing analysis(5 minutes)
Synchronous counters: definition, operation, and timing analysis(5 minutes)
Modulo-n counters and their significance
Page 8 of 14
State Diagram ( 5 minutes)
State Table (10 minutes)
Design based on derived boolean expression (10)
Introduction to shift registers and their applications (5 minutes)
Shift register types:
serial-in-serial-out (SISO) (5 minutes)
serial-in-parallel-out (SIPO) (5 minutes)
parallel-in-serial-out (PISO) (5 minutes)
32
parallel-in-parallel-out (PIPO) (5 minutes)
Universal Shift Register:
Definition (5 minutes)
Operation (15 minutes)
Applications (5 minutes)
Ring Counter:
Definition(5 minutes)
Johnson Counter: definition, operation, and applications
Definition(5 minutes)
33
Mealy model
Moore models
Introduction of FSM (10 minutes)
FSM formation (10 minutes)
34 Realization of FSM using simple logic (10 minutes)
merger graph – conceptual realization (10 minutes)
Applications of FSM (10 minutes)
35 Buffer Lecture – Unit IV
Basic PLD’s –
ROM (5 minutes)
PROM (10 minutes)
PLA (10 minutes)
36
PAL. (10 minutes)
Realization of switching function using PROM
Programming Table (10 minutes)
realization (5 minutes)
37 Realization of switching function using PLA
Page 9 of 14
minterm segregation (10 minutes)
combinational circuit programming
Real time example programming using PLA
38
Idea pitching using PLA
Realization of switching function using PAL
39
combinational circuit programming
Real time example programming using PAL
40
Idea pitching using PLA
41 Buffer Lecture -Unit V
42 Buffer Lecture
11.Lab Wise Plan
No. Content Planned [ Instruction: 30 minutes] [ Exercise : 1h: 20 minutes]
1
Realization of Logic gates
Tinker cad introduction (20 minutes)
IC numbers and Internal Logic (20 minutes)
Logic gates programming and truth table verification ( 60 minutes)
Assessment (10 minutes)
2
Minimization of Boolean functions and realization using logic gates
Page 10 of 14
Theoretical approach
Truth table formation (10 minutes)
logic diagram (10 minutes)
3
Realization of logic gates using universal gates
4
Design of Half adder, Full adder, Half subtractor and Full subtractor
5
Design of Multiplexer, Demultiplexer
6
Buffer Lab – Cycle I
7
Design of Comparators
Page 11 of 14
8
Design of Encoder, Decoder
9
Design of Code converters
10
Conversion of one flip to another flip and its realization.
11
Design of 2-bit counters
12
Design of Up- Down Counter
Page 12 of 14
13
Design of shift registers
14 Buffer Lab – Cycle II
12.Evaluation Components
Components of Course Evaluation Percentage

Mid Term Examination 15%
End Term Examination 25%
Continuous Lab Evaluation 20%
Continuous Tutorial Evaluation -
Lab Exam 25%
Quiz 5%
Assignment/Certification 10%
Project/ Hackathon -
Any Other Assessment -
14.Proposed Industry Talks: Invited Talk on Digital Electronics and its applications by Mr.Ranjith
Kannan , Senior Manager , Analog Devices inc., Banglore
15.Start-ups related to the Course:

1. Smart Home Automation
2. Wearable Technologies
3. Educational electronic kits
4. Electronic health monitoring
5. Electronic waste management
16.Certification Mapping:
1. Certified Electronics Technician (CET)
2. Certified Digital Systems Technician (CDST)
3. NI Certified LabVIEW Associate Developer (CLAD)
4. Online Course Certifications Coursera, Udemy, and edX offer online courses related to digital
electronics.
17.Software/Tools Used: Tinker CAD
18.Hardware/Devices Used: NA
Page 13 of 14
19.Proposed Case Studies:
1. Smart home automation
2. Smart agriculture solution
3. Robotics for assisted life
4. Digital electronics for education
20.Advanced Research Topics: NA
21.Attendance Policy
1. At least 75% attendance in the course is mandatory
2. A maximum of 5% shall be allowed under medical grounds and 5% on representing the
University on official events outside like sports, hackathons, NCC, NSS etc.
3. Students with less than 65% of attendance shall be prevented from writing the final assessment.
22.Academic Dishonesty & Plagiarism

Plagiarism is "to offer work or ideas from another source as one's own, with or without
authorization of the source author(s), directly by verbatim copying or by usage of any AI
software" (i.e., with or without permission from the original author). In certain cases,
authorization might be provided for the usage of other sources through written permission
may not be considered as plagiarism. It is a serious academic offence which should be
avoided, the following method will be adopted to evaluate plagiarism in submitted documents
including assignments, material, class test content and other similar academic documents.
Level 1: Similarities up to 20% - Student will be asked to revise the document and resubmit
for evaluation, once chance will be provided to revise.
Level 2: Similarities above 20% to 40%- Student will be warned and one chance will be
provided to revise the document and resubmit.
Level 3: Similarities above 40% and above: If the plagiarism level is more than 40% student
will get a Fail grade.
23.Instructor Responsible for Lecture PPTs Preparation : Mr.Chakradhar
24.Instructor Responsible for Preparation of Lab Assignments :

Dr.Syed Nageena Parveen
25.Instructor Responsible for Preparation of Tutorial Sheet : NA
26.Any Other Instructor wise Responsibility:

Course assignments and assessments (section wise)
1. Dr.L.M.I.Leo Joseph - 2 sections
2. Mr.Chakradhar - 1 section
3. Mr.Sagar – 1 section
4. Dr.Syed Nageena Parveen – 1 section
Page 14 of 14
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COURSE PLAN

Course Coordinator : Dr.L.M.I.Leo Joseph

1. Dr. L.M.I. Leo Joseph

Course Type : Professional Core

Semester and Year : III Semester and II Year

School : School of Engineering

Department : Department of Electronics and Communication

DATE THIS COURSE

Course Articulation Matrix

Boolean Algebra and Minimization of Switching Functions

Combinational Logic Design:

Definition, Design procedure – Adders-Subtractors -Serial adder / Subtractor - Parallel adder /

6.STUDIO WORK / LABORATORY EXPERIMENTS:

1. Realization of Logic gates

1. Digital Design: Principles and Practices,,Wakerly,4th edition, Pearson Education

2. Fundamentals of Logic Design, C. H. Roth, L. L. Kinney, 7th edition, Cengage Learning.

9.MOOC COURSES (Reference to the Course):

10.Lecture Wise Plan

No. Content Planned

Review of number system (10 minutes),

Introduction to logic gates (10 minutes)

11.Lab Wise Plan

No. Content Planned [ Instruction: 30 minutes] [ Exercise : 1h: 20 minutes]

Components of Course Evaluation Percentage

15.Start-ups related to the Course:

17.Software/Tools Used: Tinker CAD

20.Advanced Research Topics: NA

22.Academic Dishonesty & Plagiarism

23.Instructor Responsible for Lecture PPTs Preparation : Mr.Chakradhar

24.Instructor Responsible for Preparation of Lab Assignments :

25.Instructor Responsible for Preparation of Tutorial Sheet : NA

26.Any Other Instructor wise Responsibility:

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