21-CP-6 (Report12) DLD

UNIVERSITY OF ENGINEERING AND
TECHNOLOGY, TAXILA
Lab Report 12
Digital Logic Design Lab
Name: Alina Gulzar
Reg No.: 21-CP-06
Section: Omega
Department: Computer Engineering
Due Date: 14th August 2022

EXPERIMENT #12
DATA FLOW MODELING
Objective:
To understand and write Verilog code for small modules using data flow modeling.
Apparatus List:
• Icarus Verilog installed on PC
LAB Tasks:
1. Write Verilog Code for 2x1 and 4x1 Mux along with Test Bench and simulate it on Icarus
Verilog.
2. Write Verilog Code for 4 bit Adder using data flow modeling along with Test Bench and
simulate it on Icarus Verilog.
3. Write Verilog Code for Comparator along with Test Bench simulate it on Icarus Verilog
Design Methodology:
• First of all, we have to create a folder so that all the related files are in the same folder.
• Open Notepad, and write the Verilog code, save that notepad file in [module_name.v]
extension. The name of file and name of module must be same. As Verilog HDL is the case
sensitive Language so, a smallest mistake will cause an error.
• Again open notepad and write a test bench for the code file and save this file as syntax:
[module_nametb.v].
• Now, copy both files and open Local Disk: C → iverilog → bin → Paste the files.
• Click on the address bar.
• Write cmd in the bar and press enter key.
• A new interphase is opened…

• Now we have to write the commands, write → iverilog → -o → design name → test
bench file name (tb.v) → verilog code file name (.v) → Press Enter key.
• If there is no error present in the file, then write → vvp → design name → Press enter key.
• Now the vcd file is ready for the output.
• Copy the vcd file, and open Local Disk: C → iverilog → gtkwave → Paste the files.
• Click on the address bar.
• Write cmd in the address bar.
• Write → gtkwave → design name → Press Enter.

• The see the output on the gtkwave analyser.
Truth Table, assumptions, conventions, definitions, Karnaugh Map(s), algebraic simplification

steps, etc.
• Mux (2x1)
Verilog Code:
module mux21(Y, D0, D1, S);
output Y;
input D0, D1, S;
assign Y= (S) ? D1 : D0 ;
endmodule
Test Bench:
module mux21tb;
wire out;
reg d0, d1, s;
mux21 name(.Y(out), .D0(d0), .D1(d1), .S(s));
initial
begin
d0=1'b0;
d1=1'b0;
s=1'b0;
#100 $finish;
end
always #40 d0=~d0;
always #20 d1=~d1;
always #10 s=~s;
always@(d0 or d1 or s)
$monitor("At time = %t, Output = %d", $time, out);
initial
begin
$dumpfile ("mux21tb.vcd");
$dumpvars (0, mux21tb);
end
endmodule
Simulation:
• Mux (4x1)
Verilog Code:
module mux41 ( input a,
input b,
input c,
input d,
input s0, s1,
output out);
assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);
endmodule
Test Bench:
module mux41tb;
wire out;
reg a;
reg b;
reg c;
reg d;
reg s0, s1;
mux41 name(.out(out), .a(a), .b(b), .c(c), .d(d), .s0(s0), .s1(s1));
initial
begin
a=1'b0; b=1'b0; c=1'b0; d=1'b0;
s0=1'b0; s1=1'b0;
#500 $finish;
end
always #40 a=~a;
always #20 b=~b;
always #10 c=~c;
always #5 d=~d;
always #80 s0=~s0;
always #160 s1=~s1;
always@(a or b or c or d or s0 or s1)
$monitor("At time = %t, Output = %d", $time, out);
initial
begin
$dumpfile ("mux41tb.vcd");
$dumpvars (0, mux41tb);
end
endmodule
Simulation:
• 4-bit Adder
Verilog Code:
module adder4bit (sum, Cout, A, B, Cin);
input [3:0] A, B;
input Cin;
output [3:0] sum;
output Cout;
assign {Cout, Sum} = A + B + Cin;
endmodule
Test Bench:
module adder4bittb ( );
wire [3:0] sum, Cout;

reg [3:0] A, B;
reg Cin;
adder4bit DUT (.sum(sum) , .Cout(Cout[0]), .A(A), .B(B), .Cin(Cin));
initial
begin
A=1'b0; B=1'b0; Cin=1'b0;

#10 A=1'b0; B=1'b0; Cin=1'b1;
#10 A=1'b0; B=1'b1; Cin=1'b0;
#10 A=1'b0; B=1'b1; Cin=1'b1;
#10 A=1'b1; B=1'b0; Cin=1'b0;
#10 A=1'b1; B=1'b0; Cin=1'b1;
#10 A=1'b1; B=1'b1; Cin=1'b0;
#10 A=1'b1; B=1'b1; Cin=1'b1;
end
initial
begin
$dumpfile ("adder4bittb.vcd");
$dumpvars (0, adder4bittb);
end
endmodule
Simulation:
• Comparator
Verilog Code:
module cmp (EQ, LT, GT, In1, In2);
input In1, In2;

output EQ, LT,GT;
assign LT = (In1 < In2) ? 1'b1 : 1'b0 ;

assign EQ = (In1 == In2) ? 1'b1 : 1'b0 ;
assign GT = (In1 > In2) ? 1'b1 : 1'b0 ;
endmodule
Test Bench:
module cmptb;
reg In1 , In2;

wire LT, EQ, GT;
integer i;
cmp DUT(EQ, LT, GT, In1, In2);
initial begin
for (i=0;i<4;i=i+1)
begin
In1 = i;
In2 = i + 1;
#20;
end
for (i=0;i<4;i=i+1)
begin
In1 = i;
In2 = i;
#20;
end
for (i=0;i<4;i=i+1)
begin
In1 = i+1;
In2 = i;
#20;
end
end
initial
begin
$dumpfile ("cmptb.vcd");
$dumpvars (0, cmptb);
end
endmodule
Simulation:
Results:
We have verified the truth table of Mux (2x1 and 4x1) , 4-bit adder and comparator. Their outputs
are correct.
Conclusion:
Dataflow modelling uses the functions that determine how the circuit operates, instead of using
the gate structure of the circuit. Dataflow modelling is becoming more and more well-liked as
a design method because of the emergence of sophisticated logic synthesis tools. By using this
method, the circuit designer can focus on enhancing data flow across the circuit.

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UNIVERSITY OF ENGINEERING AND

Reg No.: 21-CP-06

Department: Computer Engineering

Due Date: 14th August 2022

• Icarus Verilog installed on PC

• Write cmd in the bar and press enter key.

• A new interphase is opened…

• Write cmd in the address bar.

• Write → gtkwave → design name → Press Enter.

Truth Table, assumptions, conventions, definitions, Karnaugh Map(s), algebraic simplification

assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);

reg s0, s1;

mux41 name(.out(out), .a(a), .b(b), .c(c), .d(d), .s0(s0), .s1(s1));

a=1'b0; b=1'b0; c=1'b0; d=1'b0;

always #40 a=~a;

always #20 b=~b;

always #10 c=~c;

always #80 s0=~s0;

always #160 s1=~s1;

$monitor("At time = %t, Output = %d", $time, out);

$dumpvars (0, mux41tb);

assign {Cout, Sum} = A + B + Cin;

wire [3:0] sum, Cout;

adder4bit DUT (.sum(sum) , .Cout(Cout[0]), .A(A), .B(B), .Cin(Cin));

A=1'b0; B=1'b0; Cin=1'b0;

input In1, In2;

assign LT = (In1 < In2) ? 1'b1 : 1'b0 ;

reg In1 , In2;

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