MODULE-4

4.1 Op-amp DC Amplifier

The resistors R1 and R2 provide negative feedback. The input signal VIN is connected to the
inverting terminal and the non-inverting terminal is grounded.
4.2 Op-amp AC Amplifier
 (1) Weighted resistor DAC

The op-amp is used as an inverting amplifier. The resistor RF provides negative feedback. The
above circuit uses four-bit digital data. Each binary bit is connected through a toggle switch as
shown in the figure.
If the switch is closed to lower position the input is VR (taken as logic 1) and if the switch is closed
to top position, then the input connected is 0V (this is considered as logic 0).
The top most toggle switch corresponds to least significant bit b0 and the bottom most toggle switch
corresponds to most significant bit b3.
The resistor connected to bit b0 is R. For other bits the value of the resistor is adjusted to match he
weightage of the corresponding binary bit.
Disadvantage:
• We need resistors of different values and it is difficult to find required resistors.
 • As the number of bits of input data is increased, we need still more number of resistors.

The output voltage for different values of binary data can be found as follows:
Let VR = 5V; RF = 1 K𝛺; R = 10 K𝛺

For different binary data, the output voltage can be tabulated as follows:
 (2) DAC with R and 2R resistors

The above circuit uses op-amp like an inverting amplifier. All input binary bits are connected
through a network which is a combination to resistor R and 2R as shown in the figure. The resistor
RF provides negative feedback.
Each binary bit is connected through a toggle switch as shown in the figure.
If the switch is closed to left position the input is VR (taken as logic 1) and if the switch is closed
to right position, then the input connected is 0V (this is considered as logic 0).
The right most toggle switch corresponds to most significant bit b3 and the left most toggle switch
corresponds to least significant significant bit b0.
To find VO
Since the circuit contains multiple inputs, the output can be found by considering one input at a
time and treating the other inputs as zero. Then, the final output can be found as sum of individual
outputs.
Case:1
Consider only b3:
Take b3 =1; b2 = 0; b1 = 0; b0 = 0
The circuit can be redrawn as follows.
The above circuit can be simplified by network reduction method as follows:

Case:2
Consider only b2:
Take b3 =0; b2 = 1; b1 = 0; b0 = 0
By similar method, the output voltage can be expressed as:

Case:3
Consider only b1:
Take b3 =0; b2 = 0; b1 =1; b0 = 0
By similar method, the output voltage can be expressed as:

Case:4
Consider only b0:
Take b3 =0; b2 = 0; b1 =0; b0 = 1
By similar method, the output voltage can be expressed as:

The complete output voltage can be expressed as:

4.4 Successive Approximation ADC

The following figure considers 8-bit ADC. The register shown contains 8 bits b7 to b0.
4.5 Small Signal Half Wave Rectifier
A rectifier is built using a diode. But, the voltage drop across the diode will reduce the magnitude
of output voltage by an amount equal to the voltage drop across the diode. A typical voltage drop
across the diode is about 0.7V. Therefore, a simple diode rectifier is not suitable for rectifying the
input signals whose magnitude is less than 0.7V. For this reason we use precision rectifier with
op-amp as a part of the rectifier circuit.
There are two types small signal half wave rectifiers that can be considered:
• Positive small signal half wave rectifier.
• Negative small signal half wave rectifier.
(1) Positive small signal half wave rectifier:

The op-amp is used as a non-inverting amplifier with the input connected to the non-inverting
terminal. The output terminal is directly connected to the inverting terminal which provides
negative feedback. Since there are no resistors in the feedback circuit, this circuit is called voltage
follower. A diode is connected as shown in the figure between output of op-amp and load resistor.
Working:
Thus, this circuit provides positive output voltage during positive half cycle of the input and zero
v f y H “ v f v f ”
 (2) Negative small signal half wave rectifier:

The op-amp is used as a non-inverting amplifier with the input connected to the non-inverting
terminal. The output terminal is directly connected to the inverting terminal which provides
negative feedback. Since there are no resistors in the feedback circuit, this circuit is called voltage
follower. A diode is connected as shown in the figure between output of op-amp and load resistor.
Working:
Thus, this circuit provides negative output voltage during negative half cycle of the input and zero
v f y H “ v f v f ”
4.6 Absolute Value Output Circuit
The absolute value output circuit provides:
(1) Positive output voltage both during positive and negative half cycle of the input.
(2) The magnitude of output voltage is same as that of the input voltage.
Circuit diagram:

The input signal is connected to both non-inverting and inverting terminal of op-amp. The diodes
D1 and D2 ensure that during positive half cycle the input is connected to the non-inverting terminal
and during negative half cycle, the input is connected to the inverting terminal. Another diode D3
is connected in the feedback path. The diode D3 is used to offset the voltage drop of D1 and D2.
The values of all resistors connected to inverting terminal, non-inverting terminal and feedback
path are equal.
Working:
During positive half cycle:
4.7 Active filters
4.8 First Order Low-Pass Butterworth Filter
Concept:
• A filter is realized by using R-C network.
• If we use a single R-C network, then it is called first order filter.

• We use op-amp for eliminating the loading effect.

• The op-amp is connected as non-inverting amplifier.
• The resistors R1 and R2 provide the negative feedback.
To find 𝒗𝒐
From the above circuit, the output voltage can be expressed as:

applying voltage divider rule at the non-inverting terminal:

4.9 Second Order Low-Pass Butterworth Filter

• Second order filter consists of two sections R-C networks.

• The op-amp is used to eliminate the loading effect
• The gain of the circuit is controlled be the resistors R1 and R2.
• The higher cut-off frequency can be found as :
4.10 First Order High Pass Butterworth Filter

The frequency response of high pass filter is as shown above. The input signal whose frequency is
less than fL is blocked and allows only the input signal with frequency greater than the lower cut-
off frequency. Hence it is called high pass filter.
 • A filter is realized by using R-C network.
• If we use one R-C networks, it is called first order filter.
• We use op-amp for eliminating the loading effect.
• The op-amp is connected as non-inverting amplifier.
• The resistors R1 and RF provide the negative feedback.
To find output voltage vo
To find lower cut-off frequency:
4.11 Second Order High Pass Butterworth Filter
4.11 Band Pass Filter

The first op-amp in the above circuit is a low-pass filter. The output of low-pass filter is fed to the
second circuit which is a high pass filter.
The low pass filter will block the input signals whose frequency is greater than fH. The high pass
filter will block input signals whose frequency is less than fL. Since fH is lower than fL only the
input signals whose frequency lies in between fH and fL will passed to the output. Hence it is called
pass band filter.
4.13 Band Reject Filter
This filter is required to block the input signals whose frequency lies in between two cut-off values.
This filter is a combination of a low pass filter and a high pass filter.
The output of a low pass filter and the output of a high pass filter can be combined to from a band
reject filter. This is depicted in the following frequency response curves.
In the above circuit, the op-amp A1 is a low-pass filter the output of VL of the low pass filter will
have a higher cut-off frequency of fH.
1
fH = 2πRC

the opamp A2 is a high pass filter. VH is the output of high pass filter. The cut-off frequency of
high pass filter is fL.
 1
fL = 2πR1 C1

The op-amp A3 is an inverting adder which combines the output of low pass and high pass filters
to give required frequency response of band reject filter. The output of A3 is found as follows.

555 timer consists of:

• Three equal resistors connected in series to the DC supply VCC. Therefore, the voltage
across each resistor is VCC/3.
• The voltage at non-inverting terminal of comparotr-2 is VCC/3. The inverting terminal is
connected to the “Trigger” pin.
 • The voltage at the inverting terminal of comparator-1 is 2VCC/3 and non-inverting terminal
is connected to “Threshold” pin.
• The output of omparator-1 is connected to Reset pin of flip-flop and Set pin of the flip-flop
is connected to the output of compaator-2.
• The transistor Q2 is connected to the “Discharge” pin. The base of the transistor Q2 is
connected to output of flip-flop.
Monostable connections:
• A resistor R and capacitor C are connected in series to the DC supply.
• The junction of R and C is connected to the Threshold pin and also to Discharge pin.
Operation:
• In the normal mode, the flip flop is in reset condition and the output of the circuit is LOW.
• The circuit operation begins with the application of Trigger pulse as shown in the figure.
• With the application of trigger pulse the voltage at the inverting terminal of comarator-2
becomes low and the output of comparator-2 becomes HIGH. This will SET the flip flop
and the output becomes HIGH. At the same time the voltage at the base of Q2 becomes
LOW and the transistor becomes OFF.
• When Q2 is OFF, the capacitor charges through R. The voltage across the capacitor
increases exponentially. When the capacitor voltage becomes greater than or equal to
2VCC/3, the output of comparator-1 becomes HIGH.
• Then, the flip-flop will be RESET and the output becomes LOW.
• Since flip-flop is RESET, the voltage at the base of the transistor becomes HIGH and the
transistor becomes ON.
• The capacitor discharges through the transistor.
• The circuit will remain in the same state until triggered again.
Waveforms:
555 timer consists of:
• Three equal resistors connected in series to the DC supply VCC. Therefore, the voltage
across each resistor is VCC/3.
• The voltage at non-inverting terminal of comparotr-2 is VCC/3. The inverting terminal is
connected to the “Trigger” pin.
• The voltage at the inverting terminal of comparator-1 is 2VCC/3 and non-inverting terminal
is connected to “Threshold” pin.
• The output of omparator-1 is connected to Reset pin of flip-flop and Set pin of the flip-flop
is connected to the output of compaator-2.
• The transistor Q2 is connected to the “Discharge” pin. The base of the transistor Q2 is
connected to output of flip-flop.
Monostable connections:
• A resistor RA, RB and capacitor C are connected in series to the DC supply.
• The junction of RA and RB is connected to the Discharge pin.
• The junction of RB and C is connected to Trigger pin and Threshold pin.
Operation:
• Let the flip-flop be SET condition. Then the output of the circuit is HIGH and base signal
of Q2 is LOW. This will turn OFF the transistor Q2.
• When Q2 is OFF, the capacitor charges through RA and RB and the capacitor voltage
increases exponentially.
 • When the capacitor voltage is greater than 2VCC/3, the output of comaprtor-1 becomes
HIGH and the flip-flop will be RESET. This makes the output of the circuit LOW and base
signal of Q2 becomes HIGH.
• The transistor Q2 is turned ON. Then the capacitor discharges through RB and Q2. With the
discharge of Q2, the capacitor voltage decreases exponentially. When the capacitor voltage
becomes less than VCC/3, the output of comaparator-2 becomes HIGH.
• This will SET the flip-flop and the output becomes HIGH. Then the signal at the base of
Q2 will become LOW and Q2 becomes OFF. Then the capacitor starts charging again.
• This process of capacitor charging up to 2VCC/3 and discharging up to VCC/3 will continue.
This results the output of the circuit toggling between HIGH and LOW state. Thus, the
output is a rectangular wave.
Waveforms: