Mipspro Assembly Language Programmer'S Guide: Document Number 007-2418-003

MIPSpro™ Assembly Language
Programmer’s Guide
Document Number 007-2418-003

CONTRIBUTORS
Written by Larry Huffman, revised by Wendy Ferguson

Edited by Larry Huffman
Production by Kirsten Johnson
Engineering contributions by Bean Anderson, Jim Dehnert, Suneel Jain, Michael
Murphy
Dedicated to the memory of our friend, Larry Huffman.
© Copyright 1997 Silicon Graphics, Inc.— All Rights Reserved

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MIPSpro™ Assembly Language Programmer’s Guide

Document Number 007-2418-003
Contents
List of Figures ix
List of Tables xi
About This Guide xiii

Audience xiv
Topics Covered xiv
1. Registers 1
Register Format 1
General Registers 2
Special Registers 4
Floating-Point Registers 5
Floating-Point Condition Codes 7
2. Addressing 9
Instructions to Load and Store Unaligned Data 9
Address Formats 11
Address Descriptions 11
3. Exceptions 13
Main Processor Exceptions 13
Floating-Point Exceptions 14
iii
Contents
4. Lexical Conventions 15
Tokens 16
Comments 16
Identifiers 16
Constants 17
Scalar Constants 17
Floating-Point Constants 18
String Constants 19
Multiple Lines Per Physical Line 20
Section and Location Counters 20
Statements 22
Label Definitions 22
Null Statements 23
Keyword Statements 23
Expressions 23
Precedence 24
Expression Operators 25
Data Types 26
Type Propagation in Expressions 28
Relocations 28
5. The Instruction Set 31

Instruction Classes 32
Reorganization Constraints and Rules 32
Instruction Notation 32
Instruction Set 34
Load and Store Instructions 34
Load Instruction Descriptions 36
Store Instruction Descriptions 40
Computational Instructions 44
Computational Instructions 44
Computational Instruction Descriptions 48
iv
Contents
Jump and Branch Instructions 59

Jump and Branch Instructions 59
Jump and Branch Instruction Descriptions 61
Special Instructions 65
Coprocessor Interface Instructions 66
Coprocessor Interface Summary 66
Coprocessor Interface Instruction Descriptions 67
6. Coprocessor Instruction Set 71

Instruction Notation 72
Floating-Point Instructions 73
Floating-Point Formats 73
Floating-Point Load and Store Formats 74
Floating-Point Load and Store Descriptions 75
Floating-Point Computational Formats 76
Floating-Point Computational Instruction Descriptions 80
Floating-Point Relational Operations 81
Floating-Point Relational Instruction Formats 84
Floating-Point Relational Instruction Descriptions 86
Floating-Point Move Formats 89
Floating-Point Move Instruction Descriptions 90
System Control Coprocessor Instructions 91
System Control Coprocessor Instruction Formats 91
System Control Coprocessor Instruction Descriptions 92
Control and Status Register 93
Exception Trap Processing 95
Invalid Operation Exception 95
Division-by-zero Exception 96
Overflow Exception 96
Underflow Exception 97
Inexact Exception 98
Unimplemented Operation Exception 98
Floating-Point Rounding 99
v
Contents
7. Linkage Conventions 101

Introduction 102
Program Design 102
The Stack Frame 103
The Shape of Data 110
Examples 111
Example of Non-Leaf Procedure 111
Example of a Leaf Procedure 113
Writing Assembly Language Code 114
8. Pseudo Op-Codes 115
Index 129
vi
List of Figures
Figure 4-1 Section and Location Counters 21

Figure 6-1 Floating-Point Formats 73
Figure 6-2 Floating Control and Status Register 31 93
Figure 7-1 Stack Organization for –32 105
Figure 7-2 Stack Organization for –n32 and –64 106
Figure 7-3 Stack Example 107
vii
List of Figures
viii
List of Tables
Table 1-1 General (Integer) Registers (–32) 2

Table 1-2 General (Integer) Registers (–n32 and –64) 3
Table 1-3 Special Registers 4
Table 1-4 Floating-Point Registers (–32) 5
Table 1-5 Floating-Point Registers (–64) 6
Table 1-6 Floating-Point Registers (–n32) 6
Table 2-1 Address Formats 11
Table 2-2 Assembler Addresses 11
Table 4-1 Backslash Conventions 19
Table 4-2 Expression Operators 25
Table 4-3 Data Types 26
Table 4-4 Relocations 29
Table 5-1 Load and Store Format Summary 34
Table 5-2 Load Instruction Descriptions 36
Table 5-3 Load Instruction Descriptions for MIPS3/4 Architecture Only 39
Table 5-4 Store Instruction Descriptions 41
Table 5-5 Store Instruction Descriptions for MIPS3/4 Architecture Only 43
Table 5-6 Computational Format Summaries 44
Table 5-7 Computational Instruction Descriptions 48
Table 5-8 Computational Instruction Descriptions for MIPS3/4 Architecture 55
Table 5-9 Jump and Branch Format Summary 59
Table 5-10 Jump and Branch Instruction Descriptions 61
Table 5-11 Special Instruction Descriptions 65
Table 5-12 Coprocessor Interface Formats 66
Table 5-13 Coprocessor Interface Instruction Descriptions 67
ix
List of Tables
Table 6-1 Floating-Point Load and Store Formats 74

Table 6-2 Floating-Point Load and Store Descriptions 75
Table 6-3 Floating-Point Computational Instructions 76
Table 6-4 Floating-Point Computational Instructions 78
Table 6-5 Floating-Point Computational Instruction Descriptions 80
Table 6-6 Floating-Point Relational Operators 82
Table 6-7 Floating-Point Relational Instructions 84
Table 6-8 Floating-Point Relational Instruction Descriptions 86
Table 6-9 Floating-Point Move Formats 89
Table 6-10 Floating-Point Move Instruction Descriptions 90
Table 6-11 System Control Coprocessor Instruction Formats 91
Table 6-12 System Control Coprocessor Instruction Descriptions 92
Table 7-1 Parameter Passing (–32) 108
Table 7-2 Parameter Passing (–n32 and –64) 109
Table 8-1 Pseudo Op-Codes 115
x
About This Guide
This book describes the assembly language supported by the RISCompiler system, its
syntax rules, and how to write assembly programs. For information on assembling and
linking an assembly language program, see the MIPSpro Compiling and Performance
Tuning Guide.
The assembler converts assembly language statements into machine code. In most
assembly languages, each instruction corresponds to a single machine instruction;
however, some assembly language instructions can generate several machine
instructions. This feature results in assembly programs that can run without modification
on future machines, which might have different machine instructions.
In this release of operating system and compiler software, the assembler supports
compilations in –o32, –n32, and –64 mode. Some of the implications of the different data
sizes are explained in this book. For additional information, please refer to the MIPSpro
64-Bit Porting and Transition Guide.
Many assembly language instructions have direct equivalents to machine instructions.

For more information about the operations of a specific architecture, see the manual that
is appropriate for your machine, for instance, the MIPS R4000 Microprocessor User’s
Manual or the MIPS R10000 Microprocessor User’s Manual.
xi
About This Guide
Audience
This book assumes that you are an experienced assembly language programmer. The
assembler produces object modules from the assembly instructions that the C, and
Fortran 77 compilers generate. It therefore lacks many functions normally present in
assemblers. You should use the assembler only when you must:
• Maximize the efficiency of a routine, which might not be possible in C, Fortran 77,
or another high-level language; for example, to write low-level I/O drivers.
• Access machine functions unavailable in high-level languages or satisfy special
constraints such as restricted register usage.
• Change the operating system.
• Change the compiler system.
Topics Covered
This book has these chapters:

• Chapter 1, “Registers,” describes the format for the general registers, the special
registers, and the floating-point registers.
• Chapter 2, “Addressing,” describes how addressing works.
• Chapter 3, “Exceptions,” describes exceptions you might encounter with assembly
programs.
• Chapter 4, “Lexical Conventions,” describes the lexical conventions that the
assembler follows.
• Chapter 5, “The Instruction Set,” describes the main processor’s instruction set,
including notation, load and store instructions, computational instructions, and
jump and branch instructions.
xii
About This Guide
• Chapter 6, “Coprocessor Instruction Set,” describes the coprocessor instruction

sets.
• Chapter 7, “Linkage Conventions,” describes linkage conventions for all
supported high-level languages. It also discusses memory allocation and register
use.
• Chapter 8, “Pseudo Op-Codes,” describes the assembler’s pseudo-operations
(directives).
• An “Index” that contains index entries for this publication.
xiii
Chapter 1
1. Registers
This chapter describes the organization of data in memory, and the naming and usage
conventions that the assembler applies to the CPU and FPU registers. This chapter covers
the following topics:
• “Register Format” on page 1
• “General Registers” on page 2
• “Special Registers” on page 4
• “Floating-Point Registers” on page 5
• “Floating-Point Condition Codes” on page 7
See Chapter 7, “Linkage Conventions,” for information on register use and linkage.
Register Format
The CPU uses four data formats: a 64-bit doubleword, a 32-bit word, a 16-bit halfword
and an 8-bit byte. Byte ordering within each of the larger data formats – doubleword,
word or halfword – the CPU’s byte ordering scheme (or endian issues), affects memory
organization and defines the relationship between address and byte position of data in
memory.
For R4000 and earlier systems, byte ordering is configurable into either big-endian or
little-endian byte ordering (configuration occurs during hardware reset). When
configured as a big-endian system, byte 0 is always the most-significant (lifetimes) byte.
When configured as a little-endian system, byte 0 is always the least-significant
(rightmost byte).
The R8000 CPU, at present, supports big-endian only.
1
Chapter 1: Registers
General Registers
For the MIPS1 and MIPS2 architectures, the CPU has thirty-two 32-bit registers. In the
MIPS3 architecture and above, the size of each of the thirty-two integer registers is 64-bit.
Table 1-1 and Table 1-2 summarize the assembler’s usage, conventions and restrictions
for these registers. The assembler reserves all register names; you must use lowercase for
the names. All register names start with a dollar sign($).
The general registers have the names $0..$31. By including the file regdef.h (use #include
<regdef.h>) in your program, you can use software names for some general registers.
The operating system and the assembler use the general registers $1, $26, $27, $28, and
$29 for specific purposes. Attempts to use these general registers in other ways can
produce unexpected results.
Table 1-1 General (Integer) Registers (–32)
Register Name Software Name Use and Linkage

(from regdef.h)
$0 Always has the value 0.
$1 or $at Reserved for the assembler.
$2..$3 v0-v1 Used for expression evaluations and to hold the

integer type function results. Also used to pass
the static link when calling nested procedures.
$4..$7 a0-a3 Pass the first 4 words of actual integer type

arguments; their values are not preserved across
procedure calls.
$8..$11 t0-t7 Temporary registers used for expression

$11..$15 t4-t7 or evaluations; their values aren’t preserved across
ta0-ta3 procedure calls.
$16..$23 s0-s7 Saved registers. Their values must be preserved

across procedure calls.
$25 t9 or jp PIC jump register.
$26..27 or k0-k1 Reserved for the operating system kernel.

$kt0..$kt1
2
General Registers
Table 1-1 (continued) General (Integer) Registers (–32)

(from regdef.h)
$28 or $gp gp Contains the global pointer.
$29 or $sp sp Contains the stack pointer.
$30 or $fp fp or s8 Contains the frame pointer (if needed);

otherwise a saved register (like s0-s7).
$31 ra Contains the return address and is used for

expression evaluation.
Note: General register $0 always contains the value 0. All other general registers are
equivalent, except that general register $31 also serves as the implicit link register for
jump and link instructions. See Chapter 7 for a description of register assignments.
Table 1-2 General (Integer) Registers (–n32 and –64)

(from regdef.h)
$0 Always has the value 0.
$1 or $at Reserved for the assembler.
$2..$3 v0-v1 Used for expression evaluations and to hold the

integer type function results. Also used to pass
the static link when calling nested procedures.
$4..$7 a0-a3 Pass up to 8 words of actual integer type

$8..$11 a4-a7 or arguments; their values are not preserved across
ta0-ta3 procedure calls.
$12..$15 t0-t3 Temporary registers used for expression

evaluations; their values aren’t preserved across
procedure calls.
$16..$23 s0-s7 Saved registers. Their values must be preserved

$25 t9 or jp PIC jump register.
$26..27 or k0-k1 Reserved for the operating system kernel.

$kt0..$kt1
3
Table 1-2 (continued) General (Integer) Registers (–n32 and –64)

(from regdef.h)
$28 or $gp gp Contains the global pointer.
$29 or $sp sp Contains the stack pointer.
$30 or $fp fp or s8 Contains the frame pointer (if needed);

otherwise a saved register (such as s0-s7).
$31 ra Contains the return address and is used for

expression evaluation.
Special Registers
The CPU defines three special registers: PC (program counter), HI and LO, as shown in
Table 1-3. The HI and LO special registers hold the results of the multiplication (mult and
multu) and division (div and divu) instructions.
You usually do not need to refer explicitly to these special registers; instructions that use
the special registers refer to them automatically.
Table 1-3 Special Registers
Name Description
PC Program Counter
HI Multiply/Divide special register holds the most-significant 32

bits of multiply, remainder of divide
LO Multiply/Divide special register holds the least-significant 32

bits of multiply, quotient of divide
Note: In MIPS3 architecture and later, the HI and Lo registers hold 64-bits.
4
Floating-Point Registers
Floating-Point Registers
The FPU has 32 floating-point registers. In –n32 and –64 compiles, each register can hold
either a single-precision (32-bit) or double-precision (64-bit) value. For –32 compiles,
only 16 register values are allowed, specified with the even floating-point registers (for
example, $f4). For –32, the registers are limited to 32 bits, so for double-precision values,
$f0 holds the least-significant half and $f1 holds the most-significant half, but the
combined double-precision value is referenced with $f0. The –n32 register conventions
are different from the –64 convention, to be more compatible with –32. Tables 1-4, 1-5, and
1-6 summarize the assembler’s usage conventions.
Table 1-4 Floating-Point Registers (–32)
Register Software Name Use and Linkage

Name (from fgregdef.h)
$f0..$f2 fv0-fv1 Hold results of floating-point type function ($f0)

and complex type function ($f0 has the real part,
$f2 has the imaginary part.
$f4..$f10 ft0-ft3 Temporary registers, used for expression

evaluation whose values are not preserved across
procedure calls.
$f12..$f14 fa0-fa1 Pass the first two single- or double-precision

actual arguments; their values are not preserved

evaluation, whose values are not preserved
$f20..$f30 fs0-fs5 Saved registers, whose values must be preserved

5
Table 1-5 Floating-Point Registers (–64)
Register Software Name Use and Linkage

Name (from fgregdef.h)
$f0, $f2 fv0,fv1 Hold results of floating-point type function ($f0)

$f1, $f3 ft12,ft13 Temporary registers, used for expression

$f4..$f11 ft0-ft7 evaluation; their values are not preserved across
procedure calls.
$f12..$f19 fa0-fa7 Pass single- or double-precision actual

arguments, whose values are not preserved

evaluation; their values are not preserved across
procedure calls.
$f24..$f31 fs0-fs7 Saved registers, whose values must be preserved

Table 1-6 Floating-Point Registers (–n32)

(from fgregdef.h)
$f0, $f2 fv0,fv1 Hold results of floating-point type function ($f0)

$f1, $f3 ft14,ft15 Temporary registers, used for expression

$f4..$f11 ft0-ft7 evaluation; their values are not preserved across
procedure calls.
$f12..$f19 fa0-fa7 Pass single- or double-precision actual

arguments, whose values are not preserved
$f21,$f23,$f25, ft8-ft13 Temporary registers, used for expression

$f27,$f29,$f31 evaluation; their values are not preserved across
procedure calls.
$f20,$f22,$f24, fs0-fs5 Saved registers, whose values must be preserved

$f26,$f28,$f30 across procedure calls.
6
Floating-Point Condition Codes
Floating-Point Condition Codes
The floating-point condition code registers hold the result of a floating-point

comparison, and then decide whether or not to branch. For –32 compiles, there is only
one register: $fcc0. For –n32 and –64 compiles, there are eight registers available:
$fcc0-$fcc7.
7
Chapter 2
2. Addressing
This chapter describes the formats that you can use to specify addresses. Silicon Graphics
CPUs use a byte addressing scheme. Access to halfwords requires alignment on even
byte boundaries, and access to words requires alignment on byte boundaries that are
divisible by four. Access to doublewords (for 64-bit systems) requires alignment on byte
boundaries that are divisible by eight. Any attempt to address a data item that does not
have the proper alignment causes an alignment exception.
This chapter covers the following topics:

• “Instructions to Load and Store Unaligned Data” on page 9
• “Address Formats” on page 11
• “Address Descriptions” on page 11
Instructions to Load and Store Unaligned Data
The unaligned assembler load and store instructions may generate multiple machine
language instructions. They do not raise alignment exceptions.
These instructions load and store unaligned data:

• Load doubleword left (LDL)
• Load word left (LWL)
• Load doubleword right (LDR)
• Load word right (LWR)
• Store doubleword left (SDL)
9
Chapter 2: Addressing
• Store word left (SWL)

• Store doubleword right (SDR)
• Store word right (SWR)
• Unaligned load doubleword (ULD)
• Unaligned load word (ULW)
• Unaligned load halfword (ULH)
• Unaligned load halfword unsigned (ULHU)
• Unaligned store doubleword (USD)
• Unaligned store word (USW)
• Unaligned store halfword (USH)
These instructions load and store aligned data

• Load doubleword (LD)
• Load word (LW)
• Load halfword (LH)
• Load halfword unsigned (LHU)
• Load byte (LB)
• Load byte unsigned (LBU)
• Store doubleword (SD)
• Store word (SW)
• Store halfword (SH)
• Store byte (SB)
10
Address Formats
Address Formats
The assembler accepts these formats shown in Table 2-1 for addresses. Table 2-2 explains
these formats in more detail.
Table 2-1 Address Formats
Format Address
(base register) Base address (zero offset assumed)
expression Absolute address
expression (base register) Based address
index-register (base register) Based address
relocatable-symbol Relocatable address
relocatable-symbol + expression Relocatable address
relocatable-symbol + expression Indexed relocatable address

(index register)
Address Descriptions
The assembler accepts any combination of the constants and operations described in this
chapter for expressions in address descriptions.
Table 2-2 Assembler Addresses
Expression Address Description
(base-register) Specifies an indexed address, which assumes a zero offset. The

base-register contents specify the address.
expression Specifies an absolute address. The assembler generates the

most locally efficient code for referencing a value at the
specified address.
expression (base-register) Specifies a based address. To get the address, the CPU adds the
value of the expression to the contents of the base-register.
11
Chapter 2: Addressing
Table 2-2 (continued) Assembler Addresses
Expression Address Description
index-register (base-register) Same as expression (base-register), except that the index register
is used as the offset.
relocatable-symbol Specifies a relocatable address. The assembler generates the

necessary instruction(s) to address the item and generates
relocatable information for the link editor.
relocatable-symbol + expression Specifies a relocatable address. To get the address, the

assembler adds or subtracts the value of the expression, which
has an absolute value, from the relocatable symbol. The
assembler generates the necessary instruction(s) to address the
item and generates relocatable information for the link editor.
If the symbol name does not appear as a label anywhere in the
assembly, the assembler assumes that the symbol is external.
relocatable-symbol (index register) Specifies an indexed relocatable address. To get the address,
the CPU adds the index register to the relocatable symbol’s
address. The assembler generates the necessary instruction(s)
to address the item and generates relocatable information for
the link editor. If the symbol name does not appear as a label
anywhere in the assembly, the assembler assumes that the
symbol is external.
relocatable + expression Specifies an indexed relocatable address. To get the address,

the assembler adds or subtracts the relocatable symbol, the
expression, and the contents of the index register. The
assembler generates the necessary instruction(s) to address the
item and generates relocation information for the link editor. If
the symbol does not appear as a label anywhere in the
assembly, the assembler assumes that the symbol is external.
12
Chapter 3
3. Exceptions
This chapter describes the exceptions that you can encounter while running assembly
programs. The system detects some exceptions directly, and the assembler inserts
specific tests that signal other exceptions. This chapter lists only those exceptions that
occur frequently:
• “Main Processor Exceptions” on page 13
• “Floating-Point Exceptions” on page 14
Main Processor Exceptions
The following exceptions are the most common to the main processor:
• Address error exceptions, which occur when a data item is referenced that is not on
its proper memory alignment or when an address is invalid for the executing
process.
• Overflow exceptions, which occur when arithmetic operations compute signed
values and the destination lacks the precision to store the result.
• Bus exceptions, which occur when an address is invalid for the executing process.
• Divide-by-zero exceptions, which occur when a divisor is zero.
13
Chapter 3: Exceptions
Floating-Point Exceptions
The following are the most common floating-point exceptions:

• Invalid operation exceptions which include:
– Magnitude subtraction of infinities, for example: -1.
– Multiplication of 0 by 1 with any signs.
– Division of 0/0 or 1/1 with any signs.
– Conversion of a binary floating-point number to an integer format when an
overflow or the operand value for the infinity or NaN precludes a faithful
representation in the format (see Chapter 4).
– Comparison of predicates that have unordered operands, and that involve
Greater Than or Less Than without Unordered.
– Any operation on a signaling NaN.
• Divide-by-zero exceptions.
• Overflow exceptions occur when a rounded floating-point result exceeds the
destination format’s largest finite number.
• Underflow exceptions these occur when a result has lost accuracy and also when a
nonzero result is between 2Emin (2 to the minimum expressible exponent).
• Inexact exceptions.
14
Chapter 4
4. Lexical Conventions
This chapter discusses lexical conventions for these topics:

• “Tokens” on page 16
• “Comments” on page 16
• “Identifiers” on page 16
• “Constants” on page 17
• “Multiple Lines Per Physical Line” on page 20
• “Section and Location Counters” on page 20
• “Statements” on page 22
• “Expressions” on page 23
• “Relocations” on page 28
This chapter uses the following notation to describe syntax:

• | (vertical bar) means “or”
• [] (square brackets) enclose options
• + indicates both addition and subtraction operations
15
Chapter 4: Lexical Conventions
Tokens
The assembler has these tokens:

• Identifiers
• Constants
• Operators
The assembler lets you put blank characters and tab characters anywhere between
tokens; however, it does not allow these characters within tokens (except for character
constants). A blank or tab must separate adjacent identifiers or constants that are not
otherwise separated.
Comments
The pound sign character (#) introduces a comment. Comments that start with a # extend
through the end of the line on which they appear. You can also use C-language notation
/*...*/ to delimit comments.
The assembler uses cpp (the C language preprocessor) to preprocess assembler code.
Because cpp interprets #s in the first column as pragmas (compiler directives), do not start
a # comment in the first column.
Identifiers
An identifier consists of a case-sensitive sequence of alphanumeric characters, including

these:
• . (period)
• _ (underscore)
• $ (dollar sign)
The first character of an identifier cannot be numeric.
16
Constants
If an identifier is not defined to the assembler (only referenced), the assembler assumes
that the identifier is an external symbol. The assembler treats the identifier like a.globl
pseudo-operation (see Chapter 8). If the identifier is defined to the assembler and the
identifier has not been specified as global, the assembler assumes that the identifier is a
local symbol.
Constants
The assembler has these constants:

• Scalar constants
• Floating-point constants
• String constants
Scalar Constants
The assembler interprets all scalar constants as twos-complement numbers. In 32-bit

mode, a scalar constant is 32 bits. 64 bits is the size of a scalar constant in 64-bit mode.
Scalar constants can be any of the alphanumeric characters 0123456789abcdefABCDEF.
You can use an all or LL suffix to identify a 64-bit constant.
Scalar constants can be one of these constants:

• Decimal constants, which consist of a sequence of decimal digits without a leading
zero.
• Hexadecimal constants, which consist of the characters 0x (or 0X) followed by a
sequence of digits.
• Octal constants, which consist of a leading zero followed by a sequence of digits in
the range 0..7.
17
Floating-Point Constants
Floating-point constants can appear only in .float and .double pseudo-operations

(directives), see Chapter 8, and in the floating-point Load Immediate instructions, see
Chapter 6. Floating-point constants have this format:
+d1[.d2][e|E+d3]
where:
• d1 is written as a decimal integer and denotes the integral part of the floating-point
value.
• d2 is written as a decimal integer and denotes the fractional part of the
floating-point value.
• d3 is written as a decimal integer and denotes a power of 10.
• The “+” symbol is optional.
For example:
21.73E–3
represents the number .02173.
Optionally, .float and .double directives may use hexadecimal floating-point constants
instead of decimal ones. A hexadecimal floating-point constant consists of:
<+ or –> 0x <1 or 0 or nothing> . <hex digits> H 0x <hex digits>
The assembler places the first set of hex digits (excluding the 0 or 1 preceding the decimal
point) in the mantissa field of the floating-point format without attempting to normalize
it. It stores the second set of hex digits into the exponent field without biasing them. It
checks that the exponent is appropriate if the mantissa appears to be demoralizing.
Hexadecimal floating-point constants are useful for generating IEEE special symbols,
and for writing hardware diagnostics.
For example, either of the following generates a single-precision “1.0”:

.float 1.0e+0
.float 0x1.0h0x7f
18
Constants
String Constants
String constants begin and end with double quotation marks (").
The assembler observes C language backslash conventions. For octal notation, the
backslash conventions require three characters when the next character can be confused
with the octal number. For hexadecimal notation, the backslash conventions require two
characters when the next character can be confused with the hexadecimal number (that
is, use a 0 for the first character of a single character hex number).
The assembler follows the backslash conventions shown in Table 4-1.
Table 4-1 Backslash Conventions
Convention Meaning
\a Alert (0x07)
\b Backspace (0x08)
\f Form feed (0x0c)
\n Newline (0x0a)
\r Carriage return (0x0d)
\t horizontal tab (0x09)
\v Vertical feed (0x0b)
\\ Backslash (0x5c)
\" Double quotation mark (0x22)
\’ Single quotation mark (0x27)
\000 Character whose octal value is 000
\Xnn Character whose hexadecimal value is nn
19
Multiple Lines Per Physical Line
You can include multiple statements on the same line by separating the statements with
semicolons. The assembler does not recognize semicolons as separators when they
follow comment symbols (# or /*).
Section and Location Counters
Assembled code and data fall in one of the sections shown in Figure 4-1.
20
Section and Location Counters
.text Text section
.rdata Read-only data section
.data
.lit8 Data sections
.lit4
Small data section, addressed

.sdata
through register $gp
Small read only data section,

.srdata
addressed through $gp
Small bss section, addressed

.sbss
through register $gp
bss (block started by storage)

.bss section, which loads zero-initialized
data
Figure 4-1 Section and Location Counters
The assembler always generates the text section before other sections. Additions to the
text section happen in four-byte units. Each section has an implicit location counter,
which begins at zero and increments by one for each byte assembled in the section.
The bss section holds zero-initialized data. If a .lcomm pseudo-op defines a variable (see
Chapter 8), the assembler assigns that variable to the bss (block started by storage) section
or to the sbss (short block started by storage) section depending on the variable’s size. The
default variable size for sbss is 8 or fewer bytes.
21
The command line option –G for each compiler (C, Pascal, Fortran 77, or the assembler),
can increase the size of sbss to cover all but extremely large data items. The link editor
issues an error message when the –G value gets too large. If a –G value is not specified
to the compiler, 8 is the default. Items smaller than, or equal to, the specified size go in
sbss. Items greater than the specified size go in bss.
Because you can address items much more quickly through $gp than through a more
general method, put as many items as possible in sdata, srdata, or sbss. The size of sdata,
srdata, and sbss combined must not exceed 64 KB.
Statements
Each statement consists of an optional label, an operation code, and the operand(s). The
system allows these statements:
• Null statements
• Keyword statements
Label Definitions
A label definition consists of an identifier followed by a colon. Label definitions assign

the current value and type of the location counter to the name. An error results when the
name is already defined, the assigned value changes the label definition, or both
conditions exist.
Label definitions always end with a colon. You can put a label definition on a line by
itself.
A generated label is a single numeric value (1...255). To reference a generated label, put
an f (forward) or a b (backward) immediately after the digit. The reference tells the
assembler to look for the nearest generated label that corresponds to the number in the
lexically forward or backward direction.
22
Expressions
Null Statements
A null statement is an empty statement that the assembler ignores. Null statements can
have label definitions. For example, this line has three null statements in it:
label: ; ;
Keyword Statements
A keyword statement begins with a predefined keyword. The syntax for the rest of the
statement depends on the keyword. All instruction opcodes are keywords. All other
keywords are assembler pseudo-operations (directives).
Expressions
An expression is a sequence of symbols that represent a value. Each expression and its
result have data types. The assembler does arithmetic in twos-complement integers (32
bits of precision in 32-bit mode; 64 bits of precision in 64-bit mode). Expressions follow
precedence rules and consist of:
• Operators
• Identifiers
• Constants
Also, you may use a single character string in place of an integer within an expression.
Thus:
.byte “a” ; .word “a”+0x19
is equivalent to:
.byte 0x61 ; .word 0x7a
23
Precedence
Unless parentheses enforce precedence, the assembler evaluates all operators of the same
precedence strictly from left to right. Because parentheses also designate index-registers,
ambiguity can arise from parentheses in expressions. To resolve this ambiguity, put a
unary + in front of parentheses in expressions.
The assembler has three precedence levels, which are listed here from lowest to highest
precedence
least binding, binary +,-
lowest precedence
.
. binary *,/,5,<<,>>,^,&, |
.
most binding, unary -,+,~
highest precedence
Note: The assembler’s precedence scheme differs from that of the C language.
24
Expressions
Expression Operators
For expressions, you can rely on the precedence rules, or you can group expressions with
parentheses. The assembler recognizes the operators listed in Table 4-2.
Table 4-2 Expression Operators
Operator Meaning
+ Addition
- Subtraction
* Multiplication
/ Division
% Remainder
<< Shift Left
>> Shift Right (sign NOT extended)
^ Bitwise Exclusive-OR
& Bitwise AND
| Bitwise OR
- Minus (unary)
+ Identity (unary)
~ Complement
25
Data Types
The assembler manipulates several types of expressions. Each symbol you reference or
define belongs to one of the categories shown in Table 4-3.
Table 4-3 Data Types
Type Description
undefined Any symbol that is referenced but not defined becomes global
undefined, and this module will attempt to import it. The
assembler uses 32-bit addressing to access these symbols.
(Declaring such a symbol in a. globl pseudo-op merely makes its
status clearer).
sundefined A symbol defined by a .extern pseudo-op becomes global small

undefined if its size is greater than zero but less than the number
of bytes specified by the –G option on the command line (which
defaults to 8). The linker places these symbols within a 64 KB
region pointed to by the $gp register, so that the assembler can
use economical 16-bit addressing to access them.
absolute A constant defined in an “=” expression.
text The text section contains the program’s instructions, which are
not modifiable during execution. Any symbol defined while
the.text pseudo-op is in effect belongs to the text section.
data The data section contains memory that the linker can initialize to
nonzero values before your program begins to execute. Any
symbol defined while the .data pseudo-op is in effect belongs to
the data section. The assembler uses 32-bit or 64-bit addressing to
access these symbols (depending on whether you are in 32-bit or
64-bit mode).
sdata This category is similar to data, except that defining a symbol

while the .sdata (“small data”) pseudo-op is in effect causes the
linker to place it within a 64 KB region pointed to by the $gp
register, so that the assembler can use economical 16-bit
addressing to access it.
26
Expressions
Table 4-3 (continued) Data Types
Type Description
rdata Any symbol defined while the .rdata pseudo-op is in effect

belongs to this category, which is similar to data, but may not be
modified during execution.
bss and sbss The bss and sbss sections consist of memory which the kernel
loader initializes to zero before your program begins to execute.
Any symbol defined in a .comm or .lcomm pseudo-op belongs to
these sections (except that a .data, .sdata, or .rdata pseudo-op can
override a .comm directive). If its size is less than the number of
bytes specified by the –G option on the command line (which
defaults to 8), it belongs to sbss (“small bss”), and the linker
places it within a 64 KB region pointed to by the $gp register so
that the assembler can use economical 16-bit addressing to access
it. Otherwise, it belongs to bss and the assembler uses 32-bit or
64-bit addressing (depending on whether you are in 32-bit or
64-bit mode). Local symbols in bss or sbss defined by .lcomm are
allocated memory by the assembler; global symbols are allocated
memory by the link editor; and symbols defined by .comm are
overlaid upon like-named symbols (in the fashion of Fortran
“COMMON” blocks) by the link editor.
Symbols in the undefined and small undefined categories are always global (that is, they
are visible to the link editor and can be shared with other modules of your program).
Symbols in the absolute, text, data, sdata, rdata, bss, and sbss categories are local unless
declared in a .globl pseudo-op.
27
Type Propagation in Expressions
When expression operators combine expression operands, the result’s type depends on
the types of the operands and on the operator. Expressions follow these type propagation
rules:
• If an operand is undefined, the result is undefined.
• If both operands are absolute, the result is absolute.
• If the operator is + and the first operand refers to a relocatable text-section,
data-section, bss-section, or an undefined external, the result has the postulated type
and the other operand must be absolute.
• If the operator is – and the first operand refers to a relocatable text-section,
data-section, or bss-section symbol, the second operand can be absolute (if it
previously defined) and the result has the first operand’s type; or the second
operand can have the same type as the first operand and the result is absolute. If the
first operand is external undefined, the second operand must be absolute.
• The operators *, /, %, <<, >>, ~, ^, &, and | apply only to absolute symbols.
Relocations
With –n32 and –64 compiles, it is possible to specify a relocation explicitly in assembly.
For example:
lui $24,%hi(.data)
This example emits a lui $24,0 instruction with a R_MIPS_HI16 relocation that references
the .data symbol.
28
Relocations
Table 4-4 lists the available relocations.
Table 4-4 Relocations
AS-SYNTAX ELF Relocation
%hi R_MIPS_HI16
%lo R_MIPS_LO16
%gp_rel R_MIPS_GPREL
%half R_MIPS_16
%call16 R_MIPS_CALL16
%call_hi R_MIPS_CALL_HI16
%call_lo R_MIPS_CALL_LO16
%got R_MIPS_GOT
%got_disp R_MIPS_GOT_DISP
%got_hi R_MIPS_GOT_HI16
%got_lo R_MIPS_GOT_LO16
%got_page R_MIPS_GOT_PAGE
%got_ofst R_MIPS_GOT_OFST
%neg R_MIPS_SUB
%higher R_MIPS_HIGHER
%highest R_MIPS_HIGHEST
See the N32/64 ELF Object-File Documentation for a description of what these
relocations do. Use these relocations in instructions only where it makes sense to do so;
otherwise they are illegal.
29
Chapter 5
5. The Instruction Set
This chapter describes instruction notation and discusses assembler instructions for the
main processor. Topics covered include:
• “Instruction Classes” on page 32
• “Reorganization Constraints and Rules” on page 32
• “Instruction Notation” on page 32
• “Instruction Set” on page 34
• “Computational Instructions” on page 44
• “Jump and Branch Instructions” on page 59
• “Special Instructions” on page 65
• “Coprocessor Interface Instructions” on page 66
For information abut coprocessor notation and instructions, see Chapter 6.
31
Chapter 5: The Instruction Set
Instruction Classes
The assembler has these classes of instructions for the main processor:
• Load and Store Instructions. These instructions load immediate values and move
data between memory and general registers.
• Computational Instructions. These instructions do arithmetic and logical
operations for values in registers.
• Jump and Branch Instructions. These instructions change program control flow.
In addition, two other classes of instruction exist:

• Coprocessor Interface. These instructions provide standard interfaces to the
coprocessors.
• Special Instructions. These instructions do miscellaneous tasks.
Reorganization Constraints and Rules
To maximize performance, the goal of RISC designs is to achieve an execution rate of one
machine cycle per instruction. When writing assembly language instructions, you must
be aware of the rules to achieve this goal. You can find this information in the appropriate
microprocessor manual for your architecture (for example, the MIPS R8000
Microprocessor User’s Manual).
Instruction Notation
The tables in this chapter list the assembler format for each load, store, computational,
jump, branch, coprocessor, and special instruction. The format consists of an op-code and
a list of operand formats. The tables list groups of closely related instructions; for those
instructions, you can use any op-code with any specified operand.
Operands can take any of these formats:

• Memory references. For example, a relocatable symbol +/– an expression(register).
• Expressions (for immediate values).
• Two or three operands. For example, ADD $3,$4 is the same as ADD $3,$3,$4.
32
The operands in the table in this chapter have the following meanings:
Operand Description
address Symbolic expression (see Chapter2)
breakcode Value that determines the break
destination Destination register
destination/src1 Destination register is also source register 1
dest-copr Destination coprocessor register
dest-gpr Destination general register
expression Absolute value
immediate Expression with an immediate value
label Symbolic label
operation Coprocessor-specific operation
return Register containing the return address
source Source register
src1, src2 Source registers
src-copr Coprocessor register from which values are assigned
src-gpr General register from which values are assigned
target Register containing the target
z Coprocessor number in the range 0..2
33
Instruction Set
The tables in this section summarize the assembly language instruction set. Most of the
assembly language instructions have direct machine equivalents.
Load and Store Instructions
Load and store are immediate type intructions that move data between memory and the
general registers. Table 5-1 summarizes the load and store instruction format, and
Table 5-2 and Table 5-3 provide more detailed descriptions for each load instruction.
Table 5-4 and Table 5-5 provide details of each store instruction.
Table 5-1 Load and Store Format Summary
Description Op-code Operands
Load Address LA destination, address
Load Doubleword Address DLA
Load Byte LB
Load Byte Unsigned LBU
Load Halfword LH
Load Halfword Unsigned LHU
Load Linked* LL
Load Word LW
Load Word Left LWL
Load Word Right LWR
Load Doubleword LD
Unaligned Load Halfword ULH
Unaligned Load Halfword ULHU

Unsigned
Unaligned Load Word ULW
Load Immediate LI destination, expression
34
Instruction Set
Table 5-1 (continued) Load and Store Format Summary
Description Op-code Operands
Load Doubleword Immediate DLI
Store Double Right SDR
Unaligned Store Doubleword USD
Load Upper Immediate LUI
Store Byte SB source, address
Store Conditional * SC
Store Double SD
Store Halfword SH
Store Word Left SWL
Store Word Right SWR
Store Word SW
Unaligned Store Halfword USH
Unaligned Store Word USW
Load Doubleword LD destination, address
Load Linked Doubleword LLD
Load Word Unsigned LWU
Load Doubleword Left LDL
Load Doubleword Right LDR
Unaligned Load Double ULD
Store Doubleword SD source, address
Store Conditional SCD

Doubleword
Store Double Left SDL
* Not valid in MIPS1 architectures
35
Load Instruction Descriptions
For all load instructions, the effective address is the 32-bit twos-complement sum of the
contents of the index-register and the (sign-extended) 16-bit offset. Instructions that have
symbolic labels imply an index register, which the assembler determines. The assembler
supports additional load instructions, which can produce multiple machine instructions.
Note: Load instructions can generate many code sequences for which the link editor
must fix the address by resolving external data items.
Table 5-2 Load Instruction Descriptions
Instruction Name Description
Load Address (LA) Loads the destination register with the effective 32-bit
address of the specified data item.
Load Doubleword Loads the destination register with the effective 64-bit
Address (DLA) address of the specified data item (MIPS3 and above only).
Load Byte (LB) Loads the least-significant byte of the destination register
with the contents of the byte that is at the memory location
specified by the effective address. The system treats the
loaded byte as a signed value: bit seven is extended to fill
the three most-significant bytes.
Load Byte Unsigned Loads the least-significant byte of the destination register
(LBU) with the contents of the byte that is at the memory location
specified by the effective address. Because the system treats
the loaded byte as an unsigned value, it fills the three
most-significant bytes of the destination register with zeros.
Load Halfword (LH) Loads the two least-significant bytes of the destination
register with the contents of the halfword that is at the
memory location specified by the effective address. The
system treats the loaded halfword as a signed value. If the
effective address is not even, the system signals an address
error exception.
36
Instruction Set
Table 5-2 (continued) Load Instruction Descriptions
Load Halfword Loads the least-significant bits of the destination register

Unsigned (LHU) with the contents of the halfword that is at the memory
location specified by the effective address. Because the
system treats the loaded halfword as an unsigned value, it
fills the two most-significant bytes of the destination
register with zeros. If the effective address is not even, the
system signals an address error exception.
Load Linked (LL) Loads the destination register with the contents of the word
that is at the memory location. This instruction performs an
SYNC operation implicitly; all loads and stores to shared
memory fetched prior to the LL must access memory before
the LL, and loads and stores to shared memory fetched
subsequent to the LL must access memory after the LL.
Load Linked and Store Conditional can be use to update
memory locations atomically. The system signals an
address exception when the effective address is not
divisible by four.
Note:This instruction is not valid in the MIPS1
architectures.
Load Word (LW) Loads the destination register with the contents of the word
that is at the memory location. The system replaces all bytes
of the register with the contents of the loaded word. The
system signals an address error exception when the
effective address is not divisible by four.
Load Word Left Loads the sign; that is, Load Word Left loads the destination
(LWL) register with the most-significant bytes of the word
specified by the effective address. The effective address
must specify the byte containing the sign. In a big-endian
system, the effective address specifies the lowest numbered
byte; in a little-endian system, the effective address specifies
the highest numbered byte. Only the bytes which share the
same aligned word in memory are merged into the
destination register.
37
Load Word Right Loads the lowest precision bytes; that is, Load Word Right
(LWR) loads the destination register with the least-significant bytes
of the word specified by the effective address. The effective
address must specify the byte containing the
least-significant bits. In a big-endian configuration, the
effective address specifies the highest numbered byte; in a
little-endian configuration, the effective address specifies
the lowest numbered byte. Only the bytes which share the
same aligned word in memory are merged into the
Load Doubleword LD is a machine instruction in the MIPS3 architecture. For

(LD) the –mips1 [default] and –mips2 option: Loads the
register pair (destination and destination +1) with the two
successive words specified by the address. The destination
register must be the even register of the pair. When the
address is not on a word boundary, the system signals an
address error exception.
Note: This is retained for use with the –mips1 and –mips2
options to provide backward compatibility only.
Unaligned Load Loads a halfword into the destination register from the
Halfword (ULH) specified address and extends the sign of the halfword.
Unaligned Load Halfword loads a halfword regardless of
the halfword’s alignment in memory.
Unaligned Load Loads a halfword into the destination register from the
Halfword Unsigned specified address and zero extends the halfword. Unaligned
(ULHU) Load Halfword Unsigned loads a halfword regardless of
the halfword’s alignment in memory.
Unaligned Load Loads a word into the destination register from the
Word (ULW) specified address. Unaligned Load Word loads a word
regardless of the word’s alignment in memory.
Load Immediate (LI) Loads the destination register with the 32-bit value of an
expression that can be computed at assembly time.
Note: Load Immediate can generate any efficient code
sequence to put a desired value in the register.
38
Instruction Set
Load Doubleword Loads the destination register with the 64-bit value of an
Immediate (DLI) expression that can be computed at assembly time.
Note: Load Immediate can generate any efficient code
sequence to put a desired value in the register (MIPS3 and
above only).
Load Upper Loads the most-significant half of a register with the

Immediate (LUI) expression’s value. The system fills the least-significant half
of the register with zeros. The expression’s value must be in
the range –32768...65535.
Table 5-3 Load Instruction Descriptions for MIPS3/4 Architecture Only
Load Doubleword Loads the destination register with the contents of the
(LD) doubleword that is at the memory location. The system
replaces all bytes of the register with the contents of the
loaded doubleword. The system signals an address error
exception when the effective address is not divisible by
eight.
Load Linked Loads the destination register with the contents of the
Doubleword (LLD) doubleword that is currently in the memory location. This
instruction performs a SYNC operation implicitly. Load
Linked Doubleword and Store Conditional Doubleword can
be used to update memory locations atomically.
Load Word Loads the least-significant bits of the destination register

Unsigned (LWU) with the contents of the word (32 bits) that is at the memory
location specified by the effective address. Because the
system treats the loaded word as an unsigned value, it fills
the four most-significant bytes of the destination register
with zeros. If the effective address is not divisible by four,
the system signals an address error exception.
39
Table 5-3 (continued) Load Instruction Descriptions for MIPS3/4 Architecture Only
Load Doubleword Loads the destination register with the most-significant

Left (LDL) bytes of the doubleword specified by the effective address.
The effective address must specify the byte containing the
sign. In a big-endian configuration, the effective address
specifies the lowest numbered byte; in a little-endian
machine, the effective address specifies the highest
numbered byte. Only the bytes which share the same
aligned doubleword in memory are merged into the
Load Doubleword Loads the destination register with the least-significant

Right (LDR) bytes of the doubleword specified by the effective address.
The effective address must specify the byte containing the
least-significant bits. In a bid-endian machine, the effective
address specifies the highest numbered byte. In a
little-endian machine, the effective address specifies the
lowest numbered byte. Only the bytes which share the same
aligned doubleword in memory are merged into the
Unaligned Load Loads a doubleword into the destination register from the
Doubleword (ULD) specified address. ULD loads a doubleword regardless of
the doubleword’s alignment in memory.
Store Instruction Descriptions
For all machine store instructions, the effective address is the 32-bit twos-complement
sum of the contents of the index-register and the (sign-extended) 16-bit offset. The
assembler supports additional store instructions, which can produce multiple machine
40
Instruction Set
instructions. Instructions that have symbolic labels imply an index-register, which the
assembler determines.
Table 5-4 Store Instruction Descriptions
Store Byte (SB) Stores the contents of the source register’s least-significant
byte in the byte specified by the effective address.
Store Conditional Stores the contents of a word from the source register into
(SC) the memory location specified by the effective address. This
instruction implicitly performs a SYNC operation; all loads
and stores to shared memory fetched prior to the sc must
access memory before the sc, and loads and stores to shared
memory fetched subsequent to the sc must access memory
after the sc. If any other processor or device has modified
the physical address since the time of the previous Load
Linked instruction, or if an RFE or ERET instruction occurs
between the Load Linked and this store instruction, the
store fails. The success or failure of the store operation (as
defined above) is indicated by the contents of the source
register after execution of the instruction. A successful store
sets it to 1; and a failed store sets it to 0. The machine signals
an address exception when the effective address is not
divisible by four.
Note: This instruction is not valid in the MIPS1
architectures.
Store Doubleword SD is a machine instruction in the MIPS3 architecture. For

(SD) the –mips1 [default] and –mips2 options: Stores the
contents of the register pair in successive words, which the
address specifies. The source register must be the even
register of the pair, and the storage address must be word
aligned.
Note: This is retained for use with the –mips1 and –mips2
options to provide backward compatibility only.
Store Halfword (SH) Stores the two least-significant bytes of the source register
in the halfword that is at the memory location specified by
the effective address. The effective address must be
divisible by two; otherwise the machine signals an address
error exception.
41
Table 5-4 (continued) Store Instruction Descriptions
Store Word Left Stores the most-significant bytes of a word in the memory
(SWL) location specified by the effective address. The contents of
the word at the memory location, specified by the effective
address, are shifted right so that the leftmost byte of the
unaligned word is in the addressed byte position. The
stored bytes replace the corresponding bytes of the effective
address. The effective address’s last two bits determine how
many bytes are involved.
Store Word Right Stores the least-significant bytes of a word in the memory
(SWR) location specified by the effective address. The contents of
the word at the memory location, specified by the effective
address, are shifted left so that the right byte of the
unaligned word is in the addressed byte position. The
stored bytes replace the corresponding bytes of the effective
address. The effective address’s last two bits determine how
many bytes are involved.
Store Word (SW) Stores the contents of a word from the source register in the
memory location specified by the effective address. The
effective address must be divisible by four; otherwise the
machine signals an address error exception.
Unaligned Store Stores the contents of the two least-significant bytes of the
Halfword (USH) source register in a halfword that the address specifies. The
machine does not require alignment for the storage address.
Unaligned Store Stores the contents of the source register in a word specified
Word (USW) by the address. The machine does not require alignment for
the storage address.
42
Instruction Set
Table 5-5 Store Instruction Descriptions for MIPS3/4 Architecture Only
Store Doubleword Stores the contents of a doubleword from the source register
(SD) in the memory location specified by the effective address.
The effective address must be divisible by eight, otherwise
the machine signals an address error exception.
Store Conditional Stores the contents of a doubleword from the source register
Doubleword (SCD) into the memory locations specified by the effective address.
This instruction implicitly performs a SYNC operation. If
any other processor or device has modified the physical
address since the time of the previous Load Linked
instruction, or if an ERET instruction occurs between the
Load Linked instruction and this store instruction, the store
fails and is inhibited from taking place. The success or
failure of the store operation (as defined above) is indicated
by the contents of the source register after execution of this
instruction. A successful store sets it to 1; and a failed store
sets it to 0. The machine signals an address exception when
the effective address is not divisible by eight.
Store Doubleword Stores the most-significant bytes of a doubleword in the

Left (SDL) memory location specified by the effective address. It alters
only the doubleword in memory which contains the byte
indicated by the effective address.
Store Doubleword Stores the least-significant bytes of a doubleword in the

Right (SDR) memory location specified by the effective address. It alters
only the doubleword in memory which contains the byte
indicated by the effective address.
Unaligned Store Stores the contents of the source register in a doubleword

Doubleword (USD) specified by the address. The machine does not require
alignment for the storage address.
43
Computational Instructions
The machine has general-purpose and coprocessor-specific computational instructions

(for example, the floating-point coprocessor). This part of the book describes
general-purpose computational instructions.
Computational instructions perform the following operations on register values;

• arithmetic
• logical
• shift
• multiply
• divide
Table 5-6 summarizes the computational format summaries, and Table 5-7 and Table 5-8
describe these instructions in more detail.
Table 5-6 Computational Format Summaries
Description Op-code Operand
Add with Overflow ADD destination, src1, src2
Add without Overflow ADDU destination, src1, src2
AND AND destination, src1, immediate
Divide Signed DIV destination/src1, immediate
Divide Unsigned DIVU
Exclusive-OR XOR
Multiply MUL
Multiply with Overflow MULO
Multiply with Overflow MULOU

Unsigned
44
Table 5-6 (continued) Computational Format Summaries
NOT OR NOR
OR OR
Set Equal SEQ
Set Greater Than SGT
Set Greater/Equal SGE
Set Greater/Equal Unsigned SGEU
Set Greater Unsigned SGTU
Set Less Than SLT
Set Less/Equal SLE
Set Less/Equal Unsigned SLEU
Set Less Than Unsigned SLTU
Set Not Equal SNE
Subtract with Overflow SUB
Subtract without Overflow SUBU
Remainder Signed REM
Remainder Unsigned REMU
Rotate Left ROL
Rotate Right ROR
Shift Right Arithmetic SRA
Shift Left Logical SLL
Shift Right Logical SRL
Absolute Value ABS destination, src1
Negate with Overflow NEG destination/src1
Negate without Overflow NEGU
45
NOT NOT
Move MOVE destination, src1
Move Conditional on Not Zero MOVN destination, src1, src2
Move Conditional on Zero MOVZ
Multiply MULT src1,src2
Multiply Unsigned MULTU
Trap if Equal TEQ src1, src2
Trap if not Equal TNE src1, immediate
Trap if Less Than TLT
Trap if Less than, Unsigned TLTU
Trap if Greater Than or Equal TGE
Trap if Greater than or Equal, TGEU

Unsigned
Doubleword Add with Overflow DADD destination,src1, src2

destination/src1,src2
Doubleword Add without DADDU destination, src1, immediate

Overflow destination/src1, immediate
Doubleword Divide Signed DDIV
Doubleword Divide Unsigned DDIVU
Doubleword Multiply DMUL
Doubleword Multiply with DMULO

Overflow
Doubleword Multiply with DMULOU

Overflow Unsigned
Doubleword Subtract with DSUB

Overflow
46
Doubleword Subtract without DSUBU

Overflow
Doubleword Remainder Signed DREM
Doubleword Remainder DREMU

Unsigned
Doubleword Rotate Left DROL
Doubleword Rotate Right DROR
Doubleword Shift Right DSRA

Arithmetic
Doubleword Shift Left Logical DSLL
Doubleword Shift Right Logical DSRL
Doubleword Absolute Value DABS destination, src1
Doubleword Negate with DNEG destination/src1

Overflow
Doubleword Negate without DNEGU

Overflow
Doubleword Multiply DMULT src1, src2
Doubleword Multiply Unsigned DMULTU src1, immediate
47
Computational Instruction Descriptions
Table 5-7 Computational Instruction Descriptions
Absolute Value Computes the absolute value of the contents of src1 and puts
(ABS) the result in the destination register. If the value in src1 is
–2147483648, the machine signals an overflow exception.
Add with Overflow Computes the twos-complement sum of two signed values.
(ADD) This instruction adds the contents of src1 to the contents of
src2, or it can add the contents of src1 to the immediate value.
Add (with Overflow) puts the result in the destination
register. When the result cannot be extended as a 32-bit
number, the machine signals an overflow exception.
Add without Computes the twos-complement sum of two 32-bit values.

Overflow (ADDU) This instruction adds the contents of src1 to the contents of
src2, or it can add the contents of src1 to the immediate value.
Add (without Overflow) puts the result in the destination
register. Overflow exceptions never occur.
AND (AND) Computes the Logical AND of two values. This instruction
ANDs (bit-wise) the contents of src1 with the contents of
src2, or it can AND the contents of src1 with the immediate
value. The immediate value is not sign extended. AND puts
the result in the destination register.
Divide Signed (DIV) Computes the quotient of two values. Divide (with
Overflow) treats src1 as the dividend. The divisor can be src2
or the immediate value. The instruction divides the contents
of src1 by the contents of src2, or it can divide src1 by the
immediate value. It puts the quotient in the destination
register. If the divisor is zero, the machine signals an error
and may issue a BREAK instruction. The DIV instruction
rounds toward zero. Overflow is signaled when dividing
–2147483648 by –1. The machine may issue a BREAK
instruction for divide-by-zero or for overflow.
Note: The special case DIV $0,src1,src2 generates the real
machine divide instruction and leaves the result in the
HI/LO register. The HI register contains the remainder and
the LO register contains the quotient. No checking for
divide-by-zero is performed.
48
Table 5-7 (continued) Computational Instruction Descriptions
Divide Unsigned Computes the quotient of two unsigned 32-bit values.

(DIVU) Divide (unsigned) treats src1 as the dividend. The divisor
can be src2 or the immediate value. This instruction divides
the contents of src1 by the contents of src2, or it can divide
the contents of src1 by the immediate value. Divide
(unsigned) puts the quotient in the destination register. If the
divisor is zero, the machine signals an exception and may
issue a BREAK instruction. See the note for DIV concerning
$0 as a destination. Overflow exceptions never occur.
Exclusive-OR (XOR) Computes the XOR of two values. This instruction XORs
(bit-wise) the contents of src1 with the contents of src2, or it
can XOR the contents of src1 with the immediate value. The
immediate value is not sign extended. Exclusive-OR puts
the result in the destination register.
Move (MOVE) Moves the contents of src1 to the destination register.
Move Conditional on Conditionally moves the contents of src1 to the destination

Not Zero (MOVN) register after testing that src2 is not equal to zero (MIPS4
only.)
Move Conditional on Conditionally moves the contents of src1 to the destination

Zero (MOVZ) register after testing that src2 is equal to zero (MIPS4 only).
Multiply (MUL) Computes the product of two values. This instruction puts
the 32-bit product of src1 and src2, or the 32-bit product of
src1 and the immediate value, in the destination register. The
machine does not report overflow.
Note: Use MUL when you do not need overflow protection:
it’s often faster than MULO and MULOU. For multiplication
by a constant, the MUL instruction produces faster machine
instruction sequences than MULT or MULTU instructions
can produce.
Multiply (MULT) Computes the 64-bit product of two 32-bit signed values.
This instruction multiplies the contents of src1 by the
contents of src2 and puts the result in the HI and LO registers
(see Chapter 1). No overflow is possible.
Note: The MULT instruction is a real machine language
instruction.
49
Multiply Unsigned Computes the product of two unsigned 32-bit values. It

(MULTU) multiplies the contents of src1 and the contents of src2 and
puts the result in the HI and LO registers (see Chapter 1). No
overflow is possible.
Note: The MULTU instruction is a real machine language
instruction.
Multiply with Computes the product of two 32-bit signed values. Multiply
Overflow (MULO) (with Overflow) puts the 32-bit product of src1 and src2, or
the 32-bit product of src1 and the immediate value, in the
destination register. When an overflow occurs, the machine
signals an overflow exception and may execute a BREAK
instruction.
Note: For multiplication by a constant, MULO produces
faster machine instruction sequences than MULT or MULTU
can produce; however, if you do not need overflow
detection, use the MUL instruction. It’s often faster than
MULO.
Multiply with Computes the product of two 32-bit unsigned values.

Overflow Unsigned Multiply (with Overflow Unsigned) puts the 32-bit product
(MULOU) of src1 and src2, or the product of src1 and the immediate
value, in the destination register. This instruction treats the
multiplier and multiplicand as 32-bit unsigned values.
When an overflow occurs, the machine signals an overflow
exception and may issue an BREAK instruction.
Note: For multiplication by a constant, MULOU produces
faster machine instruction sequences than MULT or MULTU
can reproduce; however, if you do not need overflow
detection, use the MUL instruction. It’s often faster than
MULOU.
Negate with Computes the negative of a value. This instruction negates

Overflow (NEG) the contents of src1 and puts the result in the destination
register. If the value in src1 is –2147483648, the machine
signals an overflow exception.
Negate without Negates the integer contents of src1 and puts the result in the
Overflow (NEGU) destination register. The machine does not report overflows.
50
NOT (NOT) Computes the Logical NOT of a value. This instruction

complements (bit-wise) the contents of src1 and puts the
result in the destination register.
NOT OR (NOR) Computes the NOT OR of two values. This instruction

combines the contents of src1 with the contents of src2 (or the
immediate value). NOT OR complements the result and
puts it in the destination register.
OR (OR) Computes the Logical OR of two values. This instruction

ORs (bit-wise) the contents of src1 with the contents of src2,
or it can OR the contents of src1 with the immediate value.
The immediate value is not sign-extended. OR puts the
Remainder Signed Computes the remainder of the division of two unsigned

(REM) 32-bit values. The machine defines the remainder REM(i,j)
as i–(j*div(i,j)) where j · 0. Remainder (with Overflow) treats
src1 as the dividend. The divisor can be src2 or the
immediate value. This instruction divides the contents of
src1 by the contents of src2, or it can divide the contents of
src1 by the immediate value. It puts the remainder in the
destination register. The REM instruction rounds toward
zero, rather than toward negative infinity. For example,
div(5,–3)=–1, and rem(5,–3)=2. For divide-by-zero, the
machine signals an error and may issue a BREAK
instruction.
Remainder Computes the remainder of the division of two unsigned

Unsigned (REMU) 32-bit values. The machine defines the remainder REM(i,j)
as i–(j*div(i,j)) where j · 0. Remainder (unsigned) treats src1
as the dividend. The divisor can be src2 or the immediate
value. This instruction divides the contents of src1 by the
contents of src2, or it can divide the contents of src1 by the
immediate value. Remainder (unsigned) puts the remainder
in the destination register. For divide-by-zero, the machine
signals an error and may issue a BREAK instruction.
51
Rotate Left (ROL) Rotates the contents of a register left (toward the sign bit).
This instruction inserts in the least-significant bit any bits
that were shifted out of the sign bit. The contents of src1
specify the value to shift, and the contents of src2 (or the
immediate value) specify the amount to shift. Rotate Left
puts the result in the destination register. If src2 (or the
immediate value) is greater than 31, src1 shifts by (src2 MOD
32).
Rotate Right (ROR) Rotates the contents of a register right (toward the
least-significant bit). This instruction inserts in the sign bit
any bits that were shifted out of the least-significant bit. The
contents of src1 specify the value to shift, and the contents of
src2 (or the immediate value) specify the amount to shift.
Rotate Right puts the result in the destination register. If src2
(or the immediate value) is greater than 32, src1 shifts by src2
MOD 32.
Set Equal (SEQ) Compares two 32-bit values. If the contents of src1 equal the
contents of src2 (or src1 equals the immediate value) this
instruction sets the destination register to one; otherwise, it
sets the destination register to zero.
Set Greater Than Compares two signed 32-bit values. If the contents of src1 are
(SGT) greater than the contents of src2 (or src1 is greater than the
immediate value), this instruction sets the destination
register to one; otherwise, it sets the destination register to
zero.
Set Greater/Equal Compares two signed 32-bit values. If the contents of src1 are
(SGE) greater than or equal to the contents of src2 (or src1 is greater
than or equal to the immediate value), this instruction sets
the destination register to one; otherwise, it sets the
destination register to zero.
Set Greater/Equal Compares two unsigned 32-bit values. If the contents of src1
Unsigned (SGEU) are greater than or equal to the contents of src2 (or src1 is
greater than or equal to the immediate value), this
instruction sets the destination register to one; otherwise, it
sets the destination register to zero.
52
Set Greater Than Compares two unsigned 32-bit values. If the contents of src1
Unsigned (SGTU) are greater than the contents of src2 (or src1 is greater than
the immediate value), this instruction sets the destination
zero.
Set Less Than (SLT) Compares two signed 32-bit values. If the contents of src1 are
less than the contents of src2 (or src1 is less than the
zero.
Set Less/Equal (SLE) Compares two signed 32-bit values. If the contents of src1 are
less than or equal to the contents of src2 (or src1 is less than
or equal to the immediate value), this instruction sets the
destination register to one; otherwise, it sets the destination
register to zero.
Set Less/Equal Compares two unsigned 32-bit values. If the contents of src1
Unsigned (SLEU) are less than or equal to the contents of src2 (or src1 is less
than or equal to the immediate value) this instruction sets
the destination register to one; otherwise, it sets the
destination register to zero.
Set Less Than Compares two unsigned 32-bit values. If the contents of src1
Unsigned (SLTU) are less than the contents of src2 (or src1 is less than the
zero.
Set Not Equal (SNE) Compares two 32-bit values. If the contents of scr1 do not
equal the contents of src2 (or src1 does not equal the
zero.
Shift Left Logical Shifts the contents of a register left (toward the sign bit) and
(SLL) inserts zeros at the least-significant bit. The contents of src1
specify the value to shift, and the contents of src2 or the
immediate value specify the amount to shift. If src2 (or the
immediate value) is greater than 31 or less than 0, src1 shifts
by src2 MOD 32.
53
Shift Right Shifts the contents of a register right (toward the

Arithmetic (SRA) least-significant bit) and inserts the sign bit at the
most-significant bit. The contents of src1 specify the value to
shift, and the contents of src2 (or the immediate value)
specify the amount to shift. If src2 (or the immediate value)
is greater than 31 or less than 0, src1 shifts by the result of src2
MOD 32.
Shift Right Logical Shifts the contents of a register right (toward the
(SRL) least-significant bit) and inserts zeros at the most-significant
bit. The contents of src1 specify the value to shift, and the
contents of src2 (or the immediate value) specify the amount
to shift. If src2 (or the immediate value) is greater than 31 or
less than 0, src1 shifts by the result of src2 MOD 32.
Subtract with Computes the twos-complement difference for two signed

Overflow (SUB) values. This instruction subtracts the contents of src2 from
the contents of src1, or it can subtract the contents of the
immediate from the src1 value. Subtract (with Overflow)
puts the result in the destination register. When the true
result’s sign differs from the destination register’s sign, the
machine signals an overflow exception.
Subtract without Computes the twos-complement difference for two 32-bit

Overflow (SUBU) values. This instruction subtracts the contents of src2 from
the contents of src1, or it can subtract the contents of the
immediate from the src1 value. Subtract (without Overflow)
puts the result in the destination register. Overflow
exceptions never happen.
Trap if Equal (TEQ) Compares two 32-bit values. If the contents of src1 equal the
contents of src2 (or src1 equals the immediate value), a trap
exception occurs.
Trap if Not Equal Compares two 32-bit values. If the contents of src1 do not
(TNE) equal the contents of src2 (or src1 does not equal the
immediate value), a trap exception occurs.
Trap if Less Than Compares two signed 32-bit values. If the contents of src1 are
(TLT) less than the contents of src2 (or src1 is less than the
54
Trap if Less Than Compares two unsigned 32-bit values. If the contents of src1
Unsigned (TLTU) are less than the contents of src2 (or src1 is less than the
Trap if Greater than Compares two signed 32-bit values. If the contents of src1 are
or Equal (TGE) greater than the contents of src2 (or src1 is greater than the
Trap if Greater than Compares two unsigned 32-bit values. If the contents of src1
or Equal Unsigned are greater than the contents of src2 (or src1 is greater than
(TGEU) the immediate value), a trap exception occurs.
Table 5-8 Computational Instruction Descriptions for MIPS3/4 Architecture
Doubleword Computes the absolute value of the contents of src1, treated

Absolute Value as a 64-bit signed value, and puts the result in the
(DABS) destination register. If the value in src1 is -2**63, the machine
Doubleword Add Computes the twos-complement sum of two 64-bit signed

with Overflow values. The instruction adds the contents of src1 to the
(DADD) contents of src2, or it can add the contents of src1 to the
immediate value. When the result cannot be extended as a
64-bit number, the system signals an overflow exception.
Doubleword Add Computes the twos-complement sum of two 64-bit values.

without Overflow The instruction adds the contents of src1 to the contents of
(DADDU) src2, or it can add the contents of src1 to the immediate value.
Overflow exceptions never occur.
Doubleword Divide Computes the quotient of two 64-bit values. DDIV treats src1
Signed (DDIV) as the dividend. The divisor can be src2 or the immediate
value. It puts the quotient in the destination register. If the
divisor is zero, the system signals an error and may issue a
BREAK instruction. The DDIV instruction rounds towards
zero. Overflow is signaled when dividing -2**63 by -1.
Note: The special case DDIV $0,src1,src2 generates the real
doubleword divide instruction and leaves the result in the
HI/LO register. The HI register contains the quotient. No
checking for divide-by-zero is performed.
55
Table 5-8 (continued) Computational Instruction Descriptions for MIPS3/4 Architecture
Doubleword Divide Computes the quotient of two unsigned 64-bit values.

Unsigned (DDIVU) DDIVU treats src1 as the dividend. The divisor can be src2 or
the immediate value. It puts the quotient in the destination
register. If the divisor is zero, the system signals an exception
and may issue a BREAK instruction. See note for DDIV
concerning $0 as a destination. Overflow exceptions never
occur.
Doubleword Computes the product of two values. This instruction puts

Multiply (DMUL) the 64-bit product of src1 and src2, or the 64-bit product of
src1 and the immediate value, in the destination
register.Overflow is not reported.
Note: Use DMUL when you do not need overflow
protection. It is often faster than DMULO and DMULOU.
For multiplication by a constant, the DMUL instruction
produces faster machine instruction sequences than
DMULT or DMULTU can produce.
Doubleword Computes the 128-bit product of two 64-bit signed values.

Multiply (DMULT) This instruction multiplies the contents of src1 by the
contents of src2 and puts the result in the HI and LO
registers. No overflow is possible. Note: The DMULT
instruction is a real machine language instruction.
Doubleword Computes the product of two unsigned 64-bit values. It

Multiply Unsigned multiplies the contents of src1 and the contents of src2,
(DMULTU) putting the result in the HI and LO registers. No overflow is
possible.
Note: The DMULTU instruction is a real machine language
instruction.
Doubleword Computes the product of two 64-bit signed values. It puts

Multiply with the 64-bit product of src1 and src2, or the 64-bit product of
Overflow (DMULO) src1 and the immediate value, in the destination register.
When an overflow occurs, the system signals an overflow
exception and may execute a BREAK instruction.
Note: For multiplication by a constant, DMULO produces
faster machine instruction sequences than DMULT or
DMULTU can produce; however, if you do not need
overflow detection, use the DMUL instruction. It is often
faster than DMULO.
56
Doubleword Computes the product of two 64-bit unsigned values. It puts

Multiply with the 64-bit product of src1 and src2, or the 64-bit product of
Overflow Unsigned src1 and the immediate value, into the destination register.
(DMULOU) When an overflow occurs, the system signals an overflow
exception and may issue a BREAK instruction.
Note: For multiplication by a constant, DMULOU produces
faster machine instruction sequences than DMULT or
DMULTU produces; however, if you do not need overflow
detection, use the DMUL instruction. It is often faster than
DMULOU.
Doubleword Negate Computes the negative of a 64-bit value. The instruction

with Overflow negates the contents of src1 and puts the result in the
(DNEG) destination register. If the value of src1 is -2**63, the system
Doubleword Negate Negates the 64-bit contents of src1 and puts the result in the
without Overflow destination register. Overflow is not reported.
(DNEGU)
Doubleword Computes the remainder of the division of two signed 64-bit

Remainder Signed values. It treats src1 as the dividend. The divisor can be src2
(DREM) or the immediate value. The DREMU instruction puts the
remainder in the destination register. If the divisor is zero,
the system signals an error and may issue a BREAK
instruction.
Doubleword Computes the remainder of the division of two unsigned

Remainder 64-bit values. It treats src1 as the dividend. The divisor can
Unsigned (DREMU) be src2 or the immediate value. The DREMU instruction
puts the remainder in the destination register. If the divisor
is zero, the system signals an error and may issue a BREAK
instruction.
Doubleword Rotate Rotates the contents of a 64-bit register left (towards the sign
Left (DROL) bit). This instruction inserts in the least-significant bit any
bits that were shifted out of the sign bit. The contents of src1
specify the value to shift, and contents of src2 (or the
immediate value) specify the amount to shift. If src2 (or the
immediate value) is greater than 63, src1 shifts by src2 MOD
64.
57
Doubleword Rotate Rotates the contents of a 63-bit register right (towards the
Right (DROR) least-significant bit). This instruction inserts in the sign bit
any bits that were shifted out of the least-significant bit. The
contents of src1 specify the value to shift, and the contents of
src2 (or the immediate value) specify the amount to shift. If
src2 (or the immediate value is greater than 63, src1 shifts by
src2 MOD 64.
Doubleword Shift Shifts the contents of a 64-bit register left (towards the sign
Left Logical (DSLL) bit) and inserts zeros at the least-significant bit. The contents
of src1 specify the value to shift, and the contents of src2 (or
the immediate value) specify the amount to shift. If src2 (or
the immediate value) is greater than 63, src1 shifts by src2
MOD 64.
Doubleword Shift Shifts the contents of a 64-bit register right (towards the
Right Arithmetic least-significant bit) and inserts the sign bit at the
(DSRA) most-significant bit. The contents of src2 (or the immediate
value) specify the amount to shift. If src2 (or the immediate
value) is greater than 63, src1 shifts by src2 MOD 64.
Doubleword Shift Shifts the contents of a 64-bit register right (towards the
Right Logical (DSRL) least-significant bit) and inserts zeros at the most-significant
bit. The contents of src1 specify the value to shift, and the
contents of src2 (or the immediate value) specify the amount
to shift. If src2 (or the immediate value) is greater than 63,
src1 shifts by src2 MOD 64.
Doubleword Computes the twos-complement difference for two signed

Subtract with 64-bit values. This instruction subtracts the contents of src2
Overflow (DSUB) from the contents of src1, or it can subtract the immediate
value from the contents of src1. It puts the result in the
destination register. When the true result’s sign differs from
the destination register’s sign, the system signals an
overflow exception.
Doubleword Computes the twos complement difference for two

Subtract without unsigned 64-bit values. This instruction subtracts the
Overflow (DSUBU) contents of src2 from the contents of src1, or it can subtract
the immediate value from the contents of src1. It puts the
result in the destination register. Overflow exceptions never
happen.
58
Jump and Branch Instructions
The jump and branch instructions let you change an assembly program’s control flow.
This section of the book describes jump and branch instructions.
Jump and branch instructions change the flow of a program. Table 5-9 summarizes the
formats of jump and branch instructions.
Table 5-9 Jump and Branch Format Summary
Jump J address
Jump and Link JAL address

target
return,target
Branch on Equal BEQ src1,src2,label
Branch on Greater BGT src1,immediate,label
Branch on Greater/Equal BGE
Branch on Greater/Equal Unsigned BGEU
Branch on Greater Than Unsigned BGTU
Branch on Less Than BLT
Branch on Less/Equal BLE
Branch on Less/Equal Unsigned BLEU
Branch on Less Than Unsigned BLTU
Branch on Not Equal BNE
Branch B label
Branch and Link BAL
Branch on Equal Likely* BEQL src1,src2,label
59
Table 5-9 (continued) Jump and Branch Format Summary
Branch on Greater Than Likely* BGTL src1, immediate,label
Branch on Greater/Equal Likely * BGEL
Branch on Greater/Equal Unsigned Likely* BGEUL
Branch on Greater Than Unsigned Likely* BGTUL
Branch on Less Than Likely* BLTL
Branch on Less/Equal Likely * BLEL
Branch on Less/Equal Unsigned Likely* BLEUL
Branch on Less Than Unsigned Likely* BLTUL
Branch on Not Equal Likely* BNEL
Branch on Equal to Zero BEQZ src1,label
Branch on Greater/Equal Zero BGEZ
Branch on Greater Than Zero BGTZ
Branch on Greater or Equal to Zero and Link BGEZAL
Branch on Less Than Zero and Link BLTZAL
Branch on Less/Equal Zero BLEZ
Branch on Less Than Zero BLTZ
Branch on Not Equal to Zero BNEZ
Branch on Equal to Zero Likely* BEQZL src1,label
Branch on Greater/Equal Zero Likely* BGEZL
Branch on Greater Than Zero Likely* BGTZL
Branch on Greater or Equal to Zero and Link BGEZALL

Likely*
Branch on Less Than Zero and Link Likely* BLTZALL
Branch on Less/Equal Zero Likely* BLEZL
60
Table 5-9 (continued) Jump and Branch Format Summary
Branch on Less Than Zero Likely* BLTZL
Branch on Not Equal to Zero Likely* BNEZL
* Not valid in MIPS1 architecture.
Jump and Branch Instruction Descriptions
In Table 5-10 branch instructions, branch destinations must be defined in the source
being assembled.
Table 5-10 Jump and Branch Instruction Descriptions
Branch (B) Branches unconditionally to the specified label.
Branch and Link Branches unconditionally to the specified label and puts the
(BAL) return address in general register $31.
Branch on Equal Branches to the specified label when the contents of src1 equal
(BEQ) the contents of src2, or when the contents of src1 equal the
immediate value.
Branch on Equal to Branches to the specified label when the contents of src1 equal
Zero (BEQZ) zero.
Branch on Greater Branches to the specified label when the contents of src1 are
Than (BGT) greater than the contents of src2, or it can branch when the
contents of src1 are greater than the immediate value. The
comparison treats the comparands as signed 32-bit values.
Branch on Branches to the specified label when the contents of src1 are
Greater/Equal greater than or equal to the contents of src2, or it can branch
Unsigned (BGEU) when the contents of src1 are greater than or equal to the
immediate value. The comparison treats the comparands as
unsigned 32-bit values.
Greater/Equal greater than or equal to zero.
Zero (BGEZ)
61
Table 5-10 (continued) Jump and Branch Instruction Descriptions
Greater/Equal greater than or equal to zero and puts the return address in
Zero and Link general register $31. When this write is done, it destroys the
(BGEZAL) contents of the register. See the MIPS microprocessor user’s
manual appropriate to your architecture for more
information. Do not use BGEZAL $31.
or Equal (BGE) greater than or equal to the contents of src2, or it can branch
when the contents of src1 are greater than or equal to the
immediate value. The comparison treats the comparands as
signed 32-bit values.
Than Unsigned greater than the contents of src2, or it can branch when the
(BGTU) contents of src1 are greater than the immediate value. The
comparison treats the comparands as unsigned 32-bit values.
Than Zero (BGTZ) greater than zero.
Branch on Less Branches to the specified label when the contents of src1 are
Than Zero (BLTZ) less than zero. The program must define the destination.
Than (BLT) less than the contents of src2, or it can branch when the
contents of src1 are less than the immediate value. The
comparison treats the comparands as signed 32-bit values.
Less/Equal less than or equal to the contents of src2, or it can branch when
Unsigned (BLEU) the contents of src1 are less than or equal to the immediate
value. The comparison treats the comparands as unsigned
32-bit values.
Less/Equal Zero less than or equal to zero. The program must define the
(BLEZ) destination.
62
Branch on Less or Branches to the specified label when the contents of src1 are
Equal (BLE) less than or equal to the contents of src2, or it can branch when
the contents of src1 are less than or equal to the immediate
value. The comparison treats the comparands as signed 32-bit
values.
Than Unsigned less than the contents of src2, or it can branch when the
(BLTU) contents of src1 are less than the immediate value. The
comparison treats the comparands as unsigned 32-bit values.
Than Zero and less than zero and puts the return address in general register
Link (BLTZAL) $31. Because the value is always stored in register 31, there is
a chance of a stored value being overwritten before it is used.
See the MIPS microprocessor user’s manual appropriate to
your architecture for more information. Do not use BGEZAL
$31
Branch on Not Branches to the specified label when the contents of src1 do
Equal (BNE) not equal the contents of src2, or it can branch when the
contents of src1 do not equal the immediate value.
Branch on Not Branches to the specified label when the contents of src1 do
Equal to Zero not equal zero.
(BNEZ)
Jump (J) Unconditionally jumps to a specified location. A symbolic

address or a general register specifies the destination. The
instruction J $31 returns from a JAL call instruction.
63
Jump And Link Unconditionally jumps to a specified location and puts the
(JAL) return address in a general register. A symbolic address or a
general register specifies the target location. By default, the
return address is placed in register $31. If you specify a pair of
registers, the first receives the return address and the second
specifies the target. The instruction JAL procname transfers to
procname and saves the return address. For the two-register
form of the instruction, the target register may not be the same
as the return-address register. For the one-register form, the
target may not be $31.
Branch Likely Same an the ordinary branch instruction (without the

Instructions “Likely”), except in a branch likely instruction, the instruction
in the delay slot is nullified if the conditional branch is not
taken.
Note: The branch likely instructions should be used only
inside a .set noreorder schedule in an assembly program. The
assembler does not attempt to schedule the delay slot of a
branch likely instruction.
64
Special Instructions
Special Instructions
The main processor’s special instructions do miscellaneous tasks. See Table 5-11.
Table 5-11 Special Instruction Descriptions
Break (BREAK) Unconditionally transfers control to the exception handler.

The breakcode operand is interpreted by software
conventions. The breakcode1 operand is used to fill the
low-order 10 bits of the 20-bit immediate field in the BREAK
instruction. The optional second operand, breakcode2, fills
the high-order 10 bits.
Exception Return Returns from an interrupt, exception or error trap. Similar to

(ERET) a branch or jump instruction, ERET executes the next
instruction before taking effect. Use this on R4000 processor
machines in place of RFE.
Move From HI Moves the contents of the HI register to a general-purpose

Register (MFHI) register.
Move From LO Moves the contents of the LO register to a general-purpose

Register (MFLO) register.
Move To HI Register Moves the contents of a general-purpose register to the HI

(MTHI) register.
Move To LO Register Moves the contents of a general-purpose register to the LO

(MTLO) register.
Prefetch (PREF) Prefetch location from memory: pref hint, offset(base)
Prefetch Indexed Prefetch location from memory: prefx hint, index(base)

(PREFX)
Restore From Restores the previous interrupt called and user/kernel state.
Exception (RFE) This instruction can execute only in kernel state and is
unavailable in user mode.
Syscall (SYSCALL) Causes a system call trap. The operating system interprets
the information set in registers to determine what system
call to do.
65
Coprocessor Interface Instructions
The coprocessor interface instructions provide standard ways to access your machine’s
coprocessors. See Table 5-12 and Table 5-13.
Coprocessor Interface Summary
Table 5-12 Coprocessor Interface Formats
Load Word Coprocessor z LWCz dest-copr,address
Load Double Coprocessor z* LDCz
Store Word Coprocessor z SWCz src-copr, address
Store Double Coprocessor z* SDCz
Move From Coprocessor z MFCz dest-gpr, source
Move To Coprocessor z MTCz src-gpr, destination
Doubleword Move From Coprocessor z ** DMFCz
Doubleword Move To Coprocessor z ** DMTCz
Branch Coprocessor z False BCzF label
Branch Coprocessor z True BCzT
Branch Coprocessor z False Likely* BCzFL
Branch Coprocessor z True Likely* BCzTL
Coprocessor z Operation Cz expression
Control From Coprocessor z CFCz dest-gpr, source
Control To Coprocessor z CTCz src-gpr, destination
* Not valid in MIPS1 architectures.

** Not valid in MIPS1 and MIPS2 architectures.
Note: You cannot use coprocessor load and store instructions with the system control
coprocessor (cp0).
66
Coprocessor Interface Instruction Descriptions
Table 5-13 Coprocessor Interface Instruction Descriptions
Branch Coprocessor Branches to the specified label when the specified

z True (BCzT) coprocessor asserts a true condition. The z selects one of the
coprocessors. A previous coprocessor operation sets the
condition.

z False (BCzF) coprocessor asserts a false condition. The z selects one of the
coprocessors. A previous coprocessor operation sets the
condition.

z True Likely coprocessor asserts a true condition. If the conditional
(BCzTL) branch is not taken, the instruction in the branch delay slot
is nullified.
within a .set noreorder block. The assembler does not attempt
to schedule the delay slot of a branch likely instruction.

z False Likely coprocessor asserts a false condition. If the conditional
(BCzFL) branch is not taken, the instruction in the branch delay slot
is nullified.
within a .set noreorder block. The assembler does not attempt
to schedule the delay slot of a branch likely instruction.
Control From Stores the contents of the coprocessor control register

Coprocessor z specified by the source in the general register specified by
(CFCz) dest-gpr.
Control To Stores the contents of the general register specified by src-gpr

Coprocessor (CTCz) in the coprocessor control register specified by the
destination.
Coprocessor z Executes a coprocessor-specific operation on the specified

Operation (Cz) coprocessor. The z selects one of four distinct coprocessors.
67
Table 5-13 (continued) Coprocessor Interface Instruction Descriptions
Load Word Loads the destination with the contents of a word that is at
Coprocessor z the memory location specified by the effective address. The
(LWCz) z selects one of four distinct coprocessors. Load Word
Coprocessor replaces all register bytes with the contents of
the loaded word. If bits 0 and 1 of the effective address are
not zero, the machine signals an address exception.
Load Double Loads a doubleword from the memory location specified by

Coprocessor z the effective address and makes the data available to
(LDCz) coprocessor unit z. The manner in which each coprocessor
uses the data is defined by the individual coprocessor
specifications. This instruction is not valid in MIPS1
architectures. If any of the three least-significant bits of the
effective address are non-zero, the machine signals an
Move From Stores the contents of the coprocessor register specified by

Coprocessor z the source in the general register specified by dest-gpr.
(MFCz)
Move To Stores the contents of the general register specified by src-gpr

Coprocessor z in the coprocessor register specified by the destination.
(MTCz)
Doubleword Move Stores the 64-bit contents of the coprocessor register

From Coprocessor z specified by the source into the general register specified by
(DMFCz) dest-gpr.
Doubleword Move Stores the 64-bit contents of the general register src-gpr into
To Coprocessor z the coprocessor register specified by the destination.
(DMTCz)
68
Table 5-13 (continued) Coprocessor Interface Instruction Descriptions
Store Word Stores the contents of the coprocessor register in the memory
Coprocessor z location specified by the effective address. The z selects one
(SWCz) of four distinct coprocessors. If bits 0 and 1 of the effective
address are not zero, the machine signals an address error
exception.
Store Double Coprocessor z sources a doubleword, which the processor

Coprocessor z writes the memory location specified by the effective
(SDCz) address. The data to be stored is defined by the individual
coprocessor specifications. This instruction is not valid in
MIPS1 architecture. If any of the three least-significant bits of
the effective address are non-zero, the machine signals an
69
Chapter 6
6. Coprocessor Instruction Set
This chapter describes the coprocessor instructions for these coprocessors:

• System control coprocessor (cp0) instructions
• Floating-point coprocessor instructions
Topics covered in this chapter include:

• “Instruction Notation” on page 72
• “Floating-Point Instructions” on page 73
• “System Control Coprocessor Instructions” on page 91
See Chapter 5 for a description of the main processor’s instructions and the coprocessor
interface instructions.
71
Chapter 6: Coprocessor Instruction Set
The tables in this chapter list the assembler format for each coprocessor’s load, store,
computational, jump, branch, and special instructions. The format consists of an op-code
and a list of operand formats. The tables list groups of closely related instructions; for
those instructions, you can use any op-code with any specified operand.
Note: The system control coprocessor instructions do not have operands.
Operands can have any of these formats:

• Memory references: for example, a relocatable symbol +/– an expression(register)
• Expressions (for immediate values)
• Two or three operands: for example, ADD $3,$4 is the same as ADD $3,$3,$4
• The following terms are used to discuss floating-point operations:
• infinite: A value of +1 or –1.
• infinity: A symbolic entity that represents values with magnitudes greater than the
largest value in that format.
• ordered: The usual result from a comparison, namely: <,=, or >.
• NaN: Symbolic entities that represent values not otherwise available in
floating-point formats. There are two kinds of NaNs. Quiet NaNs represent
unknown or uninitialized values. Signaling NaNs represent symbolic values and
values that are too big or too precise for the format. Signaling NaNs raise an invalid
operation exception whenever an operation is attempted on them.
• unordered: The condition that results from a floating-point comparison when one
or both operands are NaNs.
72
Floating-Point Instructions
The floating-point coprocessor has these classes of instructions:

• Load and Store Instructions: Load values and move data between memory and
coprocessor registers.
• Move Instructions: Move data between registers.
• Computational Instructions: Do arithmetic and logical operations on values in
coprocessor registers.
• Relational Instructions: Compare two floating-point values.
A particular floating-point instruction may be implemented in hardware, software, or a

combination of hardware and software.
Floating-Point Formats
The formats for the single- and double-precision floating-point constants are shown in
Figure 6-1:
0 1 8 9 31 (big−endian)
1 8 bits 23 bits
31 30 23 22 0 (little−endian)
SINGLE−PRECISION
(big−endian)
0 1 11 12 63
1 11 bits 52 bits
63 62 52 51 0
(little−endian)
DOUBLE−PRECISION
Figure 6-1 Floating-Point Formats
73
Floating-Point Load and Store Formats
Floating-point load and store instructions must use even registers. The operands in the
following table have these meanings:
Operand Meaning
address Offset (base)
Table 6-1 Floating-Point Load and Store Formats
Description Op-Code Operand
Load Fp
Double L.D destination, address
Single L.S
Load Indexed Fp
Double LDXC1 destination, index(base)
Single LWXC1
Load Immediate Fp
Double LI.D destination, floating-point constant
Single LI.S
Store Fp
Double S.D source, address
Single S.S
Store Indexed Fp
Double SDXC1 destination, index(base)
Single SWXC1
74
Floating-Point Load and Store Descriptions
This part of Chapter 6 groups the instructions by function. Please consult “Floating-Point
Instructions” for the op-codes.
Table 6-2 describes the floating-point Load and Store instructions.
Table 6-2 Floating-Point Load and Store Descriptions
Instruction Description
Load Fp Instructions Load eight bytes for double-precision and four bytes for
single-precision from the specified effective address into
the destination register, which must be an even register
(32-bit only). The bytes must be word aligned. Note: It is
recommended that you use doubleword alignment for
double-precision operands. It is required in the MIPS2
architecture (R4000 and later).
Load Indexed Fp Indexed loads follow the same description as the load
Instructions instructions above except that indexed loads use
index+base to specify the effective address (64-bit only).
Store Fp Instructions Stores eight bytes for double-precision and four bytes for
single-precision from the source floating-point register in
the destination register, which must be an even register
(32-bit only). Note: It is recommended that you use
doubleword alignment for double-precision operands. It
is required in the MIPS2 architecture and later.
Store Indexed Fp Indexed stores follow the same description as the store
Instructions instructions above except that indexed stores use
index+base to specify the effective address (64-bit only).
75
Floating-Point Computational Formats
This part of Chapter 6 describes floating-point computational instructions. The operands

in the following table have these meanings:
Operand Meaning
gpr General-purpose register
Table 6-3 Floating-Point Computational Instructions
Absolute Value Fp
Double ABS.D destination, src1
Single ABS.S
Negate Fp
Double NEG.D
Single NEG.S
Add Fp
Double ADD.D destination, src1, src2
Single ADD.S
Divide Fp
Double DIV.D
Single DIV.S
Multiply Fp
Double MUL.D
Single MUL.S
Subtract Fp
76
Table 6-3 (continued) Floating-Point Computational Instructions
Absolute Value Fp
Double SUB.D
Single SUB.S
Multiply Add FP
Double MADD.D destination, src1, src2, src3
Single MADD.S
Negative Multiply Add FP
Double NMADD.D
Single NMADD.S
Multiply Subtract FP
Double MSUB.D
Single MSUB.S
Negative Multiply Subtract FP
Double NMSUB.D
Single NMSUB.S
Convert Source to Specified Fp Precision
Double to Single Fp CVT.S.D destination, src1
Fixed Point to Single Fp CVT.S.W
Single to Double Fp CVT.D.S
Fixed Point to Double Fp CVT.D.W
Single to Fixed Point Fp CVT.W.S
Double to Fixed Point Fp CVT.W.D
Truncate and Round Operations
Truncate to Single Fp TRUNC.W.S destination, src, gpr
77
Absolute Value Fp
Truncate to Double Fp TRUNC.W.D
Round to Single Fp ROUND.W.S
Round to Double Fp ROUND.W.D
Ceiling to Double Fp CEIL.W.D
Ceiling to Single Fp CEIL.W.S
Ceiling to Double Fp, Unsigned CEILU.W.D
Ceiling to Single Fp, Unsigned CEILU.W.S
Floor to Double Fp FLOOR.W.D
Floor to Single Fp FLOOR.W.S
Floor to Double F, Unsigned FLOORU.W.D
Floor to Single Fp Unsigned FLOORU.W.S
Round to Double Fp Unsigned ROUNDU.W.D
Round to Single Fp Unsigned ROUNDU.W.S
Truncate to Double Fp Unsigned TRUNCU.W.D
Truncate to Single Fp Unsigned TRUNCU.W.S
Table 6-4 Floating-Point Computational Instructions
Convert Source to Specified Fp Precision
Long Fixed Point to Single Fp CVT.S.L destination, src1
Long Fixed Point to Double FP CVT.D.L
Single to Long Fixed Point FP CVT.L.S
Double to Long Fixed Point FP CVT.L.D
78
Truncate and Round Operations
Truncate Single to Long Fixed Point TRUNC.L.S destination, src, gpr
Truncate Double to Long Fixed Point TRUNC.L.D
Round Single to Long Fixed Point ROUND.L.S
Round Double to Long Fixed Point ROUND.L.D
Ceiling Single to Long Fixed Point CEIL.L.S
Ceiling Double to Long Fixed Point CEIL.L.D
Floor Single to Long Fixed Point FLOOR.L.S
Floor Double to Long Fixed Point FLOOR.L.D
Reciprocal Approximation Operations
Reciprocal Approximation Single Fp RECIP.S destination, src1
Reciprocal Approximation Double Fp RECIP.D
Reciprocal Square Root Single Fp RSQRT.S
Reciprocal Square Root Double Fp RSQRT.D
79
Floating-Point Computational Instruction Descriptions
This part of Chapter 6 groups the instructions by function. Refer to Table 6-6 and
Table 6-8 for the op-code names. Table 6-5 describes the floating-point Computational
instructions.
Table 6-5 Floating-Point Computational Instruction Descriptions
Absolute Value Fp Compute the absolute value of the contents of src1

Instructions and put the specified precision floating-point result
in the destination register.
Add Fp Instructions Add the contents of src1 (or the destination) to the
contents of src2 and put the result in the destination
register. When the sum of two operands with
opposite signs is exactly zero, the sum has a positive
sign for all rounding modes except round toward –1.
For that rounding mode, the sum has a negative sign.
Convert Source to Another Convert the contents of src1 to the specified precision,
Precision Fp Instructions round according to the rounding mode, and put the
Multiply-Then-Add Fp Multiply the contents of src2 and src3, then add the
Instructions result to src1 and store in the destination register
(MADD). The NMADD instruction does the same
multiply then add, but then negates the sign of the
result (64-bit only).
Multiply-Then-Subtract Fp Multiply the contents of src2 and src3, then subtract

Instructions the result from src1 and store in the destination
register (MSUB). The NMSUB instruction does the
same multiply then subtract, but then negates the
sign of the result (64-bit only).
Truncate and Round The TRUNC instructions truncate the value in the
instructions source floating-point register and put the resulting
integer in the destination floating-point register,
using the third (general-purpose) register to hold a
temporary value. (This is a macro-instruction.) The
ROUND instructions work like TRUNC, but round
the floating-point value to an integer instead of
truncating it.
80
Table 6-5 (continued) Floating-Point Computational Instruction Descriptions
Divide Fp Instructions Compute the quotient of two values. These

instructions treat src1 as the dividend and src2 as the
divisor. Divide Fp instructions divide the contents of
src1 by the contents of src2 and put the result in the
destination register. If the divisor is a zero, the
machine signals a error if the divide-by-zero
exception is enabled.
Multiply Fp Instructions Multiplies the contents of src1 (or the destination)

with the contents of src2 and puts the result in the
Negate FP Instructions Compute the negative value of the contents of src1

and put the specified precision floating-point result
in the destination register.
Subtract Fp Instructions Subtract the contents of src2 from the contents of src1
(or the destination). These instructions put the result
in the destination register. When the difference of two
operands with the same signs is exactly zero, the
difference has a positive sign for all rounding modes
except round toward –1. For that rounding mode, the
sum has a negative sign.
Reciprocal Approximation For RECIP, the reciprocal of the value in src1 is

Instructions approximated and placed into the destination
register. For RSQRT. the reciprocal of the square root
of the value in src1 is approximated and placed into
the destination register.
Floating-Point Relational Operations
Table 6-6 summarizes the floating-point relational instructions. The first column under
Condition gives a mnemonic for the condition tested. As the “branch on true/false”
condition can be used logically to negate any condition, the second column supplies a
mnemonic for the logical negation of the condition in the first column. This provides a
total of 32 possible conditions. The four columns under Relations give the result of the
comparison based on each condition. The final column states if an invalid operation is
signaled for each condition.
81
For example, with an equal condition (EQ mnemonic in the True column), the logical
negation of the condition is not equal (NEQ), and a comparison that is equal is True for
equal and False for greater than, less than, and unordered, and no Invalid Operation
Exception is given if the relation is unordered.
Table 6-6 Floating-Point Relational Operators
Conditions: Conditions: Relations: Invalid Operation

Exception If
Mnemonics Mnemonics Greater Less Equal Unordered Unordered
True False Than Than
F T F F F F no
UN OR F F F T no
EQ NEQ F F T F no
UEQ OLG F F T T no
OLT UGE F T F F no
ULT OGE F T F T no
OLE UGT F T T F no
ULE OGT F T T T no
SF ST F F F F yes
NGLE GLE F F F T yes
SEQ SNE F F T F yes
NGL GL F F T T yes
LT NLT F T F F yes
NGE GE F T F T yes
LE NLE F T T F yes
NGT GT F T T T yes
82
The mnemonics in Table 6-6 have following meanings:
Mnemonic Meaning Mnemonic Meaning
F False T True
UN Unordered OR Ordered
EQ Equal NEQ Not Equal
UEQ Unordered or Equal OLG Ordered or Less than or Greater
Than
OLT Ordered Less Than UGE Unordered or Greater Than or
Equal
ULT Unordered or Less Than OGE Ordered Greater Than or Equal
OLE Ordered Less Than or Equal UGT Unordered or Greater Than
ULE Unordered or Less Than or OGT Ordered Greater Than
Equal
SF Signaling False ST Signaling True
NGLE Not Greater Than or Less GLE Greater Than, or Less Than or
Than or Equal Equal
SEQ Signaling Equal SNE Signaling Not Equal
NGL Not Greater Than or Less GL Greater Than or Less Than
Than
LT Less Than NLT Not Less Than
NGE Not Greater Than GE Greater Than or Equal
LE Less Than or Equal NLE Not Less Than or Equal
NGT Not Greater Than GT Greater Than
To branch on the result of a relational:

/* branching on a compare result */
c.eq.s $fcc0, $f1, $f2 /* compare the single-precision values */

bc1t $fcc0, true /* if $f1 equals $f2, branch to true */
bc1f $fcc0, false /* if $f1 does not equal $f2, branch to false */
83
Floating-Point Relational Instruction Formats
These are the floating-point relational instruction formats.
Table 6-7 Floating-Point Relational Instructions
Compare F
Double C.F.D src1,src2
Single C.F.S
Compare UN
Double C.UN.D
Single C.UN.S
Compare EQ
Double C.EQ.D
Single C.EQ.S
Compare UEQ
Double C.UEQ.D
Single C.UEQ.S
Compare OLT
Double C.OLT.D
Single C>OLT.S
Compare ULT
Double C.ULT.D
Single C.ULT.S
Compare OLE
Double C.OLE.D
Single C.OLE.S
84
Table 6-7 (continued) Floating-Point Relational Instructions
Compare ULE
Double C.ULE.D
Single C.ULE.S
Compare SF
Double C.SF.D
Single C.SF.S
Compare NGLE
Double C.NGLE.D src1, src2
Single C.NGLE.S
Compare SEQ
Double C.SEQ.D
Single C.SEQ.S
Compare NGL
Double C.NGL.D
Single C.NGL.S
Compare LT
Double C.LT.D
Single C.LT.S
Compare NGE
Double C.NGE.D
Single C.NGE.S
Compare LE
Double C.LE.D
Single C.LE.S
85
Table 6-7 (continued) Floating-Point Relational Instructions
Compare NGT
Double C.NGT.D
Single C.NGT.S
Note: These are the most common Compare instructions. The MIPS coprocessor
instruction set provides others for IEEE compatibility.
Floating-Point Relational Instruction Descriptions
Table 6-8 describes the relational instruction descriptions by function. Refer to Chapter 1
for information about registers.
Table 6-8 Floating-Point Relational Instruction Descriptions
Compare EQ Instructions Compare the contents of src1 with the contents of

src2. If src1 equals src2 a true condition results;
otherwise, a false condition results. The machine
does not signal an exception for unordered values.
Compare F Instructions Compare the contents of src1 with the contents of

src2. These instructions always produce a false
condition. The machine does not signal an exception
for unordered values.
Compare LE Compare the contents of src1 with the contents of

src2. If src1 is less than or equal to src2, a true
condition results; otherwise, a false condition results.
The machine signals an exception for unordered
values.
Compare LT Compare the contents of src1 with the contents of

src2. If src1 is less than src2, a true condition results;
signals an exception for unordered values.
86
Table 6-8 (continued) Floating-Point Relational Instruction Descriptions
Compare NGE Compare the contents of src1 with the contents of

src2. If src1 is less than src2 (or the contents are
unordered), a true condition results; otherwise, a
false condition results. The machine signals an
exception for unordered values.
Compare NGL Compare the contents of src1 with the contents of

src2. If src1 equals src2 or the contents are unordered,
a true condition results; otherwise, a false condition
results. The machine signals an exception for
unordered values.
Compare NGLE Compare the contents of src1 with the contents of

src2. If src1 is unordered, a true condition results;
Compare NGT Compare the contents of src1 with the contents of

src2. If src1 is less than or equal to src2 or the contents
are unordered, a true condition results; otherwise, a
false condition results. The machine signals an
exception for unordered values.
Compare OLE Instructions Compare the contents of src1 with the contents of
src2. If src1 is less than or equal to src2, a true
The machine does not signal an exception for
unordered values.
Compare OLT Instructions Compare the contents of src1 with the contents of
src2. If src1 is less than src2, a true condition results;
does not signal an exception for unordered values.
Compare SEQ Instructions Compare the contents of src1 with the contents of
src2. If src1 equals src2, a true condition results;
Compare SF Instructions Compare the contents of src1 with the contents of

src2. This always produces a false condition. The
machine signals an exception for unordered values.
87
Table 6-8 (continued) Floating-Point Relational Instruction Descriptions
Compare ULE Instructions Compare the contents of src1 with the contents of
src2. If src1 is less than or equal to src2 (or src1 is
false condition results. The machine does not signal
an exception for unordered values.
Compare UEQ Instructions Compare the contents of src1 with the contents of
src2. If src1 equals src2 (or src1 and src2 are
Compare ULT Instructions Compare the contents of src1 with the contents of
src2. If src1 is less than src2 (or the contents are
Compare UN Instructions Compare the contents of src1 with the contents of

src2. If either src1 or src2 is unordered, a true
The machine does not signal an exception for
unordered values.
88
Floating-Point Move Formats
The floating-point move instructions move data from source to destination registers (only
floating-point registers are allowed).
Table 6-9 Floating-Point Move Formats
Move FP
Single MOV.S destination,src1
Double MOV.D
Move Conditional on FP False MOVF gpr_dest, gpr_src, cc
Move Conditional on FP True MOVT gpr_dest, gpr_src, cc
Floating-Point Move Conditional on

FP False
Single MOVF.S destination, src1, cc
Double MOVF.D

FP True
Single MOVT.S destination, src1, cc
Double MOVT.D

Not Zero
Single MOVN.S destination, src1, gpr
Double MOVN.D
Floating-Point Move Conditional on Zero
Single MOVZ.S destination, src1, gpr
Double MOVZ.D
89
Floating-Point Move Instruction Descriptions
Table 6-10 describes the floating-point move instructions.
Table 6-10 Floating-Point Move Instruction Descriptions
Move FP Instructions Move the double or single-precision contents of src1 to the

destination register, maintaining the specified precision.
Conditional Move Move the general-purpose register, src1, to the destination

Instructions register if the condition code (cc) is zero (MOVF) or is one
(MOVT).
Conditional FP Move Conditionally, move the double-precision or

Instructions single-precision contents of src1 to the destination register,
maintaining the specified precision.
Floating-Point Conditionally, move a floating-point value from src1 to the

Conditional Move destination register if the gpr_register is zero (MOVZ) or
Instructions not equal to zero (MOVN).
90
System Control Coprocessor Instructions
The system control coprocessor (cp0) handles all functions and special and privileged
registers for the virtual memory and exception handling subsystems. The system control
coprocessor translates addresses from a large virtual address space into the machine’s
physical memory space. The coprocessor uses a translation lookaside buffer (TLB) to
translate virtual addresses to physical addresses.
System Control Coprocessor Instruction Formats
These coprocessor system control instructions do not have operands.
Table 6-11 System Control Coprocessor Instruction Formats
Description Op-code
Cache (not valid in MIPS1 and MIPS2 architectures) CACHE
Translation Lookaside Buffer Probe TLBP
Translation Lookaside Buffer Read TLBR
Translation Lookaside Buffer Write Random TLBWR
Translation Lookaside Write Index TLBWI
Synchronize (not valid in MIPS1 architectures) SYNC
91
System Control Coprocessor Instruction Descriptions
Table 6-12 describes the system control coprocessor instructions.
Table 6-12 System Control Coprocessor Instruction Descriptions
Cache (CACHE) Cache is the R4000 instruction to perform cache

operations. The 16-bit offset is sign-extended and
added to the contents of general register base to form
a virtual address. The virtual address is translated to
a physical address using the TLB. The 5-bit
sub-opcode (“op”) specifies the cache operation for
that address. Part of the virtual address is used to
specify the cache block for the operation. Possible
operations include invalidating a cache block,
writeback to a secondary cache or memory, etc.
Note: This instruction is not valid in MIPS1 or MIPS2
architectures.
Translation Lookaside Probes the translation lookaside buffer (TLB) to see if

Buffer Probe (TLBP) the TLB has an entry that matches the contents of the
EntryHi register. If a match occurs, the machine loads
the Index register with the number of the entry that
matches the EntryHi register. If no TLB entry
matches, the machine sets the high-order bit of the
Index register.
Translation Lookaside Loads the EntryHi and EntryLo registers with the
Buffer Read (TLBR) contents of the translation lookaside buffer (TLB)
entry specified in the TLB Index register.
Translation Lookaside Loads the specified translation lookaside buffer (TLB)

BufferWrite Random entry with the contents of the EntryHi and EntryLo
(TLBWR) registers. The contents of the TLB Random register
specify the TLB entry to be loaded.
92
Table 6-12 (continued) System Control Coprocessor Instruction Descriptions
Translation Lookaside Loads the specified translation lookaside buffer (TLB)

Buffer Write Index (TLBWI) entry with the contents of the EntryHI and EntryLO
registers. The contents of the TLB Index register
specify the TLB entry to be loaded.
Synchronize (SYNC) Ensures that all loads and stores fetched before the
sync are completed, before allowing any following
loads or stores. Use of sync to serialize certain
memory references may be required in
multiprocessor environments.
Note: This instruction is not valid in the MIPS1
architecture.
Control and Status Register
Floating-point coprocessor control register 31 contains status and control information.

See Figure 6-2. It controls the arithmetic rounding mode and the enabling of user-level
traps, and indicates exceptions that occurred in the most recently executed instruction,
and any exceptions that may have occurred without being trapped:
31 24 23 22 18 17 12 11 7 6 2 1 0
sticky−
0 c 0 exceptions enables 0
bits
bits: 8 1 5 6 5 5 2
Control and Status Register
(c = compare bit)
11 10 9 8 7 17 16 15 14 13 12 6 5 4 3 2
V Z O U I E V Z O U I V Z O U I
Enable Bits Exception Bits Sticky Bits
Figure 6-2 Floating Control and Status Register 31
93
The exception bits are set for instructions that cause an IEEE standard exception or an
optional exception used to emulate some of the more hardware-intensive features of the
IEEE standard.
The exception field is loaded as a side-effect of each floating-point operation (excluding

loads, stores, and unformatted moves). The exceptions which were caused by the
immediately previous floating-point operation can be determined by reading the
exception field.
The meaning of each bit in the exception field is given below. If two exceptions occur
together on one instruction, the field will contain the inclusive-OR of the bits for each
exception:
Exception Description
Field Bit
E Unimplemented Operation
I Inexact Exception
O Overflow Exception
U Underflow Exception
V Invalid Operation
Z Division-by-Zero
The unimplemented operation exception is normally invisible to user-level code. It is

provided to maintain IEEE compatibility for non-standard implementations.
94
The five IEEE standard exceptions are listed below:
Field Description
I Inexact Exception
O Overflow Exception
U Underflow Exception
V Invalid Operation
Z Division-by-Zero
Each of the five exceptions is associated with a trap under user control, which is enabled
by setting one of the five bits of the enable field, shown above.
When an exception occurs, both the corresponding exception and status bits are set. If the
corresponding enable flag bit is set, a trap is taken. In some cases the result of an
operation is different if a trap is enabled.
The status flags are never cleared as a side effect of floating-point operations, but may be
set or cleared by writing a new value into the status register, using a “move to
coprocessor control” instruction.
The floating-point compare instruction places the condition which was detected into the
"c" bit of the control and status register, so that the state of the condition line may be
saved and restored. The "c" bit is set if the condition is true, and cleared if the condition
is false, and is affected only by compare and move to control register instructions.
95
Exception Trap Processing
For each IEEE standard exception, a status flag is provided that is set on any occurrence
of the corresponding exception condition with no corresponding exception trap
signaled. It may be reset by writing a new value into the status register. The flags may be
saved and restored individually, or as a group, by software. When no exception trap is
signaled, a default action is taken by the floating-point coprocessor, which provides a
substitute value for the original, exceptional, result of the floating-point operation. The
default action taken depends on the type of exception, and in the case of the Overflow
exception, the current rounding mode.
Invalid Operation Exception
The invalid operation exception is signaled if one or both of the operands are invalid for
an implemented operation. The result, when the exception occurs without a trap, is a
quiet NaN when the destination has a floating-point format, and is indeterminate if the
result has a fixed-point format. The invalid operations are:
• Addition or subtraction: magnitude subtraction of infinities, such as
( + 1 ) – ( – 1 ).
• Multiplication: 0 times 1, with any signs.
• Division: 0 over 0 or 1 over 1, with any signs.
• Square root of x: where x is less than zero.
• Conversion of a floating-point number to a fixed-point format when an overflow, or
operand value of infinity or NaN, precludes a faithful representation in that format.
• Comparison of predicates involving < or > without ?, when the operands are
“unordered”.
• Any operation on a signaling NaN.
96
Software may simulate this exception for other operations that are invalid for the given
source operands. Examples of these operations include IEEE-specified functions
implemented in software, such as Remainder: x REM y, where y is zero or x is infinite;
conversion of a floating-point number to a decimal format whose value causes and
overflow or is infinity of NaN; and transcendental functions, such as ln (–5) or cos-1(3).
Division-by-zero Exception
The division by zero exception is signaled on an implemented divide operation if the

divisor is zero and the dividend is a finite nonzero number. The result, when no trap
occurs, is a correctly signed infinity.
If division by zero traps are enabled, the result register is not modified, and the source
registers are preserved.
Software may simulate this exception for other operations that produce a signed infinity,
such as ln(0), sec(p/2), csc(0) or 0-1.
Overflow Exception
The overflow exception is signaled when what would have been the magnitude of the
rounded floating-point result, were the exponent range unbounded, is larger than the
destination format’s largest finite number. The result, when no trap occurs, is determined
by the rounding mode and the sign of the intermediate result.
If overflow traps are enabled, the result register is not modified, and the source registers
are preserved.
97
Underflow Exception
Two related events contribute to underflow. One is the creation of a tiny non-zero result
between 2 Emin (minimum expressible exponent) which, because it is tiny, may cause
some other exception later. The other is extraordinary loss of accuracy during the
approximation of such tiny numbers by denormalized numbers.
The IEEE standard permits a choice in how these events are detected, but requires that
they must be detected the same way for all operations.
The IEEE standard specifies that “tininess” may be detected either: “after rounding”
(when a nonzero result computed as though the exponent range were unbounded would
lie strictly between 2 Emin), or “before rounding” (when a nonzero result computed as
though the exponent range and the precision were unbounded would lie strictly between
2 Emin). The architecture requires that tininess be detected after rounding.
Loss of accuracy may be detected as either “denormalization loss” (when the delivered
result differs from what would have been computed if the exponent range were
unbounded), or “inexact result” (when the delivered result differs from what would
have been computed if the exponent range and precision were both unbounded). The
architecture requires that loss of accuracy be detected as inexact result.
When an underflow trap is not enabled, underflow is signaled (via the underflow flag)
only when both tininess and loss of accuracy have been detected. The delivered result
might be zero, denormalized, or 2 Emin. When an underflow trap is enabled, underflow
is signaled when tininess is detected regardless of loss of accuracy.
If underflow traps are enabled, the result register is not modified, and the source registers
are preserved.
98
Inexact Exception
If the rounded result of an operation is not exact or if it overflows without an overflow

trap, then the inexact exception is signaled. The rounded or overflowed result is
delivered to the destination register, when no inexact trap occurs. If inexact exception
traps are enabled, the result register is not modified, and the source registers are
preserved.
Unimplemented Operation Exception
If an operation is specified that the hardware may not perform, due to an implementation
restriction on the supported operations or supported formats, an unimplemented
operation exception may be signaled, which always causes a trap, for which there are no
corresponding enable or flag bits. The trap cannot be disabled.
This exception is raised at the execution of the unimplemented instruction. The

instruction may be emulated in software, possibly using implemented floating-point unit
instructions to accomplish the emulation. Normal instruction execution may then be
restarted.
This exception is also raised when an attempt is made to execute an instruction with an
operation code or format code which has been reserved for future architectural
definition. The unimplemented instruction trap is not optional, since the current
definition contains codes of this kind.
This exception may be signaled when unusual operands or result conditions are
detected, for which the implemented hardware cannot handle the condition properly.
These may include (but are not limited to), denormalized operands or results, NaN
operands, trapped overflow or underflow conditions. The use of this exception for such
conditions is optional.
99
Floating-Point Rounding
Bits 0 and 1 of the coprocessor control register 31 sets the rounding mode for
floating-point. The machine allows four rounding modes:
• Round to nearest rounds the result to the nearest representable value. When the
two nearest representable values are equally near, this mode rounds to the value
with the least significant bit zero. To select this mode, set bits 1..0 of control register
31 to 0.
• Round toward zero rounds toward zero. It rounds to the value that is closest to and
not greater in magnitude than the infinitely precise result. To select this mode, set
bits 1..0 of control register 31 to 1.
• Round toward positive infinity rounds to the value that is closest to and not less
than the infinitely precise result. To select this mode, set bits 1..0 of control register
31 to 2.
• Round toward negative infinity rounds toward negative infinity. It rounds to the
value that is closest to and not greater than the infinitely precise result. To select this
mode, set bits 1..0 of control register 31 to 3.
To set the rounding mode:
/* setting the rounding mode */

RoundNearest = Ox0
RoundZero = Ox1
RoundPosInf = Ox2
RoundNegInf = Ox3
cfc1 rt2, $31 # move from coprocessor 1
and rt, Oxfffffffc # zero the round mode bits
or rt, RoundZero # set mask as round to zero
ctc1 rt, $f31 # move to coprocessor 1
100
Chapter 7
7. Linkage Conventions
This chapter gives rules and examples to follow when designing an assembly language
program. The chapter includes a tutorial section that contains information about how
calling sequences work. This involves writing a skeleton version of your prospective
assembly routine using a high level language, and then compiling it with the –S option
to generate a human-readable assembly language file. The assembly language file can
then be used as the starting point for coding your routine. Topics covered include:
• “Program Design” on page 102
• “Examples” on page 111
• “Writing Assembly Language Code” on page 114
This assembler works in either 32-bit, high performance 32-bit (N32) or 64-bit
compilation modes. While these modes are very similar, due to the difference in data,
register and address sizes, the N32 and 64-bit assembler linkage conventions are not
always the same as those for 32-bit mode. For details on some of these differences, see the
MIPSpro 64-Bit Porting and Transition Guide and MIPSpro N32 ABI Guide.
The procedures and examples in this chapter, for the most part, describe 32-bit
compilation mode. In some cases, specific differences necessitated by 64-bit mode are
highlighted.
101
Chapter 7: Linkage Conventions
Introduction
When you write assembly language routines, you should follow the same calling
conventions that the compilers observe, for two reasons:
• Often your code must interact with compiler-generated code, accepting and
returning arguments or accessing shared global data.
• The symbolic debugger gives better assistance in debugging programs using
standard calling conventions.
The conventions for the compiler system are a bit more complicated than some, mostly
to enhance the speed of each procedure call. Specifically:
• The compilers use the full, general calling sequence only when necessary; where
possible, they omit unneeded portions of it. For example, the compilers don’t use a
register as a frame pointer whenever possible.
• The compilers and debugger observe certain implicit rules rather than
communicating via instructions or data at execution time. For example, the
debugger looks at information placed in the symbol table by a “.frame” directive at
compilation time, so that it can tolerate the lack of a register containing a frame
pointer at execution time.
Program Design
This section describes some general areas of concern to the assembly language
programmer:
• Stack frame requirements on entering and exiting a routine.
• The “shape” of data (scalars, arrays, records, sets) laid out by the various high-level
languages.
For information about register format, and general, special, and floating-point registers,
see Chapter 1.
102
Program Design
The Stack Frame
This discussion of the stack frame, particularly regarding the graphics, describes 32-bit
operations. In 32-bit mode, restrictions such as stack addressing are enforced strictly.
While these restrictions are not enforced rigidly for 64-bit stack frame usage, their
observance is probably still a good coding practice, especially if you count on reliable
debugging information.
The compilers classify each routine into one of the following categories:
• Non-leaf routines, that is, routines that call other procedures.
• Leaf routines, that is, routines that do not themselves execute any procedure calls.
Leaf routines are of two types:
– Leaf routines that require stack storage for local variables
– Leaf routines that do not require stack storage for local variables.
You must decide the routine category before determining the calling sequence.
To write a program with proper stack frame usage and debugging capabilities, use the
following procedure:
1. Regardless of the type of routine, you should include a .ent pseudo-op and an entry
label for the procedure. The .ent pseudo-op is for use by the debugger, and the entry
label is the procedure name. The syntax is:
.ent procedure_name
procedure_name:
2. If you are writing a leaf procedure that does not use the stack, skip to step 3. For leaf
procedure that uses the stack or non-leaf procedures, you must allocate all the stack
space that the routine requires. The syntax to adjust the stack size is:
subu $sp,framesize
103
where framesize is the size of frame required; framesize must be a multiple of 16.
Space must be allocated for:
• Local variables.
• Saved general registers. Space should be allocated only for those registers
saved. For non-leaf procedures, you must save $31, which is used in the calls to
other procedures from this routine. If you use registers $16–$23, you must also
save them.
• Saved floating-point registers. Space should be allocated only for those registers
saved. If you use registers $f20–$f30 (for 32-bit) or $f24-$f31 (for 64-bit), you
must also save them.
• Procedure call argument area. You must allocate the maximum number of bytes for
arguments of any procedure that you call from this routine.
Note: Once you have modified $sp, you should not modify it again for the rest of the
routine.
3. Now include a .frame pseudo-op:
.frame framereg,framesize,returnreg
The virtual frame pointer is a frame pointer as used in other compiler systems but
has no register allocated for it. It consists of the framereg ($sp, in most cases) added
to the framesize (see step 2 above). Figure 7-1 illustrates the stack components for –32
and Figure 7-2 shows the stack components for –n32 and –64.
The returnreg specifies the register containing the return address (usually $31).
These usual values may change if you use a varying stack pointer or are specifying
a kernel trap routine.
104
Program Design
high memory
argument n
•
•
•
virtual argument 1
framepointer ($fp)
frame offset local & temporaries
saved registers framesize

(including returnreg)
argument build
stack pointer($sp)
(framereg) •
•
•
low memory
Figure 7-1 Stack Organization for –32
105
high memory
•
•
•
stack parameters
virtual
frame pointer ($fp)
register parameters a0 - a7
locals, temporaries, and saved registers
stack argument build
stack pointer ($sp)

(framereg) •
•
•
low memory
Figure 7-2 Stack Organization for –n32 and –64
4. If the procedure is a leaf procedure that does not use the stack, skip to step 7.
Otherwise you must save the registers you allocated space for in step 2.
To save the general registers, use the following operations:
.mask bitmask,frameoffset
sw reg,framesize+frameoffset–N($sp)
The .mask directive specifies the registers to be stored and where they are stored. A
bit should be on in bitmask for each register saved (for example, if register $31 is
saved, bit 31 should be “1” in bitmask. Bits are set in bitmask in little-endian order,
even if the machine configuration is big-endian). The frameoffset is the offset from
the virtual frame pointer (this number is usually negative). N should be 0 for the
highest numbered register saved and then incremented by four for each
subsequently lower numbered register saved. For example:
sw $31,framesize+frameoffset($sp)
sw $17,framesize+frameoffset–4($sp)
sw $16,framesize+frameoffset–16($sp)
Figure 7-3 illustrates this example.
106
Program Design
Now save any floating-point registers that you allocated space for in step 2 as
follows:
.fmask bitmask,frameoffsets.[sd]
reg,framesize+frameoffset–N($sp)
Notice that saving floating-point registers is identical to saving general registers
except for using the .fmask pseudo-op instead of .mask, and the stores are of
floating-point singles or doubles.The discussion regarding saving general registers
applies here as well, but remember that N should be incremented by 16 for doubles.
The stack framesize must be a multiple of 16.
high memory
virtual
framepointer ($fp)
frame offset
saved $31
saved $17
saved $16 framesize
•
•
•
stack pointer($sp)
low memory
Figure 7-3 Stack Example
107
5. This step describes parameter passing: how to access arguments passed into your
routine and passing arguments correctly to other procedures. For information on
high-level language-specific constructs (call-by-name, call-by-value, string or
structure passing), refer to the MIPSpro Compiling and Performance Tuning Guide.
As specified in step 2, space must be allocated on the stack for all arguments even
though they may be passed in registers. This provides a saving area if their registers
are needed for other variables.
General registers must be used for passing arguments. For 32-bit compilations,
general registers $4–$7 and float registers $f12, $f14 are used for passing the first
four arguments (if possible). You must allocate a pair of registers (even if it’s a
single-precision argument) that start with an even register for floating-point
arguments appearing in registers.
For 64-bit compilations, general registers $4–$11 and float registers $f12, through
$f19 are used for passing the first eight arguments (if possible).
In Table 7-1 and Table 7-2, the “fN” arguments are considered single- and
double-precision floating-point arguments, and “nN” arguments are everything
else. The ellipses (...) mean that the rest of the arguments do not go in registers
regardless of their type. The “stack” assignment means that you do not put this
argument in a register. The register assignments occur in the order shown in order
to satisfy optimizing compiler protocols:
Table 7-1 Parameter Passing (–32)
Argument List Register and Stack Assignments
f1, f2 $f12, $f14
f1, n1, f2 $f12, $6, stack
f1, n1, n2 $f12, $6 $7
n1, n2, n3, n4 $4, $5, $6, $7
n1, n2, n3, f1 $4, $5, $6, stack
n1, n2, f1 $4, $5, ($6, $6)
n1, f1 $4, ($6, $7)
108
Program Design
Table 7-2 Parameter Passing (–n32 and –64)
Argument List Register and Stack Assignments
d1,d2 $f12, $f13
s1,s2 $f12, $f13
s1,d1 $f12, $f13
d1,s1 $f12, $f13
n1,d1 $4,$f13
d1,n1,d1 $f12, $5,$f14
n1,n2,d1 $4, $5,$f14
d1,n1,n2 $f12, $5,$6
s1,n1,n2 $f12, $5,$6
d1,s1,s2 $f12, $f13, $f14
s1,s2,d1 $f12, $f13, $f14
n1,n2,n3,n4 $4,$5,$6,$7
n1,n2,n3,d1 $4,$5,$6,$f15
n1,n2,n3,s1 $4,$5,$6, $f15
s1,s2,s3,s4 $f12, $f13,$f14,$f15
s1,n1,s2,n2 $f12, $5,$f14,$7
n1,s1,n2,s2 $4,$f13,$6,$f15
n1,s1,n2,n3 $4,$f13,$6,$7
d1,d2,d3,d4,d5 $f12, $f13, $f14, $f15, $f16
d1,d2,d3,d4,d5,s1,s2,s3,s4 $f12, $f13, $f14, $f15, $f16, $f17, $f18,$f19,stack
d1,d2,d3,s1,s2,s3,n1,n2,n3 $f12, $f13, $f14, $f15, $f16, $f17, $10,$11, stack
109
6. Next, you must restore registers that were saved in step 4. To restore general
purpose registers:
lw reg,framesize+frameoffset–N($sp)
To restore the floating-point registers:
l.[sd] reg,framesize+frameoffset–N($sp)
Refer to step 4 for a discussion of the value of N.)
7. Get the return address:
lw $31,framesize+frameoffset($sp)
8. Clean up the stack:
addu framesize
9. Return:
j $31
10. To end the procedure:
.end procedurename
Differences in stack frame usage for –n32 and –64 compiles are summarized here. The
portion of the argument structure beyond the initial eight doublewords is passed in
memory on the stack, pointed to by the stack pointer at the time of call. The caller does
not reserve space for the register arguments; the callee is responsible for reserving it if
required (either adjacent to any caller-saved stack arguments if required, or elsewhere as
appropriate). No requirement is placed on the callee either to allocate space and save the
register parameters, or to save them in any particular place.
The Shape of Data
In most cases, high-level language routine and assembly routines communicate via
simple variables: pointers, integers, booleans, and single- and double-precision real
numbers. Describing the details of the various high-level data structures (arrays, records,
sets, and so on) is beyond our scope here. If you need to access such a structure as an
argument or as a shared global variable, refer to the MIPSpro Compiling, Debugging and
Performance Tuning Guide.
110
Examples
Examples
This section contains the examples that illustrate program design rules. Each example
shows a procedure written in C and its equivalent written in assembly language.
Example of Non-Leaf Procedure
The following example shows a non-leaf procedure. Notice that it creates a stackframe,
and also saves its return address since it must put a new return address into register $31
when it invokes its callee:
float
nonleaf(int i, int *j;)
{
double atof();
int temp;
temp = i - *j;
if (i < *j) temp = -temp;
return atof(temp);
}
.globl nonleaf
# 1 float
# 2 nonleaf(i, j)
# 3 int i, *j;
# 4 {
.ent nonleaf 2
nonleaf:
.cpload $25 ## Load $gp
subu $sp, 32 ## Create stackframe
sw $31, 20($sp) ## Save the return address
sw $sp, 24($sp) ## Save gp
.mask 0x80000000, -4
.frame $sp, 32, $31
# 5 double atof();
# 6 int temp;
# 7
# 8 temp = i - *j;
lw $2, 0($5) ## Arguments are in $4 and $5
subu $3, $4, $2
# 9 if (i < *j) temp = -temp;
bge $4, $2, $32 ## Note: $32 is a label,not a reg
negu $3, $3
111
$32:
# 10 return atof(temp);
move $4, $3
jal atof
cvt.s. $f0, $f0 ## Return value goes in $f0
lw $gp, 24($sp) ## Restore gp
lw $31, 20($sp) ## Restore return address
addu $sp, 32 ## Delete stackframe
j $31 ## Return to caller
.end nonleaf
The –n32 code for the previous example is shown below. Note that this code is under .set
noreorder, so be aware of delay slots.
.set noreorder
# Program Unit: nonleaf
.ent nonleaf
.globl nonleaf
nonleaf: # 0x0
.frame $sp, 32, $31
.mask 0x80000000, -32
lw $7,0($5) # load *j
addiu $sp,$sp,-32 # .frame.len.nonleaf
sd $gp,8($sp) # save $gp
sd $31,0($sp) # save $ra
lui $31,%hi(%neg(%gp_rel(nonleaf +0))) # load new $gp
addiu $31,$31,%lo(%neg(%gp_rel(nonleaf +0))) #
addu $gp,$25,$31 #
slt $1,$4,$7 # compare i to *j
beq $1,$0,.L.1.1.temp #
subu $7,$4,$7 # i - *j, in delay slot of branch
subu $7,$0,$7 # temp = -temp
.L.1.1.temp: # 0x2c
lw $25,%call16(atof)($gp) #
jalr $25 # atof
or $4,$7,$0 # delay slot of jalr loads arg
ld $31,0($sp) # restore $ra
cvt.s.d $f0,$f0 #
ld $gp,8($sp) # restore $gp
jr $31 #
addiu $sp,$sp,32 # .frame.len.nonleaf
.end nonleaf
112
Examples
Example of a Leaf Procedure
The example shown below is a leaf procedure that does not require stack space for local
variables. Notice that it creates no stackframe, and saves no return address.
int
leaf(int p1, int p2)
{
return (p1 > p2) ? p1 : p2;
}
.globl leaf
# 1 int
# 2 leaf(p1, p2)
# 3 int p1, p2;
# 4 {
.ent leaf2
leaf:
.frame $sp, 0, $31
# 5 return (p1 > p2) ? p1 : p2;
ble $4, $5, $32 ## Arguments in
## $4 and $5
move $3, $4
b $33
$32:
move $3, $5
$33:
move $2, $3 ## Return value
## goes in $2
j $31 ## Return to caller
# 6 }
.end leaf
113
The –n32 code for the previous example looks like this:
.set noreorder
.ent leaf
.globl leaf
leaf: # 0x0
.frame$sp, 0, $31
slt $2,$5,$4 # compare p1 and p2
beq $2,$0,.L.1.2.temp #
or $9,$4,$0 # delay slot
b .L.1.1.temp #
or $2,$9,$0 # delay slot, return p1
.L.1.2.temp: # 0x14
or $2,$5,$0 # return p2
.L.1.1.temp: # 0x18
jr $31 #
nop # delay slot
.end leaf
Writing Assembly Language Code
The rules and parameter requirements that exist between assembly language and other
languages are varied and complex. The simplest approach to coding an interface
between an assembly routine and a routine written in a high-level language is to do the
following:
• Use the high-level language to write a skeletal version of the routine that you plan
to code in assembly language.
• Compile the program using the –S option, which creates an assembly language (.s)
version of the compiled source file (the –O option, though not required, reduces the
amount of code generated, making the listing easier to read).
• Study the assembly-language listing and then, imitating the rules and conventions
used by the compiler, write your assembly language code.
114
Chapter 8
8. Pseudo Op-Codes
This chapter describes pseudo op-codes (directives). These pseudo op-codes influence
the assembler’s later behavior. In the text, boldface type specifies a keyword and italics
represents an operand that you define.
The assembler pseudo op-codes are listed in Table 8-1.
Table 8-1 Pseudo Op-Codes
Pseudo-Op Description
.2byte expression1 [ , expression2 ] ... Truncates the expressions in the

[ , expressionN] comma-separated list to 16-bit values and
assembles the values in successive locations.
The expressions must be absolute or in the form
of a label difference (label1 - label2) if both
labels are defined in the same section.
This directive optionally can have the form
expression1 [ : expression2 ]. The expression2
replicates expression1’s value expression2
times.
This directive does no automatic alignment.
(–n32 and –64 only)

assembles the values in successive
locations.The expressions must be absolute or
in the form of a label difference (label1 - label2)
if both labels are defined in the same section.
times.
This directive does no automatic alignment.
115
Chapter 8: Pseudo Op-Codes
Table 8-1 (continued) Pseudo Op-Codes

The expressions must be absolute or in the form
of a label difference (label1 - label2) if both
labels are defined in the same section.
times. This directive does no automatic
alignment. (–n32 and –64 only)
.aent name, symno Sets an alternate entry point for the current
procedure. Use this information when you
want to generate information for the
debugger. It must appear inside an .ent/.end
pair.
.align expression Advances the location counter to make the

expression low order bits of the counter zero.
Normally, the .half, .word, .float, and .double
directives automatically align their data
appropriately. For example, .word does an
implicit .align 2 (.double does an .align 3). You
disable the automatic alignment feature with
.align 0. The assembler reinstates automatic
alignment at the next .text, .data, .rdata, or .sdata
directive.
Labels immediately preceding an automatic or
explicit alignment are also realigned. For
example, foo: .align 3; .word 0 is the same as
.align 3; foo: .word 0.
.ascii string [, string]... Assembles each string from the list into
successive locations. The .ascii directive does
not null pad the string. You MUST put
quotation marks (”) around each string. You
can use the backslash escape characters. For a
list of the backslash characters, see Chapter 4.
116
.asciiz string [, string]... Assembles each string in the list into

successive locations and adds a null. You can
use the backslash escape characters. For a list
of the backslash characters, see Chapter 4.
.byte expression1 [, expression2 ] ... Truncates the expressions from the

[, expressionN] comma-separated list to 8-bit values, and
The expressions must be absolute. The
operands can optionally have the form:
replicates expression1’s value expression2 times.
.comm name, expression [alignment] Unless defined elsewhere, name becomes a

global common symbol at the head of a block
of expression bytes of storage. The linker
overlays like-named common blocks, using
the maximum of the expressions. The 64-bit and
N32 assembler also accepts an optional value
which specifies the alignment of the symbol.
.cpadd reg Emits code that adds the value of “_gp” to reg.
.cpload reg Expands into the three instructions function

prologue that sets up the $gp register. This
directive is used by position-independent
code.
.cplocal reg Causes the assembler to use reg instead of $gp

as the context pointer. This directive is used by
position-independent code. (–n32 and –64
only)
117
.cprestore offset Causes the assembler to emit the following at

the point where it occurs:
sw $gp, offset ($sp)
Also, causes the assembler to generate:
lw $gp, offset ($sp)
after every JAL or BAL operation. Offset
should point to the saved register area as
described in Chapter 7.
This directive is used by position-independent
code following the caller saved gp convention.
.cpreturn Causes the assembler to emit the following at

ld $gp, offset ($sp)
The offset is obtained from the previous
.cpsetup pseudo-op. (–n32 and –64 only)
.cpsetup reg1, {offset | reg2}, label Causes the assembler to emit the following at
sd $gp, offset ($sp)
lui $gp, 0 { label }
daddiu $gp, $gp, 0 { label }
daddu $gp, $gp, reg1
ld $gp, offset ($sp)
This sequence is used by
position-independent code following the
callee saved gp convention. It stores $gp in the
saved register area and calculates the virtual
address of label and places it in reg1. By
convention, reg1 is $25 (t9).
If reg2 is used instead of offset, $gp is saved
and restored to and from this register. (–n32
and –64 only)
.data Tells the assembler to add all subsequent data

to the data section.
118
.double expression Initializes memory to 64-bit floating point

[ , expression2] ...[, expressionN] numbers. The operands optionally can have
the form: expression1 [ : expression2 ]. The
expression1 is the floating point value. The
optional expression2 is a non-negative
expression that specifies a repetition count.
The expression2 replicates expression1’s value
expression2 times. This directive aligns its data
and any preceding labels automatically to a
double-word boundary. You can disable this
feature by using .align 0.
.dword expression Truncates the expressions in the

[ , expression2 ] ...[, expressionN] comma-separated list to 64-bits and assembles
the values in successive locations. The
expressions must be absolute. The operands
optionally can have the form: expression1
[:expression2]. The expresssion2 replicates
expression1’s value expression2 number of
times. The directive aligns its data and
preceding labels automatically to a
doubleword boundary. You can disable this
.dynsym name value Specifies an ELF st_other value for the object
denoted by name. (–n32 and –64 only)
.end [proc_name] Sets the end of a procedure. Use this directive

when you want to generate information for
the debugger. To set the beginning of a
procedure, see .ent.
.endr Signals the end of a repeat block. To start a

repeat block, see .repeat.
.ent proc_name Sets the beginning of the procedure proc_name.

Use this directive when you want to generate
information for the debugger. To set the end of
a procedure, see .end.
119
.extern name expression name is a global undefined symbol whose size

is assumed to be expression bytes. The
advantage of using this directive, instead of
permitting an undefined symbol to become
global by default, is that the assembler can
decide whether to use the economical
$gp-relative addressing mode, depending on
the value of the –G option. As a special case, if
expression is zero, the assembler refrains from
using $gp to address this symbol regardless of
the size specified by –G.
.file file_number file_name_string Specifies the source file corresponding to the

assembly instructions that follow. For use only
by compilers, not by programmers; when the
assembler sees this, it refrains from generating
line numbers for dbx to use unless it also sees
.loc directives.
.float expression1 Initializes memory to single-precision 32-bit

[ , expression2 ] ... [, expressionN] floating point numbers. The operands
[ : expression2 ]. The optional expression2 is a
non-negative expression that specifies a
repetition count. This optional form replicates
expression1’s value expression2 times. This
directive aligns its data and preceding labels
automatically to a word boundary. You can
disable this feature by using .align 0.
.fmask mask offset Sets a mask with a bit turned on for each
floating point register that the current routine
saved. The least-significant bit corresponds to
register $f0. The offset is the distance in bytes
from the virtual frame pointer at which the
floating point registers are saved. The
assembler saves higher register numbers
closer to the virtual frame pointer. You must
use .ent before .fmask and only one .fmask may
be used per .ent. Space should be allocated for
those registers specified in the .fmask.
120
.frame frame-register offset Describes a stack frame. The first register is the
return_pc_register frame-register, the offset is the distance from
the frame register to the virtual frame pointer,
and the second register is the return program
counter (or, if the first register is $0, this
directive shows that the return program
counter is saved four bytes from the virtual
frame pointer). You must use .ent before .frame
and only one .frame may be used per .ent. No
stack traces can be done in the debugger
without .frame.
.globl name Makes the name external. If the name is

defined otherwise (by its appearance as a
label), the assembler will export the symbol;
otherwise it will import the symbol. In
general, the assembler imports undefined
symbols (that is, it gives them the UNIX
storage class “global undefined” and requires
the linker to resolve them).
.gpvalue number Sets the offset to use in gp_rel relocations; 0 by

default. (–n32 and –64 only)
.gpword local-sym This directive is similar to .word except that the

relocation entry for local-sym has the
R_MIPS_GPREL32 type. After linkage, this
results in a 32-bit value that is the distance
between local-sym and gp. local-sym must be
local. This directive is used by the code
generator for PIC switch tables.
.half expression1 [ , expression2 ] ... Truncates the expressions in the

{, expressionN] comma-separated list to 16-bit values and
The expressions must be absolute. This
directive optionally can have the form:
times. This directive automatically aligns its
data appropriately. You can disable this
121
.lab label_name Associates a named label with the current

location in the program text. For use by
compilers.
.lcomm name, expression Makes the name’s data type bss. The assembler
allocates the named symbol to the bss area, and
the expression defines the named symbol’s
length. If a .globl directive also specifies the
name, the assembler allocates the named
symbol to external bss. The assembler puts bss
symbols in one of two bss areas. If the defined
size is smaller than (or equal to) the size
specified by the assembler or compiler’s –G
command line option, the assembler puts the
symbols in the sbss area and uses $gp to
address the data.
.loc file_number line_number Specifies the source file and the line within
[column] that file that corresponds to the assembly
instructions that follow. For use by compilers.
The assembler ignores the file number when
this directive appears in the assembly source
file. Then, the assembler assumes that the
directive refers to the most recent .file
directive. The 64-bit and N32 assembler also
supports an optional value that specifies the
column number.
.mask mask, offset Sets a mask with a bit turned on for each
general purpose register that the current
routine saved. For use by compilers. Bit one
corresponds to register $1. The offset is the
distance in bytes from the virtual frame
pointer where the registers are saved. The
assembler saves higher register numbers
closer to the virtual frame pointer. Space
should be allocated for those registers
appearing in the mask. If bit zero is set it is
assumed that space is allocated for all 31
registers regardless of whether they appear in
the mask.
122
.nada Tells the assembler to put in an instruction that

has no effect on the machine state. It has the
same effect as nop (described below), but it
produces more efficient code on an R8000.
.nop Tells the assembler to put in an instruction that

has no effect on the machine state. While
several instructions cause no-operation, the
assembler only considers the ones generated
by the nop directive to be wait instructions.
This directive puts an explicit delay in the
instruction stream.
Note: Unless you use “.set noreorder”, the

reorganizer may eliminate unnecessary “nop”
instructions.
.option options Tells the assembler that certain options were

in effect during compilation. (These options
can, for example, limit the assembler’s
freedom to perform branch optimizations.)
This option is intended for
compiler-generated .s files rather than for
hand-coded ones.
.origin expression Specifies the current offset in a section to the

value of expression. (–n32 and –64 only)
.repeat expression Repeats all instructions or data between the

.repeat directive and the .endr directive. The
expression defines how many times the data
repeats. With the .repeat directive, you cannot
use labels, branch instructions, or values that
require relocation in the block. To end a .repeat,
see .endr.
.rdata Tells the assembler to add subsequent data

into the rdata section.
.sdata Tells the assembler to add subsequent data to

the sdata section.
123
.section name [, section type, section Instructs the assembler to create a section with
flags, section entry size, section the given name and optional attributes. (–n32
alignment] and –64 only)
Legal section type values are denoted by
variables prefixed by SHT_ in <elf.h>.
Legal section flags values are denoted by
variables prefixed by SHF_ in <elf.h>.
The section entry size specifies the size of each
entry in the section. For example, it is 4 for .text
sections.
The section alignment specifies the byte
boundary requirement for the section. For
example, it is 16 for .text sections.
.set option Instructs the assembler to enable or to disable

certain options. Use .set options only for
hand-crafted assembly routines. The
assembler has these default options: reorder,
macro, and at. You can specify only one option
for each .set directive. You can specify these .set
options:
The reorder option lets the assembler reorder
machine language instructions to improve
performance. The noreorder option prevents
the assembler from reordering machine
language instructions. If a machine language
instruction violates the hardware pipeline
constraints, the assembler issues a warning
message.
The macro option lets the assembler generate
multiple machine instructions from a single
assembler instruction.
The nomacro option causes the assembler to
print a warning whenever an assembler
operation generates more than one machine
language instruction. You must select the
noreorder option before using the nomacro
option; otherwise, an error results.
124
.set option (continued) The at option lets the assembler use the $at
register for macros, but generates warnings if
the source program uses $at. When you use the
noat option and an assembler operation
requires the $at register, the assembler issues a
warning message; however, the noat option
does let source programs use $at without
issuing warnings.
The nomove option tells the assembler to mark
each subsequent instruction so that it cannot
be moved during reorganization. Because the
assembler can still insert nop instructions
where necessary for pipeline constraints, this
option is less stringent than noreorder. The
assembler can still move instructions from
below the nomove region to fill delay slots
above the region or vice versa. The nomove
option has part of the effect of the “volatile” C
declaration; it prevents otherwise
independent loads or stores from occurring in
a different order than intended.
The move option cancels the effect of nomove.
The notransform option tells the assembler to
mark each subsequent instruction so that it
cannot be transformed by pixie(1), into an
equivalent set of instructions. For an overview
of pixie(1) see the SpeedShop User’s Guide.
The transform option cancels the effect of
notransform.
.size name, expression Specifies the size of an object denoted by name

to the value of expression.
.space expression Advances the location counter by the value of

the specified expression bytes. The assembler
fills the space with zeros.
125
.struct expression This permits you to lay out a structure using

labels plus directives like .word, .byte, and so
forth. It ends at the next segment directive
(.data, .text, etc.). It does not emit any code or
data, but defines the labels within it to have
values which are the sum of expression plus
their offsets from the .struct itself.
(symbolic equate) Takes one of these forms: name = expression or

name = register. You must define the name only
once in the assembly, and you cannot redefine
the name. The expression must be computable
when you assemble the program, and the
expression must involve operators, constants,
and equated symbols. You can use the name as
a constant in any later statement.
.text Tells the assembler to add subsequent code to

the text section. (This is the default.)
.type name, value Specifies the elf type of an object denoted by

name to value. Legal elf type values are
denoted by variables prefixed by STT_ in
<elf.h>. (–n32 and –64 only)
.verstamp major minor Specifies the major and minor version

numbers (for example, version 0.15 would be
.verstamp 0 15).
.weakext weak_name [strong_name] Defines a weak external name and optionally

associates it with the strong_name.
.word expression1 [, expression2 ] ... Truncates the expressions in the

[, expressionN] comma-separated list to 32-bits and assembles
the values in successive locations. The
expressions must be absolute. The operands
[ : expression2 ]. The expression2 replicates
expression1’s value expression2 times. This
directive aligns its data and preceding labels
automatically to a word boundary. You can
disable this feature by using .align 0.
126
The directives listed below are only accepted in –32 compiles; they are only meant for
compiler-generated code, and should not be used in hand-written assembly code.
.alias
.asm0
.bgnb
.endb
.err
.gjaldef
.gjallive
.gjrlive
.livereg
.noalias
.set bopt/nobopt
.vreg
127
Index
Symbols B
(symbolic equate), 126 branch instructions

filling delay slots, 32
.byte, 117
Numbers
-64 directives, 115-127 C
.comm, 117, 118

A comments, 16
computational instructions, 32, 44
address
descriptions - table, 48
description, 11
descriptions, 11 conditional codes
format, 11 floating-point, 7
addressing, 9 constants, 17
alignment, 9 floating point, 18
scalar, 17
.aent name, symno, 116
string, 19
.align, 116
conventions
aligned data data types, 26
load and store instructions, 10 expression operators, 25
alignment, 9 expressions, 23
addressing, 9 lexical, 15
.ascii, 116 linkage, 101
.asciiz, 117 precedence, 24
assembler, 9 statements, 22
tokens, 16
129
Index
coprocessor instruction E
notation, 72
coprocessor instruction set, 71 ELF
coprocessor interface instructions, 66 relocations, 28
description of, 67 .end, 119
counters endianness, 1
sections and locations, 20 .endr, 119
.ent, 119
exception
D division by zero, 96
unimplemented operation, 98
.data, 118
exceptions, 13
data types floating-point, 14
conventions, 26 main processor, 13
description exception trap processing, 95
address, 11
execption
descriptions inexact, 98
load instructions, 36 invalid operation, 95
directives overflow, 96
-n32 and 64 directives, 115 trap processing, 95
-o32 directives, 127 underflow, 97
division by zero, 96 expression
.double, 119 type propagation, 28
.dword, 119 expression operators, 25
.dysym, 119 expressions, 23
precedence, 24
.extern name expression, 120
130
Index
F H
.file, 120 .half, 121

.float, 120
floating-point
computational - description, 80 I
computational - format, 76
conditional codes, 7 identifiers, 16
control register, 93 inexact exception, 98
exceptions, 14 instructions
instruction format, 73 classes of, 32
instructions, 73 computational, 44
load and store, 74 constraints and rules, 32
move instruction - description of, 90 coprocessor interface, 66
move instructions - format, 89 coprocessor interface - description, 66, 67
registers, 5 coprocessor interface format, 66
relational instruction - description, 86 floating-point, 73
relational instruction formats, 84 instruction notation, 32
relational operations, 81 jump and branch, 59
rounding, 99 load and store - unaligned data, 9
floating point constants, 18 miscellaneous tasks, 65
.fmask, 120 reorganization rules, 32
special, 65
format
address, 11 instruction set, 31
coprocessor, 71
formats
load and store, 34 invalid operation exception, 95
.frame, 121 issues, 22
G J
general registers, 2 jump and branch instructions, 32, 59

descriptions, 61
.globl, 121
formats, 59
.gpvalue, 121
-G value
link editor, 22
131
Index
K M
keyword statements, 23 .mask, 122

move instructions
floating-point, 89
L
.lab, 121, 122 N

label definitions
statements, 22 -n32 directives, 115-127
.lcomm, 122 non-leaf routines, 103
leaf routines, 103 nop, 115, 116, 117, 118, 123, 124, 126
lexical conventions, 15 null statements, 23
linkage
conventions, 101
program design, 102 O
link editor
-G option, 22 .option, 123
load, 9 overflow exception, 96
load and store
floating-point, 74
P
load and store instructions
formats, 34 performance, 32
load instructions maximizing, 32
delayed, 32 precedence in expressions, 24
description, 36
program design
lb (load byte), 10
linkage, 102
lbu (load byte unsigned), 10
lh (load halfword), 10 pseudo op-codes, 115-127
lhu (load halfword unsigned), 10
lw (load word), 10
lwl (load word left), 9
lwr (load word right), 9
ulh (unaligned load halfword), 10
ulh (unaligned load halfword unsigned), 10
ulw (unaligned load word), 10
.loc, 122
132
Index
R statements
keyword, 23
.rdata, 123 label definitions, 22
Register, 1 null, 23
register, 1 store instructions
endianness, 1 description, 40
format, 1 description - table, 41
registers format, 34
floating-point, 5 sb (store byte), 10
general, 2 sh (store halfword), 10
special, 4 sw (store word), 10
swl (store word left), 9, 10
relational operations
swr (store word right), 10
floating-point, 81
ush (unaligned store halfword), 10
relocations, 28 usw (unaligned store word), 10
.repeat, 123 string constants, 19
.struct, 126
S system control
instruction descriptions, 92
scalar constants, 17 instruction formats, 91
.sdata, 123
See, 65, 66 T
.set, 124, 125
shape of data, 110 .text, 126
shown, 11 tokens
.space, 125 comments, 16
special instructions, 32, 65 constants, 17
identifiers, 16
special registers, 4
type propagation in expression, 28
specify
a relocation, 28
stack frame, 103
stack organization- figure, 105
133
Index
unaligned data
load and store instructions, 9
underflow exception, 97
unimplemented operation exception, 98
value, 22
.verstamp, 126
.word, 126
134
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MIPSpro™ Assembly Language

Document Number 007-2418-003

Written by Larry Huffman, revised by Wendy Ferguson

Dedicated to the memory of our friend, Larry Huffman.

© Copyright 1997 Silicon Graphics, Inc.— All Rights Reserved

RESTRICTED RIGHTS LEGEND

Silicon Graphics and IRIS are registered trademarks and CASEVision,

MIPSpro™ Assembly Language Programmer’s Guide

About This Guide xiii

5. The Instruction Set 31

Jump and Branch Instructions 59

6. Coprocessor Instruction Set 71

7. Linkage Conventions 101

8. Pseudo Op-Codes 115

Figure 4-1 Section and Location Counters 21

Table 1-1 General (Integer) Registers (–32) 2

Table 6-1 Floating-Point Load and Store Formats 74

Many assembly language instructions have direct equivalents to machine instructions.

This book has these chapters:

• Chapter 6, “Coprocessor Instruction Set,” describes the coprocessor instruction

The R8000 CPU, at present, supports big-endian only.

Table 1-1 General (Integer) Registers (–32)

Register Name Software Name Use and Linkage

$0 Always has the value 0.

$1 or $at Reserved for the assembler.

$2..$3 v0-v1 Used for expression evaluations and to hold the

$4..$7 a0-a3 Pass the first 4 words of actual integer type

$8..$11 t0-t7 Temporary registers used for expression

$16..$23 s0-s7 Saved registers. Their values must be preserved

$25 t9 or jp PIC jump register.

$26..27 or k0-k1 Reserved for the operating system kernel.

Table 1-1 (continued) General (Integer) Registers (–32)

Register Name Software Name Use and Linkage

$28 or $gp gp Contains the global pointer.

$29 or $sp sp Contains the stack pointer.

$30 or $fp fp or s8 Contains the frame pointer (if needed);

$31 ra Contains the return address and is used for

Table 1-2 General (Integer) Registers (–n32 and –64)

Register Name Software Name Use and Linkage

$0 Always has the value 0.

$1 or $at Reserved for the assembler.

$2..$3 v0-v1 Used for expression evaluations and to hold the

$4..$7 a0-a3 Pass up to 8 words of actual integer type

$12..$15 t0-t3 Temporary registers used for expression

$16..$23 s0-s7 Saved registers. Their values must be preserved

$25 t9 or jp PIC jump register.

$26..27 or k0-k1 Reserved for the operating system kernel.

Table 1-2 (continued) General (Integer) Registers (–n32 and –64)

Register Name Software Name Use and Linkage

$28 or $gp gp Contains the global pointer.

$29 or $sp sp Contains the stack pointer.

$30 or $fp fp or s8 Contains the frame pointer (if needed);

$31 ra Contains the return address and is used for

Table 1-3 Special Registers

HI Multiply/Divide special register holds the most-significant 32

LO Multiply/Divide special register holds the least-significant 32

Table 1-4 Floating-Point Registers (–32)

Register Software Name Use and Linkage

$f0..$f2 fv0-fv1 Hold results of floating-point type function ($f0)