ESE 461

Design Automation for Integrated

Circuit Systems

Xuan ‘Silvia’ Zhang

Washington University in St. Louis

http://classes.engineering.wustl.edu/ese461/
You are in the wrong class if you

• Have never taken a digital logic class

(like CSE 260) before;
• Have never heard of MOSFET or CMOS
or transistors before;
• Think writing and debugging programs
are excruciatingly painful;
• Don’t like reasoning about automation
algorithms for repetitive tasks;
• Are not interested in designing your
very own integrated circuit chips.

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Course Objectives

• Understand the design flow of modern IC

– Very-large-scale integration (VLSI)
– language: Verilog
– tools: Synopsys, Cadence
– process: design, simulation, synthesis, verification, test
– principles: performance, power, other considerations

• Understand the basics of design automation

– study the basic algorithms used in VLSI design
– learn the automation techniques used in the tools

• Pique your interest to learn more on your own

– introduce some cutting-edge research topics

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Tentative Syllabus

• W1: Intro. Review combinational logic.

• W2: Labor day. Review sequential logic.
• W3: Review quiz, Linux and VCS tutorial.
• W3-W4: Verilog. Intro of design flow.
• W5: Logic synthesis.
• W6: Timing analysis.
• W7: Physical design.
• W8: Fall break. Class project intro.
• W9: I/O design and RC extraction.
• W10: Power optimization.
• W11: Hardware acceleration. HLS.
• W12: Reliability and security.
• W13: Conclusion. Thanksgiving.
• W14: Project presentation.

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What is the big deal about IC?

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Intelligence, everywhere

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Moore’s Law
Transistor count doubles every two years

Photo Credit: Intel

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Inside an iPad Air 2

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iPad Main Board

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Interface to the Physical World:
The camera

Focus/Exposure Control

Pre-processing

White-balancing

Demosaic

Color Transform

Post-processing

Compression

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Apple iPhone:
The quintessential smart system

source: ifixit.com

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source: anandtech.com

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Why should we care now?

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Bell’s Law of Computer Classes:
A new computing class roughly every decade

“Roughly every
decade a new, lower
priced computer class
forms based on a new
programming
platform, network,
and interface
resulting in new
usage and the
establishment of a
new industry.”
year - Adapted from D. Culler

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 15x size decrease
40x transistors
UMich Phoenix Processor
55x smaller λ Introduced 2008
Initial clock speed
106 kHz @ 0.5V Vdd
Number of transistors
92,499
Manufacturing technology
0.18 µ

source: Intel, U. Michigan

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Case Study: Internet-of-Things (IoT)

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Case Study: Internet-of-Things (IoT)

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Case Study: Internet-of-Things (IoT)

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Case Study: Deep Learning Hardware

• Artificial Intelligence (AI)

• Machine Learning
– a branch of machine learning
– deep neural networks (DNN)
– convolutional neural networks (CNN)
– recurrent neural networks (RNN)

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Case Study: Deep Learning Hardware

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Case Study: Deep Learning Hardware

• Study group planned

– meet once a week (Sunday afternoon)
– faculty-moderated, students-led
– read classic foundational papers in depth
– discuss and criticize current research
– envision emerging technology direction

• Objective
– participate and lead the change
– cultivate the habit of research
– curate a community with shared interest,
understanding and language, but diverse ideas

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Outline

Course Objectives

Motivations

Course Administrivia

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Instructional Staff
(see homepage for contact info, office hours)

Xuan ‘Silvia’ Zhang Dengxue Yan

(Tue 4-5pm) (Thur 3:30-5pm)

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Prerequisites

• ESE 232: Introduction to Electronic Circuits

– analysis and design of transistors
– semiconductor memory devices

• ESE 260: Introduction to Digital Logic and

Computer Design
– combinational and sequential logic
– logic minimization, propagation delays, timing

• Plus but not required

– basic computer architecture
– basic hardware description language (Verilog, VHDL)
– basic Linux commands

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Course Overview

• Course homepage:
– http://classes.engineering.wustl.edu/ese461/
• Distribution
– 30%: reading and learning
– 70%: programming, debugging, design iteration
• Workload
– no mid or final exams
– in-class review quiz
– homework
– labs
– one group final project
• Philosophy
– learner-directed instruction

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Final Project

• Goal: learn by doing

– Work in teams of 2
– Choose from a few suggested projects
– Release around Week 8
– Optimize design to meet/exceed performance goals
– A custom designed IC chip as the end result

• Evaluation
– Completion of the design flow
– Performance achieved
– Techniques applied
– Presentation
– Report

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Grading

• Engagement 5%
• Review Quiz 10%
• Homework 10%
• Labs 40%
• Final Project 35%

• Policy:
– 90% or above A
– 80% - 89% B
– 65% - 79% C
– 45% - 64% D
– 44% or below F

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Policies

• Submission
– quiz, labs, homework due in class
– 2-day grace period, then 50% penalty
– no credits after 1 week, no exception
• Discussion & Collaboration
– learning through discussion
– help classmates to understand concepts
– sharing code or schematics not-allowed
• Plagiarism
– zero tolerance
– specify sources to avoid confusion

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Textbook

• Lecture Slides and Notes

• Tutorials
• Documentations

• Recommended Textbook
– Application-Specific Integrated Circuits (ASICs… the
book), by Michael John Sebastian Smith
– online at EDACafe
– http://www10.edacafe.com/book/ASIC/ASICs.php

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Make and Hack

• Open Source Resources

• Community

• Explore and Have Fun

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Questions?

Comments?

Discussion?

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