Current-forced single-phase reversible rectifier

Prof. J.T. Boys

A.W. Green, BE

Indexing terms: Induction motors, Transistors

s = Laplace transform variable

Abstract: A 7 kW voltage-sourced reversible rec- S = switch state (0, 1)
tifier (VSRR) which achieves bidirectional power U = manipulated control variable
flow between a single-phase AC supply and a DC VLmin= magnitude of minimum inductor voltage
busbar voltage is described. A current-forced U, = phase-to-neutral supply voltage
control (CFC) strategy is used to switch two V, = RMS value of u s .
power transistors, enabling the device to operate
with a unity power factor and a sinusoidal line 1 introduction
current to produce a regulated DC busbar
voltage. The advantages of the scheme are its sim- The three-phase diode bridge rectifier is firmly estab-
plicity, an extremely fast and well damped lished as the principal AC/DC power convertor for
response and its adaptive nature to nonlinear power levels above about 1 kW. A contributing factor to
effects such as transistor switching delays. Fur- this is the phenomenal growth in the use of variable
thermore, the harmonic currents produced by speed AC drives by industry. The dominant class of AC
multiple devices operating from the same point of drive employs a front-end three-phase bridge rectifier to
supply do not add coherently because of their convert the utility AC supply voltage into a fixed DC-
pseudorandom nature. The device operates with a voltage link, from which an inverter derives a variable
DC busbar voltage which is greater than the peak- voltage and frequency supply with which to excite an
to-peak voltage of the utility supply so that it is induction motor [13. Little attention has been paid to the
especially suitable for use as a source of power in rectifier stage of such drives becaue the three-phase
a variable-speed AC induction-motor drive. bridge rectifier is low cost, rugged, compact and has fairly
good voltage regulation. In addition, the power factor is
a good 0.97 and the DC ripple voltage is only in the
List of symbols order of 4%. Moreover, because the output ripple fre-
quency is six times the utility supply frequency only a
C, = output capacitance
comparatively small output filter is required to reduce
e = error voltage
the ripple to almost negligible levels.
eAC = DC busbar voltage ripple As the price of power semiconductor switching devices
E,, = total DC busbar voltage falls and the market for devices, such as variable-speed
E,, = negative half DC busbar voltage drives, continues to expand and promote competition
EDc+ = positive half DC busbar voltage amongst manufacturers, inverter technology will become
E,,, = reference DC busbar voltage affordable to the small user. These include people such as
i,- = negative busbar voltage
farmers and private contractors using induction motors
i, + = positive busbar current but having access to only a single-phase supply. To fully
I,, = DC load current
utilise the torque capability of a motor rated at the utility
is = supply current
supply voltage, it is necessary for an inverter to be able to
I, = RMS value of the fundamental component of i,
synthesize a PWM voltage with a fundamental com-
i, = reference current
ponent comparable in magnitude to the existing utility
I, = RMS value of i,
supply. To do this, any single-phase rectifier on the input
I, = hysteresis current
must be able to convert a single-phase utility AC supply
I,, = RMS third harmonic in supply current
voltage of say 230 V RMS into at least +280 V. For this
K , = total loop gain reason, the simple single-phase fullwave rectifier is
K , = controller gain constant unsuitable and a voltage-doubling AC/DC convertor
K , = device gain constant circuit has to be used. Although possessing qualities such
K , = busbar balance gain constant as simplicity and ruggedness, this configuration is noted
L, = supply inductance
for its poor voltage regulation and power factor and
m = modulation depth of PWM
would probably be suitable for use only in power appli-
N , = switchings/s/transistor cations less than about 1 kW, as it stands.
p = differential operator
Recently, a new generation of rectifiers that offer unity
R , = load resistance power factor, sinusoidal line currents with very little dis-
tortion and a regulated DC busbar voltage have been
Paper 6741B (P6), first received 25th October 1988 and in revised form
3rd April 1989 described [2-61. Also, unlike conventional rectifiers, most
The authors are with the Department of Electrical and Electronic of the devices described can transfer power in either
Engineering, School of Engineering, University of Auckland, Private direction, hence the term ‘reversible rectifier’. A prime
Bag, Auckland, New Zealand reason for the sudden interest in this field of work has
IEE PROCEEDINGS, Vol. 136, Pt. B, N o . 5 , S E P T E M B E R 1989 205

1 1
been the growing concern of power supply authorities any given time, or else a short-circuit of the two DC volt-
over the levels of harmonic pollution accumulating ages will result. If a transistor that is conducting current
within the power system. The diode rectifier is a principal is turned off, then owing to the inductive nature of the
offender [7, SI. The nonsinusoidal line currents of the circuit, the current instantaneously freewheels through
diode/thyristor rectifier can cause a multitude of prob- the diode in the opposite leg. If that same transistor is
lems, such as instrument malfunctions, insulation break- turned back on, then the conducting diode is reverse-
down and resonances within the power system. Most biased and the current will switch to flow back through
supply authorities already have limits on the levels of the transistor. In a CFC scheme, whenever a transistor is
harmonics that can be produced by a consumer, and as turned on the complementary transistor is always turned
more users of variable-speed AC drives appear, these off, so that the two transistors/diodes essentially behave
levels will have to be tightened and the penalties for as a two-pole bidirectional switch. This switch can conve-
failure to observe them increased. niently be represented by the variable S, allowing the for-
Most of the published work on reversible rectifiers to mulation of the following circuit differential equations :
date has been concerned with three-phase devices
because their biggest user, industry, generally has access Pis = ( u s - SEDC+ - (l - S)EDC-)/Ls (14
to a 3-phase supply. However, as mentioned earlier, there PED,+ = - EDC/Ro)/Co (14
are applications for single-phase devices provided the
performance is adequate. By adapting techniques used in PED,- = ((l - + EDC/Ro)/Co (IC)
three-phase reversible rectifiers to single-phase operation, where
it is demonstrated that acceptable performance is
obtained at realistic power levels. In this paper a single- = EDC+ - EDC-
phase reversible rectifier is presented, based on a modi- and
fied version of the simple voltage-doubling rectifier. The
device is shown schematically in Fig. 1, and it differs from S = 1 if T+ or D + is on
S =0 if T- or D - is on
ib+
I 7
I In a current-forced scheme, E D c + must be greater than
the maximum positive value of U, and E D c - must be less
j c o
than the maximum negative value of U , . Therefore, from
eqn. 1 it can be seen that if T+ is on the current is will
decrease for all U , , and if T- is on the current will
increase. Hence the current can be forced to track a refer-
ence waveform i, simply by switching on T+ if the current
is higher than i,, or by switching T- on if the current is
'b- lower than i,. In a practical situation, this simple pro-
Fig. 1 Single-phase voltage-sourced reversible rectifier cedure would be impossible to implement as the tran-
sistors have finite turn-on and turn-off times and cannot
a conventional voltage doubler in that an inverse parallel switch instantaneously. Modern bipolar power tran-
power transistor has been added across each diode, along sistors have a maximum switching rate of about 10 kHz,
with an inductor in series with the utility supply voltage. so to limit the switching rate a hysteresis band is inserted
A consumer load R , is depicted as opposed to a gener- about the reference waveform, as shown in Fig. 2. The
ating one because this is the most common mode of oper-
ation. However, it really makes little difference because
the transient nature of the two are very similar. The
power transistors are switched using a current-forced
control (CFC) strategy that enables the device to operate
with a sinusoidal line current, unity power factor and a
regulated DC busbar voltage. Details of the control tech-
nique and its implementation are discussed in subsequent
Sections.

2 Current-forcing principle 0 60 120 180 240 300 360

wt, degrees
Before the device shown in Fig. 1 can be controlled in the Fig. 2 Simulated supply current bounded b y hysteresis band
required manner, the two capacitors (designated CO)ini-
tially have to charge up to the peak voltage of the utility switching rate then becomes a function of the hysteresis
supply via the inverse parallel diodes across the tran- bandsize, the inductance and the voltage across the
sistors. The two capacitors must be large enough to inductor. As a consequence of introducing this hysteresis,
appear as an essentially constant DC voltage source with distortion components are added to the current, but if the
low ripple content. The large size of COalso means that average switching rate is kept above about 2 kHz then
some form of soft start must be included during the the resulting distortion should not warrant too much
initial charge up to prevent transient inrush currents concern by power supply authorities.
from harming circuit components. Once the capacitors
have fully charged and the diodes are reverse-biased, it 3 Current-forcing controller
becomes apparent that two virtually constant DC volt-
ages EDc+ and EDc- can be switched in series with the 3.1 Current reference
voltage source U, via the two transistor switches T+ and For the device to operate with a sinusoidal input current
T- . Note that only one of the transistors can be on at and unity power factor it is necessary to produce a
206 IEE PROCEEDINGS, Vol. 136, Pt. B, N o . 5, S E P T E M B E R 1989
sinusoidal-current reference waveform that is either in component of ED, is given by
phase or 180" out of phase with the AC utility supply
voltage. In addition, the DC voltage E,, must be main-
tained equal to a reference ED,,, under all load condi-
tions. Both these can be satisfied using the controller in

*
Fig. 3. A signal derived from the supply voltage is multi-

In a practical case, analytic expressions for i b + and i b -

are difficult to obtain, but taking a simplistic viewpoint
I I
' ~EDC+
~
that ib+ corresponds to the input-current times for the
percentage of the time that the top transistor is on (and
similarly for ib-), and assuming that the modulation is
VSRR sinusoidal PWM at high frequency with a negligible
E DC- voltage drop across the inductor, then for a supply
current J(2)1, sin (ot)
ib+ = J ( ~ ) I sin
, (wt)[O.5 + 0.5m sin ( o t ) ] (44
i b - = J(2)1, sin (ot)[O.5 - 0.5m sin (wt)] (4b)
con t ro I block where m is the modulation depth of the PWM and is
given by
Fig. 3 Hysteresis current-jorcing controller

plied by a filtered error term obtained from the DC

busbar voltage, and modified by a PI controller to
produce the required current reference. This current ref- Combining these expressions results in
erence is then compared with the actual current to deter-
mine which transistor should be turned on. If E,, is too
low then the error is positive and i, is produced in phase
with U,, so that power is transferred from the AC to the
DC side (rectifying) thus increasing E,, . Alternatively, if --
- 2zs v, [l - cos (2ot)l
E,, is too high then the error is negative and i, is
produced 180" out of phase with u s , so that power is (5)
transferred from the DC to the AC side (inverting) to
Substituting eqn. 5 into eqn. 3 gives
reduce E D , .

3.2 DC busbar balancing

Small DC offsets in the controller's analogue components
make it possible for the DC busbar voltage to become
unbalanced with respect to the neutral point, while still
maintaining a total busbar voltage that is equal to the
reference. To ensure that the positive and negative sides Both experimental and computer simulation results have
of the busbar remain equally charged, a busbar balance shown this expression to be accurate to within a few per
loop is included by summing ED,+ and ED,- and sub- cent, even at switching frequencies as low as 1-2 kHz. If
tracting the resulting DC error term from the supply no filter is present in Fig. 3 and only proportional control
current i s . If the positive busbar voltage is too low, this is used, then the current reference, including the effects of
will increase the DC component in the positive busbar, voltage ripple, is given by
allowing more charge to accumulate in the capacitor and
thus increasing the magnitude of E D , + . Similarly, if the i, = Kc[E,R - [ E , +
eAc]] sin (wt) (7)
negative busbar voltage is too low, then the DC com- Substituting eACin eqn. 6 and expanding upon it leaves
ponent in the negative busbar will be made to increase,
causing E,,- to increase in the negative direction. The i, = K,[E,,, - ED,] sin (ut)
busbar-balancing feedback loop is clearly shown in Fig. 3
Kc ID,
and is depicted having a gain Kb . -- [cos (3wt) - cos ( o t ) ] (8)
2wc,
3.3 Ripple voltage and its effects As the controller gain K , is increased to speed up the
Since the DC-side capacitance is of finite value and each response time and reduce the steady-state error, it will
half of it is charged essentially on alternate halfcycles of have the undesirable effect of distorting the AC supply
the input-voltage waveform, the error voltage term (as current through the addition of an unwanted third har-
determined in Section 3.1) will contain unwanted even- monic. A quadrature fundamental component is also
order harmonics. To estimate the effect of these harmo- added, causing a phase shift in the supply current and
nics we consider the DC voltage given by eqn. 2 hence a reduction in the power factor. The effects of the
voltage ripple can be reduced significantly by including a
= - (2) simple lowpass filter in the control loop as shown, having
As illustrated in Fig. 1, the currents flowing in the posi- a cutoff frequency which provides adequate attenuation
tive and negative busbars are represented as i b + and i b p , of the second harmonic appearing in the error term.
respectively, whereas the current flowing into the load is Typically this is about 25 Hz or less, depending on the
given by I,, . Thus, during steady-state operation the AC amount of voltage ripple present. The introduction of an
IEE PROCEEDINGS, Vol. 136, Pt. B, N o . 5, S E P T E M B E R 1989 207
additional pole so close to the jo axis degrades the tran- to the response of the DC side, thus only the dynamics of
sient performance and it worsens as a smaller busbar the DC side need be considered when deriving a transfer
capacitance is used, because the filter time constant has function for the system. Assuming 100% efficiency and
neglecting the DC busbar-voltage ripple, the power
balance equation relating the AC power to the DC power
can be written as

which can be approximately expressed as

U 2K1s 2EDC
-- -
- PED,
~

co EDCr Ro co
-50
The corresponding transfer function for eqn. 10, relating
ED, to I , , is then given by
-1 00
Fig. 4 Root locus of eqn. 15
[ 3 denote actual closed-loop poles

Before the overall device transfer function relating E,, to

a reference input E,, can be obtained, the transfer func-
tion describing the control block which incorporates full
PI control must be determined. The control block includ-
ing the second harmonic filter has a total transfer func-
tion, in this case given by
u(s) - K , ( s + 45)
_
e(s) - s(s + 150)
where
5msldiv
Fig. 5 Simulated line current and supply voltaye 44 = E,&) - ED&) (13)
Rectifying 7 k W
The analogue multiplier shown in Fig. 3 effectively pro-
vides a transformation from the DC domain into the AC
domain, hence u(s) can be equated directly to I,(s). More-
over, the current-forced nature of the control means that
I,(s) must equal I,(s), so that
4 s ) = I,@) (14)
Combining eqns. 11, 12, 13 and 14 gives the overall
closed-loop transfer function for the device of eqn. 15.
The root locus of eqn. 15 is shown in Fig. 4, together
with the closed-loop pole positions selected to give good
damping and a fast response. The root locus shape for
5msldiv the no load and maximum load conditions differ very
Fig. 6 Simulated line current and supply voltage little from each other because the pole associated with
Inverting 7 kW the DC-side load is virtually static, due to the large
amount of capacitance present
to be subsequently increased for further attenuation.
However, using this method, a substantially smaller
busbar capacitance than demonstrated in this paper can
be used while still remaining stable, provided the level of
the DC busbar-voltage ripple is acceptable to the specific
application and the maximum voltage is within the specs where
of the capacitor and transistors. One example of when a
K,=K,K,
high level of ripple can be tolerated is when the device is
supplying power to a second stage step-down DC/DC
convertor. To meet economic constraints the minimum 4.2 Simulation
COthat can be used is best determined from a computer A digital computer simulation of the VSRR, incorpo-
simulation of the model described in the following rating the controller in Fig. 3 and the data contained in
Section. Appendix 9, was performed using two different methods.
The most accurate of the two firstly involves numerically
4 Modelling integrating the differential equations that eqn. 12 rep-
resents to form the required current reference i, . The
4.1 Overall transfer function appropriate switch state represented by S, is then assign-
In a current-forced VSRR the response of the AC side to ed, depending on the magnitude of the actual current is
a demand in power is virtually instantaneous compared compared to i, . Finally, the differential equations (eqn. 1)
208 IEE PROCEEDINGS, Vol. 136, Pt. B, No. 5, S E P T E M B E R 1989

11
are integrated using a simple Euler algorithm to obtain ing the voltage across a simple 0.01 SZ resistor in series
the effect on the VSRR state variables. Effects such as with the inductor and utility supply voltage.
transistor switching delays, on-state voltages and series- The experimental results in Figs. 11-13 illustrate the
resistive voltage drops have been neglected. The second very good sinusoidal line current obtained by the
method involves solving the differential equations that
the transfer function (eqn. 15) represents. This method is 20000 r
less accurate and reveals nothing about the effects of the
hysteresis and ripple voltage, but has the advantage that
it requires the solution of only three differential equations 15000 -
instead of six, and a larger integral time-step can be used
to speed up the simulation. All the subsequent results use
the first method described, except for Fig. 9 which uses ~1000-
0
eqn. 15 directly.
5 000 -

OL I I I I
0 1 2 3 4
> hysteresis, A
.
._
U
>
0
Fig. 10 Simulated transistor switching rate as function of current
hysteresis
0
c [? 10mH
05mH
A 2.5 mH

40 msldiv
Fig. 7 Simulated response of E , t o a 7 kW step change in power
demand
Rectifying

4Omsldiv Fig. 11 Typical line current and supply voltage

Fig. 8 Simulated response of E,, t o a 7 kW step change in power 7 kW Rectifying
demand L, - 10 mH
Inverting

40 msJdiv
Fig. 9 Simulated response of E,, t o a 7 kW step change in power
demand using eqn. 15 directly
Rectifying

Fig. 12 Typical line current and supply voltage

5 Experimental results and discussion 7 kW Rectifying
L, = 2.5mH
A 7 kW prototype unit was constructed using a 1200 V/
150 A transistor module, two 14500 uF capacitors and a current-forced VSRR. In addition, because the current is
10 mH inductor. The instantaneous line-current magni- exactly in phase with the utility supply voltage during
tude required by the controller was obtained by measur- rectifying operation, and exactly 180 degrees out of phase
IEE PROCEEDINGS, Vol. 136, Pt. B, N o . 5 , S E P T E M B E R 1989 209
during inverting operation, an excellent power factor has sponding to an average current-ripple frequency of about
been achieved. The simulated current in Fig. 5 and the 7 kHz. However, after making the modification the fre-
experimentally obtained result in Fig. 11, using the quency was observed to be only about 3 kHz, and

Fig. 13 Typical line current and supply voltage Fig. 15 Response of E , to a 7 kW step change in power demand
Inverting
7 kW Inverting
100 V/div
L, = 2.5mH
40 ms/div

10 mH inductor, compare favourably. Experimentally, instead of the current distortion remaining constant it
the distortion is slightly greater at about 8.0 A peak-to- was substantially greater than before, especially near the
peak, and the switching rate is slightly less, correspond- waveform peaks. In Figs. 12 and 13 the distortion is
ing to an average current-ripple frequency of about about 12.0A peak-to-peak or nearly twice as great as
1200 Hz. These differences can be attributed to switching expected. This increase in distortion is due to the even
delays inherent in the control circuitry, transistors and more pronounced effect switching delays have on current
transistor driver boards. segments with large dildt, such as near the waveform
The simulated transient response in Fig. 9, which uses peaks, when small inductors are used.
eqn. 15, shows a good correlation with that of Fig. 7, Comparing the current waveforms in Figs. 12 and 13,
obtained using eqns. 1 and 11, thus justifying the assump- it is apparent that near the peaks the switching rate for
tion that the response of the AC side is instantaneous in the inverting case is almost a factor of two less than for
a CFC scheme. The simulated response of the DC busbar the rectifying case. This suggests that the applied induc-
voltages in Figs. 7 and 8 also compares very favourably tor voltages responsible for the smaller di/dt current seg-
with those experimentally obtained in Figs. 14 and 15, ments differ by about a factor of two in each case. An
expression for this voltage is given by eqn. 16 and
equates to VLmin= 57 V in the prototype device. At a
peak current of 40 A the accumulative voltage drop, due
to small resistances present in the utility supply, inductor,
diodes and transistors, could quite conceivably
be 5 15 V. During rectifier operation, this accumulated
voltage drop increases the effective magnitude of VLmin,
whereas for inverting operation it decreases it. Conse-
quently, during rectification VLmin= 72 V and during
inversion VLmin = 42 V, thus explaining the observed
difference in the switching rate between the two cases

The pseudorandom nature of the switchings produced in

this device means there are no dominant current harmo-
nics such as occur with devices incorporating regularly
Fig. 14 Response of E , t o a 7 kW step change in power demand sampled PWM techniques. Consequently, when multiple
Rectifying devices are operating in parallel, the current harmonics
100 V/div do not add coherently, thus eliminating the need for
40msidiv
additional filtering at the point of supply. Moreover, the
and show a recovery time of about 80 ms with only absence of a dominant harmonic component at the
about 6% droop and very little overshoot. average switching frequency means the audible noise
To reduce the cost of the VSRR and increase the emitted is a more acceptable buzz rather than an offen-
average current-ripple frequency it was decided to reduce sive screech.
the size of the inductor by a factor of four (Fig. lo), 6 Conclusions
leaving the hysteresis unaltered at 3.0 A. From the simu-
lation in Fig. 10, the average transistor switching rate A device termed a voltage-sourced reversible rectifier
should have increased to about 14000 switching+, corre- (VSRR) employing current-forced control has been
210 IEE PROCEEDINGS, Vol. 136, Pt. B, No. 5, S E P T E M B E R 1989

11
described. It is a single-phase AC/DC convertor with 2 TENTI, P., and MALSANI, L.: ‘Three-phase AC/DC PWM con-
bidirectional power-flow capability, good DC-voltage verter with sinusoidal AC currents and minimum filter requirements’,
IEEE Trans., 1987,1A-23, (l), pp. 71-77
regulation, sinusoidal line current and unity power factor. 3 HOMBO, M., UEDA, A., and NAKAZATO, M.: ‘Current-source
CFC is very simple to implement and provides excellent inverters with sinusoidal inputs and outputs’, Hitachi Review, 1987,
response time and damping, as well as being extremely 36,(l), pp. 29-34
adaptive to nonlinear effects such as switching delays and 4 MANIAS, S., PRASAD, A.R., and ZIOGAS, P.D.: ‘Three-phase
inductor-fed SMR convertor with high-frequency isolation, high-
magnetic saturation in the inductors. This paper has power density and improved power factor’, ZEE Proc. E., 1987, 134,
demonstrated that it is necessary to include a lowpass (4), pp. 183-191
filter in the feedback loop to avoid third harmonic distor- 5 GREEN, A.W., BOYS, J.T., and GATES, G.F.: ‘Three-phase voltage-
tion in the supply current, and that the transient response sourced reversible rectifier’, IEE Proc. E, 1988, 135, (6), pp. 362-370
of the AC side can be considered instantaneous com- 6 KULKARNI, A.B., DIXON, J.W., NISHIMOTO, M., and 001, B.:
‘Transient tests on a voltage-regulated controlled-current PWM con-
pared to the DC side, thus simplifying the derivation of a vertor’, IEEE Trans., 1987, IE-34, (3), pp. 319-324
suitable transfer function to describe the device. It is 7 RICE, D.E.: ‘Adjustable speed drive and power rectifier harmonics-
expected that in the near future the same prototype their effect on power system components’, IEEE Trans., 1986, IA-22,
device used here will be able to operate direct from the (l), pp. 161-177
8 ARRILLAGA, J., BRADLEY, D.A., and BODGER, P.S.: ‘Power
full utility supply voltage of 230 V, with a HVDC busbar system harmonics’ (Wiley, New York, 1985),pp. 11C-135
of 700 V, and handle power levels approaching 15 kW.
Due to the high DC voltage that is produced, the
device is especially suited as a power source in variable- 9 Appendix
speed drive systems where only a single-phase utility
supply is available. Its reversible nature eliminates dump Prototype data
resistors (often needed to dissipate energy regenerated by
overhauling loads on a motor), thus increasing the CO= 14500 u F
overall efficiency of a drive system. Another possible use ED,-, = 680 V
being investigated is the removal of unwanted harmonics
from a power system. I, = 3.0 A
K, = 1.2
7 Acknowledgements
K, = 180
The authors are grateful for the assistance of Mr. Peter
K, = 40
Jenkins at the University of Auckland in obtaining the
experimental results. K , = 7200
L, = 10 mH
8 References
R, = 60 Q
1 MOKRYTSKI, B.: ‘Pulsewidth modulated inverters for AC motor
drives’, IEEE Trans., 1967, IGA-3, pp. 493-503 v, = 200 v

IEE PROCEEDINGS, Vol. 136, Pt. E,N o . 5, S E P T E M B E R 1989 21 1

~~ ~~ ~~

IT