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    Why Do Setup and Hold Violations Occur - Quora

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    RA NDY
    Setup and hold violations occur when signals change too close to the active edge of the clock. Setup violations happen when signals are too slow and arrive late, while hold violations occur when signals are too fast and arrive early. To fix setup violations, designers can reduce delay by optimizing RTL code and physical design. To fix hold violations, designers can increase delay by adding buffers or using higher threshold voltage cells.

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    Why Do Setup and Hold Violations Occur - Quora

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    RA NDY
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    Setup and hold violations occur when signals change too close to the active edge of the clock. Setup violations happen when signals are too slow and arrive late, while hold violations occur when signals are too fast and arrive early. To fix setup violations, designers can reduce delay by optimizing RTL code and physical design. To fix hold violations, designers can increase delay by adding buffers or using higher threshold voltage cells.

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    (1) Why do setup and hold violations occur_ - Quora

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    Setup and hold violations occur when signals change too close to the active edge of the clock. Setup violations happen when signals are too slow and arrive late, while hold violations occur when signals are too fast and arrive early. To fix setup violations, designers can reduce delay by optimizing RTL code and physical design. To fix hold violations, designers can increase delay by adding buffers or using higher threshold voltage cells.

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    © All Rights Reserved
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    Download as pdf or txt
    55 views3 pages

    Why Do Setup and Hold Violations Occur - Quora

    Uploaded by

    RA NDY
    Setup and hold violations occur when signals change too close to the active edge of the clock. Setup violations happen when signals are too slow and arrive late, while hold violations occur when signals are too fast and arrive early. To fix setup violations, designers can reduce delay by optimizing RTL code and physical design. To fix hold violations, designers can increase delay by adding buffers or using higher threshold voltage cells.

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    7/16/22, 2:43 PM (1) Why do setup and hold violations occur?

    - Quora

    In order to avoid Setup and Hold Violations, one should understand the cause for Setup and Hold
    Violation.

    Setup Time: and Hold Time: If the data or signal changes just before and after the active edge of the
    clock respectively then we say that setup time/ hold time has been violated.

    Causes for Setup Time: Setup violations can happen as a result of slow conditions (slow process, high
    temperature) leading to signals arriving too late in the clock period.

    Strategy to Fix Setup Time: Reduce Delay.

    *As a RTL Design Engineer*:

    1. If the RTL code is a FSM , change the states of a FSM to one hot encode or grey code. If only one
    bit is changing at a time, it is a good chance that it would be faster and less delay.

    2. Prefer to use case statement over if else. Case statements and if else statements would have the
    same functionality but synthesis captures them differently. If there are multiple branch conditions,
    case statements (which is a mux) would be faster than synthesized if else (which would be priority
    encoder).
    3. Achieve Parallelism in RTL Serial Codes elongate the critical path and that is BAD. If we can split
    large serial operation in to multiple parallel operations then it is simple to meet timing of small
    individual units.

    *As a Physical Design Engineer*:

    1. Make use of macros Each industry I believe would be having specific macros available. These are
    usually best optimized cells.

    2. Try to make use of libraries derived from NAND logic. Since , NAND and NOR are universal gates
    and NAND being faster than NOR they could be utilized to reduce delay. For example: if NAND is
    followed by a latch, simply use latch-NAND driver.
    3. Increase Wire Thickness (reduces resistance) and increase the spacing between wires (decreases
    coupling capacitance).

    4. Use Cells with lower Threshold Voltages: Cells with lower threshold voltage have lesser transition
    times which makes the propagation of logic faster.

    5. Restructuring/Re-timing would be the best way to optimize the logic. Based upon the placement
    of data path logic cells, you can decide either to combine simple logic gates into a complex gate,
    or split a multi-stage cell into simpler logic gates.

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    7/16/22, 2:43 PM (1) Why do setup and hold violations occur? - Quora

    6. A cell with better drive strength can charge the load capacitance quickly, resulting in lesser
    propagation delay. So make sure you cell has better drive strength. (Traditionally , I believe larger
    cells should be having more driving strength).

    7. For a critical path with a capture flop and a launch flop , try to ensure that the clock at the capture
    flop comes late or the clock at the launch flop comes early. This will give some extra timing and
    will be able to relax any violations we would be facing.

    Alternative Explanation (for point 7th) : Positive skew helps improve the setup slack. So, to fix setup
    violation, we may either choose to increase the clock latency of capturing flip-flop, or decrease the clock
    latency of launching flip-flop.

    I am happy to provide diagrammatic explanations as well, if you are interested in explanation with
    diagrams do comment it.

    Causes for Hold Time Violations: Hold violations can happen as a result of fast conditions (fast process,
    low temperature) leading to signals arriving too early in the clock period.

    Strategy to Fix Hold Time:

    *As a Physical Design Engineer*

    1. Insert buffers. The timing path where hold violation is occurring, if the delay is increased due to
    these buffers, then it shall ultimately lead to positive slack thereby improving the chances of hold
    time being met.
    2. Use data-path cells with higher threshold voltages: If you have multiple varieties of cells with
    variable threshold voltages, then the cells with higher threshold voltage will have higher transition
    times. This reduces the chances of the hold time being violated.

    3. Lock up Latches: If we some how try to separate the launching edge and capturing edge by a
    phase then it will relax the timing path and improves the chances of hold time being met. [Image
    shown at the last]

    4. A positive skew degrades hold timing and a negative skew aids hold timing. So, if a data-path is
    violating, we can either decrease the latency of capturing flip-flop or increase the clock latency of
    launching flip-flop.

    Alternative explanation for last point: For a capture and launch flop, if the clock at the launch flop is made
    to arrive late or the clock at the capture flop is made to arrive early then the chances of hold time being
    violated is reduced.

    Image shown for Lockup Latches:

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    7/16/22, 2:43 PM (1) Why do setup and hold violations occur? - Quora

    References:

    https://www.quora.com/Why-do-setup-and-hold-violations-occur 3/3

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