Introduction to Assembly

Chapter 2

Sepehr Naimi

www.NicerLand.com
www.MicroDigitalEd.com
 Topics
 AVR’s CPU
 Its architecture
 Some simple programs
 Data Memory access
 Program memory RAM EEPROM Timers

 RISC architecture PROGRAM

Flash ROM

Program Data
Bus Bus
CPU

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

2
 AVR’s CPU
 AVR’s CPU
 ALU
 32 General Purpose
R0
registers (R0 to R31) R1
ALU
 PC register R2

…
 Instruction decoder SREG: I T H S V N Z C
R15

CPU R16
R17

…
PC

R30
Instruction decoder
R31
Instruction Register
registers

3
 Some simple instructions
1. Loading values into the general purpose registers

LDI (Load Immediate)

 LDI Rd, k

 Its equivalent in high level languages:

Rd = k
 Example: R0
ALU R1
 LDI R16,53 R2

…
 R16 = 53 SREG: I T H S V N Z C

CPU
R15
 LDI R19,$27 R16
R17
 LDI R23,0x27 PC

…
 R23 = 0x27 Instruction decoder
R30
R31

LDI R23,0b11101100
Instruction Register
 registers

4
 Some simple instructions
2. Arithmetic calculation
 There are some instructions for doing Arithmetic
and logic operations; such as:
ADD, SUB, MUL, AND, etc.
 ADD Rd,Rs
 Rd = Rd + Rs R0
ALU R1
 Example: R2

…
 ADD R25, R9 SREG: I T H S V N Z C

CPU
R15
 R25 = R25 + R9 R16
R17
 ADD R17,R30 PC

…
 R17 = R17 + R30 Instruction decoder
R30
R31
Instruction Register
registers

5
 A simple program
 Write a program that calculates 19 + 95

LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20

R0
ALU R1
R2

…
SREG: I T H S V N Z C

CPU
R15
R16
R17
PC

…
R30
Instruction decoder
R31
Instruction Register
registers

6
 A simple program
 Write a program that calculates 19 + 95 + 5
LDI R16, 19 ;R16 = 19
LDI R20, 95 ;R20 = 95
LDI R21, 5 ;R21 = 5
ADD R16, R20 ;R16 = R16 + R20
ADD R16, R21 ;R16 = R16 + R21

LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20
LDI R20, 5 ;R20 = 5
ADD R16, R20 ;R16 = R16 + R20

7
 Some simple instructions
2. Arithmetic calculation
 SUB Rd,Rs
 Rd = Rd - Rs
 Example:
 SUB R25, R9
 R25 = R25 - R9 R0
ALU R1
 SUB R17,R30 R2

…
 R17 = R17 - R30 SREG: I T H S V N Z C

CPU
R15
R16
R17
PC

…
R30
Instruction decoder
R31
Instruction Register
registers

8
 Some simple instructions
2. Arithmetic calculation
 INC Rd
 Rd = Rd + 1
 Example:
 INC R25
 R25 = R25 + 1 R0
ALU R1
R2

…
 DEC Rd SREG: I T H S V N Z C

CPU
R15
 Rd = Rd - 1 R16
R17
 Example: PC

…
R30
 DEC R23 Instruction decoder
R31
Instruction Register
 R23 = R23 - 1 registers

9
 Data Address Space
Address Name Address Name Address Name
Mem. I/O Mem. I/O Mem. I/O
$20 $00 - $36 $16 TIFR1 $4C $2C SPCR0
$21 $01 - $37 $17 TIFR2 $4D $2D SPSR0
$22 $02 - $38 $18 - $4E $2E SPDR0 RAM EEPROM Timers
$23 $03 PINB $39 $19 - $4F -
General
$2F
$24 $04 DDRB $3A $1A - $50 $30 ACSR Purpose
PROGRAM
$25 $05 PORTB $3B $1B PCIFR $51 $31 DWDR Registers
$26 $06 $3C $1C EIFR ROM
PINC $52 $32 -
$27 $07 DDRC $3D $1D EIMSK $53 $33 SMCR
$28 $08 $3E $1E GPIOR0
Program
CPU Data
PORTC $54 $34 MCUSR
$29 $09 PIND $3F $1F EECR $55
Bus
$35 MCUCR Bus address bus
$2A $0A DDRD $40 $20 EEDR $56 $36 -
data bus
control bus
$2B $0B PORTD $41 $21 EEARL $57 $37 SPMCSR Data
$2C $0C - $42 $22 EEARH $58 $38 -
$2D $0D - $43 $23 GTCCR $59 $39 - Bus
Data
$2E $0E - $44 $24 Data
TCCR0A $5A $3A
Address
R0
Address
-
$2F $0F - R1
$45 $25 TCCR0B $5B $3B -
$0000 R2 $0000
$30 $10
General - $46 $26 TCNT0 $5C
General $3C Other
- Interrupt
...

$31 Purpose -
$11 $47 $27 OCR0A Purpose
$5D $3D OSC Ports
...

SPL
...

$32 Registers -
$12
R31
Registers Unit Peripherals
$001F $48 $28 OCR0B
$001F $5E $3E SPH
$33
$0020 $13 - $49 $29 -
$0020 $5F $3F SREG
Standard I/O I/O Address Standard I/O
$34 $14 GPIOR1
Registers - $4A $2A$00 Registers I/O
...

...

$35
$005F
$15
(SFRs) TIFR0 $4A
Example:
$2A$01
Add contentsExample:
$005F
GPIOR2
of location
(SFRs) 0x90
Store to contents
0x53 into PINS of location
the SPH 0x95
register.
...

$0060
Example:
and store What
$0060
$3E doesinthe
theExtended
result following
location
LDS
STS
The (Store
address instruction
0x313.
(Load direct
of from
direct
SPH to
is do?space)
data
data
0x5E space)
Extended Example: Write
Example: Write
SREG $3F a program that stores 55 into location
a program that copies the contents of location0x80 of RAM.
0x80
...

I/O Memory I/O Memory

$00FF
Solution:
of LDS
RAM R20,2
into
$01FF
location 0x81.
$0100 $0200 LDS
STS Rd, addr ;[addr]=Rd
addr,Rd ;Rd = [addr]
0x90 Solution:
Internal Internal
LDS R20,
Solution: ;R20 = [0x90]
...

...

SRAM SRAM
Answer: $21FF

External
$2200
LDS R20,
Solution:
LDI R21, 55
External Example:
0x95 LDI R20, 0x53
;R20 =;R21
55 = [0x95]
;R20 = 0x53
$FFFF
SRAM
It copies
ADD
theSRAM
R20,
$FFFF contents
R21
of R2 ;R20
STS into R20;
0x5E,=
as+ 2R21
R20
R20
is the;SPH
address
= R20of R2.
ATmega328
STS 0x80,
LDS ATmega640/V
R20, 0x80 R20 LDS
STS R1,
;[0x80] =0x60
0x60,R15
;R20 R20 ; [0x60] = R15
= 55
= [0x80]
ATmega1280/V
ATmega64
STS ATmega1281/V
0x313, R20 ;[0x313] = R20
ATmega128 STS ATmega2560/V
0x81, R20 ;[0x81] = R20 = [0x80]
ATmega2561/V

10
 Data Address Space

General RAM EEPROM Timers

Purpose
PROGRAM
Registers
ROM

Program CPU Data

Bus Bus address bus
data bus
control bus
Data
Data
R0
Data Bus
Address R1
Address
R2
$0000 General $0000 General
...

Purpose Purpose Interrupt Other

...
...

$001F Registers
R31
Example:
$001F Write a programOSCthat adds the contents
Registers
Unit
Portsof the PINC I/O
Peripherals
register to Registers
the contents of PIND IN
Using (IN
and (OUT from
Names IO location)
of I/O
storestothe registers
I/Oresult in location 0x90
$0020 $0020 Standard I/O
Standard I/O I/O Address

Registers $00 OUT location)

...

...

$005F
(SFRs) of the SRAM
$01
$005F
(SFRs) I/O
PINS
...

$0060
$3E
$0060
IN Rd,IOaddress ;Rd = [addr]
Extended SREG
Solution:
$3F Extended
Example:
OUT IOAddr,Rd ;[addr]=Rd
...

I/O Memory I/O Memory

$00FF $01FF
$0100
Internal
IN Internal
$0200 R20,PINC OUT =SPH,R12
;R20 PINC ;OUT 0x3E,R12
Example:
...

...

SRAM SRAM

IN R21,PIND
$21FF
$2200
IN
;R21 =R15,SREG
Example:
PIND ;IN R15,0x3F
External
SRAM
External
ADD R20,R21
SRAM
;R20
IN R1, 0x3F
= R20
;R1 = SREG
+ R21 ;SREG = R12
$FFFF $FFFF OUT 0x3F,R12
ATmega640/V
ATmega328
STS 0x90,R20
ATmega1280/V IN R17,0x3E
;[0x90] = R20 ;R17 = SPH
ATmega64
ATmega128
ATmega1281/V
ATmega2560/V
OUT 0x3E,R15 ;SPH = R15
ATmega2561/V

11
 Machine Language
 ADD R0,R1
000011 00 0000 0001
opcode operand

 LDI R16, 2
LDI R17, 3
ADD R16, R17

1110 0000 0000 0010

1110 0000 0001 0011
0000 1111 0000 0001

12
 Status Register (SREG)
SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign Data Address
Half carry N+V Space
Example:Show
Example:
Example:
Example: Showthe
Show
Show thestatus
the
the statusof
status
status ofthe
of
of theC,
the
the C,H,
C,
C, H,$0000
H,
H, andZZ
and
and
and ZZGeneral
flagsafter
flags
flags
flags afterthe
after
after theaddition
the
the addition
$0001
subtraction
subtraction
of
of 0x9C of
of 0x9C
0x23
0x73
0x38 and 0x2F from
from
from 0x9C
0xA5
0x52 in
in the
the following
following
0x64 in the following instructions: instructions:
instructions:
Purpose

...
LDI 0x38
LDI R20,
R20, 0x9C
0xA5
0x52 Registers
LDI LDI
R16, R20,
R0 0x9C ;R16 = 0x38 $001F IO Address
ALU LDI 0x2F
LDI R1
R21,
R21, 0x9C
0x23
0x73 $0020
$00
LDI LDI
R17, R21, 0x64
;R17 = 0x2F $01
R2 Standard IO
SUB R17R20,
SUB R20,
R20, R21
R21 ;subtract
;subtract
R21 toR21R21 from R20
R20from R20

...
ADD R21;add R17;add

...
ADD R16, to Registers
R16
…

SPH $3E
SREG: I T H S V N Z C $005F
Solution:
Solution:
Solution:
SREG $3F

CPU
Solution: R15 11 $0060
$52
$9C
$A5 0101
R16 0010
1001 1100
1010 1100
0101
$38
$9C 0011
1001 1000
- $73 0111
R17 0011
...
+-- +$64
$9C
$23
$2F 1001 0100
0010
0110 1100
0011
1111
PC $DF 1101 1111 R20
R20 == $DF
…

$00
$82
$67
$100 1 00000000
1000
0110
0000 0000
0010
0111 R20
R16
R20 == 00
$00
$82
0x67
C = 1 because R21 is bigger than R20 and there is a borrow from D8 bit.
CC===100because
C becausethere
because R21 is
R21 is not
isnot bigger
bigger
a carry
R30 than R20
than
beyond R20 andbit.
and
the D7 there is
there is no
no borrow
borrow from
from D8
D8 bit.
bit.
Z
C == 00 decoder
because
because the
thereR20
is has
no a value
carry otherthe
beyond than
D7zero after the subtraction.
Instruction
ZZ =
H == 1
01 because
because there
because the R20
the R20 iscarry
is ahaszero after
a value
from the D3
other
the than 0 bit.
subtraction.
to theafter the subtraction.
D4 bit.
H = 1 because there isR31 a borrow
carry from
from D4D3
the toto
D3.
the D4 bit.
ZH===100Register
H
Instruction
becausethe
because
because there
there
R20 is(the
is no
no borrow
borrow from
result) from
has D4
aD4 to D3.
to
value D3.
0 in it after the addition.
Z = 0 because the R16 (the result) has a value other than 0 after the addition.
registers
$FFFF

13
 Assembler
Assembly

EDITOR
PROGRAM assembler
myfile.asm

ASSEMBLER
PROGRAM Machine
Language

myfile.eep myfile.hex myfile.map myfile.lst myfile.obj

DOWNLOAD TO DOWNLOAD TO
AVR’s EEPROM AVR ’s FLASH

14
 Assembler Directives
.EQU and .SET
 .EQU name = value
 Example:

.EQU COUNT = 0x25

LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28

 .SET name = value

 Example:

.SET COUNT = 0x25

LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
.SET COUNT = 0x19
LDI R21, COUNT ;R21 = 0x19

15
 Assembler Directives
.ORG
 .ORG address

00 E205
01 0000
Program.asm 02 0000
03 0000
.ORG 0
LDI R16, 0x25 04 0000
assembler
.ORG 0x7 05 0000
LDI R17, 0x34 06 0000
LDI R18, 0x31 07 E314
08 E321
09 0000
0A 0000

16
 Assembler Directives
.INCLUDE
 .INCLUDE “filename.ext”

M328def.inc
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
....

Program.asm

LDI R20, 10
OUT SPL, R20

17
 Flash memory and PC register
00 E205
LDI R16, 0x25 01 E314
LDI R17, $34
LDI R18, 0x31 02 E321
ADD R16, R17 03 0F01
ADD R16, R18 04 0F02
LDI R17, 11
0516-bit
E01B
ADD R16, R17
STS SUM, R16 06 0F01
HERE:JMP HERE 07 9300
08 0300 RAM EEPROM Timers
09 940C
940C
PROGRAM
0A 0009
Flash0009
ROM ALU

PC: 3
0
9
1
5
2
A
7
4
8
B
6 Data
16bit

14bit CPU Bus

Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

18
 Fetch and execute
Old Architectures
00 E205

01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

19
 Pipelining
Pipelining
00 E205

01 E314
02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

20
 How to speed up the CPU
 Increase the clock frequency
 More frequency  More power consumption &
more heat
 Limitations
 Change the architecture
 Pipelining
 RISC

21
 Changing the architecture
RISC vs. CISC
 CISC (Complex Instruction Set Computer)
 Put as many instruction as you can into the CPU
 RISC (Reduced Instruction Set Computer)
 Reduce the number of instructions, and use your
facilities in a more proper way.

22
 RISC architecture
 Feature 1
 RISC processors have a fixed instruction size. It
makes the task of instruction decoder easier.
 In AVR the instructions are 2 or 4 bytes.
 In CISC processors instructions have different
lengths
 E.g. in 8051
 CLR C ; a 1-byte instruction
 ADD A, #20H ; a 2-byte instruction
 LJMP HERE ; a 3-byte instruction

23
 RISC architecture
 Feature 2: reduce the number of instructions
 Pros: Reduces the number of used transistors
 Cons:
 Can make the assembly programming more difficult
 Can lead to using more memory

24
 RISC architecture
 Feature 3: limit the addressing mode
 Advantage
 hardwiring
 Disadvantage
 Can make the assembly programming more difficult

25
 RISC architecture
 Feature 4: Load/Store
LDS R20, 0x200
LDS R21, 0x220
ADD R20, R21
STS 0x230, R20

RAM EEPROM Timers

PROGRAM
Flash ROM ALU

PC: Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

26
 RISC architecture
 Feature
LDS R20, 50x100
(Harvard
; R20 = architecture):
[0x100] separate buses for
ADD R20, R21
opcodes and operands
ADD R20,R21 ; R20 = R20 + R21
LDS R20, 0x100
 Advantage: opcodes and operands can go in and out of the CPU
together.
 Disadvantage: leads to more cost in generalFetch
purpose computers.

Execute

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

27
 RISC architecture
 Feature 6: more than 95% of instructions are
executed in 1 machine cycle

28
 RISC architecture
 Feature 7
 RISC processors have at least 32 registers.
Decreases the need for stack and memory usages.
 In AVR there are 32 general purpose registers (R0
to R31)

29