Routing is the process of connecting all logic pins in a design using metal interconnect layers and vias. It has four main stages: global routing to find approximate pin connections, track assignment to assign specific routing tracks, detailed routing to create actual metal and via connections while fixing violations, and search and repair to further reduce any remaining design rule checking violations. The goals of routing are to create physical interconnects for all signals while minimizing total wirelength, number of vias, and ensuring timing constraints are met with no opens or shorts. Congestion can occur if there are too many routes in a limited area without enough routing resources and tracks. The outputs of routing include the layout file and timing constraint files.
Routing is the process of connecting all logic pins in a design using metal interconnect layers and vias. It has four main stages: global routing to find approximate pin connections, track assignment to assign specific routing tracks, detailed routing to create actual metal and via connections while fixing violations, and search and repair to further reduce any remaining design rule checking violations. The goals of routing are to create physical interconnects for all signals while minimizing total wirelength, number of vias, and ensuring timing constraints are met with no opens or shorts. Congestion can occur if there are too many routes in a limited area without enough routing resources and tracks. The outputs of routing include the layout file and timing constraint files.
Routing is the process of connecting all logic pins in a design using metal interconnect layers and vias. It has four main stages: global routing to find approximate pin connections, track assignment to assign specific routing tracks, detailed routing to create actual metal and via connections while fixing violations, and search and repair to further reduce any remaining design rule checking violations. The goals of routing are to create physical interconnects for all signals while minimizing total wirelength, number of vias, and ensuring timing constraints are met with no opens or shorts. Congestion can occur if there are too many routes in a limited area without enough routing resources and tracks. The outputs of routing include the layout file and timing constraint files.
Routing is the process of connecting all logic pins in a design using metal interconnect layers and vias. It has four main stages: global routing to find approximate pin connections, track assignment to assign specific routing tracks, detailed routing to create actual metal and via connections while fixing violations, and search and repair to further reduce any remaining design rule checking violations. The goals of routing are to create physical interconnects for all signals while minimizing total wirelength, number of vias, and ensuring timing constraints are met with no opens or shorts. Congestion can occur if there are too many routes in a limited area without enough routing resources and tracks. The outputs of routing include the layout file and timing constraint files.
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ROUTING
What is routing ? Routing is the process of converting every logical connection present in netlist into physical connection with help of metal layers and vias. making physical connections between signal pins using metal layers. Following Clock Tree Synthesis (CTS) and optimization, the routing step determines the exact pathways for interconnecting standard cells, macros, and I/O pins.
GOALS:
1. No open / shorts 2. To create physical connection to all clocks and signal pins through metal interconnect 3. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design. 4. No unnecessary detours 5. Minimum lvs 6. Route path must meet setup and hold margin 7. DRVs should be under limit
Inputs for routing
1. Netlist 2. NDR 3. CTS def 4. TLU+ 5. Tec file
Checklist before routing
1. Placement and CTS and optimization should be completed 2. PG nets should be pre-routed 3. Timing DRC and QoR post CTS should be acceptable 4. High fanout nets(HFNS) should not be greater than the specified limit 5. Check for blocked PG ports 6. Checks for overlapping cells in the design 7. Estimated congestion acceptable 8. Check routability
STAGES OF ROUTING There are four stages in routing 1. Global routing 2. Track assignment 3. Detail routing 4. Search and repair
1. Global routing : ● In this stage tool will find approximate path/direction of routing for all the pins based on manhattan distance calculation algorithm. i t randomly connect all pins in this stage by dividing design in g-cells. ● By default the width of the gcells issame as the height of a standard cell and is aligned with the standard cell rows. ● Each gcell has a finite number of horizontal and vertical tracks. ● It does not specify the actual layout of wires. ● Objective of global routing -minimize total wire length,minimize total overflow. ● Assign each net to routing region which is divided. 2. Track assignment : ● In this stage each routing tracks are assigned to each global route.these tracks are assigned in vertical and horizontal direction. The tracks are guide for routing . ● Track assignment replace all global route with actual metals, there will be many drc , timing violation etc
3.Detailed Routing: 1. In this stage the actual connection between all the nets takes place. It creates the actual via and metal connections. 2. It specifies the specific tracks for the interconnection, each layer has its own routing grid, rules. 3. The violations that were created during the track assignment stage are fixed in this stage. 4. The main goal of detailed routing is to complete all of the required interconnect without leaving open,shorts or spacing violations. 5. In this stage filler cells will be added 6. Detail route done based on timing aware, drc aware. 7. In this stage entire design devided into sbox which helps in reducing DRC’s
Connectivity of metals layers with pins is done based on track assignment
4. Search and repair
● Tool will try to fix remaining DRC violation by dividing design into small parts to find DRC violation in each region in every iteration and adjust the violation. ● Like wise for every iteration tool will reduce no. of division and again check for drc violation , by this way tool will abel to remove all drc violation with the help of search and repair. ● Left over violations can be fixed manually Checklist after routing
1. Acceptable congestion 2. Acceptable DRV’s. 3. Apply the logical PG connection to newly added cells 4. Timing QOR's details
Check list after routing
● Special cells are inserted.
● Final utilization (total & cell row). ● Final congestion figure. ● Power analysis done? ● Total power consumption in design. ● Timing analysis for setup & hold slack.
Routing congstion
● Routing congestion occurs when too many routes need to go through an area that does not have enough resources or routing tracks. ● High speed design having more signal integrity constraints such as extra route spacing or wire routes. Causes of congestion:
1. Bad floorplan 2. High placement density 3. Limited routing layers 4. High pin density
