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    5 TH

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    paridhiagarwal129

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    5 TH

    Uploaded by

    paridhiagarwal129
    25 views20 pages

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    5th

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    25 views20 pages

    5 TH

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    paridhiagarwal129

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    Dnit- 5 4 Lo_Devicen Acoma operas on cil devia Animes serie rove yon 8 81/0 ‘manage Some common UO devs ate cise, esr chp USB devs, mp sero LED, Ono atch network commen, 0, ptr te. ‘An 0 pst takes un /0 eqs seit the yi ev thn sos the espanse «lock deve: Te diver communicates with this ie by seg tot bok of ats, eb his deve © Gbps of To Denies 1. Hasanrseadsbler Tes titabe for communicating wth thee. or expe, ne, printer, hear 2 Machine-readable: These tbl for commiting with letonic easpment For ‘xample iskand ape ves sensors Communication: Sutable fr communicating with emote eves For example gt ine ders, modems te © Block Diagram for To Denies Covitro lier. ‘eae kno a deve They hy th OS an evr tra etn a de ‘ld diver HO moist ot pone ach ves ven comer and eee tht hp omni wht OSA device ‘rarcrcton ve vey, Sone devotes resort, ad © Orpentastion of To function, Techond orming To ete fot pojerng Sh SSaa Wana Dstatarter tase the cetluntand 0 doicescan be handedin gnealy te "ype ofmoses wih ae gen below 1. Pogammeao 2 erp ities 10 4 prosranmed yO Proganied YO nstuctons ae thereto strato ten computer roar Each data ta ants yh natn nh rota, Usa he rogram conto ts tanto om CPU arpa Taser dara unde pograrimed YO equres constr mantaring ote pete yt CPU work To 2 frm remanence SNE «macnn ee et fi nce @ Interrupt initiated 0 ‘Trthe programmed /0 method the CPU staysin the program oop unt he incatesthatits ready fr data transor. Tiss tie consuing process boca oops the processor busy newest, ‘This problem can be overcome by using nteruptinitated YO. nthis when the interface determines that the peripteralis ready fr data tans, generates an nterupt. tr ‘eceving the intrupt ina, the CPU stops the ask which Ris processing and service ‘the YO tanatr and then retuns back to ts previous processing tek vo CPU CPU Memory \__ Next instruction O Dire Monory Acco, (DMA) Direct Memory Access (DMA) means CPU grants UO module authority to ‘ead from or mite to memory without involvement. DMA module ise Controls exchange of data between main memory and the VO device CPU is only involved at the beginning and end of the transfer and interrupted only ater entire block has been transferred Direct Memory Access needs a special hardware called DMA controller (OMAC) that manages the data transfers and arbirates access to the system bus. The controllers are programmed with source and destination pointers (where to readiwrite the data), counters to track the number of transfered bytes, and setings, which includes UO and memory types, Block Sia gram lars ou ‘The operating system uses the DMA hardware as follows — step Description 1 Device crivris instructed to transtr disk data to a butler adress x 2 Device driver then instruct disk controller to transfer data to blr. 3 Disk contoller starts OMA transter. 4 Disk contol sends each byte to DMA conti. 5 _DMAcontroter transfers byes to butler, creases the memory address, decreases the counter C uni C becomes zero. © When © becomes zero, DMAnterupts CPU to signal ranster completion. FF I/O Aubsystin ra 10 Spe on ev ny ss ie VO Flog mo wo he Sern aa ne ing 0 ten es oe \tcacy adie mage mage tn tend bye pear Sueno ti main ey a i i ("Genet cp nth seed mama nen he pen an seer a ea ‘Stentor sos tare re neers P,P ce aco ttre ci aa Th pkg on cia We un 708 {eo he prom at te. seeping pone, ing mrad by se neon pour athe openng sons fishnet an mer ed Ear Hansing- An prog stat ps rama an id ae many ht ar eponoore {Butfering in Operating System QR T/O Buples ‘The utter is nares the ain memory vest stare orld tha Gna tampaTaA Ine Hee, utes apenas snes Itheosin matching speed between two devices n hich he data is wanted Fo example, shar dls ns to str he received from the dem. Ase know he transmission speedo mode slow conoared tothe Ra elsk. So bytes coming om te mode's accursed in the bute space, fd whe lth bytes of te nas rvs atthe but, he entre dts wit the hae skin @ singe pera, Ithaps the deics wih fern sizes of data transfer to got adapted to each other thas devies to maripiste dla beloe sending or reeing i In computer networking, the rg mace i llr a the ecaving en nd reassemble a orm complete lage message Iealeo supports copy semantics, With copy sats, he version of cata in the br is euratead tobe the version of dt the tne of syst cl rezpecive af ny subsequent change f0 dain the butler. Butlerngereases the perlermance ofthe eves. averlps the JO of one jb wth he computation ofthe sea ‘Types of Buffering ‘There re three main types of butfering in the operating system, suchas Types of Buffer Pera Buffer ee CMe Buffer + Uneaten ed or sero md eins Te User ngs a ne tae, th a earioge ret ving the er ie. «+ Byt-a tne operations wed on fom od, tein when each eyo ic In Double Butering, two schames or tw butlers ae used i the plc of one his butflorng, he poduce produces one bite le the cnsuner consumes anther ber smutaneousy. So, he podueer nat reed owt fling the bt, Datla lenge ouste Yo surrenin ‘Block oriented: This is how # double butfer works. There are two buffers inthe system. ©The crivr or controller uses one buffer to store date whl waiting frit tobe taken by abigher hierarchy level Another bute is used to store data from the loner ve module ‘© Amsjoralsscvantage of double butferng is thatthe complexity of the process gets increased, 1 the process performs rapid bursts of YO, then using double buering may be defcet. ‘Stream oriented performs these operations, euch a: © Line- at tine YO, the user process doos not need to be suspended for input of ‘output uness the process runs ahead ofthe double bute. © Byte a time operations, double bute oer no advantage over a single butfer of ‘ice he length. utter ‘when more than two butlers are used the butlers’ collection sealed a eireular butte. Each buttor is boing one unit inthe circular butter. The data transfer rate wil ncroase using the excular buffer rather than the cube buffering ‘RCULAR 0 BUFFERING «In this, the data do not eectty pass frm th producer tothe consumer because the data would change due to overwriting of butters before consume. «Te producer can ony fil upto buerx-1 while data in buffer x is waiting tobe consumed, [Advantages of Butter 1 Thetcet utes untemdoh aces Xana ste ein

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