Infineon XMC4300 DataSheet v01 02 EN-3364105

XMC4300
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Data Sheet
V1.2 2023-04
Microcontrollers
Edition 2023-04
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2023 Infineon Technologies AG
All Rights Reserved.
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XMC4300
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Data Sheet
V1.2 2023-04
Microcontrollers
XMC4300
XMC4000 Family
XMC4300 Data Sheet
Revision History: V1.2 2023-04
V1.1 2018-09
V1.0 2016-02
Page Subjects
V1.2 2023-04
10 Updated number of breakpoints from 8 to 6.
99 Added PG-LQFP-100-29 details in Table 60.
102 Added package diagram: PG-LQFP-100-29.
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
Synopsys™ is a trademark of Synopsys, Inc.
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Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet V1.2, 2023-04

Subject to Agreement on the Use of Product Information
XMC4300
XMC4000 Family
Table of Contents
Table of Contents
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.2 Analog to Digital Converters (VADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.3 Digital to Analog Converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.5 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.6 USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.7 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.8 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.9 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.4 Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . . 68
3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.7 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.8 Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 74
Data Sheet 5 V1.2, 2023-04

XMC4300
XMC4000 Family
Table of Contents
3.3.8.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.3.8.3 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.3.8.4 SDMMC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.3.9 USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3.10 Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.10.1 ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.10.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . 91
3.3.10.3 ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.3.11 EtherCAT (ECAT) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.11.1 ECAT Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.11.2 ETH Management Signal Parameters (MCLK, MDIO) . . . . . . . . . . . 94
3.3.11.3 MII Timing TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.3.11.4 MII Timing RX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.3.11.5 Sync/Latch Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Data Sheet 6 V1.2, 2023-04

XMC4300
XMC4000 Family
About this Document
About this Document

This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC4[12]00 series devices.
The document describes the characteristics of a superset of the XMC4[12]00 series
devices. For simplicity, the various device types are referred to by the collective term
XMC4[12]00 throughout this manual.
XMC4000 Family User Documentation

The set of user documentation includes:
• Reference Manual
– describes the functionality of the superset of devices.
• Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
• Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions
of those documents.
Data Sheet 7 V1.2, 2023-04

XMC4300
XMC4000 Family
Summary of Features
1 Summary of Features
The XMC4300 devices are members of the XMC4000 Family of microcontrollers based
on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance
and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial
Control, Power Conversion, Sense & Control.
Figure 1 System Block Diagram
CPU Subsystem
• CPU Core
– High Performance 32-bit ARM Cortex-M4 CPU
– 16-bit and 32-bit Thumb2 instruction set
– DSP/MAC instructions
– System timer (SysTick) for Operating System support
• Floating Point Unit
• Memory Protection Unit
• Nested Vectored Interrupt Controller
• General Purpose DMA with up-to 8 channels
• Event Request Unit (ERU) for programmable processing of external and internal
service requests
• Flexible CRC Engine (FCE) for multiple bit error detection
Data Sheet 8 V1.2, 2023-04

XMC4300
XMC4000 Family
Summary of Features
On-Chip Memories
• 16 KB on-chip boot ROM
• 64 KB on-chip high-speed program memory
• 64 KB on-chip high speed data memory
• 256 KB on-chip Flash Memory with 8 KB instruction cache
Communication Peripherals
• Ethernet MAC module capable of 10/100 Mbit/s transfer rates
• EtherCATSlave interface (ECAT) capable of 100 Mbit/s transfer rates with 2 MII
ports, 8 Fieldbus Memory Management Units (FMMU), 8 Sync Manager, 64 bit
distributed clocks
• Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY
• Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 2 nodes, 64
message objects (MO), data rate up to 1 MBaud
• Four Universal Serial Interface Channels (USIC),providing 4 serial channels, usable
as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
• LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
• SD and Multi-Media Card interface (SDMMC) for data storage memory cards
Analog Frontend Peripherals

• Two Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with
input out-of-range comparators
• Digital-Analog Converter (DAC) with two channels of 12-bit resolution
Industrial Control Peripherals

• One Capture/Compare Units 8 (CCU8) for motor control and power conversion
• Two Capture/Compare Units 4 (CCU4) for use as general purpose timers
• Window Watchdog Timer (WDT) for safety sensitive applications
• Die Temperature Sensor (DTS)
• Real Time Clock module with alarm support
• System Control Unit (SCU) for system configuration and control
Input/Output Lines
• Programmable port driver control module (PORTS)
• Individual bit addressability
• Tri-stated in input mode
• Push/pull or open drain output mode
• Boundary scan test support over JTAG interface
Data Sheet 9 V1.2, 2023-04

XMC4300
XMC4000 Family
Summary of Features
On-Chip Debug Support

• Full support for debug features: 6 breakpoints, CoreSight, trace
• Various interfaces: ARM-JTAG, SWD, single wire trace
1.1 Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:
• <DDD> the derivatives function set
• <Z> the package variant
– E: LFBGA
– F: LQFP
– Q: VQFN
• <PPP> package pin count
• <T> the temperature range:
– F: -40°C to 85°C
– K: -40°C to 125°C
• <FFFF> the Flash memory size.
For ordering codes for the XMC4300 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC4300 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC4300 is used for all derivatives throughout this document.
1.2 Device Types

These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1 Synopsis of XMC4300 Device Types

1)
Derivative Package Flash SRAM
Kbytes Kbytes
XMC4300-F100x256 PG-LQFP-100 256 128
1) x is a placeholder for the supported temperature range.
Data Sheet 10 V1.2, 2023-04

XMC4300
XMC4000 Family
Summary of Features
1.3 Device Type Features

The following table lists the available features per device type.
Table 2 Features of XMC4300 Device Types

Derivative1) LED SD ETH ECAT USB USIC MultiCAN
TS MMC Intf. Slave Intf. Chan. Nodes, MO
Intf. Intf. Intf.
XMC4300-F100x256 1 1 RMII 2 x MII 1 2x2 N0, N1
MO[0..63]
Table 3 Features of XMC4300 Device Types

Derivative1) ADC Chan. DAC Chan. CCU4 Slice CCU8 Slice
XMC4300-F100x256 16 2 2x4 1x4
1.4 Definition of Feature Variants

The XMC4300 types are offered with several memory sizes and number of available
VADC channels. Table 4 describes the location of the available Flash memory, Table 5
describes the location of the available SRAMs, Table 6 the available VADC channels.
Table 4 Flash Memory Ranges
Total Flash Size Cached Range Uncached Range
256 Kbytes 0800 0000H  0C00 0000H 
0803 FFFFH 0C03 FFFFH
Table 5 SRAM Memory Ranges

Total SRAM Size Program SRAM System Data SRAM
128 Kbytes 1FFF 0000H  2000 0000H 
1FFF FFFFH 2000 FFFFH
Table 6 ADC Channels1)

Package VADC G0 VADC G1
PG-LQFP-100 CH0..CH7 CH0..CH7
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port
I/O Function table.
Data Sheet 11 V1.2, 2023-04

XMC4300
XMC4000 Family
Summary of Features
1.5 Identification Registers

The identification registers allow software to identify the marking.
Table 7 XMC4300 Identification Registers

Register Name Value Marking
SCU_IDCHIP 0004 3001H AA
JTAG IDCODE 101D F083H AA
Data Sheet 12 V1.2, 2023-04

XMC4300
XMC4000 Family
General Device Information
2 General Device Information

This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC4300 Logic Symbol PG-LQFP-100
Data Sheet 13 V1.2, 2023-04

XMC4300
XMC4000 Family
2.2 Pin Configuration and Definition

The following figures summarize all pins, showing their locations on the four sides of the
different packages.
Figure 3 XMC4300 PG-LQFP-100 Pin Configuration (top view)
Data Sheet 14 V1.2, 2023-04

XMC4300
XMC4000 Family
2.2.1 Package Pin Summary

The following general scheme is used to describe each pin:
Table 8 Package Pin Mapping Description

Function Package A Package B ... Pad Notes
Type
Name N Ax ... A2
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type (A1, A1+, A2, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the “Notes”, special information to the respective pin/function is given, i.e. deviations
from the default configuration after reset. Per default the regular Port pins are configured
as direct input with no internal pull device active.
Table 9 Package Pin Mapping

Function LQFP-100 Pad Type Notes
P0.0 2 A1+
P0.1 1 A1+
P0.2 100 A2
P0.3 99 A2
P0.4 98 A2
P0.5 97 A2
P0.6 96 A2
P0.7 89 A2 After a system reset, via HWSEL
this pin selects the DB.TDI function.
this pin selects the DB.TRST
function, with a weak pull-down
active.
P0.9 4 A2
P0.10 3 A1+
P0.11 95 A1+
P0.12 94 A1+
Data Sheet 15 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 9 Package Pin Mapping (cont’d)

P1.0 79 A1+
P1.1 78 A1+
P1.2 77 A2
P1.3 76 A2
P1.4 75 A1+
P1.5 74 A1+
P1.6 83 A2
P1.7 82 A2
P1.8 81 A2
P1.9 80 A2
P1.10 73 A1+
P1.11 72 A1+
P1.12 71 A2
P1.13 70 A2
P1.14 69 A2
P1.15 68 A2
P2.0 52 A2
this pin selects the DB.TDO
function.
P2.2 50 A2
P2.3 49 A2
P2.4 48 A2
P2.5 47 A2
P2.6 54 A1+
P2.7 53 A1+
P2.8 46 A2
P2.9 45 A2
P2.10 44 A2
P2.14 41 A2
P2.15 40 A2
P3.0 7 A2
P3.1 6 A2
Data Sheet 16 V1.2, 2023-04

XMC4300
XMC4000 Family

P3.2 5 A2
P3.3 93 A1+
P3.4 92 A1+
P3.5 91 A2
P3.6 90 A2
P4.0 85 A2
P4.1 84 A2
P5.0 58 A1+
P5.1 57 A1+
P5.2 56 A1+
P5.7 55 A1+
P14.0 31 AN/DIG_IN
P14.1 30 AN/DIG_IN
P14.2 29 AN/DIG_IN
P14.3 28 AN/DIG_IN
P14.4 27 AN/DIG_IN
P14.5 26 AN/DIG_IN
P14.6 25 AN/DIG_IN
P14.7 24 AN/DIG_IN
P14.8 37 AN/DAC/DIG_IN
P14.9 36 AN/DAC/DIG_IN
P14.12 23 AN/DIG_IN
P14.13 22 AN/DIG_IN
P14.14 21 AN/DIG_IN
P14.15 20 AN/DIG_IN
P15.2 19 AN/DIG_IN
P15.3 18 AN/DIG_IN
P15.8 39 AN/DIG_IN
P15.9 38 AN/DIG_IN
Data Sheet 17 V1.2, 2023-04

XMC4300
XMC4000 Family

HIB_IO_0 14 A1 special At the first power-up and with every
reset of the hibernate domain this
pin is configured as open-drain
output and drives "0".
As output the medium driver mode
is active.
HIB_IO_1 13 A1 special At the first power-up and with every
reset of the hibernate domain this
pin is configured as input with no
pull device active.
As output the medium driver mode
is active.
USB_DP 9 special
USB_DM 8 special
TCK 67 A1 Weak pull-down active.
TMS 66 A1+ Weak pull-up active.
As output the strong-soft driver
mode is active.
PORST 65 special Weak pull-up permanently active,
strong pull-down controlled by EVR.
XTAL1 61 clock_IN
XTAL2 62 clock_O
RTC_XTAL1 16 clock_IN
RTC_XTAL2 15 clock_O
VBAT 17 Power When VDDP is supplied VBAT has
to be supplied as well.
VBUS 10 special
VAREF 33 AN_Ref
VAGND 32 AN_Ref
VDDA 35 AN_Power
VSSA 34 AN_Power
VDDC 12 Power
VDDC 42 Power
VDDC 64 Power
VDDC 86 Power
VDDP 11 Power
Data Sheet 18 V1.2, 2023-04

XMC4300
XMC4000 Family

VDDP 43 Power
VDDP 60 Power
VDDP 87 Power
VSS 59 Power
VSSO 63 Power
VSS Exp. Pad Power Exposed Die Pad
The exposed die pad is connected
internally to VSS. For proper
operation, it is mandatory to connect
the exposed pad directly to the
common ground on the board.
For thermal aspects, please refer to
the Data Sheet. Board layout
examples are given in an
application note.
Data Sheet 19 V1.2, 2023-04

XMC4300
XMC4000 Family
2.2.2 Port I/O Functions

The following general scheme is used to describe each Port pin:
Table 10 Port I/O Function Description

Function Outputs Inputs
ALT1 ALTn HWO0 HWI0 Input Input
P0.0 MODA.OUT MODB.OUT MODB.INA MODC.INA
Pn.y MODA.OUT MODA.INA MODC.INB
Figure 4 Simplified Port Structure

Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly driven by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL it is possible to select between different hardware “masters”
(HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control
overrules settings in the respective port pin registers.
Data Sheet 20 V1.2, 2023-04

2.2.2.1 Port I/O Function Table
Table 11 Port I/O Functions
Data Sheet
Function Output Input
ALT1 ALT2 ALT3 ALT4 HWO0 HWI0 Input Input Input Input Input Input Input Input
P0.0 ECAT0. CAN. CCU80. LEDTS0. U1C1. ETH0. ERU0. ETH0.
PHY_RST N0_TXD OUT21 COL2 DX0D CLK_RMIIB 0B0 CLKRXB
P0.1 USB. U1C1. CCU80. LEDTS0. ETH0. ERU0. ECAT0. ETH0.

DRIVEVBUS DOUT0 OUT11 COL3 CRS_DVB 0A0 P1_RX_CLKA RXDVB
P0.2 ECAT0. U1C1. CCU80. U1C0. U1C0. ETH0. ERU0.

P1_TXD2 SELO1 OUT01 DOUT3 HWIN3 RXD0B 3B3
P0.3 ECAT0. CCU80. U1C0. U1C0. ETH0. ERU1.

P1_TXD3 OUT20 DOUT2 HWIN2 RXD1B 3B0
P0.4 ETH0. CCU80. U1C0. U1C0. U1C0. ERU0. ECAT0.

TX_EN OUT10 DOUT1 HWIN1 DX0A 2B3 P1_RXD3A
P0.5 ETH0. U1C0. CCU80. U1C0. U1C0. U1C0. ERU1. ECAT0.

TXD0 DOUT0 OUT00 DOUT0 HWIN0 DX0B 3A0 P1_RXD2A
P0.6 ETH0. U1C0. CCU80. U1C0. ERU0. CCU80. ECAT0.

TXD1 SELO0 OUT30 DX2A 3B2 IN2B P1_RXD1A
P0.7 WWDT. U0C0. ECAT0. DB. U0C0. ERU0. CCU80. CCU80. CCU80. CCU80.
SERVICE_OUT SELO0 LED_ERR TDI DX2B 2B1 IN0A IN1A IN2A IN3A
21
P0.8 SCU. U0C0. ECAT0. DB. U0C0. ERU0. CCU80.
EXTCLK SCLKOUT LED_RUN TRST DX1B 2A1 IN1B
P0.9 U1C1. CCU80. LEDTS0. ETH0. ETH0. U1C1. USB. ERU0. ECAT0.
SELO0 OUT12 COL0 MDO MDIA DX2A ID 1B0 P1_RX_DVA
P0.10 ETH0. U1C1. CCU80. LEDTS0. U1C1. ERU0. ECAT0.

MDC SCLKOUT OUT02 COL1 DX1A 1A0 P1_TX_CLKA
P0.11 ECAT0. U1C0. CCU80. SDMMC. ETH0. U1C0. ERU0. ECAT0.

P1_LINK_ACT SCLKOUT OUT31 RST RXERB DX1A 3A2 P1_RXD0A
P0.12 U1C1. CCU40. ECAT0. ECAT0. U1C1. ERU0.

SELO0 OUT3 MDO MDIA DX2B 2B2
P1.0 U0C0. CCU40. ERU1. U0C0. ERU0. CCU40. ECAT0.

SELO0 OUT3 PDOUT3 DX2A 3B0 IN3A P0_TX_CLKA
P1.1 U0C0. CCU40. ERU1. SDMMC. U0C0. ERU0. CCU40. ECAT0.

SCLKOUT OUT2 PDOUT2 SDWC DX1A 3A0 IN2A P0_RX_CLKA
P1.2 ECAT0. CCU40. ERU1. U0C0. U0C0. ERU1. CCU40.

P0_TXD3 OUT1 PDOUT1 DOUT3 HWIN3 2B0 IN1A
P1.3 ECAT0. U0C0. CCU40. ERU1. U0C0. U0C0. ERU1. CCU40.

P0_TX_ENA MCLKOUT OUT0 PDOUT0 DOUT2 HWIN2 2A0 IN0A
P1.4 WWDT. CAN. CCU80. U0C0. U0C0. U0C0. CAN. ERU0. CCU41. ECAT0.
SERVICE_OUT N0_TXD OUT33 DOUT1 HWIN1 DX0B N1_RXDD 2B0 IN0C P0_RXD0A
P1.5 CAN. U0C0. CCU80. U0C0. U0C0. U0C0. CAN. ERU0. ERU1. CCU41. ECAT0.
N1_TXD DOUT0 OUT23 DOUT0 HWIN0 DX0A N0_RXDA 2A0 0A0 IN1C P0_RXD1A
P1.6 ECAT0. U0C0. SDMMC. SDMMC.

P0_TXD0 SCLKOUT DATA1_OUT DATA1_IN
V1.2, 2023-04
XMC4000 Family
XMC4300
Table 11 Port I/O Functions (cont’d)
P1.7 ECAT0. U0C0. U1C1. SDMMC. SDMMC.
Data Sheet
P0_TXD1 DOUT0 SELO2 DATA2_OUT DATA2_IN
P1.8 ECAT0. U0C0. U1C1. SDMMC. SDMMC.

P0_TXD2 SELO1 SCLKOUT DATA4_OUT DATA4_IN
P1.9 U0C0. U1C1. SDMMC. SDMMC. ECAT0.

SCLKOUT DOUT0 DATA5_OUT DATA5_IN P0_RX_DVA
P1.10 ETH0. U0C0. ECAT0. SDMMC. CCU41. ECAT0.

MDC SCLKOUT LED_ERR SDCD IN2C P0_RXD2A
P1.11 ECAT0. U0C0. ECAT0. ETH0. ETH0. CCU41. ECAT0.

LED_STATE_R SELO0 LED_RUN MDO MDIC IN3C P0_RXD3A
UN
P1.12 ETH0. CAN. ECAT0. SDMMC. SDMMC.

TX_EN N1_TXD P0_LINK_ACT DATA6_OUT DATA6_IN
P1.13 ETH0. U0C1. ECAT0. SDMMC. SDMMC. CAN.

TXD0 SELO3 PHY_CLK25 DATA7_OUT DATA7_IN N1_RXDC
P1.14 ETH0. U0C1. ECAT0. U1C0.

TXD1 SELO2 SYNC0 DX0E
P1.15 SCU. U1C0. ERU1. ECAT0.

EXTCLK DOUT0 1A0 P0_LINKB
P2.0 CAN. LEDTS0. ETH0. ETH0. ERU0. CCU40.

N0_TXD COL1 MDO MDIB 0B3 IN1C
22
P2.1 LEDTS0. DB.TDO/ ETH0. ERU1. CCU40. ETH0.
COL0 TRACESWO CLK_RMIIA 0B0 IN0C CLKRXA
P2.2 VADC. CCU41. LEDTS0. LEDTS0. LEDTS0. ETH0. U0C1. ERU0. CCU41.
EMUX00 OUT3 LINE0 EXTENDED0 TSIN0A RXD0A DX0A 1B2 IN3A
P2.3 VADC. U0C1. CCU41. LEDTS0. LEDTS0. LEDTS0. ETH0. U0C1. ERU0. CCU41.
EMUX01 SELO0 OUT2 LINE1 EXTENDED1 TSIN1A RXD1A DX2A 1A2 IN2A
P2.4 VADC. U0C1. CCU41. LEDTS0. LEDTS0. LEDTS0. ETH0. U0C1. ERU0. CCU41.
EMUX02 SCLKOUT OUT1 LINE2 EXTENDED2 TSIN2A RXERA DX1A 0B2 IN1A
P2.5 ETH0. U0C1. CCU41. LEDTS0. LEDTS0. LEDTS0. ETH0. U0C1. ERU0. CCU41. ETH0.
TX_EN DOUT0 OUT0 LINE3 EXTENDED3 TSIN3A RXDVA DX0B 0A2 IN0A CRS_DVA
P2.6 ERU1. CCU80. LEDTS0. CAN. ERU0. CCU40. ECAT0.

PDOUT3 OUT13 COL3 N1_RXDA 1B3 IN3C P0_RX_ERRB
P2.7 ETH0. CAN. CCU80. LEDTS0. ERU1. CCU40.

MDC N1_TXD OUT03 COL2 1B0 IN2C
P2.8 ETH0. ERU1. CCU80. LEDTS0. LEDTS0. LEDTS0. DAC. CCU40. CCU40. CCU40. CCU40.
TXD0 PDOUT1 OUT32 LINE4 EXTENDED4 TSIN4A TRIGGER5 IN0B IN1B IN2B IN3B
P2.9 ETH0. ERU1. CCU80. LEDTS0. LEDTS0. LEDTS0. DAC. CCU41. CCU41. CCU41. CCU41.
TXD1 PDOUT2 OUT22 LINE5 EXTENDED5 TSIN5A TRIGGER4 IN0B IN1B IN2B IN3B
P2.10 VADC. ERU1. ECAT0. ECAT0.

EMUX10 PDOUT0 PHY_RST SYNC1
P2.14 VADC. U1C0. CCU80. U1C0.

EMUX11 DOUT0 OUT21 DX0D
P2.15 VADC. ECAT0. CCU80. LEDTS0. LEDTS0. LEDTS0. ETH0. U1C0.

EMUX12 P1_TXD3 OUT11 LINE6 EXTENDED6 TSIN6A COLA DX0C
V1.2, 2023-04
XMC4000 Family
XMC4300
P3.0 U0C1. ECAT0. U0C1. CCU80.
Data Sheet
SCLKOUT P1_TX_ENA DX1B IN2C
P3.1 U0C1. ECAT0. U0C1. ERU0. CCU80.

SELO0 P1_TXD0 DX2B 0B1 IN1C
P3.2 USB. CAN. ECAT0. LEDTS0. ERU0. CCU80.

DRIVEVBUS N0_TXD P1_TXD1 COLA 0A1 IN0C
P3.3 U1C1. ECAT0. SDMMC. CCU80.

SELO1 MCLK LED IN3B
P3.4 U1C1. SDMMC. CCU80. ECAT0.

SELO2 BUS_POWER IN0B P1_LINKA
P3.5 U1C1. U0C1. SDMMC. SDMMC. ERU0. ECAT0.

SELO3 DOUT0 CMD_OUT CMD_IN 3B1 P1_RX_ERRA
P3.6 U1C1. U0C1. SDMMC. SDMMC. ERU0.

SELO4 SCLKOUT CLK_OUT CLK_IN 3A1
P4.0 ECAT0. U1C0. SDMMC. SDMMC. U1C1. U0C1. ECAT0.

PHY_CLK25 SCLKOUT DATA0_OUT DATA0_IN DX1C DX0E P0_RX_ERRA
P4.1 U1C1. U0C1. SDMMC. SDMMC. ECAT0.

MCLKOUT SELO0 DATA3_OUT DATA3_IN P0_LINKA
P5.0 ERU1. ETH0. U0C0. ECAT0.

PDOUT0 RXD0D DX0D P0_RXD0B
P5.1 U0C0. ERU1. ETH0. ECAT0.
23
DOUT0 PDOUT1 RXD1D P0_RXD1B
P5.2 ECAT0. ERU1. ETH0. ECAT0. ETH0.

P0_LINK_ACT PDOUT2 CRS_DVD P0_RXD2B RXDVD
P5.7 ECAT0. LEDTS0. ECAT0.

SYNC0 COLA P0_RXD3B
P14.0 VADC.
G0CH0
P14.1 VADC.
G0CH1
P14.2 VADC. VADC.

G0CH2 G1CH2
P14.3 VADC. VADC. CAN.

G0CH3 G1CH3 N0_RXDB
P14.4 VADC. ECAT0.

G0CH4 LATCH1A
P14.5 VADC. ECAT0.

G0CH5 LATCH0A
P14.6 VADC. G0ORC6 ECAT0.

G0CH6 P1_RX_CLKB

G0CH7 P1_RXD0B
P14.8 DAC. VADC. ETH0.

OUT_0 G1CH0 RXD0C
P14.9 DAC. VADC. ETH0.

OUT_1 G1CH1 RXD1C
V1.2, 2023-04
XMC4000 Family
XMC4300
P14.12 VADC. ECAT0.
Data Sheet
G1CH4 P1_RXD1B
P14.13 VADC. ECAT0.

G1CH5 P1_RXD2B

G1CH6 P1_RXD3B

G1CH7 P1_RX_DVB
P15.2 ECAT0.
P1_RX_ERRB
P15.3 ECAT0.
P1_LINKB
P15.8 ETH0. ETH0.

CLK_RMIIC CLKRXC
P15.9 ETH0. ETH0.

CRS_DVC RXDVC
HIB_IO_0 HIBOUT WWDT. WAKEUPA

SERVICE_OUT
HIB_IO_1 HIBOUT WWDT. WAKEUPB

SERVICE_OUT
USB_DP
24
USB_DM
TCK DB.TCK/
SWCLK
TMS DB.TMS/
SWDIO
PORST
XTAL1 U0C0. U0C1. U1C0. U1C1.

DX0F DX0F DX0F DX0F
XTAL2
RTC_XTAL1 ERU0.
1B1
RTC_XTAL2
V1.2, 2023-04
XMC4000 Family
XMC4300
XMC4300
XMC4000 Family
2.3 Power Connection Scheme

Figure 5 shows a reference power connection scheme for the XMC4300.
Figure 5 Power Connection Scheme

Every power supply pin needs to be connected. Different pins of the same supply need
also to be externally connected. As example, all VDDP pins must be connected externally
to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each
supply pin against VSS. An additional 10 μF capacitor is connected to the VDDP nets and
an additional 10 uF capacitor to the VDDC nets.
Data Sheet 25 V1.2, 2023-04

XMC4300
XMC4000 Family
The XMC4300 has a common ground concept, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
VAGND is the low potential to the analog reference VAREF. Depending on the application it
can share the common ground or have a different potential. In devices with shared
VDDA/VAREF and VSSA/VAGND pins the reference is tied to the supply. Some analog
channels can optionally serve as “Alternate Reference”; further details on this operating
mode are described in the Reference Manual.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connected directly to VDDP.
Data Sheet 26 V1.2, 2023-04

XMC4300
XMC4000 Family
Electrical Parameters
3 Electrical Parameters
Attention: All parameters in this chapter are preliminary target values and may
change based on characterization results.
3.1 General Parameters
3.1.1 Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the XMC4300
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with a two-letter abbreviation in
column “Symbol”:
• CC
Such parameters indicate Controller Characteristics, which are a distinctive feature
of the XMC4300 and must be regarded for system design.
• SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC4300 is designed in.
Data Sheet 27 V1.2, 2023-04

XMC4300
XMC4000 Family
3.1.2 Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 12 Absolute Maximum Rating Parameters

Parameter Symbol Values Unit Note /
Min. Typ. Max. Test Con
dition
Storage temperature TST SR -65 – 150 C –
Junction temperature TJ SR -40  150 °C –
Voltage at 3.3 V power supply VDDP SR – – 4.3 V –
pins with respect to VSS
Voltage on any Class A and VIN SR -1.0 – VDDP + 1.0 V whichever
dedicated input pin with or max. 4.3 is lower
respect to VSS
Voltage on any analog input VAIN -1.0 – VDDP + 1.0 V whichever
pin with respect to VAGND VAREF SR or max. 4.3 is lower
Input current on any pin IIN SR -10 – +10 mA
during overload condition
Absolute maximum sum of all IIN SR -25 – +25 mA
input circuit currents for one
port group during overload
condition1)
Absolute maximum sum of all IIN SR -100 – +100 mA
input circuit currents during
overload condition
1) The port groups are defined in Table 16.
Figure 6 explains the input voltage ranges of VIN and VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in “Pin Reliability in Overload”.
Data Sheet 28 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 6 Absolute Maximum Input Voltage Ranges
3.1.3 Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 13 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time is not exceeded
• “Operating Conditions” are met for
– pad supply levels (VDDP or VDDA)
– temperature
If a pin current is outside of the “Operating Conditions” but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery.
Data Sheet 29 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 13 Overload Parameters

Min. Typ. Max. Test Condition
Input current on any port pin IOV SR -5 – 5 mA

during overload condition
Absolute sum of all input IOVG SR – – 20 mA IOVx|, for all
circuit currents for one port IOVx  0 mA
group during overload – – 20 mA IOVx|, for all
condition1) IOVx  0 mA
Absolute sum of all input IOVS SR – – 80 mA IOVG
circuit currents during
overload condition
Figure 7 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Figure 7 Input Overload Current via ESD structures

Table 14 and Table 15 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as defined in the “Absolute Maximum
Ratings” must not be exceeded during overload.
Data Sheet 30 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 14 PN-Junction Characterisitics for positive Overload

Pad Type IOV = 5 mA, TJ = -40 °C IOV = 5 mA, TJ = 150 °C
A1 / A1+ VIN = VDDP + 1.0 V VIN = VDDP + 0.75 V
A2 VIN = VDDP + 0.7 V VIN = VDDP + 0.6 V
AN/DIG_IN VIN = VDDP + 1.0 V VIN = VDDP + 0.75 V
Table 15 PN-Junction Characterisitics for negative Overload

Pad Type IOV = 5 mA, TJ = -40 °C IOV = 5 mA, TJ = 150 °C
A1 / A1+ VIN = VSS - 1.0 V VIN = VSS - 0.75 V
A2 VIN = VSS - 0.7 V VIN = VSS - 0.6 V
AN/DIG_IN VIN = VDDP - 1.0 V VIN = VDDP - 0.75 V
Table 16 Port Groups for Overload and Short-Circuit Current Sum

Parameters
Group Pins
1 P0.[12:0], P3.[6:0]
2 P14.[15:0], P15.[9:2]
3 P2.[15:0], P5.[7:0]
4 P1.[15:0], P4.[1:0]
Data Sheet 31 V1.2, 2023-04

XMC4300
XMC4000 Family
3.1.4 Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and their basic
characteristics.
Table 17 Pad Driver and Pad Classes Overview

Class Power Type Sub-Class Speed Load Termination
Supply Grade
A 3.3 V LVTTL A1 6 MHz 100 pF No
I/O (e.g. GPIO)
A1+ 25 MHz 50 pF Series termination
(e.g. serial I/Os) recommended
A2 80 MHz 15 pF Series termination
(e.g. ext. Bus) recommended
Figure 8 Output Slopes with different Pad Driver Modes
Figure 8 is a qualitative display of the resulting output slope performance with different
output driver modes. The detailed input and output characteristics are listed in
“Input/Output Pins”.
Data Sheet 32 V1.2, 2023-04

XMC4300
XMC4000 Family
3.1.5 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC4300. All parameters specified in the following
sections refer to these operating conditions, unless noted otherwise.
Table 18 Operating Conditions Parameters

Ambient Temperature TA SR -40  85 °C Temp. Range F

-40  125 °C Temp. Range K
Digital supply voltage VDDP SR 3.131) 3.3 3.63 2) V
Core Supply Voltage VDDC 1) 1.3  V Generated
CC internally
Digital ground voltage VSS SR 0   V
2)
ADC analog supply VDDA SR 3.0 3.3 3.6 V
voltage
Analog ground voltage for VSSA SR -0.1 0 0.1 V
VDDA
Battery Supply Voltage for VBAT SR 1.953)  3.63 V When VDDP is
Hibernate Domain supplied VBAT
has to be
supplied as
well.
System Frequency fSYS SR   144 MHz
Short circuit current of ISC SR -5  5 mA
digital outputs
Absolute sum of short ISC_PG   20 mA
circuit currents per pin SR
group4)
Absolute sum of short ISC_D   100 mA
circuit currents of the SR
device
1) See also the Supply Monitoring thresholds, “Power-Up and Supply Monitoring”.
2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 s and the cumulated sum of the pulses does not exceed 1 h over lifetime.
3) To start the hibernate domain it is required that VBAT  2.1 V, for a reliable start of the oscillation of RTC_XTAL
in crystal mode it is required that VBAT  3.0 V.
Data Sheet 33 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2 DC Parameters
3.2.1 Input/Output Pins
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/output pins.
The Pull-up on the PORST pin is identical to the Pull-up on the standard digital
input/output pins.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19 Standard Pad Parameters

Parameter Symbol Values Unit Note / Test Condition
Min. Max.
Pin capacitance (digital CIO CC  10 pF
inputs/outputs)
1)
Pull-down current |IPDL| 150  A VIN  0.6  VDDP
SR  10 A 2)
VIN  0.36  VDDP
2)
Pull-Up current |IPUH|  10 A VIN  0.6  VDDP
SR 100  A 1)
VIN  0.36  VDDP
Input Hysteresis for HYSA 0.1   V
pads of all A classes3) CC VDDP
PORST spike filter tSF1 CC  10 ns
always blocked pulse
duration
PORST spike filter tSF2 CC 100  ns
pass-through pulse
duration
PORST pull-down |IPPD| 13  mA VIN  1.0 V
current CC
1) Current required to override the pull device with the opposite logic level (“force current”).
With active pull device, at load currents between force and keep current the input state is undefined.
2) Load current at which the pull device still maintains the valid logic level (“keep current”).
With active pull device, at load currents between force and keep current the input state is undefined.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
Data Sheet 34 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 9 Pull Device Input Characteristics

Figure 9 visualizes the input characteristics with an active internal pull device:
• in the cases “A” the internal pull device is overridden by a strong external driver;
• in the cases “B” the internal pull device defines the input logical state against a weak
external load.
Data Sheet 35 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 20 Standard Pads Class_A1

Min. Max. Test Condition
Input leakage current IOZA1 CC -500 500 nA 0 V  VIN  VDDP

Input high voltage VIHA1 SR 0.6  VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA1 SR -0.3 0.36  VDDP V
Output high voltage, VOHA1 VDDP - 0.4  V IOH  -400 A
POD1) = weak CC 2.4  V IOH  -500 A
Output high voltage, VDDP - 0.4  V IOH  -1.4 mA
POD1) = medium 2.4  V IOH  -2 mA
Output low voltage VOLA1  0.4 V IOL  500 A;
CC POD1) = weak
 0.4 V IOL  2 mA;
POD1) = medium
Fall time tFA1 CC  150 ns CL = 20 pF;
POD1) = weak
 50 ns CL = 50 pF;
POD1) = medium
Rise time tRA1 CC  150 ns CL = 20 pF;
POD1) = weak
 50 ns CL = 50 pF;
POD1) = medium
1) POD = Pin Out Driver
Table 21 Standard Pads Class_A1+

Input leakage current IOZA1+ CC -1 1 A 0 V  VIN  VDDP

Input high voltage VIHA1+ SR 0.6  VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA1+ SR -0.3 0.36 VDDP V
Data Sheet 36 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 21 Standard Pads Class_A1+

Output high voltage, VOHA1+ VDDP - 0.4  V IOH  -400 A
POD1) = weak CC 2.4  V IOH  -500 A
POD1) = medium 2.4  V IOH  -2 mA
POD1) = strong 2.4  V IOH  -2 mA
Output low voltage VOLA1+  0.4 V IOL  500 A;
CC POD1) = weak
 0.4 V IOL  2 mA;
POD1) = medium
 0.4 V IOL  2 mA;
POD1) = strong
Fall time tFA1+ CC  150 ns CL = 20 pF;
POD1) = weak
 50 ns CL = 50 pF;
POD1) = medium
 28 ns CL = 50 pF;
POD1) = strong;
edge = slow
 16 ns CL = 50 pF;
POD1) = strong;
edge = soft;
Rise time tRA1+ CC  150 ns CL = 20 pF;
POD1) = weak
 50 ns CL = 50 pF;
POD1) = medium
 28 ns CL = 50 pF;
POD1) = strong;
edge = slow
 16 ns CL = 50 pF;
POD1) = strong;
edge = soft
1) POD = Pin Out Driver
Data Sheet 37 V1.2, 2023-04

XMC4300
XMC4000 Family

Input Leakage current IOZA2 -6 6 A 0 V  VIN <

CC 0.5*VDDP - 1 V;
0.5*VDDP + 1 V
<VIN  VDDP
-3 3 A 0.5*VDDP - 1 V <
VIN < 0.5*VDDP
+1V
Input high voltage VIHA2 0.6  VDDP VDDP + 0.3 V max. 3.6 V
SR
Input low voltage VILA2 SR -0.3 0.36  V
VDDP
Output high voltage, VOHA2 VDDP - 0.4  V IOH  -400 A
POD = weak CC 2.4  V IOH  -500 A
POD = medium 2.4  V IOH  -2 mA
POD = strong 2.4  V IOH  -2 mA
Output low voltage, VOLA2  0.4 V IOL  500 A
POD = weak CC
Output low voltage,  0.4 V IOL  2 mA
POD = medium
Output low voltage,  0.4 V IOL  2 mA
POD = strong
Data Sheet 38 V1.2, 2023-04

XMC4300
XMC4000 Family

Fall time tFA2 CC  150 ns CL = 20 pF;
POD = weak
 50 ns CL = 50 pF;
POD = medium
 3.7 ns CL = 50 pF;
POD = strong;
edge = sharp
 7 ns CL = 50 pF;
POD = strong;
edge = medium
 16 ns CL = 50 pF;
POD = strong;
edge = soft
Rise time tRA2 CC  150 ns CL = 20 pF;
POD = weak
 50 ns CL = 50 pF;
POD = medium
 3.7 ns CL = 50 pF;
POD = strong;
edge = sharp
 7.0 ns CL = 50 pF;
POD = strong;
edge = medium
 16 ns CL = 50 pF;
POD = strong;
edge = soft
Data Sheet 39 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 23 HIB_IO Class_A1 special Pads

Input leakage current IOZHIB -500 500 nA 0 V  VIN  VBAT

CC
Input high voltage VIHHIB 0.6  VBAT VBAT + 0.3 V max. 3.6 V
SR
Input low voltage VILHIB -0.3 0.36  VBAT V
SR
Input Hysteresis for HYSHIB 0.1  VBAT  V VBAT  3.13 V
HIB_IO pins1) CC 0.06   V VBAT  3.13 V
VBAT
Output high voltage, VOHHIB VBAT - 0.4  V IOH  -1.4 mA
POD1) = medium CC
Output low voltage VOLHIB  0.4 V IOL  2 mA
CC
Fall time tFHIB CC  50 ns VBAT  3.13 V
CL = 50 pF
 100 ns VBAT  3.13 V
CL = 50 pF
Rise time tRHIB CC  50 ns VBAT  3.13 V
CL = 50 pF
 100 ns VBAT  3.13 V
CL = 50 pF
Data Sheet 40 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.2 Analog to Digital Converters (VADC)
characterization.
Table 24 VADC Parameters (Operating Conditions apply)

Analog reference voltage5) VAREF VAGND  VDDA  V

SR +1 0.051)
Analog reference ground5) VAGND VSSM -  VAREF - V
SR 0.05 1
Analog reference voltage VAREF - 1  VDDA  V
range2)5) VAGND 0.1
SR
Analog input voltage VAIN SR VAGND  VDDA V
Input leakage at analog IOZ1 CC -100  200 nA 0.03  VDDA 
inputs3) VAIN  0.97  VDDA
-500  100 nA 0 V  VAIN  0.03
 VDDA
-100  500 nA 0.97  VDDA
 VAIN  VDDA
Input leakage current at IOZ2 CC -1  1 A 0 V  VAREF
VAREF  VDDA
Input leakage current at IOZ3 CC -1  1 A 0 V  VAGND
VAGND  VDDA
Internal ADC clock fADCI CC 2  36 MHz VDDA = 3.3 V
Switched capacitance at CAINSW  4 6.5 pF
the analog voltage inputs4) CC
Total capacitance of an CAINTOT  12 20 pF
analog input CC
Switched capacitance at CAREFSW  15 30 pF
the positive reference CC
voltage input5)6)
Total capacitance of the CAREFTOT  20 40 pF
voltage reference inputs5) CC
Data Sheet 41 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 24 VADC Parameters (Operating Conditions apply)

Total Unadjusted Error TUE CC -4  4 LSB 12-bit resolution;
Differential Non-Linearity EADNL -3  3 LSB VDDA = 3.3 V;
Error8) CC VAREF = VDDA7)
8)
Gain Error EAGAIN -4  4 LSB
CC
Integral Non-Linearity8) EAINLCC -3  3 LSB
8)
Offset Error EAOFF -4  4 LSB
CC
RMS Noise9) ENRMS  1 210)11) LSB
CC
Worst case ADC VDDA IDDAA  1.5 2 mA during conversion
power supply current per CC VDDP = 3.6 V,
active converter TJ = 150 oC
Charge consumption on QCONV  30  pC 0 V  VAREF
VAREF per conversion5) CC  VDDA12)
ON resistance of the RAIN CC  600 1 200 Ohm
analog input path
ON resistance for the ADC RAIN7T 180 550 900 Ohm
test (pull down for AIN7) CC
Resistance of the RAREF  700 1 700 Ohm
reference voltage input CC
path
1) A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot).
2) If the analog reference voltage is below VDDA, then the ADC converter errors increase. If the reference voltage
is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset errors increase also by the factor 1/k.
3) The leakage current definition is a continuous function, as shown in figure ADCx Analog Inputs Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step function (see Figure 12).
4) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements, the voltage measured at AINx can deviate from VAREF/2.
5) Applies to AINx, when used as alternate reference input.
6) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead, smaller capacitances are successively switched to the reference voltage.
7) For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16.
Never less than ±1 LSB.
8) The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE.
Data Sheet 42 V1.2, 2023-04

XMC4300
XMC4000 Family
9) This parameter is valid for soldered devices and requires careful analog board design.
10) Resulting worst case combined error is arithmetic combination of TUE and ENRMS.
11) Value is defined for one sigma Gauss distribution.
12) The resulting current for a conversion can be calculated with IAREF = QCONV / tc.
The fastest 12-bit post-calibrated conversion of tc = 459 ns results in a typical average current of
IAREF = 65.4 μA.
Figure 10 VADC Reference Voltage Range

The power-up calibration of the VADC requires a maximum number of 4 352 fADCI cycles.
Data Sheet 43 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 11 VADC Input Circuits
Figure 12 VADC Analog Input Leakage Current
Data Sheet 44 V1.2, 2023-04

XMC4300
XMC4000 Family
Conversion Time
Table 25 Conversion Time (Operating Conditions apply)

Parameter Symbol Values Unit Note
Conversion tC CC 2  TADC + s N = 8, 10, 12 for
time (2 + N + STC + PC +DM)  TADCI N-bit conversion
TADC = 1 / fPERIPH
TADCI = 1 / fADCI
• STC defines additional clock cycles to extend the sample time

• PC adds two cycles if post-calibration is enabled
• DM adds one cycle for an extended conversion time of the MSB
Conversion Time Examples

System assumptions:
fADC = 144 MHz i.e. tADC = 6.9 ns, DIVA = 3, fADCI = 36 MHz i.e. tADCI = 27.8 ns
According to the given formulas the following minimum conversion times can be
achieved (STC = 0, DM = 0):
12-bit post-calibrated conversion (PC = 2):
tCN12C = (2 + 12 + 2)  tADCI + 2  tADC = 16  27.8 ns + 2  6.9 ns = 459 ns
12-bit uncalibrated conversion:
tCN12 = (2 + 12)  tADCI + 2  tADC = 14  27.8 ns + 2  6.9 ns = 403 ns
10-bit uncalibrated conversion:
8-bit uncalibrated:
Data Sheet 45 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.3 Digital to Analog Converters (DAC)

characterization.
Table 26 DAC Parameters (Operating Conditions apply)

RMS supply current IDD CC  2.5 4 mA per active DAC

channel,
without load
currents of DAC
outputs
Resolution RES CC  12  Bit
Update rate fURATE_ACC  2 Msam data rate, where
ple/s DAC can follow
64 LSB code jumps
to ± 1LSB accuracy
Update rate fURATE_F CC  5 Msam data rate, where
ple/s DAC can follow
64 LSB code jumps
to ± 4 LSB accuracy
Settling time tSETTLE CC  1 2 s at full scale jump,
output voltage
reaches target
value ± 20 LSB
Slew rate SR CC 2 5  V/s
Minimum output VOUT_MIN  0.3  V code value
voltage CC unsigned: 000H;
signed: 800H
Maximum output VOUT_MAX  2.5  V code value
voltage CC unsigned: FFFH;
signed: 7FFH
Integral non-linearity INL CC -5.5 ±2.5 5.5 LSB RL  5 kOhm,
CL  50 pF
Differential non- DNL CC -2 ±1 2 LSB RL  5 kOhm,
linearity CL  50 pF
Offset error EDOFF CC ±20 mV
Data Sheet 46 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 26 DAC Parameters (Operating Conditions apply) (cont’d)

Gain error EDG_IN CC -6.5 -1.5 3 %
Startup time tSTARTUP CC  15 30 s time from output
enabling till code
valid ±16 LSB
3dB Bandwidth of fC1 CC 2.5 5  MHz verified by design
Output Buffer
Output sourcing IOUT_SOURCE  -30  mA
current CC
Output sinking IOUT_SINK  0.6  mA
current CC
Output resistance ROUT CC  50  Ohm
Load resistance RL SR 5   kOhm
Load capacitance CL SR   50 pF
Signal-to-Noise SNR CC  70  dB examination
Ratio bandwidth < 25 kHz
Total Harmonic THD CC  70  dB examination
Distortion bandwidth < 25 kHz
Power Supply PSRR CC  56  dB to VDDA
Rejection Ratio verified by design
Conversion Calculation
Unsigned:
DACxDATA = 4095  (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN)
Signed:
DACxDATA = 4095  (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048
Data Sheet 47 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 13 DAC Conversion Examples
Data Sheet 48 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.4 Out-of-Range Comparator (ORC)

The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
analog reference1) (VAREF) on selected input pins (GxORCy) and generates a service
request trigger (GxORCOUTy).
characterization.
The parameters in Table 27 apply for the maximum reference voltage
VAREF = VDDA + 50 mV.
Table 27 ORC Parameters (Operating Conditions apply)

Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
DC Switching Level VODC CC 100 125 210 mV VAIN  VAREF + VODC
Hysteresis VOHYS CC 50  VODC mV
Detection Delay of a tODD CC 50  450 ns VAIN VAREF + 210 mV
persistent 45  105 ns VAIN VAREF + 400 mV
Overvoltage
Always detected tOPDD CC 440   ns VAIN VAREF + 210 mV
Overvoltage Pulse 90   ns VAIN VAREF + 400 mV
Never detected tOPDN CC   45 ns VAIN VAREF + 210 mV
Overvoltage Pulse   30 ns VAIN VAREF + 400 mV
Release Delay tORD CC 65  105 ns VAIN VAREF
Enable Delay tOED CC  100 200 ns
1) Always the standard VADC reference, alternate references do not apply to the ORC.
Data Sheet 49 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 14 GxORCOUTy Trigger Generation
Figure 15 ORC Detection Ranges
Data Sheet 50 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.5 Die Temperature Sensor
The Die Temperature Sensor (DTS) measures the junction temperature TJ.
characterization.
Table 28 Die Temperature Sensor Parameters

Temperature sensor range TSR SR -40  150 °C

Linearity Error TLE CC  ±1  °C per TJ  30 °C
(to the below defined formula)
Offset Error TOE CC  ±6  °C TOE = TJ - TDTS
VDDP  3.3 V1)
Measurement time tM CC   100 s
Start-up time after reset tTSST SR   10 s
inactive
1) At VDDP_max = 3.63 V the typical offset error increases by an additional TOE = ±1 °C.
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
Temperature TDTS = (RESULT - 605) / 2.05 [°C]
This formula and the values defined in Table 28 apply with the following calibration
values:
• DTSCON.BGTRIM = 8H
• DTSCON.REFTRIM = 4H
Data Sheet 51 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.6 USB OTG Interface DC Characteristics

The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.
characterization.
Table 29 USB OTG VBUS and ID Parameters (Operating Conditions apply)

VBUS input voltage VIN CC 0.0  5.25 V

range
A-device VBUS valid VB1 CC 4.4   V
threshold
A-device session valid VB2 CC 0.8  2.0 V
threshold
B-device session valid VB3 CC 0.8  4.0 V
threshold
B-device session end VB4 CC 0.2  0.8 V
threshold
VBUS input RVBUS_IN 40  100 kOhm
resistance to ground CC
B-device VBUS pull- RVBUS_PU 281   Ohm Pull-up voltage =
up resistor CC 3.0 V
B-device VBUS pull- RVBUS_PD 656   Ohm
down resistor CC
USB.ID pull-up RUID_PU 14  25 kOhm
resistor CC
VBUS input current IVBUS_IN   150 A 0 V  VIN  5.25 V:
CC TAVG = 1 ms
Data Sheet 52 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 30 USB OTG Data Line (USB_DP, USB_DM) Parameters (Operating

Conditions apply)
Input low voltage VIL SR   0.8 V

Input high voltage VIH SR 2.0   V
(driven)
Input high voltage VIHZ SR 2.7  3.6 V
(floating) 1)
Differential input VDIS CC 0.2   V
sensitivity
Differential common VCM CC 0.8  2.5 V
mode range
Output low voltage VOL CC 0.0  0.3 V 1.5 kOhm pull-
up to 3.6 V
Output high voltage VOH CC 2.8  3.6 V 15 kOhm pull-
down to 0 V
DP pull-up resistor (idle RPUI CC 900  1 575 Ohm
bus)
DP pull-up resistor RPUA CC 1 425  3 090 Ohm
(upstream port
receiving)
DP, DM pull-down RPD CC 14.25  24.8 kOhm
resistor
Input impedance DP, ZINP CC 300   kOhm 0 V  VIN  VDDP
DM
Driver output resistance ZDRV CC 28  44 Ohm
DP, DM
1) Measured at A-connector with 1.5 kOhm ± 5% to 3.3 V ± 0.3 V connected to USB_DP or USB_DM and at B-
connector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.
Data Sheet 53 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.7 Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative

resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
characterization.
The oscillator pins can be operated with an external crystal (see Figure 16) or in direct
input mode (see Figure 17).
Figure 16 Oscillator in Crystal Mode
Data Sheet 54 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 17 Oscillator in Direct Input Mode
Data Sheet 55 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 31 OSC_XTAL Parameters

Input frequency fOSC SR 4  40 MHz Direct Input Mode

selected
4  25 MHz External Crystal
Mode selected
Oscillator start-up tOSCS   10 ms
time1)2) CC
Input voltage at XTAL1 VIX SR -0.5  VDDP + V
0.5
Input amplitude (peak- VPPX SR 0.4   VDDP + V
to-peak) at XTAL12)3) VDDP 1.0
Input high voltage at VIHBXSR 1.0  VDDP + V
XTAL14) 0.5
Input low voltage at VILBX SR -0.5  0.4 V
XTAL14)
Input leakage current at IILX1 CC -100  100 nA Oscillator power
XTAL1 down
0 V  VIX  VDDP
1) tOSCS is defined from the moment the oscillator is enabled wih SCU_OSCHPCTRL.MODE until the oscillations
reach an amplitude at XTAL1 of 0.4 * VDDP.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) If the shaper unit is enabled and not bypassed.
4) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
Data Sheet 56 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 32 RTC_XTAL Parameters

Input frequency fOSC SR  32.768  kHz

Oscillator start-up tOSCS   5 s
time1)2)3) CC
Input voltage at VIX SR -0.3  VBAT + V
RTC_XTAL1 0.3
Input amplitude (peak- VPPX SR 0.4   V
to-peak) at
RTC_XTAL12)4)
Input high voltage at VIHBXSR 0.6   VBAT + V
RTC_XTAL15) VBAT 0.3
Input low voltage at VILBX SR -0.3  0.36  V
RTC_XTAL15) VBAT
Input Hysteresis for VHYSX 0.1   V 3.0 V 
RTC_XTAL15)6) CC VBAT VBAT < 3.6 V
0.03   V VBAT < 3.0 V
VBAT
Input leakage current at IILX1 CC -100  100 nA Oscillator power
RTC_XTAL1 down
0 V  VIX  VBAT
1) tOSCS is defined from the moment the oscillator is enabled by the user with SCU_OSCULCTRL.MODE until the
oscillations reach an amplitude at RTC_XTAL1 of 400 mV.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) For a reliable start of the oscillation in crystal mode it is required that VBAT  3.0 V. A running oscillation is
maintained across the full VBAT voltage range.
4) If the shaper unit is enabled and not bypassed.
5) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
Data Sheet 57 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.8 Power Supply Current

The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
characterization.
If not stated otherwise, the operating conditions for the parameters in the following table
are:
VDDP = 3.3 V, TA = 25 oC
Table 33 Power Supply Parameters

Active supply current1)11) IDDPA CC  135  mA 144 / 144 / 144

Peripherals enabled  125  144 / 72 / 72
Frequency:
fCPU / fPERIPH / fCCU in MHz  97  72 / 72 / 144
 80  24 / 24 / 24
 68  1/1/1
Active supply current IDDPA CC  108  mA 144 / 144 / 144
Code execution from RAM  98  144 / 72 / 72
Flash in Sleep mode
Active supply current2) IDDPA CC  86  mA 144 / 144 / 144
Peripherals disabled  85  144 / 72 / 72
Frequency:
 55  24 / 24 / 24
 50  1/1/1
Sleep supply current3) IDDPS CC  127  mA 144 / 144 / 144
Peripherals enabled  115  144 / 72 / 72
Frequency:
 57  24 / 24 / 24
 47  1/1/1
fCPU / fPERIPH / fCCU in kHz  48  100 / 100 / 100
Data Sheet 58 V1.2, 2023-04

XMC4300
XMC4000 Family

Sleep supply current4) IDDPS CC  77  mA 144 / 144 / 144
Peripherals disabled  76  144 / 72 / 72
Frequency:
 53  24 / 24 / 24
 46  1/1/1
fCPU / fPERIPH / fCCU in kHz  47  100 / 100 / 100
Deep Sleep supply IDDPD CC  11  mA 24 / 24 / 24
current5)  7.0  4/4/4
Flash in Sleep mode
Frequency:  6.6  1/1/1
fCPU / fPERIPH / fCCU in MHz
fCPU / fPERIPH / fCCU in kHz  7.6  100 / 100 / 100
6)
Hibernate supply current IDDPH CC  8.7  A VBAT = 3.3 V

RTC on7)  6.5  VBAT = 2.4 V
 5.7  VBAT = 2.0 V
Hibernate supply current IDDPH CC  8.0  A VBAT = 3.3 V
RTC off8)  6.0  VBAT = 2.4 V
 5.0  VBAT = 2.0 V
Hibernate off9) IDDPH CC  4.4  A VBAT = 3.3 V
 3.5  VBAT = 2.4 V
 3.1  VBAT = 2.0 V
Worst case active supply IDDPA CC   250 mA VDDP = 3.6 V,
current10) 11)
TJ = 150 oC
VDDA power supply current IDDA CC   12) mA
IDDP current at PORST Low IDDP_PORST  5 10 mA VDDP = 3.3 V,
CC TJ = 25 oC
 13 55 mA VDDP = 3.6 V,
TJ = 150 oC
Power Dissipation PDISS CC   1.4 W VDDP = 3.6 V,
TJ = 150 oC
Data Sheet 59 V1.2, 2023-04

XMC4300
XMC4000 Family

Wake-up time from Sleep to tSSA CC  6  cycles
Active mode
Wake-up time from Deep    ms Defined by the
Sleep to Active mode wake-up of the
Flash module,
see “Flash
Memory
Parameters”
Wake-up time from    ms Wake-up via
Hibernate mode power-on reset
event, see
“Power-Up
and Supply
Monitoring”
1) CPU executing code from Flash, all peripherals idle.
2) CPU executing code from Flash.
3) CPU in sleep, all peripherals idle, Flash in Active mode.
4) CPU in sleep, Flash in Active mode.
5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM.
6) To wake-up the Flash from its Sleep mode, fCPU  1 MHz is required.
7) OSC_ULP operating with external crystal on RTC_XTAL
8) OSC_ULP off, Hibernate domain operating with OSC_SI clock
9) VBAT supplied, but Hibernate domain not started; for example state after factory assembly
10) Test Power Loop: fSYS = 144 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer
mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in
500kHz internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE,
DTS measurements and FPU calculations.
The power consumption of each customer application will most probably be lower than this value, but must be
evaluated separately.
11) IDDP decreases typically by approximately 5 mA when fSYS decreases by 10 MHz, at constant TJ
12) Sum of currents of all active converters (ADC and DAC)
Data Sheet 60 V1.2, 2023-04

XMC4300
XMC4000 Family
Peripheral Idle Currents

Default test conditions:
• fsys and derived clocks at 144 MHz
• VDDP = 3.3 V, Ta =25 °C
• all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit
of the SCU)
• the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control
Unit of the SCU
• no I/O activity
The given values are a result of differential measurements with asserted and deasserted
peripheral reset as well as disabled and enabled clock of the peripheral under test.
The tested peripheral is left in the state after the peripheral reset is deasserted, no further
initialisation or configuration is done. E.g. no timer is running in the CCUs, no
communication active in the USICs, etc.
Table 34 Peripheral Idle Currents

PORTS IPER CC  0.3  mA

FCE
WDT
MultiCAN   1.0 
ERU
LEDTSCU0
ETH
CCU4x1), CCU8x1)
DAC (digital)2)  1.3 
USICx  3.0 
SDMMC
VADC (digital)2)  4.5 
DMA0, USB, EtherCAT  6.0 
1) Enabling the fCCU clock for the CCU4x/CCU8x modules adds approximately IPER = 4.8 mA, disregarding which
and how many of those peripherals are enabled.
2) The current consumption of the analog components are given in the dedicated Data Sheet sections of the
respective peripheral.
Data Sheet 61 V1.2, 2023-04

XMC4300
XMC4000 Family
3.2.9 Flash Memory Parameters
characterization.
Table 35 Flash Memory Parameters

Erase Time per 256 tERP CC  5 5.5 s

Kbyte Sector
Erase Time per 64 Kbyte tERP CC  1.2 1.4 s
Sector
Erase Time per 16 Kbyte tERP CC  0.3 0.4 s
Logical Sector
Program time per page1) tPRP CC  5.5 11 ms
Erase suspend delay tFL_ErSusp   15 ms
CC
Wait time after margin tFL_Margin 10   s
change Del CC
Wake-up time tWU CC   270 s

Read access time ta CC 22   ns For operation
with 1 / fCPU < ta
wait states must
be configured2)
Data Retention Time, tRET CC 20   years Max. 1000
Physical Sector3)4) erase/program
cycles
Data Retention Time, tRETL CC 20   years Max. 100
Logical Sector3)4) erase/program
cycles
Data Retention Time, tRTU CC 20   years Max. 4
User Configuration Block erase/program
(UCB)3)4) cycles per UCB
Endurance on 64 Kbyte NEPS4 10000   cycles Cycling
Physical Sector PS4 CC distributed over
life time5)
Data Sheet 62 V1.2, 2023-04

XMC4300
XMC4000 Family
1) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes an additional time of 5.5 ms.
2) The following formula applies to the wait state configuration: FCON.WSPFLASH  (1 / fCPU)  ta.
3) Storage and inactive time included.
4) Values given are valid for an average weighted junction temperature of TJ = 110°C.
5) Only valid with robust EEPROM emulation algorithm, equally cycling the logical sectors. For more details see
the Reference Manual.
Data Sheet 63 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3 AC Parameters
3.3.1 Testing Waveforms
Figure 18 Rise/Fall Time Parameters
Figure 19 Testing Waveform, Output Delay
Figure 20 Testing Waveform, Output High Impedance
Data Sheet 64 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.2 Power-Up and Supply Monitoring

PORST is always asserted when VDDP and/or VDDC violate the respective thresholds.
characterization.
Figure 21 PORST Circuit
Table 36 Supply Monitoring Parameters

Digital supply voltage reset VPOR CC 2.791)  3.052) V 3)
threshold
Core supply voltage reset VPV CC   1.17 V
threshold
VDDP voltage to ensure VDDPPA  1.0  V
defined pad states CC
4)
PORST rise time tPR SR   2 s
Startup time from power-on tSSW CC  2.5 3.5 ms Time to the first
reset with code execution user code
from Flash instruction
VDDC ramp up time tVCR CC  550  s Ramp up after
power-on or
after a reset
triggered by a
violation of
VPOR or VPV
1) Minimum threshold for reset assertion.
Data Sheet 65 V1.2, 2023-04

XMC4300
XMC4000 Family
2) Maximum threshold for reset deassertion.
3) The VDDP monitoring has a typical hysteresis of VPORHYS = 180 mV.
4) If tPR is not met, low spikes on PORST may be seen during start up (e.g. reset pulses generated by the supply
monitoring due to a slow ramping VDDP).
Figure 22 Power-Up Behavior
Data Sheet 66 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.3 Power Sequencing

While starting up and shutting down as well as when switching power modes of the
system it is important to limit the current load steps. A typical cause for such load steps
is changing the CPU frequency fCPU. Load steps exceeding the below defined values
may cause a power on reset triggered by the supply monitor.
characterization.
Table 37 Power Sequencing Parameters

Positive Load Step Current IPLS SR -  50 mA Load increase

on VDDP
t  10 ns
Negative Load Step INLS SR -  150 mA Load decrease
Current on VDDP
t  10 ns
VDDC Voltage Over- VLS CC -  ±100 mV For maximum
/ Undershoot from Load positive or
Step negative load
step
Positive Load Step Settling tPLSS SR 50  - s
Time
Negative Load Step tNLSS SR 100  - s
Settling Time
External Buffer Capacitor CEXT SR - 10 - F In addition
on VDDC C = 100 nF
capacitor on
each VDDC pin
Positive Load Step Examples

System assumptions:
fCPU = fSYS, target frequency fCPU = 144 MHz, main PLL fVCO = 288 MHz, stepping done
by K2 divider, tPLSS between individual steps:
24 MHz - 48 MHz - 72 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 4 - 3 - 2)
24 MHz - 48 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 3 - 2)
24 MHz - 72 MHz - 144 MHz (K2 steps 12 - 4 - 2)
Data Sheet 67 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.4 Phase Locked Loop (PLL) Characteristics

characterization.
Main and USB PLL
Table 38 PLL Parameters

Accumulated Jitter DP CC   ±5 ns accumulated

over 300 cycles
fSYS = 144 MHz
Duty Cycle1) DDC CC 46 50 54 % Low pulse to
total period,
assuming an
ideal input clock
source
PLL base frequency fPLLBASE 30  140 MHz
CC
VCO input frequency fREF CC 4  16 MHz
VCO frequency range fVCO CC 260  520 MHz
PLL lock-in time tL CC   400 s
1) 50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.
Data Sheet 68 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.5 Internal Clock Source Characteristics

characterization.
Fast Internal Clock Source
Table 39 Fast Internal Clock Parameters

Nominal frequency fOFINC  36.5  MHz not calibrated

CC  24  MHz calibrated
Accuracy fOFI -0.5  0.5 % automatic
CC calibration1)2)
-15  15 % factory
calibration,
VDDP = 3.3 V
-25  25 % no calibration,
VDDP = 3.3 V
-7  7 % Variation over
voltage range3)
3.13 V  VDDP 
3.63 V
Start-up time tOFIS CC  50  s
1) Error in addition to the accuracy of the reference clock.
2) Automatic calibration compensates variations of the temperature and in the VDDP supply voltage.
3) Deviations from the nominal VDDP voltage induce an additional error to the uncalibrated and/or factory
calibrated oscillator frequency.
Data Sheet 69 V1.2, 2023-04

XMC4300
XMC4000 Family
Slow Internal Clock Source

Table 40 Slow Internal Clock Parameters
Nominal frequency fOSI CC  32.768  kHz

Accuracy fOSI -4  4 % VBAT = const.
CC 0 °C  TA 
85 °C
-5  5 % VBAT = const.
TA  0 °C or
TA  85 °C
-5  5 % 2.4 V  VBAT,
TA = 25 °C
-10  10 % 1.95 V 
VBAT < 2.4 V,
TA = 25 °C
Start-up time tOSIS CC  50  s
Data Sheet 70 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.6 JTAG Interface Timing

The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
characterization.
Note: Operating conditions apply.
Table 41 JTAG Interface Timing Parameters

TCK clock period t1 SR 25 – – ns

TCK high time t2 SR 10 – – ns
TCK low time t3 SR 10 – – ns
TCK clock rise time t4 SR – – 4 ns
TCK clock fall time t5 SR – – 4 ns
TDI/TMS setup t6 SR 6 – – ns
to TCK rising edge
TDI/TMS hold t7 SR 6 – – ns
after TCK rising edge
TDO valid after TCK falling t8 CC – – 13 ns CL = 50 pF
edge1) (propagation delay) 3 – – ns CL = 20 pF
TDO hold after TCK falling t18 CC 2 – – ns
edge1)
TDO high imped. to valid t9 CC – – 14 ns CL = 50 pF
from TCK falling edge1)2)
TDO valid to high imped. t10 CC – – 13.5 ns CL = 50 pF
from TCK falling edge1)
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet 71 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 23 Test Clock Timing (TCK)
Figure 24 JTAG Timing
Data Sheet 72 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.7 Serial Wire Debug Port (SW-DP) Timing

The following parameters are applicable for communication through the SW-DP
interface.
characterization.
Note: Operating conditions apply.
Table 42 SWD Interface Timing Parameters (Operating Conditions apply)

SWDCLK clock period tSC SR 25 – – ns CL = 30 pF

40 – – ns CL = 50 pF
SWDCLK high time t1 SR 10 – 500000 ns
SWDCLK low time t2 SR 10 – 500000 ns
SWDIO input setup t3 SR 6 – – ns
to SWDCLK rising edge
SWDIO input hold t4 SR 6 – – ns
after SWDCLK rising edge
SWDIO output valid time t5 CC – – 17 ns CL = 50 pF
after SWDCLK rising edge – – 13 ns CL = 30 pF
SWDIO output hold time t6 CC 3 – – ns
from SWDCLK rising edge
Figure 25 SWD Timing
Data Sheet 73 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.8 Peripheral Timing
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing

The following parameters are applicable for a USIC channel operated in SSC mode.
characterization.
Table 43 USIC SSC Master Mode Timing

SCLKOUT master clock tCLK CC 33.3   ns

period
Slave select output SELO t1 CC tPB -   ns
active to first SCLKOUT 6.51)
transmit edge
Slave select output SELO t2 CC tPB -   ns
inactive after last 8.51)
SCLKOUT receive edge
Data output DOUT[3:0] t3 CC -6  8 ns
valid time
Receive data input t4 SR 23   ns
DX0/DX[5:3] setup time to
SCLKOUT receive edge
Data input DX0/DX[5:3] t5 SR 1   ns
hold time from SCLKOUT
receive edge
1) tPB = 1 / fPB
Data Sheet 74 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 44 USIC SSC Slave Mode Timing

Values Note /
Parameter Symbol Unit
DX1 slave clock period tCLK SR 66.6   ns
Select input DX2 setup to
first clock input DX1 transmit t10 SR 3   ns
edge1)
Select input DX2 hold after
last clock input DX1 receive t11 SR 4   ns
edge1)
Receive data input
DX0/DX[5:3] setup time to t12 SR 6   ns
shift clock receive edge1)
Data input DX0/DX[5:3] hold
time from clock input DX1 t13 SR 4   ns
receive edge1)
Data output DOUT[3:0] valid
t14 CC 0  24 ns
time
1) This input timing is valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet 75 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 26 USIC - SSC Master/Slave Mode Timing

Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
Data Sheet 76 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.8.2 Inter-IC (IIC) Interface Timing

The following parameters are applicable for a USIC channel operated in IIC mode.
characterization.
Table 45 USIC IIC Standard Mode Timing1)

Fall time of both SDA and t1 - - 300 ns

SCL CC/SR
Rise time of both SDA and t2 - - 1000 ns
SCL CC/SR
Data hold time t3 0 - - μs
CC/SR
Data set-up time t4 250 - - ns
CC/SR
LOW period of SCL clock t5 4.7 - - μs
CC/SR
HIGH period of SCL clock t6 4.0 - - μs
CC/SR
Hold time for (repeated) t7 4.0 - - μs
START condition CC/SR
Set-up time for repeated t8 4.7 - - μs
Set-up time for STOP t9 4.0 - - μs
condition CC/SR
Bus free time between a t10 4.7 - - μs
STOP and START CC/SR
condition
Capacitive load for each Cb SR - - 400 pF
bus line
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Data Sheet 77 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 46 USIC IIC Fast Mode Timing1)

Fall time of both SDA and t1 20 + - 300 ns

SCL CC/SR 0.1*Cb
2)
Rise time of both SDA and t2 20 + - 300 ns

SCL CC/SR 0.1*Cb
2)
Data hold time t3 0 - - μs

CC/SR
Data set-up time t4 100 - - ns
CC/SR
LOW period of SCL clock t5 1.3 - - μs
CC/SR
HIGH period of SCL clock t6 0.6 - - μs
CC/SR
Hold time for (repeated) t7 0.6 - - μs
Set-up time for repeated t8 0.6 - - μs
Set-up time for STOP t9 0.6 - - μs
condition CC/SR
Bus free time between a t10 1.3 - - μs
STOP and START CC/SR
condition
Capacitive load for each Cb SR - - 400 pF
bus line
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet 78 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 27 USIC IIC Stand and Fast Mode Timing
3.3.8.3 Inter-IC Sound (IIS) Interface Timing

The following parameters are applicable for a USIC channel operated in IIS mode.
characterization.
Table 47 USIC IIS Master Transmitter Timing

Clock period t1 CC 33.3   ns

Clock high time t2 CC 0.35 x   ns
t1min
Clock low time t3 CC 0.35 x   ns
t1min
Hold time t4 CC 0   ns
Clock rise time t5 CC   0.15 x ns
t1min
Data Sheet 79 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 28 USIC IIS Master Transmitter Timing
Table 48 USIC IIS Slave Receiver Timing

Clock period t6 SR 66.6   ns

Clock high time t7 SR 0.35 x   ns
t6min
Clock low time t8 SR 0.35 x   ns
t6min
Set-up time t9 SR 0.2 x   ns
t6min
Hold time t10 SR 0   ns
Figure 29 USIC IIS Slave Receiver Timing
Data Sheet 80 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.8.4 SDMMC Interface Timing
characterization.
Note: Operating Conditions apply, total external capacitive load CL = 40 pF.
AC Timing Specifications (Full-Speed Mode)
Table 49 SDMMC Timing for Full-Speed Mode

Parameter Symbol Values Unit Note/ Test
Min. Max. Condition
Clock frequency in full speed fpp CC 0 24 MHz

transfer mode (1/tpp)
Clock cycle in full speed tpp CC 40  ns
transfer mode
Clock low time tWL CC 10  ns
Clock high time tWH CC 10  ns
Clock rise time tTLH CC  10 ns
Clock fall time tTHL CC  10 ns
Inputs setup to clock rising tISU_F SR 2  ns
edge
Inputs hold after clock rising tIH_F SR 2  ns
edge
Outputs valid time in full speed tODLY_F CC  10 ns
mode
Outputs hold time in full speed tOH_F CC 0  ns
mode
Data Sheet 81 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 50 SD Card Bus Timing for Full-Speed Mode1)

Min. Max. Condition
SD card input setup time tISU 5  ns

SD card input hold time tIH 5  ns
SD card output valid time tODLY  14 ns
SD card output hold time tOH 0  ns
1) Reference card timing values for calculation examples. Not subject to production test and not characterized.
Full-Speed Output Path (Write)
Figure 30 Full-Speed Output Path
Data Sheet 82 V1.2, 2023-04

XMC4300
XMC4000 Family
Full-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
No clock delay:
(1)
t ODLY_F + t DATA_DELAY + t TAP_DELAY + t ISU  t WL
With clock delay:

(2)
t ODLY_F + t DATA_DELAY + t TAP_DELAY + t ISU  t WL + t CLK_DELAY
(3)
t DATA_DELAY + t TAP_DELAY + t WL  t PP + t CLK_DELAY – t ISU – t ODLY_F
t DATA_DELAY + t TAP_DELAY + 20  40 + t CLK_DELAY – 5 – 10
t DATA_DELAY  5 + t CLK_DELAY – t TAP_DELAY
The data can be delayed versus clock up to 5 ns in ideal case of tWL= 20 ns.
Full-Speed Write Meeting Hold (Minimum Delay)

(4)
t CLK_DELAY  t WL + t OH_F + t DATA_DELAY + t TAP_DELAY – t IH
t CLK_DELAY  20 + t DATA_DELAY + t TAP_DELAY – 5
t DATA_DELAY  15 + t CLK_DELAY + t TAP_DELAY
The clock can be delayed versus data up to 18.2 ns (external delay line) in ideal case of
tWL= 20 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
Data Sheet 83 V1.2, 2023-04

XMC4300
XMC4000 Family
Full-Speed Input Path (Read)
Figure 31 Full-Speed Input Path
Full-Speed Read Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(5)
t CLK_DELAY + t DATA_DELAY + t TAP_DELAY + t ODLY + t ISU_F  0.5  t pp
t CLK_DELAY + t DATA_DELAY  0.5  t pp – t ODLY – t ISU_F – t TAP_DELAY
t CLK_DELAY + t DATA_DELAY  20 – 14 – 2 – t TAP_DELAY
t CLK_DELAY + t DATA_DELAY  4 – t TAP_DELAY
The data + clock delay can be up to 4 ns for a 40 ns clock cycle.
Data Sheet 84 V1.2, 2023-04

XMC4300
XMC4000 Family
Full-Speed Read Meeting Hold (Minimum Delay)

(6)
t CLK_DELAY + t OH + t DATA_DELAY + t TAP_DELAY  t IH_F
t CLK_DELAY + t DATA_DELAY  t IH_F – t OH – t TAP_DELAY
t CLK_DELAY + t DATA_DELAY  2 – t TAP_DELAY
The data + clock delay must be greater than 2 ns if tTAP_DELAY is not used.
If the tTAP_DELAY is programmed to at least 2 ns, the data + clock delay must be greater
than 0 ns (or less). This is always fulfilled.
AC Timing Specifications (High-Speed Mode)
Table 51 SDMMC Timing for High-Speed Mode

Min. Max. Condition
Clock frequency in high speed fpp CC 0 48 MHz

transfer mode (1/tpp)
Clock cycle in high speed tpp CC 20  ns
transfer mode
Clock low time tWL CC 7  ns
Clock high time tWH CC 7  ns
Clock rise time tTLH CC  3 ns
Clock fall time tTHL CC  3 ns
Inputs setup to clock rising tISU_H SR 2  ns
edge
Inputs hold after clock rising tIH_H SR 2  ns
edge
Outputs valid time in high tODLY_H CC  14 ns
speed mode
Outputs hold time in high tOH_H CC 2  ns
speed mode
Data Sheet 85 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 52 SD Card Bus Timing for High-Speed Mode1)

Min. Max. Condition
SD card input setup time tISU 6  ns

SD card input hold time tIH 2  ns
SD card output valid time tODLY  14 ns
SD card output hold time tOH 2.5  ns
1) Reference card timing values for calculation examples. Not subject to production test and not characterized.
High-Speed Output Path (Write)
Figure 32 High-Speed Output Path
Data Sheet 86 V1.2, 2023-04

XMC4300
XMC4000 Family
High-Speed Write Meeting Setup (Maximum Delay)

No clock delay:
(7)
t ODLY_H + t DATA_DELAY + t TAP_DELAY + t ISU  t WL
With clock delay:

(8)
t ODLY_H + t DATA_DELAY + t TAP_DELAY + t ISU  t WL + t CLK_DELAY
(9)
t DATA_DELAY + t TAP_DELAY – t CLK_DELAY  t WL – t ISU – t ODLY_H
t DATA_DELAY – t CLK_DELAY  t WL – t ISU – t ODLY_H – t TAP_DELAY
t DATA_DELAY – t CLK_DELAY  10 – 6 – 14 – t TAP_DELAY
t DATA_DELAY – t CLK_DELAY  – 10 – t TAP_DELAY
The data delay is less than the clock delay by at least 10 ns in the ideal case where tWL=
10 ns.
High-Speed Write Meeting Hold (Minimum Delay)

(10)
t CLK_DELAY  t WL + t OH_H + t DATA_DELAY + t TAP_DELAY – t IH
t CLK_DELAY – t DATA_DELAY  t WL + t OH_H + t TAP_DELAY – t IH
t CLK_DELAY – t DATA_DELAY  10 + 2 + t TAP_DELAY – 2
t CLK_DELAY – t DATA_DELAY  10 + t TAP_DELAY
Data Sheet 87 V1.2, 2023-04

XMC4300
XMC4000 Family
The clock can be delayed versus data up to 13.2 ns (external delay line) in ideal case of
tWL= 10 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
High-Speed Input Path (Read)
Figure 33 High-Speed Input Path
High-Speed Read Meeting Setup (Maximum Delay)

(11)
t CLK_DELAY + t DATA_DELAY + t TAP_DELAY + t ODLY + t ISU_H  t pp
t CLK_DELAY + t DATA_DELAY  t pp – t ODLY – t ISU_H – t TAP_DELAY
t CLK_DELAY + t DATA_DELAY  20 – 14 – 2 – t TAP_DELAY
t CLK_DELAY + t DATA_DELAY  4 – t TAP_DELAY
The data + clock delay can be up to 4 ns for a 20 ns clock cycle.
Data Sheet 88 V1.2, 2023-04

XMC4300
XMC4000 Family
High-Speed Read Meeting Hold (Minimum Delay)

(12)
t CLK_DELAY + t OH + t DATA_DELAY + t TAP_DELAY  t IH_H
t CLK_DELAY + t DATA_DELAY  t IH_H – t OH – t TAP_DELAY
t CLK_DELAY + t DATA_DELAY  2 – 2.5 – t TAP_DELAY
t CLK_DELAY + t DATA_DELAY  – 0.5 – t TAP_DELAY
The data + clock delay must be greater than -0.5 ns for a 20 ns clock cycle. This is always
fulfilled.
3.3.9 USB Interface Characteristics

The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.
characterization.
Table 53 USB Timing Parameters (operating conditions apply)

Rise time tR CC 4 – 20 ns CL = 50 pF
Fall time tF CC 4 – 20 ns CL = 50 pF
Rise/Fall time matching tR/tF CC 90 – 111.11 % CL = 50 pF
Crossover voltage VCRS CC 1.3 – 2.0 V CL = 50 pF
Data Sheet 89 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 34 USB Signal Timing
3.3.10 Ethernet Interface (ETH) Characteristics

For proper operation of the Ethernet Interface it is required that fSYS  100 MHz.
characterization.
3.3.10.1 ETH Measurement Reference Points
Figure 35 ETH Measurement Reference Points
Data Sheet 90 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.10.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 54 ETH Management Signal Timing Parameters

ETH_MDC period t1 CC 400 – – ns CL = 25 pF

ETH_MDC high time t2 CC 160 – – ns
ETH_MDC low time t3 CC 160 – – ns
ETH_MDIO setup time t4 CC 10 – – ns
(output)
ETH_MDIO hold time t5 CC 10 – – ns
(output)
ETH_MDIO data valid t6 SR 0 – 300 ns
(input)
Figure 36 ETH Management Signal Timing
Data Sheet 91 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.10.3 ETH RMII Parameters

In the following, the parameters of the RMII (Reduced Media Independent Interface) are
described.
Table 55 ETH RMII Signal Timing Parameters

ETH_RMII_REF_CL clock t13 SR 20 – – ns CL = 25 pF; 50

period ppm
ETH_RMII_REF_CL clock high t14 SR 7 – 13 ns CL = 25 pF
time
ETH_RMII_REF_CL clock low t15 SR 7 – 13 ns
time
ETH_RMII_RXD[1:0], t16 SR 4 – – ns
ETH_RMII_CRS setup time
ETH_RMII_RXD[1:0], t17 SR 2 – – ns
ETH_RMII_CRS hold time
ETH_RMII_TXD[1:0], t18 CC 4 – 15 ns
ETH_RMII_TXEN data valid
Data Sheet 92 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 37 ETH RMII Signal Timing
Data Sheet 93 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.11 EtherCAT (ECAT) Characteristics
3.3.11.1 ECAT Measurement Reference Points
Figure 38 Measurement Reference Points
3.3.11.2 ETH Management Signal Parameters (MCLK, MDIO)
Table 56 ECAT Management Signal Timing Parameters

ECAT_MCLK period tMCLK – 400 – ns IEEE802.3

CC requirement (2.5
ECAT_MCLK high time tMCLK_h 160 – – ns MHz) CL = 25 pF
CC
ECAT_MCLK low time tMCLK_l 160 – – ns
CC
ECAT_MDIO setup time tD_setup 10 – – ns
(output) CC
ECAT_MDIO hold time tD_hold 10 – – ns
(output) CC
ECAT_MDIO data valid tD_valid 0 – 300 ns
(input) SR
Data Sheet 94 V1.2, 2023-04

XMC4300
XMC4000 Family
Figure 39 ECAT Management Signal Timing
3.3.11.3 MII Timing TX Characteristics
Table 57 ETH MII TX Signal Timing Parameters

PHY_CLK25, TX_CLK tTX_CLK – 40 – ns

period SR
Delay between PHY clock tPHY_delay – – – ns PHY dependent
source PHY_CLK25 and SR
TX_CLK output of the PHY
Data Sheet 95 V1.2, 2023-04

XMC4300
XMC4000 Family
Table 57 ETH MII TX Signal Timing Parameters (cont’d)

PHY setup requirement: tTX_setup 15 – 0 ns PHY dependent
TXEN/TXD[3:0] with respect SR IEEE802.3 limit
to TX_CLK is 15 ns
PHY hold requirement: tTX_hold 0 – 25 ns PHY dependent
TXEN/TXD[3:0] with respect CC IEEE802.3 limit
to TX_CLK is 0 ns
Note: ECAT0_CONPx.TX_SHIFT can be adjusted by displaying TX_CLK of a PHY and

TXEN/TXD[3:0] on an oscilloscope. TXEN/TXD[3:0] is allowed to change between
0 ns and 25 ns after a rising edge of TX_CLK (according to IEEE802.3 – check
your PHY’s documentation). Configure TX_SHIFT so that TXEN/TXD[3:0] change
near the middle of this range. It is sufficient to check just one of the TXEN/TXD[3:0]
signals, because they are nearly generated at the same time.
Figure 40 MII TX Characteristics
Data Sheet 96 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.11.4 MII Timing RX Characteristics
Table 58 ETH MII RX Signal Timing Parameters

RX_CLK period tRX_CLK – 40 – ns CL = 25 pF,

SR IEEE802.3
RX_DV/RX_DV/RXD[3:0] tRX_setup 10 – – ns requirement
valid before rising SR
edge of RX_CLK
RX_DV/RX_DV/RXD[3:0] tRX_hold 10 – – ns
valid after rising SR
edge of RX_CLK
Figure 41 MII RX characteristics
Data Sheet 97 V1.2, 2023-04

XMC4300
XMC4000 Family
3.3.11.5 Sync/Latch Timings
Table 59 Sync/Latch Timings

SYNC0/1 tDC_SYNC_ – – 11 + ns
Jitter SR m1)
LATCH0/1 tDC_LATCH 12 + – – ns
SR n2)
1) additional delay form logic and pad, number is added after characterization
2) additional shaping delay, number is added after characterization
Note: SYNC0/1 pulse length are initially loaded by EEPROM content ADR 0x0002. The
actual used value can be read back from Register DC_PULSE_LEN.
Figure 42 Sync/Latch Timings
Data Sheet 98 V1.2, 2023-04

XMC4300
XMC4000 Family
Package and Reliability
4 Package and Reliability

The XMC4300 is a member of the XMC4000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Die Pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1 Package Parameters

Table 60 provides the thermal characteristics of the packages used in XMC4300.
Table 60 Thermal Characteristics of the Packages

Parameter Symbol Limit Values Unit Package Types
Min. Max.
Exposed Die Pad Ex  Ey - 7.0 7.0 mm PG-LQFP-100-25
dimensions including CC
U-Groove
Exposed Die Pad Ax  Ay - 6.2 6.2 mm PG-LQFP-100-25
dimensions excluding CC
U-Groove
Exposed Die Pad - - 7.0 7.0 mm PG-LQFP-100-29
dimensions
Thermal resistance RJA - 22.5 K/W PG-LQFP-100-251)
Junction-Ambient CC PG-LQFP-100-291)
TJ  150 °C
1) Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSS, independent of EMC and thermal requirements.
Data Sheet 99 V1.2, 2023-04

XMC4300
XMC4000 Family
4.1.1 Thermal Considerations

When operating the XMC4300 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
T = (PINT + PIOSTAT + PIODYN)  RJA
The internal power consumption is defined as
PINT = VDDP  IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = ((VDDP-VOH)  IOH) + (VOL  IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers
Data Sheet 100 V1.2, 2023-04

XMC4300
XMC4000 Family
4.2 Package Outlines

The exposed die pad dimensions are listed in Table 60.
STAND OFF
0.127 +0.073
1.6 MAX.
-0.037
1.4 ±0.05
0.1 ±0.05
24 x 0.5 = 12
H
0°...7°
0.5 0.6 ±0.15
C 0.08 C 100x
SEATING COPLANARITY
2) PLANE
0.2 +0.07
-0.03
0.08 M C A-B D 100x
Bottom View
16
14 1) 0.2 C A-B D 100x Ex 3)
0.2 H A-B D 4x Ax 3)
D
Ay 3)
Ey 3)
A B
1)
16
14
100 100
1 1
Index Marking Exposed Diepad
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
3) Refer table for exposed pad dimension details PG-LQFP-100-24, -25-PO V04
Figure 43 PG-LQFP-100-25 (Plastic Green Low Profile Quad Flat Package)
Data Sheet 101 V1.2, 2023-04

XMC4300
XMC4000 Family
PG-LQFP-100-29
Figure 44 PG-LQFP-100-29 (Plastic Green Low Profile Quad Flat Package)

All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet 102 V1.2, 2023-04

XMC4300
XMC4000 Family
Quality Declarations
5 Quality Declarations
The qualification of the XMC4300 is executed according to the JEDEC standard
JESD47I.
Note: For automotive applications refer to the Infineon automotive microcontrollers.
Table 61 Quality Parameters

Operation lifetime tOP CC 20   a TJ  109°C,

device permanent
on
ESD susceptibility VHBM   3 000 V EIA/JESD22-
according to Human Body SR A114-B
Model (HBM)
ESD susceptibility VCDM   1 000 V Conforming to
according to Charged SR JESD22-C101-C
Device Model (CDM)
Moisture sensitivity level MSL   3  JEDEC
CC J-STD-020D
Soldering temperature TSDR   260 °C Profile according
SR to JEDEC
J-STD-020D
Data Sheet 103 V1.2, 2023-04

w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG

Mouser Electronics
Authorized Distributor
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XMC4300

XMC4300 Data Sheet

Revision History: V1.2 2023-04

We Listen to Your Comments

Data Sheet V1.2, 2023-04

Data Sheet 5 V1.2, 2023-04

3.3.8.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data Sheet 6 V1.2, 2023-04

About this Document

XMC4000 Family User Documentation

Data Sheet 7 V1.2, 2023-04

Figure 1 System Block Diagram

Data Sheet 8 V1.2, 2023-04

Analog Frontend Peripherals

Industrial Control Peripherals

Data Sheet 9 V1.2, 2023-04

On-Chip Debug Support

1.1 Ordering Information

1.2 Device Types

Table 1 Synopsis of XMC4300 Device Types

Data Sheet 10 V1.2, 2023-04

1.3 Device Type Features

Table 2 Features of XMC4300 Device Types

Table 3 Features of XMC4300 Device Types

1.4 Definition of Feature Variants

Table 5 SRAM Memory Ranges

Table 6 ADC Channels1)

Data Sheet 11 V1.2, 2023-04

1.5 Identification Registers

Table 7 XMC4300 Identification Registers

Data Sheet 12 V1.2, 2023-04

2 General Device Information

2.1 Logic Symbols

Figure 2 XMC4300 Logic Symbol PG-LQFP-100

Data Sheet 13 V1.2, 2023-04

2.2 Pin Configuration and Definition

Figure 3 XMC4300 PG-LQFP-100 Pin Configuration (top view)

Data Sheet 14 V1.2, 2023-04

2.2.1 Package Pin Summary

Table 8 Package Pin Mapping Description

Table 9 Package Pin Mapping

Data Sheet 15 V1.2, 2023-04

Table 9 Package Pin Mapping (cont’d)

Data Sheet 16 V1.2, 2023-04

Table 9 Package Pin Mapping (cont’d)

Data Sheet 17 V1.2, 2023-04

Table 9 Package Pin Mapping (cont’d)

Data Sheet 18 V1.2, 2023-04

Table 9 Package Pin Mapping (cont’d)

Data Sheet 19 V1.2, 2023-04

2.2.2 Port I/O Functions

Table 10 Port I/O Function Description

Figure 4 Simplified Port Structure

Data Sheet 20 V1.2, 2023-04

Table 11 Port I/O Functions

P0.1 USB. U1C1. CCU80. LEDTS0. ETH0. ERU0. ECAT0. ETH0.

P0.2 ECAT0. U1C1. CCU80. U1C0. U1C0. ETH0. ERU0.

P0.3 ECAT0. CCU80. U1C0. U1C0. ETH0. ERU1.