DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

LIST OF EXPERIMENTS

EC3361 - ELECTRONIC DEVICES AND CIRCUITS LABORATORY

1. Characteristics of PN Junction Diode and Zener diode.

2. Full Wave Rectifier with Filters.

3. Design of Zener diode Regulator.

4. Common Emitter input-output Characteristics.

5. MOSFET Drain current and Transfer Characteristics.

6. Frequency response of CE and CS amplifiers.

7. Frequency response of CB and CC amplifiers.

8. Frequency response of Cascode Amplifier

9. CMRR measurement of Differential Amplifier

10. Class A Transformer Coupled Power Amplifier.

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Ex.No: 1. CHARACTERISTICS OF PN JUNCTION DIODE &

ZENER DIODE
Ex.No: (1A) CHARACTERISTICS OF PN JUNCTION DIODE
AIM:
To study the PN junction diode characteristics under Forward & Reverse bias
conditions.
APPARATUS REQUIRED: COMPONENTS REQUIRED:
S.No. Name Range Type Qty S.No. Name Range Type Qty

1 R.P.S (0-30)V 1 1 Diode IN4007 1

(0–30)mA 1 2 Resistor 1k 1

2 Ammeter Bread
(0-500)µA 1 3 1
Board
(0–1)V 1 4 Wires
3 Voltmeter
(0-10)V 1

THEORY:
A PN junction diode is a two terminal junction device. It conducts only in one
direction (only on forward biasing).
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier potential. As the
applied potential exceeds the barrier potential the charge carriers gain sufficient energy to
cross the potential barrier and hence enter the other region. The holes, which are majority
carriers in the P-region, become minority carriers on entering the N-regions, and
electrons, which are the majority carriers in the N-region, become minority carriers on
entering the P-region. This injection of Minority carriers results in the current flow,
opposite to the direction of electron movement.

REVERSE BIAS:
On reverse biasing, the majority charge carriers are attracted towards the
terminals due to the applied potential resulting in the widening of the depletion region.
Since the charge carriers are pushed towards the terminals no current flows in the device
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due to majority charge carriers. There will be some current in the device due to the
thermally generated minority carriers. The generation of such carriers is independent of
the applied potential and hence the current is constant for all increasing reverse potential.
This current is referred to as Reverse Saturation Current (I O) and it increases with
temperature. When the applied reverse voltage is increased beyond the certain limit, it
results in breakdown. During breakdown, the diode current increases tremendously.
PROCEDURE:
FORWARD BIAS:
1. Connect the circuit as per the diagram.
2. Vary the applied voltage V in steps of 0.1V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
OBSERVATIONS
1. Find the d.c (static) resistance = V/I.
V2  V1
2. Find the a.c (dynamic) resistance r = V / I (r = V/I) = .
I 2  I1
3. Find the forward voltage drop = [Hint: it is equal to 0.7 for Si and 0.3 for Ge]
REVERSE BIAS:
1. Connect the circuit as per the diagram.
2. Vary the applied voltage V in steps of 1.0V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
5. Find the dynamic resistance r = V / I.

FORMULA FOR REVERSE SATURATION CURRENT (IO):

Io = I/ [exp (V/VT)]-1

Where VT is the voltage equivalent of Temperature = kT/q

-k is Boltzmann’s constant, q is the charge of the electron and T is the temperature in
degrees Kelvin.

 =1 for Silicon and 2 for Germanium

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CIRCUIT DIAGRAM:
FORWARD BIAS:

REVERSE BIAS:

Specification for 1N4007: Silicon Diode

Peak Inverse Voltage: 50V
Idc = 1A.
Maximum forward voltage drop at 1 Amp is 1.1 volts
Maximum reverse current @50 volts is 5A

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TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:

S.No. VOLTAGE CURRENT S..No. VOLTAGE CURRENT

(In Volts) (In mA) (In Volts) (In A)

MODEL GRAPH:
If (mA)
I2

Vb I1
V1 V2 Vf (Volts)
( Volts)

Ir (A)

RESULT:
Forward and Reverse bias characteristics of the PN junction diode and the
dynamic resistance under
 Forward bias = ---------------------
 Reverse bias =----------------------.
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Ex.No.1B DATE:

CHARACTERISTICS OF ZENER DIODE

AIM:
To determine the breakdown voltage of a given zener diode
APPARATUS REQUIRED: COMPONENTS REQUIRED:
S.No. Name Range Type Qty S.No. Name Range Type Qty
1 R.P.S (0-30)V 2 1 zener diode FZ5.1 1
(0–30)mA 1 2 Resistor 1K 1
2 Ammeter Bread
(0–250)µA 1 3 1
Board
(0–30)V 1 4 Wires
3 Voltmeter
(0–10)V 1

THEORY:
A properly doped crystal diode, which has a sharp breakdown voltage, is known as zener
diode.
FORWARD BIAS:
On forward biasing, initially no current flows due to barrier potential. As the
applied potential increases, it exceeds the barrier potential at one value and the charge
carriers gain sufficient energy to cross the potential barrier and enter the other region. the
holes ,which are majority carriers in p-region, become minority carriers on entering the
N-regions and electrons, which are the majority carriers in the N-regions become
minority carriers on entering the P-region. This injection of minority carriers results
current, opposite to the direction of electron movement.

REVERSE BIAS:
When the reverse bias is applied due to majority carriers small amount of current
(ie) reverse saturation current flows across the junction. As the reverse bias is increased
to breakdown voltage, sudden rise in current takes place due to zener effect.

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ZENER EFFECT:
Normally, PN junction of Zener Diode is heavily doped. Due to heavy doping the
depletion layer will be narrow. When the reverse bias is increased the potential across the
depletion layer is more. This exerts a force on the electrons in the outermost shell.
Because of this force the electrons are pulled away from the parent nuclei and become
free electrons. This ionization, which occurs due to electrostatic force of attraction, is
known as Zener effect. It results in large number of free carriers, which in turn increases
the reverse saturation current
PROCEDURE:
FORWARD BIAS:
1. Connect the circuit as per the circuit diagram.
2. Vary the power supply in such a way that the readings are taken in steps of 0.1V
in the voltmeter till the needle of power supply shows 30V.
3. Note down the corresponding ammeter readings.
4. Plot the graph :V (vs) I.
5. Find the dynamic resistance r = V / I.

REVERSE BIAS:
1. Connect the circuit as per the diagram.
2. Vary the power supply in such a way that the readings are taken in steps of 0.1V
in the voltmeter till the needle of power supply shows 30V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
5. Find the dynamic resistance r = V / I.
6. Find the reverse voltage Vr at Iz=20 mA.

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CIRCUIT DIAGRAM:
FORWARD BIAS:

REVERSE BIAS:

ZENER DIODE:

If (in mA)

I2

I1
VB
Vr V1 V2 Vf
(in volts) (in volts)

Ir (in uA)
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TABULAR COLUMN:
FORWARD BIAS: REVERSE BIAS:

S..No. VOLTAGE CURRENT S.No. VOLTAGE CURRENT

(In Volts) (In mA) (In Volts) (In A)

RESULT:
Forward and Reverse bias characteristics of the zener diode was studied and
Forward bias dynamic resistance = ---------------------
Reverse bias dynamic resistance = ----------------------

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Ex.No: 2 DATE:

FULL WAVE RECTIFIER WITH FILTERS

AIM:
To construct a Full wave rectifier using diode and to draw its performance
characteristics.

APPARATUS REQUIRED: COMPONENTS REQUIRED:

S. S.
Name Range Type Qty Name Range Type Qty
No. No.
1 Transformer 230/(9-0-9)V 1 Diode IN4007
1 2

2 Resistor 1K  1
Bread
3 1
Board
4 Capacitor 100µf 1
5 CRO 1

FORMULAE:
WITHOUT FILTER:

(i)
Vrms = Vm / 2
(ii)
Vdc = 2Vm / 
(iii)
Ripple Factor = VAC/VDC
(iv)
Efficiency = (Vdc / Vrms)2 x 100

WITH FILTER:
i. Vrms = Vrpp /(2* 3)
ii. Vdc = Vm – V rpp
iii. Efficiency = (Vdc / Vrms)2 x 100
iv. Ripple Factor = Vrms’/ Vdc

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PROCEDURE:
WITHOUT FILTER:
1. Give the connections as per the circuit diagram.
2. Give 230v, 50HZ I/P to the step down TFR where secondary connected to the
Rectifier I/P.
3. Take the rectifier output across the Load.
4. Plot its performance graph.

WITH FILTER:
1. Give the connections as per the circuit diagram.
2. Give 230v, 50HZ I/P to the step down TFR where secondary connected to the
Rectifier I/P.
3. Connect the Capacitor across the Load.
4. Take the rectifier output across the Load.
5. Plot its performance graph.
CIRCUIT DIAGRAM:
WITHOUT FILTER:

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WITH FILTER:

TABULAR COLUMN:
WITHOUT FILTER:
Vm Vrms= Vm / 2 Vdc=2Vm /  VAC=Vm/2 3 Ripple factor

WITH FILTER:
Vm Vrms= Vm / 2 Vdc=2Vm /  VAC=Vm/2 3 Ripple factor

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MODEL GRAPH:

Vin
(Volts)

t (ms)

Vo
(Volts) Without Filter

t (ms)
Vo
With Filter
(Volts)

t (ms)

RESULT:
Thus the performance characteristics of 1 Full wave rectifier were obtained.

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Ex.No: 3 DATE:

DESIGN OF ZENER DIODE REGULATOR

AIM:
To setup and study a zener diode shunt regulator and to plot its line and load regulation characteristics.

COMPONENTS REQUIRED:

Quantity
S.No Name of the equipment Type Range
(No.S)
1 Zener diode IZ5.6 1
2 Resistor, 150 Ω, 1
Variable 0-2.4K
Resistor(rheostat)
(0-10V)
3 Voltmeter MC One from each
(0-30V)
(0-10 mA)
4 Ammeter MC One

(0 -30V)
5 Regulated power supply 1

6 Bread board 1
7 Connecting wires As required

THEORY:
A zener diode functions as an ordinary diode when it is forward biased. It is a specially designed device to operate
in the reverse bias. When it is in the reverse breakdown region, the zener voltage remains almost constant irrespective of
the current Iz through it. A series resistor Rs is used to limit the zener current below its maximum current rating.
The current through Rs is given by the expression Is = Iz+IL, where ILis the current through the load resistorR L .
The value of must be properly selected to fulfil the following condition requirements.
When the input voltage, VI increases IL remains the same, Is and Iz increases. Similarly if input voltage
decreases, IL remains the same, Is and Iz decreases. But if Iz falls lower than the minimum zener current enough to keep
the zener in the breakdown region, the regulation will cease and output voltage decreases. A low input voltage can cause the
regulator fail to regulate. The series resistance should be selected between Rs maxandRsmin which are given by the
expressions,
Rsmin = [VImax -Vz]/Izmax
Rsmax = [VImin-Vz]/[Izmin+IL]

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PROCEDURE:
1. Wire up the circuit on the bread board after testing all the components.
2. Keep the load constant. Note down the output voltage varying input from 8V to 14V in steps of 1V. Plot the line
regulation graph with Vi along x-axis andV 0 along y-axis. Calculate percentage line regulation using the expression
(∆Vo⁄∆Vi )x100%.
3. 3. Keep the input voltage constant (say 10V) and note down the output voltage for various values of load current
starting from 0 to 5 mA, by varying RL using a rheostat. Plot the load regulation graph with I L along x-axis and Vo
along y-axis.
4. To calculate percentage load regulation, mark VNL and VFLon y-axis on the load regulation graph. VNL is the output
voltage in the absence of load resistor and V FL is the output voltage corresponding to rated I L ( here, 5 mA).
Calculate the percentage load regulation VR as per the equation,
VR

DESIGN

Assume Vo = 5.6V, ILmax = 5mA Input voltage is in the range 8-14V.

Select 5.6V zener [Po = 400mW , Vz = 5.6 , rd= 8Ω at Iz= 10mA ].

Use 2.4 k rheostat as load resistance load current can be varied from 2.4 mA and upwards.

Izmax

Iz min = 10%of = 0.1 x 71.42 = 7.142mA

Rsmax > R > Rsmin

Rsmax= [VImin−Vz ]⁄[Izmin +ILmax ]

RSmin= [VImax −Vz]⁄Izmax

Select Rs= 150

Power rating of Rs

(14-5.6)V

Max current through Rs

=Im=[VImin-Vz ]⁄Rs= =56mA
150 Ω

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Power rating of Rs = Im2xRs = 0.4704W >> Select 150 ohms 0.5W resistor

CIRCUIT DIAGRAM

TABULAR COLUMNS

LINE REGULATION

Keeping load current constant at IL= 5mA, The input voltage is varied from 8 V to 14V and corresponding
observations are made.
(volts) (volts)

LOAD REGULATION

Keeping input voltage at 10V, the load current is varied from 0 to 5 mA and observations are made. For taking
reading corresponding to no load ( IL = 0 ), the loading rheostat may be disconnected.
mA (volts)

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EXPECTED OUTPUT PLOTS

Line Regulation Load Regulation

Result:

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Ex. No: 4 DATE:

COMMON EMITTER (CE) INPUT-OUTPUT

CHARACTERISTICS
AIM:
To plot the transistor characteristics of CE configuration
APPARATUS REQUIRED: COMPONENTS REQUIRED:
S.No. Name Range Type Qty S.No. Name Range Type Qty
1 R.P.S (0-30)V 2 1 Transistor BC 107 1
10k
(0–30)mA 1 2 Resistor 1
1K
2 Ammeter
Bread
(0–250)uA 1 3 1
Board
(0–30)V 1 4 Wires
3 Voltmeter
(0–1)V 1

THEORY:
A BJT is a three terminal two – junction semiconductor device in which the
conduction is due to both the charge carrier. Hence it is a bipolar device and it amplifier
the sine waveform as they are transferred from input to output. BJT is classified into two
types – NPN or PNP. A NPN transistor consists of two N types in between which a layer
of P is sandwiched. The transistor consists of three terminal emitter, collector and base.
The emitter layer is the source of the charge carriers and it is heartily doped with a
moderate cross sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts a path for the
movement of the charge carriers. In order to reduce the recombination of holes and
electrons the base region is lightly doped and is of hollow cross sectional area. Normally
the transistor operates with the EB junction forward biased. In transistor, the current is
same in both junctions, which indicates that there is a transfer of resistance between the
two junctions. One to this fact the transistor is known as transfer resistance of transistor.

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PROCEDURE:

INPUT CHARECTERISTICS:

1. Connect the circuit as per the circuit diagram.

2. Set VCE ,vary VBE in regular interval of steps and note down the corresponding
IB reading. Repeat the above procedure for different values of VCE.
3. Plot the graph: VBE Vs IB for a constant VCE.
4. Input impedance hie=∆VBE/∆IB

OUTPUT CHARACTERISTICS:

1. Connect the circuit as per the circuit diagram.

2. Set IB, Vary VCE in regular interval of steps and note down the corresponding IC
reading. Repeat the above procedure for different values of IB.
3. Plot the graph: VCE Vs IC for a constant IB.
4. Output admittance hoe=∆Ic/∆VCE
PIN DIAGRAM:
B

E C
CIRCUIT DIAGRAM:
(0 – 30)mA 1 K
- +
A
(0 – 250) A C
+ +
10 K + A - (0-30)V
BC107 V (0-30)V
+ B -
+ -
(0-30)V - (0-1)VV - E

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MODEL GRAPH:
INPUT CHARACTERISTICS: OUTPUT CHARACTERISTICS:

µA
mA
IC
IB
VCE = 0V
VCE = 5V
IB=60A
IB=40A IB=20A

0
TABULAR COLU 0
VBE(V)
MN: VCE(V)
INPUT CHARACTERISTICS:

VCE=1V VCE=3V
VBE(V) IB(μA) VBE(V) IB(μA)

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OUTPUT CHARACTERISTICS:

IB=40A IB=60A
VCE(V) IC(mA) VCE(V) IC(mA)

RESULT:
The transistor characteristics of a Common Emitter (CE) configuration
were plotted

1) Input impedance=

2) Output admittance=
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Ex.No: 5 DATE:

MOSFET DRAIN CURRENT AND TRANSFER CHARACTERISTICS

AIM:
To study the drain current and transfer characteristics of MOSFET

APPARATUS REQUIRED:
1. MOSFET Trainer Module
2. Ammeters (0-100) mA , (0-500 µ A)
3. Voltmeter (0-30) V DC-2 N0s.
4. Patch cord

THEORY:
The power MOSFET has three terminals namely drain, source and gate.The drain and source are called as
power terminals and the gate is called as control terminals. The control voltage to implement to turn on is applied
between the gate & the source terminals. The direction of the direct current flow in an Nchannel device is from
the drain to the source. This results from the flow of electrons from the source to the drain. If the drain terminal is
made positive with respect to the source without gate voltage, no current flow from the drain to the source
because the junction between the N drain region and the P region is reverse biased. Only a small reverse leakage
current flows which is negligibly small. This is the off state of the power MOSFET. The power MOSFET is
widely used in analog and digital signal processing circuits both in discrete and integrated circuits.

CONNECTION PROCEDURE:

1. Connect MOSFET drain, source, and gate terminal to MOSFET characteristic circuit.
2. Connect voltmeter across the gate –source terminal.
3. Connect Ammeter in drain terminal.
4. Connect Voltmeter across the drain and source terminal to measure VDS.

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CIRCUIT DIAGRAM:

MODEL GRAPH:

TABULAR COLUMN:
DRAIN CHARACTERISTICS TRANSFER CHARACTERISTICS

VGS= V VDS= V
VDS(V) ID (mA) VGS(V) ID (mA)

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EXPERIMENTAL PROCEDURE:
Output Characteristics
1. Switch on the 230 V supply.
2. Keep the gate to source –voltage (VGS) at particular voltage by varying the pot.
3. Smoothly vary the drain to source voltage till the MOSFET gets turned on and note down the voltmeter
(VDS) and ammeter (ID) reading.
4. Further increase the VDS voltage and note down the current ID.
5. Repeat the same procedure for different values of VGS.
6. Draw a graph between VDS & ID keeping VGS as a constant. Calculate the pinch-off voltage.
Transfer Characteristics
1. Switch on the 230V supply.
2. Keep the drain to source –voltage (VDS) at particular voltage by varying the pot.
3. Smoothly vary the gate to source voltage till the MOSFET gets turned on and note down the voltmeter
(VGS) and ammeter (ID) reading.
4. Further increase the VGS voltage and note down the current ID.
5. Repeat the same procedure for different values of VDS
6. Draw a graph between VDS & ID keeping VGS as a constant. Calculate the pinch-off voltage.

REVIEW QUESTIONS:
1. What is Forward Transconductance?
2. Mention the operating modes of MOSFET
3. Comparison of E – only MOSFET and DMOSFET
4. Why MOSFETs are never connected or disconnected in the circuit when power is ON?
5. List some advantages of MOSFETs.

RESULT:
Thus the drain current and transfer characteristics of MOSFET was studied.

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Ex. No: 6 DATE:

FRQUENCY RESPONSE OF CE AND CS AMPLIFIERS

6(A). Frequency response of common emitter amplifier

AIM:
To observe input -output waveforms of common emitter (CE) amplifier .To
measure gain of amplifier at different frequencies and plot frequency response.
APPARATUS REQUIRED:
Name of the apparatus Range Type Quantity
S.No
1. Signal Generator (0-1)MHz 01
2. Resistor 560Ω 02
3. Capacitor 0.2uF 02
4. CRO 01
5. Inductor 35mH 01
6. Breadboard 01

THEORY:
Common emitter amplifier is used to amplify weak signal. It utilizes energy from DC
power supply to amplify input AC signal. Biasing of transistor is done to tie Q point at the
middle of the load line. In the circuit shown, voltage divider bias I formed using resistors
10K and 2 .2K. During positive cycle, forward bias of base emitter junction increases and
base current increases .Q point moves in upward direction on load line and collector current
increases times than base current.( is current gain ). Collector resistor drop IcRc increases due
to increase in collector current Ic.This will reduce collector voltage. Thus during positive
input cycle, we get negative output cycle.
When input is negative cycle, forward bias of base emitter junction and base current
will reduce Collector current reduces (Q point moves down side). Due to decrease in
collector current collector resistance voltage drop IcRc reduces and collector voltage
increases Change in collector voltage is much higher than applied base voltage because less
base current variation causes large collector current variation due to current gain B. This

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large collector current further multiplied by collector resistance Rc which provides large
voltage output. Thus CE amplifier provides voltage gain and amplifies the input signal

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without emitter resistance gain of amplifier is highest but it is not stable. Emitter resistance is
used to provide stability. To compensate effect of emitter resistance emitter bypass capacitor
is used which provides AC ground to the emitter. This will increase gain of amplifier.

CIRCUIT DIAGRAM:

PROCEDURE:

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TABULAR COLUMN:

MODEL GRAPH:

RESULT:

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6(B). FREQUENCY RESPONSE OF CS AMPLIFIER

Aim:
To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product
(GBW) of CS amplifier.

Components Required:

S.No Component Name Range Quantity Required

1 Power Supply 0-30 V 1
2 Resistor 1MΩ,1.5,220Ω, 10KΩ Each 1
3 Capacitor 100µF,0.01 µF 2
4 Transistor BC107 1
5 Function generator (0-1)MHz 1
6 CRO (0-30) MHz 1
7 Breadboard 1

Theory:
A weak signal is applied between gate and source and output is obtained at drain. For the proper
operation of FET, gate must be reverse biased. A small change in reverse bias on the gate produces a
large drain current. This fact makes FET capable of raising the strength of a weak signal. The gain of the
common source FET amplifier is very high which is greater than unity.
Formula Used:
Voltage gain AV= gmrL
Bandwidth =f2 – f1

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Circuit Diagram:

Tabular Form:

Input voltage (Vi)=

Frequency Output Gain Av=Vo/Vi Gain in db

Voltage(Vo) 20 log (gain)

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Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set Vi =50 mV, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps and
note down the corresponding output voltage.
4. Plot the graph; Gain (dB) Vs Frequency (Hz).
5. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a Semi log graph
sheet.
Theoreticalcalculations :
R D × R L 1500 ×10000
r L= = =1300 Ω
RD + RL 1500+10000
I DSS =10 mA , V GS =4 V
2 I DSS 2 ×10 mA
gmo= = =5 mS
−V GS (off ) 4V

[
gm =g mo 1−
V GS
V GS(off ) ] [
=5 mS 1−
−1
−4
= 3.75 mS ]
AV =¿g m ×r L=3.75 mS ×1300=4.875¿

V ¿ =0.2 V PP
V out =A V ×V ¿ =4.875 × 0.2V PP=0.935 V PP
Practical calculations:
V ¿ =0.2 V PP
V out =¿
V out
AV = =¿
V¿
Model Graph:

Result :
The frequency response of common source amplifier is obtained and the bandwidth is noted.
Ex.No: 7 DATE:
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 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

FREQUENCY RESPONSE OF CB AND CC AMPLIFIERS

7(A). FREQUENCY RESPONSE OF CB AMPLIFIER

Aim:
To measure the gain and to plot the frequency response and to determine the Gain Bandwidth
product (GBW) of CB amplifier.

Components Required:

S.No Component Name Range Quantity Required

1 Power Supply 0-30 V 1
2 Resistor 12KΩ,2.4KΩ,330Ω,1.5KΩ, 1KΩ, Each 1
600Ω
3 Capacitor 10µF,100µF 2
4 Transistor BC107 1
5 Function generator (0-1)MHz 1
6 CRO (0-30) MHz 1

Theory:

The common base amplifier configuration is not used as widely as transistor amplifier
configurations. However it does find uses with amplifiers that require low input impedance levels. One
application is for moving-coil microphones preamplifiers - these microphones have very low impedance
levels. Another application is within VHF and UHF RF amplifiers where the low input impedance allows
accurate matching to the feeder impedance which is typically 50Ω or 75Ω.
It is worth noting that the current gain of a common-base amplifier is always less than unity.
However the voltage gain may be more, but it is a function of input and output resistances (and also the
internal resistance of the emitter-base junction). As a result, the voltage gain of a common-base amplifier
can be very high.
Formula Used:

AV= 20log(Vo/Vin)
Bandwidth = f2-f1

Circuit Diagram:
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 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

Tabular Form:

Input voltage (Vi)=

Frequency Output Gain Av=Vo/Vi Gain in db

Voltage(Vo) 20 log (gain)

Procedure

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 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

1. Connect the circuit as per the circuit diagram.

2. Give l00Hz signal and 20mv p-p as Vs from the signal generator
3. Observe the output on CRO and note down the output voltage.
4. Keeping input voltage constant and by varying the frequency in steps 100Hz-1MHz, note down
the corresponding output voltages.
5. Calculate gain in dB and plot the frequency response on semi log sheet

Model Graph:
Frequency response :

Result:
The voltage gain and frequency response of the CB amplifier are obtained. Also gain bandwidth
product of the amplifier is calculated.

Ex.No:7 (B) DATE:

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 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

FREQUENCY RESPONSE OF CC AMPLIFIER

Aim:
To construct a common collector amplifier circuit and to plot the frequency
response characteristics.

Apparatus Required:

S.No. Name Range Quantity

1. Transistor BC 107 1
2. Resistor 15kΩ,10kΩ,680Ω,6kΩ 1,1,1,1
3. Capacitor 0.1μF, 47μF 2, 1
4. Function Generator (0-3)MHz 1
5. CRO 30MHz 1
6. Regulated power (0-30)V 1
supply
7. Bread Board 1

Theory:

The D.C biasing in common collector is provided by R1, R2 and RE .The load resistance is
capacitor coupled to the emitter terminal of the transistor.

When a signal is applied to the base of the transistor ,VB is increased and decreased as the signal
goes positive and negative, respectively. Considering VBE is constant the variation in the VB appears at
the emitter and emitter voltage VE will vary same as base voltage VB . Since the emitter is output
terminal, it can be noted that the output voltage from a common collector circuit is the same as its input
voltage. Hence the common collector circuit is also known as an emitter follower.

Formula Used:

AV= 20log(Vo/Vin)
Bandwidth = f2-f1

Circuit Diagram:
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 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

Model Graph:

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 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

Tabular Form:

Input voltage (Vi)=

Frequency Output Gain Av=Vo/Vi Gain in db

Voltage(Vo) 20 log (gain)

Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set Vi =50 mV, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps and
note down the corresponding output voltage.
4. Plot the graph; Gain (dB) Vs Frequency (Hz).
5. A graph is drawn by taking frequency on X-axis and gain in dB on Y-axis on a Semi log graph
sheet.

Result

Thus, the Common collector amplifier was constructed and the frequency response curve is
plotted. The Gain Bandwidth Product is found to be =

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ISO 9001:2008 JEPPIAAR ENGINEERING COLLEGE
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

FREQUENCY RESPONSE OF CASCODE AMPLIFIER

EX.NO: 8 DATE:
AIM:
To design and construct a cascode amplifier circuit and to draw its frequency response graph.

EQUIPMENTS REQUIRED

S.NO EQUIPMENT RANGE QUANTITY

1 Transistor BC 547 2
2 RPS (0-30)V 1
3 Resistor 1.2K, 33 K,22K, 12K 1
4 Resistor 680Ω 1
5 Capacitor 1 uf, 2.2uf 2
6 Bread Board - 1
7 Single strand Wires - -
8 CRO (0 - 30) MHz 1
9 CRO Probes - 3
10 Function Generator (0 - 3) MHz 1

PROCEDURE

1. Connect the circuit as per the circuit diagram

2. Set Vs = 50mV using signal generator.
3. Keep the input voltage constant; vary the frequency from 50 Hz to 1 MHz in steps.
4. Note down the corresponding output voltage.
5. Plot the graph gain Vs
frequency. Calculate the bandwidth
from the graph

THEORY
A cascode amplifier comprises of a common emitter amplifier and a common base
amplifier stages in cascade. In the circuit diagram Q1 common base configuration and Q2 is common
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

emitter configuration. Principal advantage of this circuit is its low internal capacitance which is a
limiting factor gain at high frequencies. Cascode amplifier can able to amplify wide range of
frequencies than that is possible with CE amplifier. This is because no high frequency feedback occurs
from the output back to

input through the miller capacitance as it occurs in transistor CE configuration. Cascode amplifier
provides same voltage gain of CE amplifier but in wide range of frequencies. The advantage of CE
and CB stages are put together in cascode connection.

CASCODE AMPLIFIER CIRCUIT DIAGRAM

 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

DESIGN OF FIXED BIAS COMMON EMITTER AMPLIFIER

Design parameters
Vcc=12V, Ic =2mA, hfe (β) =100, Vbe
=0.7V, VCE1= VCE2=35% of Vcc = 4.2V
VRE=10% of VCC
=1.2V VRC=20% of
VCC=2.4V

To find Rc

VRC =Ic*Rc
=2.4V
Rc=1.2KΩ
To find RE

VRE =IE*RE
=1.2V
RE=600Ω

To find R1, R2 and R3

Vcc-VR1-VBE1-VCE2-
VRE=0 VR1=Vcc-VBE1-
VCE2-VRE VR1=12-0.6-
4.2-12= 6V
IB=Ic/Hfe = 20µA
If 10IB assumed flowing through R1 we get
R1= VR1/10 IB = 30KΩ
Vcc-VR1-VR2-VBE2-
VRE=0 VR2=Vcc- VR1 -
VBE2-VRE VR2=12- 6-
0.6-1.2= 4.2V
IB=Ic/Hfe = 20µA
If 9IB assumed flowing through R2 we get
R2= VR2/9 IB = 23KΩ
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

VR3-VBE2-VRE=0
VR3= VBE2+VRE
VR3= 0.6+1.2=
1.8V
IB=Ic/Hfe = 20µA
If 8IB assumed flowing through R3 we get
R3= VR3/8 IB = 11.2KΩ
To find CE (Bypass
capacitor) XCE =RE / 10
XCE = 600Ω /10 =60
XCE =1 / 2π f CE Let f=1000
C E = 1 / 2*π *1000* 60 =2.2 µf

TABULATION
Vin =
Frequency Output Voltage Gain = 20 log (Vo / Vi)
SL.NO
(Hz) (Vo) (db)
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

RESULT

Hence designed and constructed Cascode amplifier and plotted its frequency response.
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

CMRR MEASUREMENT OF DIFFERENTIAL AMPLIFIER

EX.NO:9 DATE:

Aim:
To construct differential amplifier in
i) Common mode
ii) differential mode, and to find the common mode rejection ratio (CMRR).

Components Required:
S.No Component Name Range Quantity Required
1 Power Supply 0-30 V 1
2 Resistor 1KΩ,470Ω 2,1
3 Breadboard 1
4 Transistor BC107 2
5 Function generator (0-1)MHz 1
6 CRO (0-30) MHz 1

Theory:
The differential amplifier amplifies the difference between two input signals. Hence it is called
differential amplifier. V1, V2 are the input voltages then the output voltage V o will be directly
proportional to the difference between two input signals.
If we apply two input voltages equal in all respects then in ideal case output should be zero. But
output voltage depends on the average common level of the inputs. Such an average level of two input
signals is called common mode signal.
Higher the value of C.M.R.R, better the performance of the differential amplifier. To improve
C.M.R.R we have to increase differential mode gain and decrease common mode gain

Formula Used:
C.M.R.R = Ad /Ac
C.M.R.R in dB = 20 log Ad /Ac
Ad= Differential mode gain
Ac = Common mode gain
hfe RC
Ad=
hie
−hfe RC
A C=
hie +2 R E (1+h fe)
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

Circuit Diagram:

Differential Mode:

Common Mode:
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

Tabular Column:

Theoretical Value Practical value

Ad AC CMRR Differential Mode Common Mode CMR
(Differentia (Common Vo Vin Ad Vo Vin Ac R
l mode mode
gain) gain)

Procedure:
1. Connections are given as per the circuit diagram
2. Set Vi=5mV and note down Vo in both differential mode & common mode
3. Calculate the gain for both the modes
4. Calculate C.M.R.R

Result
Thus a differential amplifier is constructed in both common mode and differential mode and the
corresponding gains are obtained and the CMRR is calculated.

CMRR : Practical Value=

Theoretical Value=
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

CLASS -A POWER AMPLIFIER(TRANSFORMER COUPLED)

EX.NO: 10 DATE:
AIM: To observe the input and output waveforms and to calculate the

efficiency.

EQUIPMENT REQUIRED:

APPARATUS REQUIRED:
Power supply 0-30V- 1 No.
CRO 20MHz - 1 No.
Digital multimeter - 1 No.
Signal generator 1Hz - 1MHz - 1 No.

COMPONNTS REQUIRED:
Resistors 33KΩ - 1N0
5.6KΩ -2NO
470Ω -1NO
Capacitors 47uf -1NO
2.2uf - 1NO
TRANSFORMER -1NO

CIRCUIT DIAGRAM:
 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

THEORY:
The amplifier is said to be class A power amplifier if the q point and the input
signal are selected such that the output signal is obtained for a full input cycle . For this
class the position of q point is approximately y at the mid point of the load line.
For all the values of input signal the transistor remains in the active region and
never entire into the cutoff or saturation region. The collector current flows for 3600
(life cycle) of the input signal in other words the angle of the collector current flow
is 3600 the claa a amplifiers or furthers classified as directly coupled and transformer
coupled and transformer coupled amplifiers in directly coupled type .The load is
directly connected in the collector circuit while in the transformer coupled type,
the load is coupled to the collector using the transformer.

Advantages:
1. Distortion analysis is very important
2. It amplifies audio frequency signals faithfully hence they are called as audio amplifiers

Disadvantages:
1. H parameter analysis is not applicable
2. Due to large power handling the transistor is used power transistor which is large in
size and having large power rating

PROCEDURE:

1. CONNCECT the circuit as per the ciecuit diadram

2. Set Vs (say 250 to 300 mV), at 10 KHz using signal generator.

3. Connect milli ammeter to the ammeter terminals

4. By keeping the input voltage constant, vary the frequency from 0 to 1MHz

in regular steps .

5. Note down the corresponding output voltage from CRO

6. Calculate the DC input power using the formula Pdc= VccIc

7. Calculate the AC output power using the formula Pac = V 2/8R

O L

8. Calculate the efficiency n = Pac /Pdc

9. Plot the graph between Gain (db) and frequency.

10. Calculate bandwidth from the graph.

 DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY

OBSERVATIONS:
VO = , VI =

VCC =

RL =

CALCULATIONS:
Efficiency (Pac/ Pdc) = _

P ac = Vcc Ic

PDC = Vm/2RL = V2pp/8RL

%n = Pac/ PDC X 100

GRAPH: I/P

O/P

RESULT: Gain and frequency as observed of Class A power amplifier.

%n = Pac/ PDC X 100 =
DEPARTMENT OF ECE EC3361- ELECTRONICS LABORATORY