200b z32m SDP DDP QDP Auto Lpddr4 Lpddr4x

Micron Confidential and Proprietary
200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Features
Automotive LPDDR4/LPDDR4X SDRAM

MT53E1G16D1, MT53E1G32D2, MT53E2G32D4
Features Options Marking

• VDD1/VDD2/VDDQ: 1.80V/1.10V/1.10V or E
This data sheet specifies the operation of the unified 0.60V
LPDDR4 and LPDDR4X product, and first describes • Array configuration
specific requirements for LPDDR4X 0.6V V DDQ opera- – 1 Gig × 16 1G16
tion. When using the product as an LPDDR4 device, (1 channel ×16 I/O × 1 rank)
refer to LPDDR4 setting section LPDDR4 1.10V V DDQ – 1 Gig × 32 1G32
at the end of this data sheet. (2 channels ×16 I/O × 1 rank)
• Ultra-low-voltage core and I/O power supplies – 2 Gig × 32 2G32
– VDD1 = 1.70–1.95V; 1.80V nominal (2 channels ×16 I/O × 2 ranks)
– VDD2 = 1.06–1.17V; 1.10V nominal • Device configuration
– VDDQ = 1.06–1.17V; 1.10V nominal – 1 die in package D1
or low V DDQ = 0.57–0.65V; 0.60V nominal – 2 die in package D2
• Frequency range – 4 die in package D4
– 2133–10 MHz (data rate range: 4266–20 Mb/s per • FBGA “green” package
pin) – 200-ball VFBGA (10mm × 14.5mm × DT
• 16n prefetch DDR architecture 0.95mm, Ø0.35 SMD)
• 8 internal banks per channel for concurrent opera- – 200-ball TFBGA (10mm × 14.5mm × FW
tion 1.1mm, Ø0.40 SMD)
• Single-data-rate CMD/ADR entry – 200-ball TFBGA (10mm × 14.5mm × DE
• Bidirectional/differential data strobe per byte lane 1.14mm, Ø0.40 SMD)
• Programmable READ and WRITE latencies (RL/WL) • Speed grade, cycle time
• Programmable and on-the-fly burst lengths (BL = – 468ps @ RL = 36/40 -046
16, 32) • Special option
• Directed per-bank refresh for concurrent bank op- – Automotive grade (package-level A
eration and ease of command scheduling burn-in)
• Up to 8.5 GB/s per die • Operating temperature range
• On-chip temperature sensor to control self refresh – –40°C to +95°C IT
rate – –40°C to +105°C AT
• Partial-array self refresh (PASR) – –40°C to +125°C UT1
• Selectable output drive strength (DS) • Revision :A
• Clock-stop capability
• RoHS-compliant, “green” packaging Note: 1. Based on automotive usage model. Contact
• Programmable V SS (ODT) termination Micron sales representative with questions.
• Single-ended CK and DQS support
• Improved tRFCab/tRFCpb = 280ns/140ns
• AEC-Q100
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate WRITE Latency READ Latency

Grade (MHz) (Mb/s/pin) Set A Set B DBI Disabled DBI Enabled
-046 2133 4266 18 34 36 40
CCM005-554574167-10729
200b_z32m_sdp_ddp_qdp_auto_lpddr4_lpddr4x.pdf – Rev. F 12/2020 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

Features
Device Configuration
The table below shows 16Gb single-channel die configuration used in the package.
Table 2: Device Configuration
1G16 1G32 2G32

(16 Gb/Package) (32 Gb/Package) (64 Gb/Package)
Die organization in Channel A, rank 0 ×16 mode × 1 die ×16 mode × 1 die ×16 mode × 1 die
the package Channel A, rank 1 – – ×16 mode × 1 die
Channel B, rank 0 – ×16 mode × 1 die ×16 mode × 1 die
Channel B, rank 1 – – ×16 mode × 1 die
Die addressing Bank address BA[2:0] BA[2:0] BA[2:0]
Row addresses R[16:0] R[16:0] R[16:0]
Column addresses C[9:0] C[9:0] C[9:0]
Note: 1. Refer to Package Block Diagrams section and SDRAM Addressing section.
Refresh Requirement Parameters
Table 3: Refresh Requirement Parameters
Parameter Symbol 16Gb Single-Channel Die Unit

REFRESH cycle time (all banks) tRFCab 280 ns
REFRESH cycle time (per bank) tRFCpb 140 ns
Per bank refresh to per bank refresh time (different bank) tPBR2PBR 90 ns
Notes: 1. This table only describes refresh parameters which are density dependent.
2. tRFCab and tRFCpb in this table supersede and are improved values from JEDEC specifications. Refer to Re-
fresh Requirement section for all the refresh parameters.
CCM005-554574167-10729

Features
Part Number and Part Marking Information

Part Number Ordering
Micron LPDDR4 devices are available in different configurations and densities. Verify valid part numbers by using
Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit
www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Number Chart

MT 53 E 2G32 D4 DT -046 A IT :A
Micron Technology Design Revision

:A
Product Family
53 = Mobile LPDDR4 SDRAM Operating Temperature
IT = –40°C to +95°C
Operating Voltage AT = –40°C to +105°C
UT = –40°C to +125°C
E = 1.10V VDD2/0.60V or 1.10V VDDQ
Automotive Certification (option)

Configuration A = Package-level burn-in
1G16 = 1 Gig x 16 Blank = Standard
1G32 = 1 Gig x 32
2G32 = 2 Gig x 32
Cycle Time
-046 = 468ps, tCK RL = 36/40
Addressing
D1 = LPDDR4, 1 die
D2 = LPDDR4, 2 die Package Codes
D4 = LPDDR4, 4 die DT = 200-ball VFBGA 10 x 14.5 x 0.95mm (Ø0.35 SMD)
FW = 200-ball TFBGA 10 x 14.5 x 1.1mm (Ø0.40 SMD)
DE = 200-ball TFBGA 10 x 14.5 x 1.14mm (Ø0.40 SMD)
Table 4: Part Number List
Part Number Total Density Data Rate per Pin

MT53E1G16D1FW-046 AIT:A 2GB (16Gb) 4266 Mb/s
MT53E1G16D1FW-046 AAT:A 2GB (16Gb) 4266 Mb/s
MT53E1G32D2FW-046 AIT:A 4GB (32Gb) 4266 Mb/s
MT53E1G32D2FW-046 AAT:A 4GB (32Gb) 4266 Mb/s
MT53E1G32D2FW-046 AUT:A 4GB (32Gb) 4266 Mb/s
MT53E2G32D4DT-046 AIT:A 8GB (64Gb) 4266 Mb/s
MT53E2G32D4DT-046 AAT:A 8GB (64Gb) 4266 Mb/s
MT53E2G32D4DE-046 AIT:A 8GB (64Gb) 4266 Mb/s
MT53E2G32D4DE-046 AAT:A 8GB (64Gb) 4266 Mb/s
FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
CCM005-554574167-10729

Features
Contents
Important Notes and Warnings ....................................................................................................................... 17
General Description ....................................................................................................................................... 17
General Notes ............................................................................................................................................ 18
Package Block Diagrams ................................................................................................................................. 19
Ball Assignments and Descriptions ................................................................................................................. 21
Package Dimensions ....................................................................................................................................... 25
MR0, MR[6:5], MR8, MR13, MR24 Definition ................................................................................................... 28
LPDDR4 IDD Parameters ................................................................................................................................. 29
LPDDR4X IDD Parameters ............................................................................................................................... 31
Functional Description ................................................................................................................................... 33
SDRAM Addressing ......................................................................................................................................... 34
Simplified Bus Interface State Diagram ............................................................................................................ 37
Power-Up and Initialization ............................................................................................................................ 38
Voltage Ramp ............................................................................................................................................. 39
Reset Initialization with Stable Power .......................................................................................................... 41
Power-Off Sequence ....................................................................................................................................... 42
Controlled Power-Off .................................................................................................................................. 42
Uncontrolled Power-Off .............................................................................................................................. 42
Mode Registers ............................................................................................................................................... 43
Mode Register Assignments and Definitions ................................................................................................ 43
Commands and Timing .................................................................................................................................. 69
Truth Tables ................................................................................................................................................... 69
ACTIVATE Command ..................................................................................................................................... 71
Read and Write Access Modes ......................................................................................................................... 73
Preamble and Postamble ................................................................................................................................ 73
Burst READ Operation .................................................................................................................................... 77
Read Timing ............................................................................................................................................... 79
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ..................................................................................... 79
tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) .................................................... 80
tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) ........................................................ 81
Burst WRITE Operation .................................................................................................................................. 83

Write Timing .............................................................................................................................................. 86
tWPRE Calculation for ATE (Automatic Test Equipment) .............................................................................. 87
tWPST Calculation for ATE (Automatic Test Equipment) ............................................................................... 87
MASK WRITE Operation ................................................................................................................................. 88

Mask Write Timing Constraints for BL16 ...................................................................................................... 90
Data Mask and Data Bus Inversion (DBI [DC]) Function ................................................................................... 92
WRITE and MASKED WRITE Operation DQS Control (WDQS Control) ............................................................. 96
WDQS Control Mode 1 – Read-Based Control .............................................................................................. 96
WDQS Control Mode 2 – WDQS_On/Off ...................................................................................................... 96
Preamble and Postamble Behavior ................................................................................................................. 100
Preamble, Postamble Behavior in READ-to-READ Operations ..................................................................... 100
READ-to-READ Operations – Seamless ....................................................................................................... 101
READ-to-READ Operations – Consecutive .................................................................................................. 102
WRITE-to-WRITE Operations – Seamless ................................................................................................... 109
WRITE-to-WRITE Operations – Consecutive ............................................................................................... 112
PRECHARGE Operation ................................................................................................................................. 116
Burst READ Operation Followed by Precharge ............................................................................................ 116
Burst WRITE Followed by Precharge ........................................................................................................... 117
Auto Precharge .............................................................................................................................................. 118
CCM005-554574167-10729

Features
Burst READ With Auto Precharge ............................................................................................................... 118

Burst WRITE With Auto Precharge .............................................................................................................. 119
RAS Lock Function .................................................................................................................................... 123
Delay Time From WRITE-to-READ with Auto Precharge .............................................................................. 124
REFRESH Command ..................................................................................................................................... 125
Burst READ Operation Followed by Per-Bank Refresh .................................................................................. 131
Refresh Requirement ..................................................................................................................................... 132
SELF REFRESH Operation .............................................................................................................................. 133
Self Refresh Entry and Exit ......................................................................................................................... 133
Power-Down Entry and Exit During Self Refresh ......................................................................................... 134
Command Input Timing After Power-Down Exit ......................................................................................... 135
Self Refresh Abort ...................................................................................................................................... 136
MRR, MRW, MPC Commands During tXSR, tRFC ........................................................................................ 136
Power-Down Mode ........................................................................................................................................ 139
Power-Down Entry and Exit ....................................................................................................................... 139
Input Clock Stop and Frequency Change ........................................................................................................ 149
Clock Frequency Change – CKE LOW ......................................................................................................... 149
Clock Stop – CKE LOW ............................................................................................................................... 149
Clock Frequency Change – CKE HIGH ........................................................................................................ 149
Clock Stop – CKE HIGH ............................................................................................................................. 150
MODE REGISTER READ Operation ................................................................................................................ 151
MRR After a READ and WRITE Command .................................................................................................. 152
MRR After Power-Down Exit ...................................................................................................................... 154
MODE REGISTER WRITE ............................................................................................................................... 155
Mode Register Write States ......................................................................................................................... 156
VREF Current Generator (VRCG) ..................................................................................................................... 157
VREF Training ................................................................................................................................................. 159
VREF(CA) Training ........................................................................................................................................ 159
VREF(DQ) Training ....................................................................................................................................... 164
Command Bus Training ................................................................................................................................. 169
Command Bus Training Mode .................................................................................................................... 169
Training Sequence for Single-Rank Systems ................................................................................................ 170
Training Sequence for Multiple-Rank Systems ............................................................................................ 171
Relation Between CA Input Pin and DQ Output Pin ..................................................................................... 172
Write Leveling ............................................................................................................................................... 176
Mode Register Write-WR Leveling Mode ..................................................................................................... 176
Write Leveling Procedure ........................................................................................................................... 176
Input Clock Frequency Stop and Change .................................................................................................... 177
MULTIPURPOSE Operation ........................................................................................................................... 180
Read DQ Calibration Training ........................................................................................................................ 185
Read DQ Calibration Training Procedure .................................................................................................... 185
Read DQ Calibration Training Example ...................................................................................................... 187
MPC[READ DQ CALIBRATION] After Power-Down Exit ............................................................................... 188
Write Training ............................................................................................................................................... 188
Internal Interval Timer .............................................................................................................................. 194
DQS Interval Oscillator Matching Error ...................................................................................................... 196
OSC Count Readout Time .......................................................................................................................... 197
Thermal Offset .............................................................................................................................................. 199
Temperature Sensor ...................................................................................................................................... 199
ZQ Calibration ............................................................................................................................................... 200
ZQCAL Reset ............................................................................................................................................. 201
Multichannel Considerations ..................................................................................................................... 202
CCM005-554574167-10729

Features
ZQ External Resistor, Tolerance, and Capacitive Loading ............................................................................. 202

Frequency Set Points ..................................................................................................................................... 203
Frequency Set Point Update Timing ........................................................................................................... 204
Pull-Up and Pull-Down Characteristics and Calibration .................................................................................. 208
On-Die Termination for the Command/Address Bus ....................................................................................... 209
ODT Mode Register and ODT State Table .................................................................................................... 209
ODT Mode Register and ODT Characteristics ............................................................................................. 210
ODT for CA Update Time ........................................................................................................................... 211
DQ On-Die Termination ................................................................................................................................ 211
Output Driver and Termination Register Temperature and Voltage Sensitivity .............................................. 213
ODT Mode Register ................................................................................................................................... 214
Asynchronous ODT ................................................................................................................................... 214
DQ ODT During Power-Down and Self Refresh Modes ................................................................................ 216
ODT During Write Leveling Mode .............................................................................................................. 216
Target Row Refresh Mode ............................................................................................................................... 216
TRR Mode Operation ................................................................................................................................. 217
Post-Package Repair ...................................................................................................................................... 218
Failed Row Address Repair ......................................................................................................................... 218
Read Preamble Training ................................................................................................................................. 220
Electrical Specifications ................................................................................................................................. 221
Absolute Maximum Ratings ....................................................................................................................... 221
AC and DC Operating Conditions ................................................................................................................... 221
AC and DC Input Measurement Levels ........................................................................................................... 223
Input Levels for CKE .................................................................................................................................. 223
Input Levels for RESET_n ........................................................................................................................... 223
Differential Input Voltage for CK ................................................................................................................ 223
Peak Voltage Calculation Method ............................................................................................................... 224
Single-Ended Input Voltage for Clock ......................................................................................................... 225
Differential Input Slew Rate Definition for Clock ......................................................................................... 226
Differential Input Cross-Point Voltage ........................................................................................................ 227
Differential Input Voltage for DQS .............................................................................................................. 228
Peak Voltage Calculation Method ............................................................................................................... 228
Single-Ended Input Voltage for DQS ........................................................................................................... 229
Differential Input Slew Rate Definition for DQS .......................................................................................... 230
Differential Input Cross-Point Voltage ........................................................................................................ 231
Input Levels for ODT_CA ........................................................................................................................... 232
Output Slew Rate and Overshoot/Undershoot specifications ........................................................................... 232
Single-Ended Output Slew Rate .................................................................................................................. 232
Differential Output Slew Rate ..................................................................................................................... 233
Overshoot and Undershoot Specifications .................................................................................................. 234
Driver Output Timing Reference Load ............................................................................................................ 234
LVSTL I/O System .......................................................................................................................................... 235
Input/Output Capacitance ............................................................................................................................. 236
IDD Specification Parameters and Test Conditions ........................................................................................... 237
IDD Specifications ...................................................................................................................................... 253
AC Timing ..................................................................................................................................................... 255
CA Rx Voltage and Timing .............................................................................................................................. 264
DQ Tx Voltage and Timing ............................................................................................................................. 267
DRAM Data Timing ................................................................................................................................... 267
DQ Rx Voltage and Timing ............................................................................................................................. 268
Clock Specification ........................................................................................................................................ 271
tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 272
CCM005-554574167-10729

Features
Clock Period Jitter .......................................................................................................................................... 272

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 272
Cycle Time Derating for Core Timing Parameters ........................................................................................ 273
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 273
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 273
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 273
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 274
LPDDR4 1.10V V DDQ ...................................................................................................................................... 275
Power-Up and Initialization - LPDDR4 ....................................................................................................... 275
Mode Register Definition - LPDDR4 ........................................................................................................... 276
Burst READ Operation - LPDDR4 ATE Condition ........................................................................................ 285
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ................................................................................ 285
tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) ............................................... 285
tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) ................................................... 287
VREF Specifications - LPDDR4 .................................................................................................................... 289

Internal V REF(CA) Specifications .............................................................................................................. 289
Internal V REF(DQ) Specifications .............................................................................................................. 290
Command Definitions and Timing Diagrams - LPDDR4 .............................................................................. 292
Pull Up/Pull Down Driver Characteristics and Calibration ....................................................................... 292
On-Die Termination for the Command/Address Bus ............................................................................... 292
ODT Mode Register and ODT State Table ................................................................................................ 293
ODT Mode Register and ODT Characteristics ......................................................................................... 294
DQ On-Die Termination ........................................................................................................................ 295
Output Driver and Termination Register Temperature and Voltage Sensitivity .......................................... 298
AC and DC Operating Conditions - LPDDR4 ............................................................................................... 299
Recommended DC Operating Conditions ............................................................................................... 299
Output Slew Rate and Overshoot/Undershoot specifications - LPDDR4 ....................................................... 299
Single-Ended Output Slew Rate .............................................................................................................. 299
Differential Output Slew Rate ................................................................................................................. 300
LVSTL I/O System - LPDDR4 ...................................................................................................................... 301
Revision History ............................................................................................................................................ 303
Rev. F – 12/2020 ......................................................................................................................................... 303
Rev. E – 12/2020 ......................................................................................................................................... 303
Rev. D – 3/2020 .......................................................................................................................................... 303
Rev. C – 2/2020 .......................................................................................................................................... 303
Rev. B – 11/2019 ........................................................................................................................................ 303
Rev. A – 8/2019 .......................................................................................................................................... 303
CCM005-554574167-10729

Features
List of Figures
Figure 1: Part Number Chart ............................................................................................................................ 3
Figure 2: Single-Die, Single-Channel, Single-Rank Package Block Diagram (x16 I/O) ........................................ 19
Figure 3: Dual-Die, Dual-Channel, Single-Rank Package Block Diagram (x32 I/O) ............................................ 19
Figure 4: Quad-Die, Dual-Channel, Dual-Rank Package Block Diagram (x32 I/O) ............................................. 20
Figure 5: 200-Ball Single-Channel, Single-Rank Discrete FBGA (x16 I/O) .......................................................... 21
Figure 6: 200-Ball Dual-Channel, Single-Rank Discrete FBGA (x32 I/O) ............................................................ 22
Figure 7: 200-Ball Dual-Channel, Dual-Rank Discrete FBGA (x32 I/O) ............................................................. 23
Figure 8: 200-Ball VFBGA – 10mm x 14.5mm x 0.95mm (Package Code: DT) ..................................................... 25
Figure 9: 200-Ball TFBGA – 10mm x 14.5mm x 1.1mm (Package Code: FW) ...................................................... 26
Figure 10: 200-Ball TFBGA – 10mm x 14.5mm x 1.14mm (Package Code: DE) ................................................... 27
Figure 11: Functional Block Diagram ............................................................................................................. 34
Figure 12: Simplified State Diagram ............................................................................................................... 37
Figure 13: Simplified State Diagram ............................................................................................................... 38
Figure 14: Voltage Ramp and Initialization Sequence ...................................................................................... 40
Figure 15: ACTIVATE Command .................................................................................................................... 72
Figure 16: tFAW Timing .................................................................................................................................. 73
Figure 17: DQS Read Preamble and Postamble – Toggling Preamble and 0.5nCK Postamble ............................. 74
Figure 18: DQS Read Preamble and Postamble – Static Preamble and 1.5nCK Postamble .................................. 74
Figure 19: DQS Write Preamble and Postamble – 0.5nCK Postamble ................................................................ 75
Figure 20: DQS Write Preamble and Postamble – 1.5nCK Postamble ................................................................ 76
Figure 21: Burst Read Timing ......................................................................................................................... 77
Figure 22: Burst Read Followed by Burst Write or Burst Mask Write .................................................................. 78
Figure 23: Seamless Burst Read ...................................................................................................................... 78
Figure 24: Read Timing .................................................................................................................................. 79
Figure 25: tLZ(DQS) Method for Calculating Transitions and Endpoint ............................................................ 80
Figure 26: tHZ(DQS) Method for Calculating Transitions and Endpoint ........................................................... 80
Figure 27: tLZ(DQ) Method for Calculating Transitions and Endpoint .............................................................. 81
Figure 28: tHZ(DQ) Method for Calculating Transitions and Endpoint ............................................................. 82
Figure 29: Burst WRITE Operation ................................................................................................................. 84
Figure 30: Burst Write Followed by Burst Read ................................................................................................ 85
Figure 31: Write Timing ................................................................................................................................. 86
Figure 32: Method for Calculating tWPRE Transitions and Endpoints ............................................................... 87
Figure 33: Method for Calculating tWPST Transitions and Endpoints ............................................................... 87
Figure 34: MASK WRITE Command – Same Bank ........................................................................................... 88
Figure 35: MASK WRITE Command – Different Bank ...................................................................................... 89
Figure 36: MASKED WRITE Command with Write DBI Enabled; DM Enabled .................................................. 94
Figure 37: WRITE Command with Write DBI Enabled; DM Disabled ................................................................ 95
Figure 38: WDQS Control Mode 1 .................................................................................................................. 96
Figure 39: Burst WRITE Operation ................................................................................................................. 98
Figure 40: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Disable) ............................... 99
Figure 41: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Enable) ............................... 100
Figure 42: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble ........................................... 101
Figure 43: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble ......................................... 102
Figure 44: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble .................................... 102
Figure 45: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble ..................................... 103
CCM005-554574167-10729

Features
Figure 55: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble ......................................................................... 109
Figure 56: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency ≤ 800 MHz, ODT
Worst Timing Case ..................................................................................................................................... 110
Figure 57: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble ......................................................................... 111
Figure 58: Consecutive WRITE: tCCD = MIN + 1, 0.5nCK Postamble ................................................................ 112
Figure 65: Burst READ Followed by Precharge – BL16, Toggling Preamble, 0.5nCK Postamble .......................... 117
Figure 66: Burst READ Followed by Precharge – BL32, 2tCK, 0.5nCK Postamble ............................................... 117
Figure 67: Burst WRITE Followed by PRECHARGE – BL16, 2nCK Preamble, 0.5nCK Postamble ........................ 118
Figure 68: Burst READ With Auto Precharge – BL16, Non-Toggling Preamble, 0.5nCK Postamble ..................... 119
Figure 69: Burst READ With Auto Precharge – BL32, Toggling Preamble, 1.5nCK Postamble ............................. 119
Figure 70: Burst WRITE With Auto Precharge – BL16, 2 nCK Preamble, 0.5nCK Postamble ................................ 120
Figure 71: Command Input Timing with RAS Lock ......................................................................................... 124
Figure 72: Delay Time From WRITE-to-READ with Auto Precharge ................................................................. 124
Figure 73: All-Bank REFRESH Operation ....................................................................................................... 127
Figure 74: Per-Bank REFRESH Operation ...................................................................................................... 128
Figure 75: Postponing REFRESH Commands (Example) ................................................................................. 130
Figure 76: Pulling in REFRESH Commands (Example) ................................................................................... 130
Figure 77: Burst READ Operation Followed by Per-Bank Refresh ..................................................................... 131
Figure 78: Burst READ With AUTO PRECHARGE Operation Followed by Per-Bank Refresh .............................. 132
Figure 79: Self Refresh Entry/Exit Timing ...................................................................................................... 134
Figure 80: Self Refresh Entry/Exit Timing with Power-Down Entry/Exit .......................................................... 135
Figure 81: Command Input Timings after Power-Down Exit During Self Refresh ............................................. 136
Figure 82: MRR, MRW, and MPC Commands Issuing Timing During tXSR ....................................................... 137
Figure 83: MRR, MRW, and MPC Commands Issuing Timing During tRFC ...................................................... 138
Figure 84: Basic Power-Down Entry and Exit Timing ...................................................................................... 140
Figure 85: Read and Read with Auto Precharge to Power-Down Entry ............................................................. 141
Figure 86: Write and Mask Write to Power-Down Entry .................................................................................. 142
Figure 87: Write With Auto Precharge and Mask Write With Auto Precharge to Power-Down Entry ................... 143
Figure 88: Refresh Entry to Power-Down Entry .............................................................................................. 144
Figure 89: ACTIVATE Command to Power-Down Entry .................................................................................. 144
Figure 90: PRECHARGE Command to Power-Down Entry .............................................................................. 145
Figure 91: Mode Register Read to Power-Down Entry ..................................................................................... 146
Figure 92: Mode Register Write to Power-Down Entry .................................................................................... 147
Figure 93: MULTI PURPOSE Command for ZQCAL Start to Power-Down Entry ............................................... 148
Figure 94: MODE REGISTER READ Operation ............................................................................................... 152
Figure 95: READ-to-MRR Timing .................................................................................................................. 153
Figure 96: WRITE-to-MRR Timing ................................................................................................................. 154
Figure 97: MRR Following Power-Down ......................................................................................................... 155
Figure 98: MODE REGISTER WRITE Timing .................................................................................................. 155
Figure 99: VRCG Enable Timing .................................................................................................................... 158
Figure 100: VRCG Disable Timing ................................................................................................................. 158
Figure 101: V REF Operating Range (VREF,max, V REF,min) ..................................................................................... 159
CCM005-554574167-10729

Features
Figure 102: V REF Set-Point Tolerance and Step Size ........................................................................................ 160
Figure 103: tV
ref for Short, Middle, and Long Timing Diagram ......................................................................... 161
Figure 104: V REF(CA) Single-Step Increment .................................................................................................... 161
Figure 105: V REF(CA) Single-Step Decrement ................................................................................................... 162
Figure 106: V REF(CA) Full Step from V REF,min to V REF,max .................................................................................... 162
Figure 107: V REF(CA) Full Step from V REF,max to V REF,min .................................................................................... 162
Figure 108: V REF Operating Range (VREF,max, V REF,min) ..................................................................................... 164
Figure 109: V REF Set Tolerance and Step Size .................................................................................................. 165
Figure 110: V REF(DQ) Transition Time for Short, Middle, or Long Changes ........................................................ 166
Figure 111: V REF(DQ) Single-Step Size Increment ............................................................................................. 166
Figure 112: V REF(DQ) Single-Step Size Decrement ............................................................................................ 167
Figure 113: V REF(DQ) Full Step from V REF,min to V REF,max ................................................................................... 167
Figure 114: V REF(DQ) Full Step from V REF,max to V REF,min ................................................................................... 167
Figure 115: Command Bus Training Mode Entry – CA Training Pattern I/O with V REF(CA) Value Update ............ 172
Figure 116: Consecutive V REF(CA) Value Update .............................................................................................. 173
Figure 117: Command Bus Training Mode Exit with Valid Command .............................................................. 174
Figure 118: Command Bus Training Mode Exit with Power-Down Entry .......................................................... 175
Figure 119: Write Leveling Timing – tDQSL(MAX) .......................................................................................... 177
Figure 120: Write Leveling Timing – tDQSL(MIN) ........................................................................................... 177
Figure 121: Clock Stop and Timing During Write Leveling .............................................................................. 178
Figure 122: DQS_t/DQS_c to CK_t/CK_c Timings at the Pins Referenced from the Internal Latch .................... 179
Figure 123: WRITE-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK ............................................................................ 181
Figure 124: READ-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK, tRPRE = Toggling, tRPST = 1.5nCK ......................... 182
Figure 125: READ-FIFO – tRPRE = Toggling, tRPST = 1.5nCK ........................................................................... 183
Figure 126: Read DQ Calibration Training Timing: Read-to-Read DQ Calibration ............................................ 186
Figure 127: Read DQ Calibration Training Timing: Read DQ Calibration to Read DQ Calibration/Read ............ 186
Figure 128: MPC[READ DQ CALIBRATION] Following Power-Down State ....................................................... 188
Figure 129: WRITE-to-MPC[WRITE-FIFO] Operation Timing ......................................................................... 190
Figure 130: MPC[WRITE-FIFO]-to-MPC[READ-FIFO] Timing ........................................................................ 191
Figure 131: MPC[READ-FIFO] to Read Timing ............................................................................................... 192
Figure 132: MPC[WRITE-FIFO] with DQ ODT Timing .................................................................................... 193
Figure 133: Power-Down Exit to MPC[WRITE-FIFO] Timing ........................................................................... 194
Figure 134: Interval Oscillator Offset – OSCoffset ............................................................................................. 196
Figure 135: In Case of DQS Interval Oscillator is Stopped by MPC Command .................................................. 197
Figure 136: In Case of DQS Interval Oscillator is Stopped by DQS Interval Timer ............................................. 198
Figure 137: Temperature Sensor Timing ........................................................................................................ 200
Figure 138: ZQCAL Timing ............................................................................................................................ 201
Figure 139: Frequency Set Point Switching Timing ......................................................................................... 205
Figure 140: Training for Two Frequency Set Points ......................................................................................... 207
Figure 141: Example of Switching Between Two Trained Frequency Set Points ................................................ 207
Figure 142: Example of Switching to a Third Trained Frequency Set Point ....................................................... 208
Figure 143: ODT for CA ................................................................................................................................. 209
Figure 144: ODT for CA Setting Update Timing in 4-Clock Cycle Command .................................................... 211
Figure 145: Functional Representation of DQ ODT ........................................................................................ 212
Figure 146: Asynchronous ODTon/ODToff Timing ......................................................................................... 215
Figure 147: Target Row Refresh Mode ............................................................................................................ 218
Figure 148: Post-Package Repair Timing ........................................................................................................ 219
Figure 149: Read Preamble Training .............................................................................................................. 220
Figure 150: Input Timing Definition for CKE .................................................................................................. 223
Figure 151: Input Timing Definition for RESET_n .......................................................................................... 223
Figure 152: CK Differential Input Voltage ....................................................................................................... 224
Figure 153: Definition of Differential Clock Peak Voltage ................................................................................ 225
CCM005-554574167-10729

Features
Figure 154: Clock Single-Ended Input Voltage ................................................................................................ 225

Figure 155: Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 226
Figure 156: V ix Definition (Clock) .................................................................................................................. 227
Figure 157: DQS Differential Input Voltage .................................................................................................... 228
Figure 158: Definition of Differential DQS Peak Voltage .................................................................................. 229
Figure 159: DQS Single-Ended Input Voltage ................................................................................................. 229
Figure 160: Differential Input Slew Rate Definition for DQS_t, DQS_c ............................................................. 230
Figure 161: V ix Definition (DQS) .................................................................................................................... 231
Figure 162: Single-Ended Output Slew Rate Definition ................................................................................... 233
Figure 163: Differential Output Slew Rate Definition ...................................................................................... 233
Figure 164: Overshoot and Undershoot Definition ......................................................................................... 234
Figure 165: Driver Output Timing Reference Load ......................................................................................... 235
Figure 166: LVSTL I/O Cell ............................................................................................................................ 235
Figure 167: Pull-Up Calibration ..................................................................................................................... 236
Figure 168: tCMDCKE Timing ....................................................................................................................... 259
Figure 169: tESCKE Timing ........................................................................................................................... 262
Figure 170: CA Receiver (Rx) Mask ................................................................................................................ 264

Figure 171: Across Pin V REF (CA) Voltage Variation ........................................................................................... 264
Figure 172: CA Timings at the DRAM Pins ..................................................................................................... 265
Figure 173: CA tcIPW and SRIN_cIVW Definition (for Each Input Pulse) .......................................................... 265
Figure 174: CA V IHL_AC Definition (for Each Input Pulse) ................................................................................ 265
Figure 175: Read Data Timing Definitions – tQH and tDQSQ Across DQ Signals per DQS Group ....................... 267
Figure 176: DQ Receiver (Rx) Mask ................................................................................................................ 268
Figure 177: Across Pin V REF DQ Voltage Variation ........................................................................................... 268
Figure 178: DQ-to-DQS tDQS2DQ and tDQDQ .............................................................................................. 269
Figure 179: DQ tDIPW and SRIN_dIVW Definition for Each Input Pulse .......................................................... 270
Figure 180: DQ V IHL(AC) Definition (for Each Input Pulse) ............................................................................... 270
Figure 181: tLZ(DQS) Method for Calculating Transitions and Endpoint ......................................................... 285
Figure 182: tHZ(DQS) Method for Calculating Transitions and Endpoint ......................................................... 286
Figure 183: tLZ(DQ) Method for Calculating Transitions and Endpoint ........................................................... 287
Figure 184: tHZ(DQ) Method for Calculating Transitions and Endpoint .......................................................... 287
Figure 185: ODT for CA ................................................................................................................................. 293

Figure 186: Functional Representation of DQ ODT ........................................................................................ 296
Figure 187: Single-Ended Output Slew Rate Definition ................................................................................... 300
Figure 188: Differential Output Slew Rate Definition ...................................................................................... 301
Figure 189: LVSTL I/O Cell ............................................................................................................................ 301
Figure 190: Pull-Up Calibration ..................................................................................................................... 302
CCM005-554574167-10729

Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Device Configuration .......................................................................................................................... 2
Table 3: Refresh Requirement Parameters ........................................................................................................ 2
Table 4: Part Number List ................................................................................................................................ 3
Table 5: Ball/Pad Descriptions ....................................................................................................................... 24
Table 6: Mode Register Contents .................................................................................................................... 28
Table 7: LPDDR4 IDD Specifications under 4266 Mb/s – Single Die .................................................................. 29
Table 8: LPDDR4 IDD6 Full-Array Self Refresh Current ..................................................................................... 30
Table 9: LPDDR4X IDD Specifications under 4266 Mb/s – Single Die ................................................................ 31
Table 10: LPDDR4X IDD6 Full-Array Self Refresh Current ................................................................................. 32
Table 11: SDRAM Addressing – Dual-Channel Die .......................................................................................... 35
Table 12: SDRAM Addressing – Single-Channel Die ......................................................................................... 36
Table 13: Mode Register Default Settings ........................................................................................................ 39
Table 14: Voltage Ramp Conditions ................................................................................................................ 39
Table 15: Initialization Timing Parameters ...................................................................................................... 41
Table 16: Reset Timing Parameter .................................................................................................................. 42
Table 17: Power Supply Conditions ................................................................................................................ 42
Table 18: Power-Off Timing ............................................................................................................................ 43
Table 19: Mode Register Assignments ............................................................................................................. 43
Table 20: MR0 Device Feature 0 (MA[5:0] = 00h) .............................................................................................. 44
Table 21: MR0 Op-Code Bit Definitions .......................................................................................................... 44
Table 24: Burst Sequence for Read .................................................................................................................. 47
Table 25: Burst Sequence for Write ................................................................................................................. 47
Table 28: Frequency Ranges for RL, WL, nWR, and nRTP Settings .................................................................... 50
Table 29: MR3 I/O Configuration 1 (MA[5:0] = 03h) ......................................................................................... 50
Table 31: MR4 Device Temperature (MA[5:0] = 04h) ........................................................................................ 52
Table 33: MR5 Basic Configuration 1 (MA[5:0] = 05h) ...................................................................................... 53
Table 41: MR9 Test Mode (MA[5:0] = 09h) ....................................................................................................... 54
Table 42: MR9 Op-Code Definitions ............................................................................................................... 54
Table 43: MR10 Calibration (MA[5:0] = 0Ah) ................................................................................................... 54
Table 44: MR10 Op-Code Bit Definitions ........................................................................................................ 55
Table 45: MR11 ODT Control (MA[5:0] = 0Bh) ................................................................................................. 55
Table 47: MR12 Register Information (MA[5:0] = 0Ch) ..................................................................................... 56
Table 49: MR13 Register Control (MA[5:0] = 0Dh) ............................................................................................ 56
Table 50: MR13 Op-Code Bit Definition .......................................................................................................... 57
CCM005-554574167-10729

Features
Table 51: Mode Register 14 (MA[5:0] = 0Eh) .................................................................................................... 58

Table 52: MR14 Op-Code Bit Definition .......................................................................................................... 58
Table 53: V REF Setting for Range[0] and Range[1] ............................................................................................. 59
Table 54: MR15 Register Information (MA[5:0] = 0Fh) ..................................................................................... 60
Table 55: MR15 Op-code Bit Definition .......................................................................................................... 60
Table 56: MR15 Invert Register Pin Mapping ................................................................................................... 60
Table 57: MR16 PASR Bank Mask (MA[5:0] = 010h) .......................................................................................... 60
Table 59: MR17 PASR Segment Mask (MA[5:0] = 11h) ...................................................................................... 61
Table 60: MR17 PASR Segment Mask Definitions ............................................................................................ 61
Table 61: MR17 PASR Segment Mask .............................................................................................................. 61
Table 62: MR18 Register Information (MA[5:0] = 12h) ..................................................................................... 62
Table 63: MR18 LSB DQS Oscillator Count ...................................................................................................... 62
Table 65: MR19 DQS Oscillator Count ............................................................................................................ 62
Table 67: MR20 Register Information ............................................................................................................. 63
Table 68: MR20 Invert Register Pin Mapping ................................................................................................... 63
Table 78: MR26:29 Register Information (MA[5:0] = 1Ah–1Dh) ......................................................................... 66
Table 79: MR30 Register Information (MA[5:0] = 1Eh) ..................................................................................... 67
Table 81: MR31 Register Information (MA[5:0] = 1Fh) ..................................................................................... 67
Table 84: MR33:38 Register Information (MA[5:0] = 21h–26h) .......................................................................... 68
Table 89: MR41:47 Register Information (MA[5:0] = 29h–2Fh) .......................................................................... 69
Table 90: MR48:63 Register Information (MA[5:0] = 30h–3Fh) .......................................................................... 69
Table 91: Command Truth Table .................................................................................................................... 69
Table 92: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements ..................................................... 81
Table 93: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements ........................................................ 82
Table 94: Method for Calculating tWPRE Transitions and Endpoints ................................................................ 87
Table 95: Reference Voltage for tWPST Timing Measurements ......................................................................... 88
Table 96: Same Bank (ODT Disabled) ............................................................................................................. 90
Table 97: Different Bank (ODT Disabled) ........................................................................................................ 90
Table 98: Same Bank (ODT Enabled) .............................................................................................................. 91
Table 99: Different Bank (ODT Enabled) ......................................................................................................... 91
Table 100: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations ............... 92
Table 101: WDQS_On/WDQS_Off Definition .................................................................................................. 97
Table 102: WDQS_On/WDQS_Off Allowable Variation Range .......................................................................... 97
CCM005-554574167-10729

Features
Table 103: DQS Turn-Around Parameter ......................................................................................................... 98

Table 104: Precharge Bank Selection ............................................................................................................. 116
Table 105: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable ............... 120
Table 106: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Enable ................ 123
Table 107: Bank and Refresh Counter Increment Behavior ............................................................................. 125
Table 108: REFRESH Command Timing Constraints ...................................................................................... 127
Table 109: Legacy REFRESH Command Timing Constraints ........................................................................... 129
Table 110: Modified REFRESH Command Timing Constraints ........................................................................ 129
Table 111: Refresh Requirement Parameters .................................................................................................. 132
Table 112: MRR ............................................................................................................................................ 151
Table 113: Truth Table for MRR and MRW ..................................................................................................... 156
Table 114: MRR/MRW Timing Constraints: DQ ODT is Disable ...................................................................... 156
Table 115: MRR/MRW Timing Constraints: DQ ODT is Enable ....................................................................... 157
Table 116: VRCG Enable/Disable Timing ....................................................................................................... 158
Table 117: Internal V REF(CA) Specifications ..................................................................................................... 163
Table 118: Internal V REF(DQ) Specifications .................................................................................................... 168
Table 119: Mapping MR12 Op Code and DQ Numbers ................................................................................... 170
Table 120: Mapping CA Input Pin and DQ Output Pin .................................................................................... 172
Table 121: Write Leveling Timing Parameters ................................................................................................. 178
Table 122: Write Leveling Setup and Hold Timing .......................................................................................... 178
Table 123: MPC Command Definition ........................................................................................................... 180
Table 124: MPC Commands .......................................................................................................................... 181
Table 125: Timing Constraints for Training Commands .................................................................................. 183
Table 126: Invert Mask Assignments .............................................................................................................. 185
Table 127: Read DQ Calibration Bit Ordering and Inversion Example .............................................................. 187
Table 128: MR Setting vs. DMI Status ............................................................................................................. 188
Table 129: MPC[WRITE-FIFO] AC Timing ...................................................................................................... 194
Table 130: DQS Oscillator Matching Error Specification ................................................................................. 196
Table 131: DQS Interval Oscillator AC Timing ................................................................................................ 198
Table 132: Temperature Sensor ..................................................................................................................... 200
Table 133: ZQ Calibration Parameters ........................................................................................................... 201
Table 134: Mode Register Function With Two Physical Registers ..................................................................... 203
Table 135: Relation Between MR Setting and DRAM Operation ...................................................................... 204
Table 136: Frequency Set Point AC Timing ..................................................................................................... 205
Table 137: tFC Value Mapping ....................................................................................................................... 205
Table 138: tFC Value Mapping: Example ........................................................................................................ 206
Table 139: Pull-Down Driver Characteristics – ZQ Calibration ........................................................................ 208

Table 140: Pull-Up Characteristics – ZQ Calibration ....................................................................................... 208
Table 141: Valid Calibration Points ................................................................................................................ 208
Table 142: Command Bus ODT State ............................................................................................................. 210
Table 143: ODT DC Electrical Characteristics for Command/Address Bus ....................................................... 210
Table 144: ODT DC Electrical Characteristics for DQ Bus ............................................................................... 212
Table 145: Output Driver and Termination Register Sensitivity Definition ....................................................... 213
Table 146: Output Driver and Termination Register Temperature and Voltage Sensitivity ................................. 213
Table 147: ODTLON and ODTLOFF Latency Values .......................................................................................... 215
Table 148: Termination State in Write Leveling Mode ..................................................................................... 216
Table 149: Post-Package Repair Timing Parameters ........................................................................................ 219
Table 150: Absolute Maximum DC Ratings .................................................................................................... 221
Table 151: Recommended DC Operating Conditions ..................................................................................... 221
Table 152: Input Leakage Current .................................................................................................................. 221
Table 153: Input/Output Leakage Current ..................................................................................................... 222
Table 154: Operating Temperature Range ...................................................................................................... 222
CCM005-554574167-10729

Features
Table 155: Input Levels ................................................................................................................................. 223

Table 156: Input Levels ................................................................................................................................. 223
Table 157: CK Differential Input Voltage ........................................................................................................ 224
Table 158: Clock Single-Ended Input Voltage ................................................................................................. 226
Table 159: Differential Input Slew Rate Definition for CK_t, CK_c ................................................................... 226
Table 160: Differential Input Level for CK_t, CK_c .......................................................................................... 227
Table 161: Differential Input Slew Rate for CK_t, CK_c .................................................................................... 227
Table 162: Cross-Point Voltage for Differential Input Signals (Clock) ............................................................... 228
Table 163: DQS Differential Input Voltage ...................................................................................................... 228
Table 164: DQS Single-Ended Input Voltage ................................................................................................... 230
Table 165: Differential Input Slew Rate Definition for DQS_t, DQS_c .............................................................. 230
Table 166: Differential Input Level for DQS_t, DQS_c ..................................................................................... 231
Table 167: Differential Input Slew Rate for DQS_t, DQS_c ............................................................................... 231
Table 168: Cross-Point Voltage for Differential Input Signals (DQS) ................................................................ 232
Table 169: Input Levels for ODT_CA .............................................................................................................. 232
Table 170: Single-Ended Output Slew Rate .................................................................................................... 232
Table 171: Differential Output Slew Rate ....................................................................................................... 233
Table 172: AC Overshoot/Undershoot Specifications ..................................................................................... 234
Table 173: Overshoot/Undershoot Specification for CKE and RESET .............................................................. 234
Table 174: Input/Output Capacitance ........................................................................................................... 236
Table 175: IDD Measurement Conditions ....................................................................................................... 237
Table 176: CA Pattern for IDD4R for BL = 16 ..................................................................................................... 237
Table 177: CA Pattern for IDD4W for BL = 16 .................................................................................................... 238
Table 178: Data Pattern for IDD4W (DBI Off) for BL = 16 .................................................................................. 238
Table 179: Data Pattern for IDD4R (DBI Off) for BL = 16 ................................................................................... 239
Table 180: Data Pattern for IDD4W (DBI On) for BL = 16 ................................................................................... 241
Table 181: Data Pattern for IDD4R (DBI On) for BL = 16 .................................................................................... 242
Table 182: CA Pattern for IDD4R for BL = 32 ..................................................................................................... 243
Table 183: CA Pattern for IDD4W for BL = 32 .................................................................................................... 244
Table 184: Data Pattern for IDD4W (DBI Off) for BL = 32 .................................................................................. 245
Table 185: Data Pattern for IDD4R (DBI Off) for BL = 32 ................................................................................... 246
Table 186: Data Pattern for IDD4W (DBI On) for BL = 32 ................................................................................... 248
Table 187: Data Pattern for IDD4R (DBI On) for BL = 32 .................................................................................... 250
Table 188: IDD Specification Parameters and Operating Conditions ................................................................ 253
Table 189: Clock Timing ............................................................................................................................... 255
Table 190: Read Output Timing ..................................................................................................................... 255
Table 191: Write Timing ................................................................................................................................ 257
Table 192: CKE Input Timing ........................................................................................................................ 258
Table 193: Command Address Input Timing .................................................................................................. 259
Table 194: Boot Timing Parameters (10–55 MHz) ........................................................................................... 260
Table 195: Mode Register Timing Parameters ................................................................................................. 260
Table 196: Core Timing Parameters ............................................................................................................... 260
Table 197: CA Bus ODT Timing ..................................................................................................................... 262
Table 198: CA Bus Training Parameters .......................................................................................................... 262
Table 199: Asynchronous ODT Turn On and Turn Off Timing ......................................................................... 263
Table 200: Temperature Derating Parameters ................................................................................................ 263
Table 201: DRAM CMD/ADR, CS ................................................................................................................... 266
Table 202: DQs In Receive Mode ................................................................................................................... 270
Table 203: Definitions and Calculations ........................................................................................................ 271
Table 204: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................. 272
Table 205: Mode Register Default Settings ..................................................................................................... 275

Table 206: Mode Register Assignments .......................................................................................................... 276
CCM005-554574167-10729

Features
Table 207: MR0 Device Feature 0 (MA[5:0] = 00h) ........................................................................................... 277

Table 208: MR0 Op-Code Bit Definitions ....................................................................................................... 277
Table 209: MR3 I/O Configuration 1 (MA[5:0] = 03h) ...................................................................................... 278
Table 210: MR3 Op-Code Bit Definitions ....................................................................................................... 279
Table 211: MR12 Register Information (MA[5:0] = 0Ch) .................................................................................. 280
Table 212: MR12 Op-Code Bit Definitions ...................................................................................................... 280
Table 213: Mode Register 14 (MA[5:0] = 0Eh) ................................................................................................. 280
Table 214: MR14 Op-Code Bit Definition ....................................................................................................... 281
Table 215: V REF Setting for Range[0] and Range[1] .......................................................................................... 282
Table 216: MR22 Register Information (MA[5:0] = 16h) ................................................................................... 283
Table 217: MR22 Register Information ........................................................................................................... 283
Table 218: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements .................................................. 286
Table 219: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements ..................................................... 288
Table 220: Internal V REF(CA) Specifications ..................................................................................................... 289
Table 221: Internal V REF(DQ) Specifications .................................................................................................... 290
Table 222: Pull-Down Driver Characteristics – ZQ Calibration ........................................................................ 292
Table 223: Pull-Up Characteristics – ZQ Calibration ....................................................................................... 292
Table 224: Terminated Valid Calibration Points .............................................................................................. 292
Table 225: Command Bus ODT State ............................................................................................................. 293
Table 226: ODT DC Electrical Characteristics for Command/Address Bus – up to 3200 Mb/s ........................... 294
Table 227: ODT DC Electrical Characteristics for Command/Address Bus – Beyond 3200 Mb/s ....................... 295
Table 228: ODT DC Electrical Characteristics for DQ Bus– up to 3200 Mb/s .................................................... 296
Table 229: ODT DC Electrical Characteristics for DQ Bus – Beyond 3200 Mb/s ................................................ 297
Table 230: Output Driver and Termination Register Sensitivity Definition ....................................................... 298
Table 231: Output Driver and Termination Register Temperature and Voltage Sensitivity ................................. 298
Table 232: Recommended DC Operating Conditions ..................................................................................... 299
Table 233: Single-Ended Output Slew Rate .................................................................................................... 299
Table 234: Differential Output Slew Rate ....................................................................................................... 300
CCM005-554574167-10729

Important Notes and Warnings
Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
General Description
The 16Gb low-power DDR4 SDRAM (LPDDR4) or low V DDQ (LPDDR4X) is a high-speed,
CMOS dynamic random-access memory device. This 8-bank device is internally config-
ured with ×16 I/O.
CCM005-554574167-10729

General Description
Each of the ×16 2,147,483,648-bit banks is organized as 131,072 rows by 1024 columns
by 16 bits.
General Notes
Throughout the data sheet, figures and text refer to DQs as DQ. DQ should be interpre-
ted as any or all DQ collectively, unless stated otherwise.
DQS and CK should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively, un-
less stated otherwise. CA includes all CA pins used for a given density.
In timing diagrams, CMD is used as an indicator only. Actual signals occur on CA[5:0].
VREF indicates V REF(CA) and V REF(DQ).
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all re-
quirements.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, not sup-
ported, and will result in unknown operation.
For single-ended CK and DQS features or specifications, refer to the LPDDR4X Single-
Ended CK and DQS Addendum.
CCM005-554574167-10729

Package Block Diagrams
Figure 2: Single-Die, Single-Channel, Single-Rank Package Block Diagram (x16 I/O)
VDD1 VDD2 VSS VDDQ

VDDQ
Die RZQ
ZQ
RESET_n
CS DMI[1:0]
CKE LPDDR4 DQ[15:0]
DQS[1:0]_t
CK_t DQS[1:0]_c
CK_c
CA[5:0] ODT_CA ODT_CA
Figure 3: Dual-Die, Dual-Channel, Single-Rank Package Block Diagram (x32 I/O)

VDD1 VDD2 VSS VDDQ
VDDQ
Die RZQ
ZQ0
RESET_n
CS0_A DMI[1:0]_A
CKE0_A LPDDR4 DQ[15:0]_A
Channel A DQS[1:0]_t_A
CK_t_A DQS[1:0]_c_A
CK_c_A
CA[5:0]_A ODT_CA ODT_CA_A
Die
CS0_B DMI[1:0]_B
CKE0_B LPDDR4 DQ[15:0]_B
Channel B DQS[1:0]_t_B
CK_t_B DQS[1:0]_c_B
CK_c_B
CA[5:0]_B ODT_CA ODT_CA_B
CCM005-554574167-10729

Figure 4: Quad-Die, Dual-Channel, Dual-Rank Package Block Diagram (x32 I/O)

VDD1 VDD2 VSS VDDQ
VDDQ
Die RZQ
ZQ0
RESET_n
CS0_A DMI[1:0]_A
CKE0_A LPDDR4 DQ[15:0]_A
Channel A DQS[1:0]_t_A
CK_t_A DQS[1:0]_c_A
CK_c_A
CA[5:0]_A ODT_CA ODT_CA_A
Die
CS0_B DMI[1:0]_B
CKE0_B LPDDR4 DQ[15:0]_B
Channel B DQS[1:0]_t_B
CK_t_B DQS[1:0]_c_B
CK_c_B
CA[5:0]_B ODT_CA ODT_CA_B
VDDQ
Die RZQ
ZQ1
CS1_A
CKE1_A LPDDR4
Channel A
ODT_CA
VSS
Die
CS1_B
CKE1_B LPDDR4
Channel B
ODT_CA
VSS
Note: 1. ODT(ca) for rank 0 of each channel is wired to the respective ODT ball. ODT(ca) for rank
1 of each channel is wired to VSS in the package.
CCM005-554574167-10729

Ball Assignments and Descriptions
Figure 5: 200-Ball Single-Channel, Single-Rank Discrete FBGA (x16 I/O)

1 2 3 4 5 6 7 8 9 10 11 12
A DNU DNU VSS VDD2 ZQ NC VDD2 VSS DNU DNU
B DNU DQ0 VDDQ DQ7 VDDQ VDDQ DQ15 VDDQ DQ8 DNU
C VSS DQ1 DMI0 DQ6 VSS VSS DQ14 DMI1 DQ9 VSS
D VDDQ VSS DQS0_t VSS VDDQ VDDQ VSS DQS1_t VSS VDDQ
E VSS DQ2 DQS0_c DQ5 VSS VSS DQ13 DQS1_c DQ10 VSS
F VDD1 DQ3 VDDQ DQ4 VDD2 VDD2 DQ12 VDDQ DQ11 VDD1
G VSS ODT_CA VSS VDD1 VSS VSS VDD1 VSS NC VSS
H VDD2 CA0 NC CS VDD2 VDD2 CA2 CA3 CA4 VDD2
J VSS CA1 VSS CKE NC CK_t CK_c VSS CA5 VSS
K VDD2 VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2
N VDD2 VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2
P VSS NC VSS NC NC NC NC VSS NC VSS
R VDD2 NC NC NC VDD2 VDD2 NC NC NC VDD2
T VSS NC VSS VDD1 VSS VSS VDD1 VSS RESET_n VSS
U VDD1 NC VDDQ NC VDD2 VDD2 NC VDDQ NC VDD1
V VSS NC NC NC VSS VSS NC NC NC VSS
W VDDQ VSS NC VSS VDDQ VDDQ VSS NC VSS VDDQ
Y VSS NC NC NC VSS VSS NC NC NC VSS
AA DNU NC VDDQ NC VDDQ VDDQ NC VDDQ NC DNU
AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU DNU
1 2 3 4 5 6 7 8 9 10 11 12
Top View (ball down)
LPDDR4 ZQ, ODT_CA, RESET Supply Ground
CCM005-554574167-10729

Figure 6: 200-Ball Dual-Channel, Single-Rank Discrete FBGA (x32 I/O)

1 2 3 4 5 6 7 8 9 10 11 12
A DNU DNU VSS VDD2 ZQ0 NC VDD2 VSS DNU DNU
B DNU DQ0_A VDDQ DQ7_A VDDQ VDDQ DQ15_A VDDQ DQ8_A DNU
C VSS DQ1_A DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSS
D VDDQ VSS DQS0_t_A VSS VDDQ VDDQ VSS DQS1_t_A VSS VDDQ
E VSS DQ2_A DQS0_c_A DQ5_A VSS VSS DQ13_A DQS1_c_A DQ10_A VSS
F VDD1 DQ3_A VDDQ DQ4_A VDD2 VDD2 DQ12_A VDDQ DQ11_A VDD1
G VSS ODT_CA_A VSS VDD1 VSS VSS VDD1 VSS NC VSS
H VDD2 CA0_A NC CS0_A VDD2 VDD2 CA2_A CA3_A CA4_A VDD2
J VSS CA1_A VSS CKE0_A NC CK_t_A CK_c_A VSS CA5_A VSS
P VSS CA1_B VSS CKE0_B NC CK_t_B CK_c_B VSS CA5_B VSS
R VDD2 CA0_B NC CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2
T VSS ODT_CA_B VSS VDD1 VSS VSS VDD1 VSS RESET_n VSS
U VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1
V VSS DQ2_B DQS0_c_B DQ5_B VSS VSS DQ13_B DQS1_c_B DQ10_B VSS
W VDDQ VSS DQS0_t_B VSS VDDQ VDDQ VSS DQS1_t_B VSS VDDQ
Y VSS DQ1_B DMI0_B DQ6_B VSS VSS DQ14_B DMI1_B DQ9_B VSS
AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15_B VDDQ DQ8_B DNU
1 2 3 4 5 6 7 8 9 10 11 12
LPDDR4_A (Channel A) LPDDR4_B (Channel B) ZQ, ODT_CA, RESET Supply Ground
CCM005-554574167-10729

Figure 7: 200-Ball Dual-Channel, Dual-Rank Discrete FBGA (x32 I/O)

1 2 3 4 5 6 7 8 9 10 11 12
A DNU DNU VSS VDD2 ZQ0 ZQ1 VDD2 VSS DNU DNU
B DNU DQ0_A VDDQ DQ7_A VDDQ VDDQ DQ15_A VDDQ DQ8_A DNU
C VSS DQ1_A DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSS
D VDDQ VSS DQS0_t_A VSS VDDQ VDDQ VSS DQS1_t_A VSS VDDQ
E VSS DQ2_A DQS0_c_A DQ5_A VSS VSS DQ13_A DQS1_c_A DQ10_A VSS
F VDD1 DQ3_A VDDQ DQ4_A VDD2 VDD2 DQ12_A VDDQ DQ11_A VDD1
G VSS ODT_CA_A VSS VDD1 VSS VSS VDD1 VSS NC VSS
H VDD2 CA0_A CS1_A CS0_A VDD2 VDD2 CA2_A CA3_A CA4_A VDD2
J VSS CA1_A VSS CKE0_A CKE1_A CK_t_A CK_c_A VSS CA5_A VSS
P VSS CA1_B VSS CKE0_B CKE1_B CK_t_B CK_c_B VSS CA5_B VSS
R VDD2 CA0_B CS1_B CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2
T VSS ODT_CA_B VSS VDD1 VSS VSS VDD1 VSS RESET_n VSS
U VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1
V VSS DQ2_B DQS0_c_B DQ5_B VSS VSS DQ13_B DQS1_c_B DQ10_B VSS
W VDDQ VSS DQS0_t_B VSS VDDQ VDDQ VSS DQS1_t_B VSS VDDQ
Y VSS DQ1_B DMI0_B DQ6_B VSS VSS DQ14_B DMI1_B DQ9_B VSS
AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15_B VDDQ DQ8_B DNU
1 2 3 4 5 6 7 8 9 10 11 12
LPDDR4_A (Channel A) LPDDR4_B (Channel B) ZQ, ODT_CA, RESET Supply Ground
CCM005-554574167-10729

Table 5: Ball/Pad Descriptions
Symbol Type Description

CK_t_A, CK_c_A, Input Clock: CK_t and CK_c are differential clock inputs. All address, command and control in-
CK_t_B, CK_c_B put signals are sampled on positive edge of CK_t and the negative edge of CK_c. AC tim-
ings for CA parameters are referenced to clock. Each channel (A, B) has its own clock pair.
CKE0_A, CKE1_A, Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, in-
CKE0_B, CKE1_B put buffers, and output drivers. Power-saving modes are entered and exited via CKE tran-
sitions. CKE is sampled at the rising edge of CK.
CS0_A, CS1_A, Input Chip select: Each channel (A, B) has its own CS signals.
CS0_B, CS1_B
CA[5:0]_A, Input Command/address inputs: Provide the command and address inputs according to the
CA[5:0]_B command truth table. Each channel (A, B) has its own CA signals.
ODT_CA_A, Input LPDDR4 CA ODT control: The ODT_CA pin is used in conjunction with the mode register
ODT_CA_B to turn on/off the on-die termination for CA pins. It is bonded to VDD2 within the package,
or at the package ball, for the terminating rank, and the non-terminating ranks are bon-
ded to VSS (or left floating with a weak pull-down on the DRAM die). The terminating
rank is the DRAM that terminates the CA bus for all die on the same channel.
LPDDR4X CA ODT control: The ODT_CA pin is ignored by LPDDR4X devices. CA ODT is
fully controlled through MR11 and MR22. The ODT_CA pin shall be connected to a valid
logic level.
RESET_n Input RESET: When asserted LOW, the RESET pin resets all channels of the die.
DQ[15:0]_A, I/O Data input/output: Bidirectional data bus.
DQ[15:0]_B
DQS[1:0]_t_A, I/O Data strobe: DQS_t and DQS_c are bi-directional differential output clock signals used to
DQS[1:0]_c_A, strobe data during a READ or WRITE. The data strobe is generated by the DRAM for a
DQS[1:0]_t_B, READ and is edge-aligned with data. The data strobe is generated by the SoC memory
DQS[1:0]_c_B controller for a WRITE and is trained to precede data. Each byte of data has a data strobe
signal pair. Each channel (A, B) has its own DQS_t and DQS_c strobes.
DMI[1:0]_A, I/O Data mask/data bus inversion: Data mask inversion (DMI) is a dual use bidirectional sig-
DMI[1:0]_B nal used to indicate data to be masked, and data which is inverted on the bus. For data
bus inversion (DBI), the DMI signal is driven HIGH when the data on the data bus is inver-
ted, or driven LOW when the data is in its normal state. DBI can be disabled via a mode
register setting. For data mask, the DMI signal is used in combination with the data lines
to indicate data to be masked in a MASK WRITE command (see the Data Mask (DM) and
Data Bus Inversion (DBI) sections for details). The data mask function can be disabled via a
mode register setting. Each byte of data has a DMI signal. Each channel has its own DMI
signals.
ZQ0, ZQ1 Reference ZQ calibration reference: Used to calibrate the output drive strength and the termina-
tion resistance. The ZQ pin shall be connected to VDDQ through a 240Ω ±1% resistor.
VDDQ, VDD1, VDD2 Supply Power supplies: Isolated on the die for improved noise immunity.
VSS Supply Ground reference: Power supply ground reference.
DNU – Do not use: Must be grounded or left floating.
NC – No connect: Not internally connected.
CCM005-554574167-10729

Package Dimensions
Package Dimensions
Figure 8: 200-Ball VFBGA – 10mm x 14.5mm x 0.95mm (Package Code: DT)
Seating plane
A 0.08 A
200X Ø0.363 ±0.05

Dimensions apply to
solder balls post-reflow Ball A1 ID Ball A1 ID
on Ø0.35 SMD ball pads.
12 11 10 9 8 5 4 3 2 1
A
B
C
D
E
F
G
H
J
14.5 ±0.1 K
L
13.65 CTR M
N
P
R
T
U
V
W
Y
AA
0.65 TYP AB
0.8 TYP 0.85 ±0.1
8.8 CTR 0.227 ±0.05
10 ±0.1
Notes: 1. All dimensions are in millimeters.

2. Solder ball composition: SAC302 with NiAu pads (96.8% Sn, 3.0% Ag, 0.2% Cu).
CCM005-554574167-10729

Package Dimensions
Figure 9: 200-Ball TFBGA – 10mm x 14.5mm x 1.1mm (Package Code: FW)
Seating plane
A 0.08 A
200X Ø0.436 ±0.05

Dimensions apply to
12 11 10 9 8 5 4 3 2 1
A
B
C
D
E
F
G
H
J
14.5 ±0.1 K
L
13.65 CTR M
N
P
R
T
U
V
W
Y
AA
0.65 TYP AB
0.8 TYP 1 ±0.1
8.8 CTR 0.306 ±0.05
10 ±0.1

2. Solder ball composition: SACQ with CuOSP pads (Sn, 4% Ag, 0.5% Cu, 3% Bi, 0.05% Ni).
CCM005-554574167-10729

Package Dimensions
Figure 10: 200-Ball TFBGA – 10mm x 14.5mm x 1.14mm (Package Code: DE)
Seating plane
A 0.08 A
200X Ø0.436 ±0.05

Dimensions apply to
12 11 10 9 8 5 4 3 2 1
A
B
C
D
E
F
G
H
J
14.5 ±0.1 K
L
13.65 CTR M
N
P
R
T
U
V
W
Y
AA
0.65 TYP AB
0.8 TYP 1.04 ±0.1
8.8 CTR 0.306 ±0.05
10 ±0.1

2. Solder ball composition: SACQ with CuOSP pads (Sn, 4% Ag, 0.5% Cu, 3% Bi, 0.05% Ni).
CCM005-554574167-10729

MR0, MR[6:5], MR8, MR13, MR24 Definition
MR0, MR[6:5], MR8, MR13, MR24 Definition
Table 6: Mode Register Contents

Notes 1 and 2 apply to entire table.
Mode Register OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
MR0 Single- Latency REF
ended mode
mode
OP[0] = 0b: Both legacy and modified refresh mode supported
OP[1] = 0b: Device supports normal latency
OP[5] = 1b: Device supports single-ended mode
MR5 Manufacturer ID
1111 1111b : Micron
MR6 Revision ID1
0000 0110b
MR8 I/O width Density
OP[7:6] = OP[5:2] = 0110b: 16Gb single-channel die
00b: x16/channel
MR13 VRO
OP[2] = 0b: Normal operation (default)
1b: Output the VREF(CA) value on DQ7 and VREF(DQ) value on DQ6
MR24 TRR Unlimited MAC value
mode MAC
OP[3:0] = 1000b: Unlimited MAC
OP[7] = 0b: Disable (default)
1b: Reserved
Notes: 1. The contents of MR0, MR[6:5], MR8, MR13, and MR24 reflect information specific to
each die in these packages.
2. Other bits not defined above and other mode registers are referred to Mode Register
Assignments and Definitions section.
CCM005-554574167-10729

LPDDR4 IDD Parameters

Refer to LPDDR4 IDD Specification Parameters and Test Conditions section for detailed
conditions.
Table 7: LPDDR4 IDD Specifications under 4266 Mb/s – Single Die

VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V
TC/4266 Mb/s
Parameter Supply 95°C 105°C 125°C Unit Note
IDD01 VDD1 5.2 5.2 6.0 mA
IDD02 VDD2 37.0 37.0 39.0
IDD0Q VDDQ 0.75 0.75 0.75
IDD2P1 VDD1 2.2 2.2 3.8 mA
IDD2P2 VDD2 4.6 4.6 5.0
IDD2PQ VDDQ 0.75 0.75 0.75
IDD2PS1 VDD1 2.2 2.2 3.8 mA
IDD2PS2 VDD2 4.6 4.6 5.0
IDD2PSQ VDDQ 0.75 0.75 0.75
IDD2N1 VDD1 2.2 2.2 3.7 mA
IDD2N2 VDD2 20.0 20.0 21.0
IDD2NQ VDDQ 0.75 0.75 0.75
IDD2NS1 VDD1 2.2 2.2 3.7 mA
IDD2NS2 VDD2 18.0 18.0 19.0
IDD2NSQ VDDQ 0.75 0.75 0.75
IDD3P1 VDD1 2.2 2.2 4.0 mA
IDD3P2 VDD2 9.8 9.8 9.8
IDD3PQ VDDQ 0.75 0.75 0.75
IDD3PS1 VDD1 2.2 2.2 4.0 mA
IDD3PS2 VDD2 9.8 9.8 9.8
IDD3PSQ VDDQ 0.75 0.75 0.75
IDD3N1 VDD1 2.7 2.7 4.4 mA
IDD3N2 VDD2 26.0 26.0 27.0
IDD3NQ VDDQ 0.75 0.75 0.75
IDD3NS1 VDD1 2.7 2.7 4.4 mA
IDD3NS2 VDD2 25.0 25.0 26.0
IDD3NSQ VDDQ 0.75 0.75 0.75
IDD4R1 VDD1 4.7 4.7 5.6 mA 2, 3
IDD4R2 VDD2 285 285 293
IDD4RQ VDDQ 79.6 79.6 79.6
IDD4W1 VDD1 3.3 3.3 4.0 mA 2
IDD4W2 VDD2 217 217 224
IDD4WQ VDDQ 0.75 0.75 0.75
CCM005-554574167-10729

Table 7: LPDDR4 IDD Specifications under 4266 Mb/s – Single Die (Continued)
VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V
TC/4266 Mb/s
IDD51 @tRFC = 280ns VDD1 34.0 34.0 34.0 mA
IDD52 @tRFC = 280ns VDD2 164 164 178
IDD5Q @tRFC = 280ns VDDQ 0.75 0.75 0.75
IDD51 @tRFC = 380ns VDD1 26.0 26.0 26.0 mA
IDD52 @tRFC = 380ns VDD2 124 124 134
IDD5Q @tRFC = 380ns VDDQ 0.75 0.75 0.75
IDD5AB1 VDD1 4.7 4.7 8.2 mA
IDD5AB2 VDD2 29.0 29.0 31.0
IDD5ABQ VDDQ 0.75 0.75 0.75
IDD5PB1 VDD1 4.7 4.7 8.2 mA
IDD5PB2 VDD2 29.0 29.0 31.0
IDD5PBQ VDDQ 0.75 0.75 0.75
Notes: 1. Published IDD values except IDD4RQ are the maximum IDD values considering the worst-
case conditions of process, temperature, and voltage.
2. BL = 16, DBI disabled.
3. IDD4RQ value is reference only. Typical value. VOH = VDDQ/3, TC = 25°C.
Table 8: LPDDR4 IDD6 Full-Array Self Refresh Current

VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V
Self Refresh Current
Temperature Supply Full-Array 1/2-Array 1/4-Array 1/8-Array Unit
25°C VDD1 0.40 0.40 0.40 0.40 mA
VDD2 0.90 0.90 0.90 0.90
VDDQ 0.01 0.01 0.01 0.01
95°C VDD1 6.2 4.6 3.8 3.4
VDD2 28.0 19.0 13.0 10.0
VDDQ 0.75 0.75 0.75 0.75
105°C VDD1 6.2 4.6 3.8 3.4
VDD2 28.0 19.0 13.0 10.0
VDDQ 0.75 0.75 0.75 0.75
Notes: 1. IDD6 25°C is the typical value in the distribution with nominal VDD and a reference-only
value, IDD6 95°C and IDD6 105°C are the maximum IDD value considering the worst-case
conditions of process, temperature, and voltage.
2. When TC > 105°C, self refresh mode is not available.
CCM005-554574167-10729

LPDDR4X IDD Parameters

Refer to LPDDR4X IDD Specification Parameters and Test Conditions section for detailed
conditions.
Table 9: LPDDR4X IDD Specifications under 4266 Mb/s – Single Die

VDD2 = 1.06–1.17V; VDDQ = 0.57–0.65V; VDD1 = 1.70–1.95V
TC/4266 Mb/s
IDD01 VDD1 5.2 5.2 6.0 mA
IDD02 VDD2 37.0 37.0 39.0
IDD0Q VDDQ 0.75 0.75 0.75
IDD2P1 VDD1 2.2 2.2 3.8 mA
IDD2P2 VDD2 4.6 4.6 5.0
IDD2PQ VDDQ 0.75 0.75 0.75
IDD2PS1 VDD1 2.2 2.2 3.8 mA
IDD2PS2 VDD2 4.6 4.6 5.0
IDD2PSQ VDDQ 0.75 0.75 0.75
IDD2N1 VDD1 2.2 2.2 3.7 mA
IDD2N2 VDD2 20.0 20.0 21.0
IDD2NQ VDDQ 0.75 0.75 0.75
IDD2NS1 VDD1 2.2 2.2 3.7 mA
IDD2NS2 VDD2 18.0 18.0 19.0
IDD2NSQ VDDQ 0.75 0.75 0.75
IDD3P1 VDD1 2.2 2.2 4.0 mA
IDD3P2 VDD2 9.8 9.8 9.8
IDD3PQ VDDQ 0.75 0.75 0.75
IDD3PS1 VDD1 2.2 2.2 4.0 mA
IDD3PS2 VDD2 9.8 9.8 9.8
IDD3PSQ VDDQ 0.75 0.75 0.75
IDD3N1 VDD1 2.7 2.7 4.4 mA
IDD3N2 VDD2 26.0 26.0 27.0
IDD3NQ VDDQ 0.75 0.75 0.75
IDD3NS1 VDD1 2.7 2.7 4.4 mA
IDD3NS2 VDD2 25.0 25.0 26.0
IDD3NSQ VDDQ 0.75 0.75 0.75
IDD4R1 VDD1 4.7 4.7 5.6 mA 2, 3
IDD4R2 VDD2 285 285 293
IDD4RQ VDDQ 61.6 61.6 61.6
IDD4W1 VDD1 3.3 3.3 4.0 mA 2
IDD4W2 VDD2 217 217 224
IDD4WQ VDDQ 0.75 0.75 0.75
CCM005-554574167-10729

Table 9: LPDDR4X IDD Specifications under 4266 Mb/s – Single Die (Continued)
VDD2 = 1.06–1.17V; VDDQ = 0.57–0.65V; VDD1 = 1.70–1.95V
TC/4266 Mb/s
IDD51 @tRFC = 280ns VDD1 34.0 34.0 34.0 mA
IDD52 @tRFC = 280ns VDD2 164 164 178
IDD5Q @tRFC = 280ns VDDQ 0.75 0.75 0.75
IDD51 @tRFC = 380ns VDD1 26.0 26.0 26.0 mA
IDD52 @tRFC = 380ns VDD2 124 124 134
IDD5Q @tRFC = 380ns VDDQ 0.75 0.75 0.75
IDD5AB1 VDD1 4.7 4.7 8.2 mA
IDD5AB2 VDD2 29.0 29.0 31.0
IDD5ABQ VDDQ 0.75 0.75 0.75
IDD5PB1 VDD1 4.7 4.7 8.2 mA
IDD5PB2 VDD2 29.0 29.0 31.0
IDD5PBQ VDDQ 0.75 0.75 0.75
Notes: 1. Published IDD values except IDD4RQ are the maximum IDD values considering the worst-
case conditions of process, temperature, and voltage.
2. BL = 16, DBI disabled.
3. IDD4RQ value is reference only. Typical value. VOH = 0.5 × VDDQ, TC = 25°C.
Table 10: LPDDR4X IDD6 Full-Array Self Refresh Current

VDD2 = 1.06–1.17V; VDDQ = 0.57–0.65V; VDD1 = 1.70–1.95V
Self Refresh Current
Temperature Supply Full-Array 1/2-Array 1/4-Array 1/8-Array Unit
25°C VDD1 0.40 0.40 0.40 0.40 mA
VDD2 0.90 0.90 0.90 0.90
VDDQ 0.01 0.01 0.01 0.01
95°C VDD1 6.2 4.6 3.8 3.4
VDD2 28.0 19.0 13.0 10.0
VDDQ 0.75 0.75 0.75 0.75
105°C VDD1 6.2 4.6 3.8 3.4
VDD2 28.0 19.0 13.0 10.0
VDDQ 0.75 0.75 0.75 0.75
Notes: 1. IDD6 25°C is the typical value in the distribution with nominal VDD and a reference-only
value, IDD6 95°C and IDD6 105°C are the maximum IDD value considering the worst-case
conditions of process, temperature, and voltage.
2. When TC > 105°C, self refresh mode is not available.
CCM005-554574167-10729

Functional Description
Functional Description
The mobile low-power DDR4 SDRAM (LPDDR4) is a high-speed CMOS, dynamic ran-
dom-access memory internally configured with either 1 or 2 channels. Each channel is
comprised of 16 DQs and 8 banks.
LPDDR4 uses a 2-tick, single-data-rate (SDR) protocol on the CA bus to reduce the
number of input signals in the system. The term "2-tick" means the command/address
is decoded across two transactions, such that half of the command/address is captured
with each of two consecutive rising edges of CK. The 6-bit CA bus contains command,
address, and bank information. Some commands such as READ, WRITE, MASKED
WRITE, and ACTIVATE require two consecutive 2-tick SDR commands to complete the
instruction.
LPDDR4 uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed
operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle
and is matched to a 16n-prefetch DRAM architecture. A write/read access consists of a
single 16n-bit-wide data transfer to/from the DRAM core and 16 corresponding n-bit-
wide data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected
column address and continue for a programmed number of columns in a programmed
sequence.
Accesses begin with the registration of an ACTIVATE command to open a row in the
memory core, followed by a WRITE or READ command to access column data within
the open row. The address and bank address (BA) bits registered by the ACTIVATE com-
mand are used to select the bank and row to be opened. The address and BA bits regis-
tered with the WRITE or READ command are used to select the bank and the starting
column address for the burst access.
Prior to normal operation, the LPDDR4 SDRAM must be initialized. Following sections
provide detailed information about device initialization, register definition, command
descriptions and device operations.
CCM005-554574167-10729

SDRAM Addressing
Figure 11: Functional Block Diagram

VDDQ
RZQ
To CLK, CS, CA ODT calibration DQ ODT control
ZQ
ZQ Cal To DQS, DQ, DMI ODT calibration
RESET Control
CKE logic
CK_t, CK_c
CS_n Bank 7 COL[3:0]
Bank 7 Bank 6
Command/Address
CA[5:0]
Bank 6 Bank 5
Multiplex and
ODT_CA Bank 5 Bank 4

Decode
Bank 4 Bank 3 Read 16n n

RCVRS Bank 3 Bank 2 16n MUX DRVRS Read data path
Bank 2 Bank 1 latch
DATA
Bank 1 Bank 0
Bank 0
x row- DQS
address Memory array generator DQS_t,
Mode Refresh
counter Row- latch DQS_c
registers and (1...n)
address
decoder
CA ODT control MUX
VSS
Sense amplifier
(1...n) RTT,nom
16n
SW
VSS
WRITE n n/16
RTT,nom I/O gating
0–7 FIFO Mask
Bank DM mask logic
SW 16n and Input RCVRS
control drivers registers DQ[n-1:0]
0–7 logic Write data path DQS_t, DQS_c
CK out
CK_t, 16n n DMI
CK in
CK_c
Column Data
Column- y-4 decoder
address
4 COL[3:0]
counter/
latch
SDRAM Addressing
The table below includes all SDRAM addressing options defined by JEDEC. Under the
Device Configuration heading near the beginning of this data sheet are addressing de-
tails for this product data sheet.
CCM005-554574167-10729
200b_z32m_sdp_ddp_qdp_auto_lpddr4_lpddr4x.pdf – Rev. F 12/2020 EN
CCM005-554574167-10729
Table 11: SDRAM Addressing – Dual-Channel Die
Memory Density
(Per Die) 4Gb 6Gb 8Gb 12Gb 16Gb 24Gb 32Gb
Memory density 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb
(per channel)
Configuration 16Mb × 16DQ 24Mb × 16DQ 32Mb × 16DQ 48Mb × 16DQ 64Mb × 16DQ 96Mb × 16DQ 128Mb × 16DQ
× 8 banks × 8 banks × 8 banks × 8 banks × 8 banks × 8 banks × 8 banks
× 2 channels × 2 channels × 2 channels × 2 channels × 2 channels × 2 channels × 2 channels
Number of chan- 2 2 2 2 2 2 2
nels (per die)
Number of banks 8 8 8 8 8 8 8
(per channel)

Array prefetch 256 256 256 256 256 256 256
(bits, per channel)

Number of rows 16,384 24,576 32,768 49,152 65,536 98,304 131,072
(per channel)
Number of col- 64 64 64 64 64 64 64
umns (fetch boun-
35
daries)
Page size (bytes) 2048 2048 2048 2048 2048 2048 2048
Channel density 2,147,483,648 3,221,225,472 4,294,967,296 6,442,450,944 8,589,934,592 12,884,901,888 17,179,869,184
(bits per channel)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Total density (bits 4,294,967,296 6,442,450,944 8,589,934,592 12,884,901,888 17,179,869,184 25,769,803,776 34,359,738,368
per die)
Bank address BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0]
×16 Row add R[13:0] R[14:0] R[14:0] R[15:0] R[15:0] R[16:0] R[16:0]
(R13 = 0 when (R14 = 0 when (R15 = 0 when
R14 = 1) R15 = 1) R16 = 1)
Col. add C[9:0] C[9:0] C[9:0] C[9:0] C[9:0] C[9:0] C[9:0]
SDRAM Addressing
Burst starting ad- 64-bit 64-bit 64-bit 64-bit 64-bit 64-bit 64-bit
dress boundary
CCM005-554574167-10729
Table 12: SDRAM Addressing – Single-Channel Die
Memory Density
(Per Die) 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb
Memory density 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb
(per channel)
Configuration 16Mb × 16 DQ 24Mb × 16 DQ 32Mb × 16 DQ 48Mb × 16 DQ 64Mb × 16 DQ 96Mb × 16 DQ 128Mb × 16 DQ
× 8 banks × 8 banks × 8 banks × 8 banks × 8 banks × 8 banks × 8 banks
Number of chan- 1 1 1 1 1 1 1
nels (per die)
Number of banks 8 8 8 8 8 8 8
(per channel)
Array prefetch 256 256 256 256 256 256 256

(bits, per channel)

Number of rows 16,384 24,576 32,768 49,152 65,536 98,304 131,072
(per channel)
Number of col- 64 64 64 64 64 64 64
umns (fetch boun-
daries)
36
Page size (bytes) 2048 2048 2048 2048 2048 2048 2048
Channel density 2,147,483,648 3,221,225,472 4,294,967,296 6,442,450,944 8,589,934,592 12,884,901,888 17,179,869,184
(bits per channel)
Total density (bits 2,147,483,648 3,221,225,472 4,294,967,296 6,442,450,944 8,589,934,592 12,884,901,888 17,179,869,184
per die)
Bank address BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0]
×16 Row add R[13:0] R[14:0] R[14:0] R[15:0] R[15:0] R[16:0] R[16:0]
(R13 = 0 when (R14 = 0 when (R15 = 0 when
R14 = 1) R15 = 1) R16 = 1)
Col. add C[9:0] C[9:0] C[9:0] C[9:0] C[9:0] C[9:0] C[9:0]
SDRAM Addressing
Burst starting ad- 64-bit 64-bit 64-bit 64-bit 64-bit 64-bit 64-bit
dress boundary
Notes: 1. The lower two column addresses (C[1:0]) are assumed to be zero and are not transmitted on the CA bus.
2. Row and column address values on the CA bus that are not used for a particular density should be at valid logic
levels.
3. For non-binary memory densities, only a quarter of the row address space is invalid. When the MSB address bit is
HIGH, then the MSB - 1 address bit must be LOW.

Simplified Bus Interface State Diagram
Simplified Bus Interface State Diagram

The state diagram provides a simplified illustration of the bus interface, supported state
transitions, and the commands that control them. For a complete description of device
behavior, use the information provided in the state diagram with the truth tables and
timing specifications. The truth tables describe device behavior and applicable restric-
tions when considering the actual state of all banks. For command descriptions, see the
Commands and Timing section.
Figure 12: Simplified State Diagram

Automatic sequence
Command sequence
MPC-
Power-on based
training
MR
MR
write
read
RE = L
MPC- MPC
SR
SE
based
T_
RR
power-
M
n
training MR
RW
M
down write
Reset MR
Per bank write
CK
RW
E
CK
Command refresh
=
M
MPC
RW
E
REF
L
bus
=
MRW M
RE = H
H
training
SE
T_
MRW
n
MPC- SRE REF MPC MPC-

MPC Self All bank
based Idle refresh based
refresh SRX
training training
R MR M
W RR
MR
MR
W
Command
MR read
bus MR
=L
=H
training read
MR
CKE
MRW
CKE
ACT
Idle
MR write MR read
power-
down
Activating
Active
power- MR
down write
MR
CK
RW
write
E
MR read
CK
M
=
E
R
L
MR W
=
MR
H
MPC- REF MPC

Bank Per bank MPC-
based
active refresh based
training
training
M WR RD M
or RR
WR or MWR WR RD
RA
MR
W
Write or
M
Read read
or
mask write
RD
RA
A
W
WRA or
PRE or PREA RDA
MWRA
A PRE(A) = PRECHARGE (ALL)
PR
E PRE
ACT = ACTIVATE
or or
PR E Read WR(A) = WRITE (with auto precharge)
Write or mask EA PR with auto MWR(A) = Mask WRITE
write with precharge (with auto precharge)
auto RD(A) = READ (with auto precharge)
precharge MRW = MODE REGISTER WRITE
MRR = MODE REGISTER READ
Precharging "CKE = L" = Enter power-down
"CKE = H" = Exit power-down
SRE = Enter self refresh
SRX = Exit self refresh
REF = REFRESH
MPC = Mult-purpose command (with NOP)
Notes: 1. From the self refresh state, the device can enter power-down, MRR, MRW, or any of the
training modes initiated with the MPC command. See the Self Refresh section.
CCM005-554574167-10729

Power-Up and Initialization
2. All banks are precharged in the idle state.

3. In the case of using an MRW command to enter a training mode, the state machine will
not automatically return to the idle state at the conclusion of training. See the applica-
ble training section for more information.
4. In the case of an MPC command to enter a training mode, the state machine may not
automatically return to the idle state at the conclusion of training. See the applicable
training section for more information.
5. This diagram is intended to provide an overview of the possible state transitions and
commands to control them; however, it does not contain the details necessary to oper-
ate the device. In particular, situations involving more than one bank are not captured
in complete detail.
6. States that have an "automatic return" and can be accessed from more than one prior
state (that is, MRW from either idle or active states) will return to the state where they
were initiated (that is, MRW from idle will return to idle).
7. The RESET pin can be asserted from any state and will cause the device to enter the re-
set state. The diagram shows RESET applied from the power-on and idle states as an ex-
ample, but this should not be construed as a restriction on RESET.
8. MRW commands from the active state cannot change operating parameters of the de-
vice that affect timing. Mode register fields which may be changed via MRW from the
active state include: MR1-OP[3:0], MR1-OP[7], MR3-OP[7:6], MR10-OP[7:0], MR11-
OP[7:0], MR13-OP[5], MR15-OP[7:0], MR16-OP[7:0], MR17-OP[7:0], MR20-OP[7:0], and
MR22-OP[4:0].
Figure 13: Simplified State Diagram

a) FIFO-Based Write/Read Timing b) Read DQ Calibration
MPC MPC MPC

Automatic sequence
Command sequence Write Read DQ

MPC MPC MPC
-FIFO -FIFO Calibration
MPC-
MPC =
based
training WRW MPC
MRW
WRW
c) ZQCAL Start d) ZQCAL Latch
ZQ ZQ
MPC Calibration MPC Calibration
Start Latch

To ensure proper functionality for power-up and reset initialization, default values for
the MR settings are provided in the table below.
CCM005-554574167-10729

Table 13: Mode Register Default Settings
Item Mode Register Setting Default Setting Description

FSP-OP/WR MR13 OP[7:6] 00b FSP-OP/WR[0] are enabled
WLS MR2 OP[6] 0b WRITE latency set A is selected
WL MR2 OP[5:3] 000b WL = 4
RL MR2 OP[2:0] 000b RL = 6, nRTP = 8
nWR MR1 OP[6:4] 000b nWR = 6
DBI-WR/RD MR3 OP[7:6] 00b Write and read DBI are disa-
bled
CA ODT MR11 OP[6:4] 000b CA ODT is disabled
DQ ODT MR11 OP[2:0] 000b DQ ODT is disabled
VREF(CA) setting MR12 OP[6] 1b VREF(CA) range[1] is enabled
VREF(CA) value MR12 OP[5:0] 011101b Range1: 50.3% of VDDQ
VREF(DQ) setting MR14 OP[6] 1b VREF(DQ) range[1] enabled
VREF(DQ) value MR14 OP[5:0] 011101b Range1: 50.3% of VDDQ
The following sequence must be used to power up the device. Unless specified other-
wise, this procedure is mandatory. The power-up sequence of all channels must pro-
ceed simultaneously.
Voltage Ramp
1. While applying power (after Ta), RESET_n should be held LOW (≤0.2 × V DD2), and all
other inputs must be between V IL,min and V IH,max. The device outputs remain at High-Z
while RESET_n is held LOW. Power supply voltage ramp requirements are provided in
the table below. V DD1 must ramp at the same time or earlier than V DD2. V DD2 must ramp
at the same time or earlier than V DDQ.
Table 14: Voltage Ramp Conditions
After... Applicable Conditions

Ta is reached VDD1 must be greater than VDD2
VDD2 must be greater than VDDQ - 200mV
Notes: 1. Ta is the point when any power supply first reaches 300mV.
2. Voltage ramp conditions in above table apply between Ta and power-off (controlled or
uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined oper-
ating ranges.
4. Power ramp duration tINIT0 (Tb–Ta) must not exceed 20ms.
5. The voltage difference between any VSS and VSSQ must not exceed 100mV.
2. Following completion of the voltage ramp (Tb), RESET_n must be held LOW for tIN-
IT1. DQ, DMI, DQS_t, and DQS_c voltage levels must be between V SSQ and V DDQ during
voltage ramp to avoid latch-up. CK_t and CK_c, CS, and CA input levels must be be-
tween V SS and V DD2 during voltage ramp to avoid latch-up. Voltage ramp power supply
requirements are provided in the table below.
CCM005-554574167-10729

3. Beginning at Tb, RESET_n must remain LOW for at least tINIT1(Tc), after which RE-
SET_n can be de-asserted to HIGH(Tc). At least 10ns before CKE de-assertion, CKE is
required to be set LOW. All other input signals are "Don't Care."
Figure 14: Voltage Ramp and Initialization Sequence

Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
Power Ramp Reset Initialization Training
tINIT4=5tCK(MIN)
CK_c
CK_t
tINIT0=20ms(MAX) tINIT1=200µs(MIN)
Supplies
RESET_n
tINIT2=10ns(MIN) tINIT3=2ms(MIN)
CKE
tINIT5=2µs(MIN) tZQCAL=1µs(MIN) tZQLAT=MAX(30ns, 8 t CK)(MIN)
CA[5:0] MRW ZQ Cal ZQ Cal CA BUS Write DQ

Exit PD DES MRR DES Start DES Latch DES Training DES Leveling DES Training DES Valid
CS
DQs Valid Valid Valid
Don’t Care
Note: 1. Training is optional and may be done at the system designer's discretion. The order of
training may be different than what is shown here.
4. After RESET_n is de-asserted(Tc), wait at least tINIT3 before activating CKE. CK_t,
CK_c must be started and stabilized for tINIT4 before CKE goes active(Td). CS must re-
main LOW when the controller activates CKE.
5. After CKE is set to HIGH, wait a minimum of tINIT5 to issue any MRR or MRW com-
mands(Te). For MRR and MRW commands, the clock frequency must be within the
range defined for tCKb. Some AC parameters (for example, tDQSCK) could have relaxed
timings (such as tDQSCKb) before the system is appropriately configured.
6. After completing all MRW commands to set the pull-up, pull-down, and Rx termina-
tion values, the controller can issue the ZQCAL START command to the memory(Tf).
This command is used to calibrate the V OH level and the output impedance over proc-
ess, voltage, and temperature. In systems where more than one device share one exter-
nal ZQ resistor, the controller must not overlap the ZQ calibration sequence of each de-
vice. The ZQ calibration sequence is completed after tZQCAL (Tg). The ZQCAL LATCH
command must be issued to update the DQ drivers and DQ + CA ODT to the calibrated
values.
7. After tZQLAT is satisfied (Th), the command bus (internal V REF(CA), CS, and CA)
should be trained for high-speed operation by issuing an MRW command (command
bus training mode). This command is used to calibrate the device's internal V REF and
align CS/CA with CK for high-speed operation. The device will power-up with receivers
configured for low-speed operations and with V REF(CA) set to a default factory setting.
Normal device operation at clock speeds higher than tCKb may not be possible until
command bus training is complete. The command bus training MRW command uses
the CA bus as inputs for the calibration data stream, and it outputs the results asynchro-
CCM005-554574167-10729

nously on the DQ bus. See command bus training in the MRW section for information
on how to enter/exit the training mode.
8. After command bus training, the controller must perform write leveling. Write level-
ing mode is enabled when MR2 OP[7] is HIGH(Ti). See the Write Leveling section for a
detailed description of the write leveling entry and exit sequence. In write leveling
mode, the controller adjusts write DQS timing to the point where the device recognizes
the start of write DQ data burst with desired WRITE latency.
9. After write leveling, the DQ bus (internal V REF(DQ), DQS, and DQ) should be trained
for high-speed operation using the MPC TRAINING commands and by issuing MRW
commands to adjust V REF(DQ). The device will power-up with receivers configured for
low-speed operations and with V REF(DQ) set to a default factory setting. Normal device
operation at clock speeds higher than tCKb should not be attempted until DQ bus train-
ing is complete. The MPC[READ DQ CALIBRATION] command is used together with
MPC[READ-FIFO] or MPC[WRITE-FIFO] commands to train the DQ bus without dis-
turbing the memory array contents. See the DQ Bus Training section for more informa-
tion on the DQ bus training sequence.
10. At Tk, the device is ready for normal operation and is ready to accept any valid com-
mand. Any mode registers that have not previously been configured for normal opera-
tion should be written at this time.
Table 15: Initialization Timing Parameters
Parameter Min Max Unit Comment

tINIT0 – 20 ms Maximum voltage ramp time
tINIT1 200 – µs Minimum RESET_n LOW time after completion of voltage
ramp
tINIT2 10 – ns Minimum CKE LOW time before RESET_n goes HIGH
tINIT3 2 – ms Minimum CKE LOW time after RESET_n goes HIGH
tINIT4 5 – tCK Minimum stable clock before first CKE HIGH
tINIT5 2 – μs Minimum idle time before first MRW/MRR command
tCKb Note 1, 2 Note 1, 2 ns Clock cycle time during boot
Notes: 1. Minimum tCKb guaranteed by DRAM test is 18ns.

2. The system may boot at a higher frequency than dictated by minimum tCKb. The higher
boot frequency is system dependent.
Reset Initialization with Stable Power

The following sequence is required for RESET at no power interruption initialization.
1. Assert RESET_n below 0.2 × V DD2 anytime when reset is needed. RESET_n needs
to be maintained for minimum tPW_RESET. CKE must be pulled LOW at least
10ns before de-asserting RESET_n.
2. Repeat steps 4–10 in Voltage Ramp section.
CCM005-554574167-10729

Power-Off Sequence
Table 16: Reset Timing Parameter
Value
Parameter Min Max Unit Comment
tPW_RESET 100 – ns Minimum RESET_n LOW time for reset initialization
with stable power
Power-Off Sequence
Controlled Power-Off
While powering off, CKE must be held LOW (≤0.2 × V DD2); all other inputs must be be-
tween V IL,min and V IH,max. The device outputs remain at High-Z while CKE is held LOW.
DQ, DMI, DQS_t, and DQS_c voltage levels must be between V SSQ and V DDQ during the
power-off sequence to avoid latch-up. CK_t, CK_c, CS, and CA input levels must be be-
tween V SS and V DD2 during the power-off sequence to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified in
the minimum DC Operating Condition.
Tz is the point where all power supplies are below 300mV. After Tz, the device is pow-
ered off.
Table 17: Power Supply Conditions

The voltage difference between VSS and VSSQ must not exceed 100mV
Between... Applicable Conditions
Tx and Tz VDD1 must be greater than VDD2
VDD2 must be greater than VDDQ - 200mV
Uncontrolled Power-Off
When an uncontrolled power-off occurs, the following conditions must be met:
• At Tx, when the power supply drops below the minimum values specified in the Rec-
ommended DC Operating Conditions table, all power supplies must be turned off and
all power supply current capacity must be at zero, except for any static charge remain-
ing in the system.
• After Tz (the point at which all power supplies first reach 300mV), the device must
power off. During this period, the relative voltage between power supplies is uncon-
trolled. V DD1 and V DD2 must decrease with a slope lower than 0.5 V/µs between Tx
and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of
the device.
CCM005-554574167-10729

Mode Registers
Table 18: Power-Off Timing
Parameter Symbol Min Max Unit

Power-off ramp time tPOFF – 2 sec
Mode Registers
Mode Register Assignments and Definitions
Mode register definitions are provided in the Mode Register Assignments table. In the
access column of the table, R indicates read-only; W indicates write-only; R/W indicates
read- or write-capable or enabled. The MRR command is used to read from a register.
The MRW command is used to write to a register.
Table 19: Mode Register Assignments

Notes 1–5 apply to entire table
MR# MA[5:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0
0 00h Device info R RFU RZQI RFU Latency REF
mode
1 01h Device feature 1 W RD-PST nWR (for AP) RD-PRE WR-PRE BL
2 02h Device feature 2 W WR Lev WLS WL RL
3 03h I/O config-1 W DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL
4 04h Refresh and R /W TUF Thermal offset PPRE SR abort Refresh rate
training
5 05h Basic config-1 R Manufacturer ID
6 06h Basic config-2 R Revision ID1
8 08h Basic config-4 R I/O width Density Type
9 09h Test mode W Vendor-specific test mode
10 0Ah I/O calibration W RFU ZQ RST
11 0Bh ODT W RFU CA ODT RFU DQ ODT
12 0Ch VREF(CA) R/W RFU VRCA VREF(CA)
13 0Dh Register control W FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT
14 0Eh VREF(DQ) R/W RFU VRDQ VREF(DQ)
15 0Fh DQI-LB W Lower-byte invert register for DQ calibration
16 10h PASR_Bank W PASR bank mask
17 11h PASR_Seg W PASR segment mask
18 12h IT-LSB R DQS oscillator count – LSB
19 13h IT-MSB R DQS oscillator count – MSB
20 14h DQI-UB W Upper-byte invert register for DQ calibration
21 15h Vendor use W RFU
22 16h ODT feature 2 W ODTD for x8_2ch ODTD ODTE ODTE SoC ODT
-CA -CS -CK
CCM005-554574167-10729

Mode Registers
Table 19: Mode Register Assignments (Continued)

23 17h DQS oscillator W DQS oscillator run-time setting
stop
24 18h TRR control R/W TRR TRR mode BAn Unltd MAC value
mode MAC
25 19h PPR resources R B7 B6 B5 B4 B3 B2 B1 B0
26–29 1Ah~1D – – Reserved for future use
h
30 1Eh Reserved for W SDRAM will ignore
test
31 1Fh – – Reserved for future use
32 20h DQ calibration W See DQ calibration section
pattern A
33–38 21h≈26h Do not use – Do not use
39 27h Reserved for W SDRAM will ignore
test
pattern B
41–47 29h≈2Fh Do not use – Do not use
48–63 30h≈3Fh Reserved – Reserved for future use
Notes: 1. RFU bits must be set to 0 during MRW commands.

2. RFU bits are read as 0 during MRR commands.
3. All mode registers that are specified as RFU or write-only shall return undefined data
when read via an MRR command.
4. RFU mode registers must not be written.
5. Writes to read-only registers will not affect the functionality of the device.
Table 20: MR0 Device Feature 0 (MA[5:0] = 00h)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

RFU RZQI RFU Latency mode REF
Table 21: MR0 Op-Code Bit Definitions
Register Information Type OP Definition Notes

Refresh mode Read-only OP[0] 0b: Both legacy and modified refresh mode supported
1b: Only modified refresh mode supported
Latency mode Read-only OP[1] 0b: Device supports normal latency 5, 6
1b: Device supports byte mode latency
CCM005-554574167-10729

Mode Registers
Table 21: MR0 Op-Code Bit Definitions (Continued)

Built-in self-test for RZQ in- Read-only OP[4:3] 00b: RZQ self-test not supported 1–4
formation 01b: ZQ may connect to VSSQ or float
10b: ZQ may short to VDDQ
11b: ZQ pin self-test completed, no error condition de-
tected (ZQ may not connect to VSSQ, float, or short to
VDDQ)
Notes: 1. RZQI MR value, if supported, will be valid after the following sequence:
• Completion of MPC[ZQCAL START] command to either channel
• Completion of MPC[ZQCAL LATCH] command to either channel then tZQLAT is satis-
fied
RZQI value will be lost after reset.
2. If ZQ is connected to VSSQ to set default calibration, OP[4:3] must be set to 01b. If ZQ is
not connected to VSSQ, either OP[4:3] = 01b or OP[4:3] = 10b might indicate a ZQ pin as-
sembly error. It is recommended that the assembly error be corrected.
3. In the case of possible assembly error, the device will default to factory trim settings for
RON, and will ignore ZQ CALIBRATION commands. In either case, the device may not
function as intended.
4. If the ZQ pin self-test returns OP[4:3] = 11b, the device has detected a resistor connected
to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or
that the ZQ resistor meets the specified limits (that is, 240Ω ±1%).
5. See byte mode addendum spec for byte mode latency details.
6. Byte mode latency for 2Ch. x16 device is only allowed when it is stacked in a same pack-
age with byte mode device.

RD-PST nWR (for AP) RD-PRE WR-PRE BL
Feature Type OP Definition Notes

BL Write-only OP[1:0] 00b: BL = 16 sequential (default) 1
Burst length 01b: BL = 32 sequential
10b: BL = 16 or 32 sequential (on-the-fly)
11b: Reserved
WR-PRE Write-only OP[2] 0b: Reserved 5, 6
Write preamble length 1b: WR preamble = 2 × tCK
RD-PRE Write-only OP[3] 0b: RD preamble = Static (default) 3, 5, 6

Read preamble type 1b: RD preamble = Toggle
CCM005-554574167-10729

Mode Registers

nWR Write-only OP[6:4] 000b: nWR = 6 (default) 2, 5, 6
Write-recovery for AUTO 001b: nWR = 10
PRECHARGE command
010b: nWR = 16
011b: nWR = 20
100b: nWR = 24
101b: nWR = 30
110b: nWR = 34
111b: nWR = 40
RD-PST Write-only OP[7] 0b: RD postamble = 0.5 × tCK (default) 4, 5, 6
Read postamble length 1b: RD postamble = 1.5 × tCK
Notes: 1. Burst length on-the-fly can be set to either BL = 16 or BL = 32 by setting the BL bit in the
command operands. See the Command Truth Table.
2. The programmed value of nWR is the number of clock cycles the device uses to deter-
mine the starting point of an internal precharge after a write burst with auto precharge
(AP) enabled. See Frequency Ranges for RL, WL, and nWR Settings table.
3. For READ operations, this bit must be set to select between a toggling preamble and a
non-toggling preamble (see the Preamble section).
4. OP[7] provides an optional read postamble with an additional rising and falling edge of
DQS_t. The optional postamble cycle is provided for the benefit of certain memory con-
trollers.
5. There are two physical registers assigned to each bit of this MR parameter: designated
set point 0 and set point 1. Only the registers for the set point determined by the state
of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
address.
set point 0 and set point 1. The device will operate only according to the values stored
in the registers for the active set point, that is, the set point determined by the state of
the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be
ignored by the device and may be changed without affecting device operation.
CCM005-554574167-10729
CCM005-554574167-10729
Table 24: Burst Sequence for Read
C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
16-Bit READ Operation
V 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F
V 0 1 0 0 4 5 6 7 8 9 A B C D E F 0 1 2 3
V 1 0 0 0 8 9 A B C D E F 0 1 2 3 4 5 6 7
V 1 1 0 0 C D E F 0 1 2 3 4 5 6 7 8 9 A B
32-Bit READ Operation
0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0 0 1 0 0 4 5 6 7 8 9 A B C D E F 0 1 2 3 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13
0 1 0 0 0 8 9 A B C D E F 0 1 2 3 4 5 6 7 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17

0 1 1 0 0 C D E F 0 1 2 3 4 5 6 7 8 9 A B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B

1 0 0 0 0 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 1 2 3 4 5 6 7 8 9 A B C D E F
1 0 1 0 0 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 4 5 6 7 8 9 A B C D E F 0 1 2 3
1 1 0 0 0 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 8 9 A B C D E F 0 1 2 3 4 5 6 7
1 1 1 0 0 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B C D E F 0 1 2 3 4 5 6 7 8 9 A B
47
Notes: 1. C[1:0] are not present on the CA bus; they are implied to be zero.
2. The starting burst address is on 64-bit (4n) boundaries.
Table 25: Burst Sequence for Write
C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
16-Bit WRITE Operation
V 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F
32-Bit WRITE Operation
0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
Notes: 1. C[1:0] are not present on the CA bus; they are implied to be zero.
Mode Registers
2. The starting burst address is on 256-bit (16n) boundaries for burst length 16.
3. The starting burst address is on 512-bit (32n) boundaries for burst length 32.
4. C[3:2] must be set to 0 for all WRITE operations.

Mode Registers

WR Lev WLS WL RL

RL Write-only OP[2:0] RL and nRTP for DBI-RD disabled (MR3 OP[6] = 0b) 1, 3, 4
READ latency 000b: RL = 6, nRTP = 8 (default)
001b: RL = 10, nRTP = 8
010b: RL = 14, nRTP = 8
011b: RL = 20, nRTP = 8
100b: RL = 24, nRTP = 10
101b: RL = 28, nRTP = 12
110b: RL = 32, nRTP = 14
111b: RL = 36, nRTP = 16
RL and nRTP for DBI-RD enabled (MR3 OP[6] = 1b)

000b: RL = 6, nRTP = 8
001b: RL = 12,nRTP = 8
010b: RL = 16, nRTP = 8
011b: RL = 22, nRTP = 8
100b: RL = 28, nRTP = 10
101b: RL = 32, nRTP = 12
110b: RL = 36, nRTP = 14
111b: RL = 40, nRTP = 16
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Mode Registers

WL Write- OP[5:3] WL set A (MR2 OP[6] = 0b) 1, 3, 4
WRITE latency only 000b: WL = 4 (default)
001b: WL = 6
010b: WL = 8
011b: WL = 10
100b: WL = 12
101b: WL = 14
110b: WL = 16
111b: WL = 18
WL set B (MR2 OP[6] = 1b)

000b: WL = 4
001b: WL = 8
010b: WL = 12
011b: WL = 18
100b: WL = 22
101b: WL = 26
110b: WL = 30
111b: WL = 34
WLS Write- OP[6] 0b: Use WL set A (default) 1, 3, 4
WRITE latency set only 1b: Use WL set B
WR Lev Write- OP[7] 0b: Disable write leveling (default) 2
Write leveling only 1b: Enable write leveling
Notes: 1. See Latency Code Frequency Table for allowable frequency ranges for RL/WL/nWR.
2. After an MRW command to set the write leveling enable bit (OP[7] = 1b), the device re-
mains in the MRW state until another MRW command clears the bit (OP[7] = 0b). No
other commands are allowed until the write leveling enable bit is cleared.
of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command this MR ad-
dress, or read from with an MRR command to this address.
in the registers for the active set point, that is, the set point determined by the state of
the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be
ignored by the device and may be changed without affecting device operation.
5. nRTP is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value be-
fore starting a precharge.
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Table 28: Frequency Ranges for RL, WL, nWR, and nRTP Settings
READ Latency WRITE Latency Lower Upper

Frequency Frequency
No DBI w/DBI Set A Set B nWR nRTP Limit (>) Limit(≤) Units Notes
6 6 4 4 6 8 10 266 MHz 1–6
10 12 6 8 10 8 266 533
14 16 8 12 16 8 533 800
20 22 10 18 20 8 800 1066
24 28 12 22 24 10 1066 1333
28 32 14 26 30 12 1333 1600
32 36 16 30 34 14 1600 1866
36 40 18 34 40 16 1866 2133
Notes: 1. The device should not be operated at a frequency above the upper frequency limit or
below the lower frequency limit shown for each RL, WL, or nWR value.
2. DBI for READ operations is enabled in MR3 OP[6]. When MR3 OP[6] = 0, then the "No
DBI" column should be used for READ latency. When MR3 OP[6] = 1, then the "w/DBI"
column should be used for READ latency.
3. WRITE latency set A and set B are determined by MR2 OP[6]. When MR2 OP[6] = 0, then
WRITE latency set A should be used. When MR2 OP[6] = 1, then WRITE latency set B
should be used.
4. The programmed value for nRTP is the number of clock cycles the device uses to deter-
mine the starting point of an internal PRECHARGE operation after a READ burst with AP
(auto precharge) enabled . It is determined by RU(tRTP/tCK).
5. The programmed value of nWR is the number of clock cycles the device uses to deter-
mine the starting point of an internal PRECHARGE operation after a WRITE burst with
AP (auto precharge) enabled. It is determined by RU(tWR/tCK).
6. nRTP shown in this table is valid for BL16 only. For BL32, the device will add 8 clocks to
the nRTP value before starting a precharge.
Table 29: MR3 I/O Configuration 1 (MA[5:0] = 03h)

DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL
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Mode Registers

PU-CAL Write-only OP[0] 0b: VDDQ × 0.6 1–4
(Pull-up calibration point) 1b: VDDQ × 0.5 (default)
WR-PST OP[1] 0b: WR postamble = 0.5 × tCK (default) 2, 3, 5
(WR postamble length) 1b: WR postamble = 1.5 × tCK
PPRP OP[2] 0b: PPR protection disabled (default) 6

(Post-package repair pro- 1b: PPR protection enabled
tection)
PDDS OP[5:3] 000b: RFU 1, 2, 3
(Pull-down drive strength) 001b: RZQ/1
010b: RZQ/2
011b: RZQ/3
100b: RZQ/4
101b: RZQ/5
110b: RZQ/6 (default)
111b: Reserved
DBI-RD OP[6] 0b: Disabled (default) 2, 3
(DBI-read enable) 1b: Enabled
DBI-WR OP[7] 0b: Disabled (default) 2, 3
(DBI-write enable) 1b: Enabled
Notes: 1. All values are typical. The actual value after calibration will be within the specified toler-
ance for a given voltage and temperature. Recalibration may be required as voltage and
temperature vary.
address, or read from with an MRR command to this address.
set point 0 and set point 1.The device will operate only according to the values stored in
the registers for the active set point, for example, the set point determined by the state
of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will
be determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers
for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
4. For dual-channel device, PU‐CAL (MR3‐OP[0]) must be set the same for both channels on
a die. The SDRAM will read the value of only one register (Ch.A or Ch.B); the choice is
vendor-specific, so both channels must be set the same.
5. 1.5 × tCK apply > 1.6 GHz clock.
6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a
sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR
mode. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4
OP[4].
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Table 31: MR4 Device Temperature (MA[5:0] = 04h)

TUF Thermal offset PPRE SR abort Refresh rate

Refresh rate Read-only OP[2:0] 000b: SDRAM low temperature operating limit exceeded 1–4,
001b: 4x refresh 7–9
010b: 2x refresh
011b: 1x refresh (default)
100b: 0.5x refresh
101b: 0.25x refresh, no derating
110b: 0.25x refresh, with derating
111b: SDRAM high temperature operating limit excee-
ded
SR abort Write OP[3] 0b: Disable (default) 9
(Self refresh abort) 1b: Device dependent
PPRE Write OP[4] 0b: Exit PPR mode (default) 5, 9
(Post-package repair entry/ 1b: Enter PPR mode (Reference MR25 OP[7:0] for availa-
exit) ble PPR resources)
Thermal offset-controller Write OP[6:5] 00b: No offset, 0~5°C gradient (default) 9
offset to TCSR 01b: 5°C offset, 5~10°C gradient
10b: 10°C offset, 10~15°C gradient
11b: Reserved
TUF Read-only OP7 0b: OP[2:0] No change in OP[2:0] since last MR4 read (de- 6–8
(Temperature update flag) fault)
1b: Change in OP[2:0] since last MR4 read
Notes: 1. The refresh rate for each MR4 OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. MR4
OP[2:0] = 011b corresponds to a device temperature of 85°C. Other values require either
a longer (2x, 4x) refresh interval at lower temperatures or a shorter (0.5x, 0.25x) refresh
interval at higher temperatures. If MR4 OP[2] = 1b, the device temperature is greater
than 85°C.
2. At higher temperatures (>85°C), AC timing derating may be required. If derating is re-
quired the device will set MR4 OP[2:0] = 110b. See derating timing requirements in the
AC Timing section.
3. DRAM vendors may or may not report all of the possible settings over the operating
temperature range of the device. Each vendor guarantees that their device will work at
any temperature within the range using the refresh interval requested by their device.
4. The device may not operate properly when MR4 OP[2:0 ] = 000b or 111b.
5. Post‐package repair can be entered or exited by writing to MR4 OP[4].
6. When MR4 OP[7] = 1b, the refresh rate reported in MR4 OP[2:0] has changed since the
last MR4 read. A mode register read from MR4 will reset MR4 OP[7] to 0b.
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Mode Registers
7. MR4 OP[7] = 0b at power‐up. MR4 OP[2:0] bits are valid after initialization sequence
(Te).
8. See the Temperature Sensor section for information on the recommended frequency of
reading MR4.
9. MR4 OP[6:3] can be written in this register. All other bits will be ignored by the device
during an MRW command to this register.
Table 33: MR5 Basic Configuration 1 (MA[5:0] = 05h)

Manufacturer ID
Feature Type OP Definition

Manufacturer ID Read-only OP[7:0] 1111 1111b : Micron
All others: Reserved

Revision ID1
Note: 1. MR6 is vendor-specific.

Revision ID1 Read-only OP[7:0] xxxx xxxxb: Revision ID1

Revision ID2

Revision ID2 Read-only OP[7:0] xxxx xxxxb: Revision ID2
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Mode Registers

I/O width Density Type

Type Read-only OP[1:0] 00b: S16 SDRAM (16n prefetch)
Density Read-only OP[5:2] 0000b: 4Gb dual-channel die/2Gb single-channel die
0001b: 6Gb dual-channel die/3Gb single-channel die
I/O width Read-only OP[7:6] 00b: x16/channel
01b: x8/channel
Table 41: MR9 Test Mode (MA[5:0] = 09h)

Vendor-specific test mode
Table 42: MR9 Op-Code Definitions

Test mode Write-only OP[7:0] 0000000b; Vendor-specific test mode disabled (default)
Table 43: MR10 Calibration (MA[5:0] = 0Ah)

RFU ZQ RESET
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Mode Registers

ZQ reset Write-only OP[0] 0b: Normal operation (default)
1b: ZQ reset
Notes: 1. See AC Timing table for calibration latency and timing.

2. If ZQ is connected to VDDQ through RZQ, either the ZQ CALIBRATION function or default
calibration (via ZQ reset) is supported. If ZQ is connected to VSS, the device operates
with default calibration and ZQ CALIBRATION commands are ignored. In both cases, the
ZQ connection must not change after power is supplied to the device.
Table 45: MR11 ODT Control (MA[5:0] = 0Bh)

RFU CA ODT RFU DQ ODT

DQ ODT Write-only OP[2:0] 000b: Disable (default) 1, 2, 3
DQ bus receiver on-die ter- 001b: RZQ/1
mination
010b: RZQ/2
011b: RZQ/3
100b: RZQ/4
101b: RZQ/5
110b: RZQ/6
111b: RFU
CA ODT Write-only OP[6:4] 000b: Disable (default) 1, 2, 3
CA bus receiver on-die ter- 001b: RZQ/1
mination
010b: RZQ/2
011b: RZQ/3
100b: RZQ/4
101b: RZQ/5
110b: RZQ/6
111b: RFU
ance for a given voltage and temperature. Re‐calibration may be required as voltage
and temperature vary.
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Mode Registers
in the registers for the active set point, for example, the set point determined by the
state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set
point will be ignored by the device and may be changed without affecting device opera-
tion.
Table 47: MR12 Register Information (MA[5:0] = 0Ch)

RFU VRCA VREF(CA)
Feature Type OP Data Notes

VREF(CA) Read/ OP[5:0] 000000b–110010b: See VREF Settings table 1–3, 5, 6
VREF(CA) settings Write All others: Reserved
VRCA Read/ OP[6] 0b: VREF(CA) range[0] enabled 1, 2, 4, 5,
VREF(CA) range Write 1b: VREF(CA) range[1] enabled (default) 6
Notes: 1. This register controls the VREF(CA) levels for frequency set point[1:0]. Values from either
VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately.
2. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ
will be set to 0. See the MRR Operation section.
3. A write to MR12 OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6] = 0b
or sets the internal VREF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for
VREF(CA) to reach the set level depends on the step size from the current level to the new
level. See the VREF(CA) training section.
4. A write to MR12 OP[6] switches the device between two internal VREF(CA) ranges. The
range (range[0] or range[1]) must be selected when setting the VREF(CA) register. The val-
ue, once set, will be retained until overwritten or until the next power‐on or reset
event.
point will be ignored by the device, and may be changed without affecting device oper-
ation.
Table 49: MR13 Register Control (MA[5:0] = 0Dh)
OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0]

FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT
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Mode Registers
Table 50: MR13 Op-Code Bit Definition

CBT Write-only OP[0] 0b: Normal operation (default) 1
Command bus training 1b: Command bus training mode enabled
RPT OP[1] 0b: Disabled (default)
Read preamble training 1b: Read preamble training mode enabled
VRO OP[2] 0b: Normal operation (default) 2
VREF output 1b: Output the VREF(CA) and VREF(DQ) values on DQ bits
VRCG OP[3] 0b: Normal operation (default) 3
VREF current generator 1b: Fast response (high current) mode
RRO OP[4] 0b: Disable codes 001 and 010 in MR4 OP[2:0] 4, 5
Refresh rate option 1b: Enable all codes in MR4 OP[2:0]
DMD OP[5] 0b: DATA MASK operation enabled (default) 6
Data mask disable 1b: DATA MASK operation disabled
FSP-WR OP[6] 0b: Frequency set point[0] (default) 7
Frequency set point write/ 1b: Frequency set point[1]
read
FSP-OP OP[7] 0b: Frequency set point[0] (default) 8
FREQUENCY SET POINT op- 1b: Frequency set point[1]
eration mode
Notes: 1. A write to set OP[0] = 1 causes the LPDDR4 SDRAM to enter the command bus training
mode. When OP[0] = 1 and CKE goes LOW, commands are ignored and the contents of
CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to
clear this bit (OP[0] = 0) and return to normal operation. See the Command Bus Training
section for more information.
2. When set, the device will output the VREF(CA) and VREF(DQ) voltage on DQ pins. Only the
"active" frequency set point, as defined by MR13 OP[7], will be output on the DQ pins.
This function allows an external test system to measure the internal VREF levels. The DQ
pins used for VREF output are vendor-specific.
3. When OP[3] = 1, the VREF circuit uses a high current mode to improve VREF settling time.
4. MR13 OP[4] RRO bit is valid only when MR0 OP[0] = 1. For LPDDR4 SDRAM with MR0
OP[0] = 0, MR4 OP[2:0] bits are not dependent on MR13 OP[4].
5. When OP[4] = 0, only 001b and 010b in MR4 OP[2:0] are disabled. LPDDR4 SDRAM must
report 011b instead of 001b or 010b in this case. Controller should follow the refresh
mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not de-
pend on RRO setting.
6. When enabled (OP[5] = 0b) data masking is enabled for the device. When disabled
(OP[5] = 1b), the device will ignore any mask patterns issued during a MASKED WRITE
command. See the Data Mask section for more information.
7. FSP‐WR determines which frequency set point registers are accessed with MRW and
MRR commands for the following functions such as VREF(CA) setting, VREF(CA) range,
VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point sec-
tion.
8. FSP‐OP determines which frequency set point register values are currently used to speci-
fy device operation for the following functions such as VREF(CA) setting, VREF(CA) range,
VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point sec-
tion.
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Mode Registers
Table 51: Mode Register 14 (MA[5:0] = 0Eh)

RFU VRDQ VREF(DQ)

VREF(DQ) Read/ OP[5:0] 000000b–110010b: See VREF Settings table 1–3, 5, 6
VREF(DQ) setting Write All others: Reserved
VRDQ OP[6] 0b: VREF(DQ) range[0] enabled 1, 2, 4–6
VREF(DQ) range 1b: VREF(DQ) range[1] enabled (default)
Notes: 1. This register controls the VREF(DQ) levels for frequency set point[1:0]. Values from either
VRDQ[0] (vendor defined) or VRDQ[1] (vendor defined) may be selected by setting OP[6]
appropriately.
2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and
unused DQ shall be set to 0. See the MRR Operation section.
3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or
sets FSP[1] when MR13 OP[6] = 1b. The time required for VREF(DQ) to reach the set level
depends on the step size from the current level to the new level. See the VREF(DQ) train-
ing section.
4. A write to OP[6] switches the device between two internal VREF(DQ) ranges. The range
(range[0] or range[1]) must be selected when setting the VREF(DQ) register. The value,
once set, will be retained until overwritten, or until the next power‐on or reset event.
ation.
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Mode Registers
Table 53: VREF Setting for Range[0] and Range[1]

Notes 1-3 apply to entire table
Range[0] Values Range[1] Values
VREF(CA) (% of VDDQ) VREF(CA) (% of VDDQ)
Function OP VREF(DQ) (% of VDDQ) VREF(DQ) (% of VDDQ)
VREF setting OP[5:0] 000000b: 15.0% 011010b: 30.5% 000000b: 32.9% 011010b: 48.5%
for MR12 000001b: 15.6% 011011b: 31.1% 000001b: 33.5% 011011b: 49.1%
and MR14
000010b: 16.2% 011100b: 31.7% 000010b: 34.1% 011100b: 49.7%
000011b: 16.8% 011101b: 32.3% 000011b: 34.7% 011101b: 50.3% (default)
000100b: 17.4% 011110b: 32.9% 000100b: 35.3% 011110b: 50.9%
000101b: 18.0% 011111b: 33.5% 000101b: 35.9% 011111b: 51.5%
000110b: 18.6% 100000b: 34.1% 000110b: 36.5% 100000b: 52.1%
000111b: 19.2% 100001b: 34.7% 000111b: 37.1% 100001b: 52.7%
001000b: 19.8% 100010b: 35.3% 001000b: 37.7% 100010b: 53.3%
001001b: 20.4% 100011b: 35.9% 001001b: 38.3% 100011b: 53.9%
001010b: 21.0% 100100b: 36.5% 001010b: 38.9% 100100b: 54.5%
001011b: 21.6% 100101b: 37.1% 001011b: 39.5% 100101b: 55.1%
001100b: 22.2% 100110b: 37.7% 001100b: 40.1% 100110b: 55.7%
001101b: 22.8% 100111b: 38.3% 001101b: 40.7% 100111b: 56.3%
001110b: 23.4% 101000b: 38.9% 001110b: 41.3% 101000b: 56.9%
001111b: 24.0% 101001b: 39.5% 001111b: 41.9% 101001b: 57.5%
010000b: 24.6% 101010b: 40.1% 010000b: 42.5% 101010b: 58.1%
010001b: 25.1% 101011b: 40.7% 010001b: 43.1% 101011b: 58.7%
010010b: 25.7% 101100b: 41.3% 010010b: 43.7% 101100b: 59.3%
010011b: 26.3% 101101b: 41.9% 010011b: 44.3% 101101b: 59.9%
010100b: 26.9% 101110b: 42.5% 010100b: 44.9% 101110b: 60.5%
010101b: 27.5% 101111b: 43.1% 010101b: 45.5% 101111b: 61.1%
010110b: 28.1% 110000b: 43.7% 010110b: 46.1% 110000b: 61.7%
010111b: 28.7% 110001b: 44.3% 010111b: 46.7% 110001b: 62.3%
011000b: 29.3% 110010b: 44.9% 011000b: 47.3% 110010b: 62.9%
011001b: 29.9% All others: Reserved 011001b: 47.9% All others: Reserved
Notes: 1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or
VREF(DQ) levels in the device.
2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] ap-
propriately.
3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set
points each for CA and DQ are provided to allow for faster switching between termina-
ted and unterminated operation or between different high‐frequency settings, which
may use different terminations values.
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Mode Registers
Table 54: MR15 Register Information (MA[5:0] = 0Fh)

Lower-byte invert register for DQ calibration
Table 55: MR15 Op-code Bit Definition

Lower-byte invert for DQ Write-only OP[7:0] The following values may be written for any operand 1–3
calibration OP[7:0] and will be applied to the corresponding DQ lo-
cations DQ[7:0] within a byte lane
0b: Do not invert
1b: Invert the DQ calibration patterns in MR32 and MR40
Default value for OP[7:0] = 55h
Notes: 1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any sin-
gle DQ or any combination of DQ. Example: If MR15 OP[7:0] = 00010101b, then the DQ
calibration patterns transmitted on DQ[7, 6, 5, 3, 1] will not be inverted, but the DQ cali-
bration patterns transmitted on DQ[4, 2, 0] will be inverted.
2. DM[0] is not inverted and always transmits the "true" data contained in MR32 and
MR40.
3. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if
DBI is enabled in MR3-OP[6].
Table 56: MR15 Invert Register Pin Mapping
PIN DQ0 DQ1 DQ2 DQ3 DMIO DQ4 DQ5 DQ6 DQ7
MR15 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7
Table 57: MR16 PASR Bank Mask (MA[5:0] = 010h)

PASR bank mask

Bank[7:0] mask Write-only OP[7:0] 0b: Bank refresh enabled (default)
1b: Bank refresh disabled
OP[n] Bank Mask 8-Bank SDRAM

0 xxxxxxx1 Bank 0
1 xxxxxx1x Bank 1
2 xxxxx1xx Bank 2
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Mode Registers
OP[n] Bank Mask 8-Bank SDRAM

3 xxxx1xxx Bank 3
4 xxx1xxxx Bank 4
5 xx1xxxxx Bank 5
6 x1xxxxxx Bank 6
7 1xxxxxxx Bank 7
Notes: 1. When a mask bit is asserted (OP[n] = 1), refresh to that bank is disabled.
2. PASR bank masking is on a per-channel basis; the two channels on the die may have dif-
ferent bank masking in dual-channel devices.
Table 59: MR17 PASR Segment Mask (MA[5:0] = 11h)

PASR segment mask
Table 60: MR17 PASR Segment Mask Definitions

Segment[7:0] mask Write-only OP[7:0] 0b: Segment refresh enabled (default)
1b: Segment refresh disabled
Table 61: MR17 PASR Segment Mask
Density (per channel)
Segment 1Gb 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb

Segment OP Mask R[12:10] R[13:11] R[14:12] R[14:12] R[15:13] R[15:13] R[16:14] R[16:14]
0 0 XXXXXXX1 000b
1 1 XXXXXX1X 001b
2 2 XXXXX1XX 010b
3 3 XXXX1XXX 011b
4 4 XXX1XXXX 100b
5 5 XX1XXXXX 101b
6 6 X1XXXXXX 110b 110b Not 110b Not 110b Not 110b
7 7 1XXXXXXX 111b 111b allowed 111b allowed 111b allowed 111b
Notes: 1. This table indicates the range of row addresses in each masked segment. "X" is “Don’t
Care” for a particular segment.
2. PASR segment-masking is on a per-channel basis. The two channels on the die may have
different segment masking in dual-channel devices.
3. For 3Gb, 6Gb, and 12Gb density per channel, OP[7:6] must always be LOW (= 00b).
CCM005-554574167-10729

Mode Registers
Table 62: MR18 Register Information (MA[5:0] = 12h)

DQS oscillator count - LSB
Table 63: MR18 LSB DQS Oscillator Count

Function Type OP Definition
DQS oscillator count Read-only OP[7:0] 0h–FFh LSB DRAM DQS oscillator count
(WR training DQS oscillator)
Notes: 1. MR18 reports the LSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator
count value is used to train DQS to the DQ data valid window. The value reported by
the DRAM in this mode register can be used by the memory controller to periodically
adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS
oscillator count.
3. The value in this register is reset each time an MPC command is issued to start in the
DQS oscillator counter.

DQS oscillator count – MSB
Table 65: MR19 DQS Oscillator Count

Notes 1–3 apply to the entire table
DQS oscillator count – MSB Read-only OP[7:0] 0h–FFh MSB DRAM DQS oscillator count
(WR training DQS oscillator)
Notes: 1. MR19 reports the MSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator
count value is used to train DQS to the DQ data valid window. The value reported by
the DRAM in this mode register can be used by the memory controller to periodically
adjust the phase of DQS relative to DQ.
2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS
oscillator count.
3. A new MPC[START DQS OSCILLATOR] should be issued to reset the contents of MR18/
MR19.

Upper-byte invert register for DQ calibration
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Mode Registers
Table 67: MR20 Register Information

Upper-byte invert for DQ Write-only OP[7:0] The following values may be written for any operand OP[7:0] and
calibration will be applied to the corresponding DQ locations DQ[15:8] within a
byte lane
0b: Do not invert
1b: Invert the DQ calibration patterns in MR32 and MR40
Default value for OP[7:0] = 55h
Notes: 1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any sin-
gle DQ or any combination of DQ. For example, if MR20 OP[7:0] = 00010101b, the DQ
calibration patterns transmitted on DQ[15, 14, 13, 11, 9] will not be inverted, but the DQ
calibration patterns transmitted on DQ[12, 10, 8] will be inverted.
2. DM[1] is not inverted and always transmits the true data contained in MR32 and MR40.
DBI is enabled in MR3 OP[6].
Table 68: MR20 Invert Register Pin Mapping
Pin DQ8 DQ9 DQ10 DQ11 DMI1 DQ12 DQ13 DQ14 DQ15
MR20 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7

RFU

ODTD for x8_2ch ODTD-CA ODTE-CS ODTE-CK SOC ODT
CCM005-554574167-10729

Mode Registers
Function Type OP Data Notes

SOC ODT (controller ODT Write-only OP[2:0] 000b: Disable (default) 1, 2, 3
value for VOH calibration) 001b: RZQ/1 (Illegal if MR3 OP[0] = 0b)
010b: RZQ/2
011b: RZQ/3 (Illegal if MR3 OP[0] = 0b)
100b: RZQ/4
111b: RFU
ODTE-CK (CK ODT enabled Write-only OP[3] ODT bond PAD is ignored 2, 3
for non-terminating rank) 0b: ODT-CK enable (default)
1b: ODT-CK disable
ODTE-CS (CS ODT enabled Write-only OP[4] ODT bond PAD is ignored 2, 3
for non-terminating rank) 0b: ODT-CS enable (default)
1b: ODT-CS disable
ODTD-CA (CA ODT termina- Write-only OP[5] ODT bond PAD is ignored 2, 3
tion disable) 0b: CA ODT enable (default)
1b: CA ODT disable
ODTD for x8_2ch (Byte) Write-only OP[7:6] See Byte Mode section
mode
Notes: 1. All values are typical.

of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR
state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set
ation.

DQS interval timer run-time setting
CCM005-554574167-10729

Mode Registers

Function Type OP Data
DQS interval timer run-time Write-only OP[7:0] 00000000b: Disabled (default)
00000001b: DQS timer stops automatically at the 16th clock after tim-
er start
00000010b: DQS timer stops automatically at the 32nd clock after
timer start
er start
er start
--------- Through ---------
00111111b: DQS timer stops automatically at the (63 × 16)th clock af-
ter timer start
01XXXXXXb: DQS timer stops automatically at the 2048th clock after
timer start
10XXXXXXb: DQS timer stops automatically at the 4096th clock after
timer start
11XXXXXXb: DQS timer stops automatically at the 8192nd clock after
timer start
Notes: 1. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) stops the
DQS interval timer in the case of MR23 OP[7:0] = 00000000b.
2. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) is illegal
with valid nonzero values in MR23 OP[7:0].

TRR mode TRR mode BAn Unlimited MAC value
MAC

MAC value Read OP[2:0] 000b: Unknown (OP[3] = 0) or unlimited (OP[3] = 1) 1
001b: 700K
010b: 600K
011b: 500K
100b: 400K
101b: 300K
110b: 200K
111b: Reserved
CCM005-554574167-10729

Mode Registers
Table 75: MR24 Register Information (Continued)

Unlimited MAC Read OP[3] 0b: OP[2:0] defines the MAC value 2
1b: Unlimited MAC value
TRR mode BAn Write OP[6:4] 000b: Bank 0
001b: Bank 1
010b: Bank 2
011b: Bank 3
100b: Bank 4
101b: Bank 5
110b: Bank 6
111b: Bank 7
TRR mode Write OP[7] 0b: Disabled (default)
1b: Enabled
Notes: 1. OP[2:0] = 000b Unknown means that the device is not tested for tMAC and pass/fail val-
ues are unknown. OP[2:0] = 000b Unlimited means that there is no restriction on the
number of activates between refresh windows. However, specific attempts to by-pass
TRR may result in data disturb.
2. When OP[3] = 1b, MR24 OP[2:0] set to 000b.

Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0

PPR resources Read-only OP[7:0] 0b: PPR resource is not available
1b: PPR resource is available
Note: 1. When OP[n] = 0, there is no PPR resource available for that bank. When OP[n] = 1, there
is a PPR resource available for that bank, and PPR can be initiated by the controller.
Table 78: MR26:29 Register Information (MA[5:0] = 1Ah–1Dh)

Reserved for future use
CCM005-554574167-10729

Mode Registers
Table 79: MR30 Register Information (MA[5:0] = 1Eh)

Valid 0 or 1

SDRAM will ignore Write-only OP[7:0] Don't care
Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0]
will have no effect on SDRAM operation; however, timings need to be observed as for
any other MR access command.
Table 81: MR31 Register Information (MA[5:0] = 1Fh)


DQ calibration pattern A (default = 5Ah)

Return DQ calibration pat- Write-only OP[7:0] Xb: An MPC command issued with OP[6:0] = 1000011b 1, 2, 3
tern MR32 + MR40 causes the device to return the DQ calibration pattern
contained in this register and (followed by) the contents
of MR40. A default pattern 5Ah is loaded at power-up or
reset, or the pattern may be overwritten with a MRW to
this register. The contents of MR15 and MR20 will invert
the MR32/MR40 data pattern for a given DQ (see MR15/
MR20 for more information).
Notes: 1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0]
when read DQ calibration is initiated via an MPC command. The pattern is transmitted
serially on each data lane and organized little endian such that the low-order bit in a
byte is transmitted first. If the data pattern is 27H, the first bit transmitted is a 1 fol-
lowed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111.
2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins.
See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins.
3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3
OP[6].
CCM005-554574167-10729

Mode Registers
Table 84: MR33:38 Register Information (MA[5:0] = 21h–26h)

Do not use

Valid 0 or 1

SDRAM will ignore Write-only OP[7:0] Don't care
Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0]
will have no effect on SDRAM operation; however, timings need to be observed as for
any other MR access command.

DQ calibration pattern B (default = 3Ch)

Return DQ calibration pat- Write-only OP[7:0] Xb: A default pattern 3Ch is loaded at power-up or reset, 1, 2, 3
tern MR32 + MR40 or the pattern may be overwritten with a MRW to this
register. See MR32 for more information.
Notes: 1. The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on
DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via an MPC command. The
pattern is transmitted serially on each data lane and organized little endian such that
the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, the
first bit transmitted will be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be
00100111.
2. MR15 and MR20 may be used to invert the MR32/MR40 data patterns on the DQ pins.
3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3
OP[6].
CCM005-554574167-10729

Commands and Timing
Table 89: MR41:47 Register Information (MA[5:0] = 29h–2Fh)

Do not use
Table 90: MR48:63 Register Information (MA[5:0] = 30h–3Fh)

Commands and Timing

Commands transmitted on the CA bus are encoded into two parts and are latched on
two consecutive rising edges of the clock. This is called 2-tick CA capture because each
command requires two clock edges to latch and decode the entire command.
Truth Tables
Truth tables provide complementary information to the state diagram. They also clarify
device behavior and applicable restrictions when considering the actual state of the
banks.
Unspecified operations and timings are illegal. To ensure proper operation after an ille-
gal event, the device must be either reset by asserting the RESET_n command or pow-
ered down and then restarted using the specified initialization sequence before normal
operation can continue.
CKE signal has to be held HIGH when the commands listed in the command truth table
input.
Table 91: Command Truth Table

Commands are transmitted to the device across a six-lane interface and use CK, CKE, and CS to control the capture of
transmitted data
SDR CA Pins
Command CS CA0 CA1 CA2 CA3 CA4 CA5 CK Edge Notes
MRW-1 H L H H L L OP7 1 1, 11
L MA0 MA1 MA2 MA3 MA4 MA5 2
MRW-2 H L H H L H OP6 1 1, 11
L OP0 OP1 OP2 OP3 OP4 OP5 2
MRR-1 H L H H H L V 1 1, 2, 12
L MA0 MA1 MA2 MA3 MA4 MA5 2
REFRESH H L L L H L AB 1 1, 2, 3, 4
(all/per bank) L BA0 BA1 BA2 V V V 2
ENTER SELF RE- H L L L H H V 1 1, 2

FRESH L V 2
CCM005-554574167-10729

Truth Tables
Table 91: Command Truth Table (Continued)

Commands are transmitted to the device across a six-lane interface and use CK, CKE, and CS to control the capture of
transmitted data
SDR CA Pins
Command CS CA0 CA1 CA2 CA3 CA4 CA5 CK Edge Notes
ACTIVATE-1 H H L R12 R13 R14 R15 1 1, 2, 3, 11
L BA0 BA1 BA2 R16 R10 R11 2
ACTIVATE-2 H H H R6 R7 R8 R9 1 1, 11
L R0 R1 R2 R3 R4 R5 2
WRITE-1 H L L H L L BL 1 1, 2, 3, 6,
L BA0 BA1 BA2 V C9 AP 2
7, 9
EXIT SELF RE- H L L H L H V 1 1, 2

FRESH L V 2
MASK WRITE-1 H L L H H L BL 1 1, 2, 3, 5,
6, 7, 9
RFU H L L H H H V 1 1, 2
L V 2
RFU H L H L H L V 2 1, 2
L V 2
RFU H L H L H H V 2 1, 2
L V 2
READ-1 H L H L L L BL 1 1, 2, 3, 6,
7, 9
CAS-2 H L H L L H C8 1 1, 8, 9
(WRITE-2, L C2 C3 C4 C5 C6 C7 2
MASKED
WRITE-2,
READ-2, MRR-2,
MPC (except
NOP)
PRECHARGE H L L L L H AB 1 1, 2, 3, 4
(all/per bank) L BA0 BA1 BA2 V V V 2
MPC H L L L L L OP6 1 1, 2, 13
(TRAIN, NOP) L OP0 OP1 OP2 OP3 OP4 OP5 2
DESELECT L X 1 1, 2
Notes: 1. All commands except for DESELECT are two clock cycles and are defined by the current
state of CS and CA[5:0] at the rising edge of the clock. DESELECT command is one clock
cycle and is not latched by the device.
2. V = H or L (a defined logic level); X = "Don't Care," in which case CS, CK_t, CK_c, and
CA[5:0] can be floated.
3. Bank addresses BA[2:0] determine which bank is to be operated upon.
CCM005-554574167-10729

ACTIVATE Command
4. AB HIGH during PRECHARGE or REFRESH commands indicate the command must be ap-
plied to all banks, and the bank addresses are "Don't Care."
5. MASK WRITE-1 command only supports BL16. For MASK WRITE-1 commands, CA5 must
be driven LOW on the first rising clock cycle (R1).
6. AP HIGH during a WRITE-1, MASK WRITE-1, or READ-1 command indicates that an auto
precharge will occur to the bank the command is operating on. AP LOW indicates that
no auto precharge will occur and the bank will remain open upon completion of the
command.
7. When enabled in the mode register, BL HIGH during a WRITE-1, MASK-WRITE-1, or
READ-1 command indicates the burst length should be set on-the-fly to BL = 32; BL LOW
during one of these commands indicates the burst length should be set on-the-fly to BL
= 16. If on-the-fly burst length is not enabled in the mode register, this bit should be
driven to a valid level and is ignored by the device.
8. For CAS-2 commands (WRITE-2, MASK WRITE-2, READ-2, MRR-2, or MPC (only WRITE-
FIFO, READ-FIFO, and READ DQ CALIBRATION)), C[1:0] are not transmitted on the CA
[5:0] bus and are assumed to be zero. Note that for CAS-2 WRITE-2 or CAS-2 MASK
WRITE-2 command, C[3:2] must be driven LOW.
9. WRITE-1, MASK-WRITE-1, READ-1, MODE REGISTER READ-1, or MPC (only WRITE-FIFO,
READ-FIFO, and READ DQ CALIBRATION) command must be immediately followed by
CAS-2 command consecutively without any other command in between. WRITE-1, MASK
WRITE-1, READ-1, MRR-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRA-
TION) command must be issued first before issuing CAS-2 command. MPC (only START
and STOP DQS OSCILLATOR, ZQCAL START and LATCH) commands do not require CAS-2
command; they require two additional DES or NOP commands consecutively before issu-
ing any other commands.
10. The ACTIVATE-1 command must be followed by the ACTIVATE-2 command consecutively
without any other command between them. The ACTIVATE-1 command must be issued
prior to the ACTIVATE-2 command. When the ACTIVATE-1 command is issued, the ACTI-
VATE-2 command must be issued before issuing another ACTIVATE-1 command.
11. The MRW-1 command must be followed by the MRW-2 command consecutively without
any other command between them. The MRW-1 command must be issued prior to the
MRW-2 command.
12. The MRR-1 command must be followed by the CAS-2 command consecutively without
any other commands between them. The MRR-1 command must be issued prior to the
CAS-2 command.
13. The MPC command for READ or WRITE TRAINING operations must be followed by the
CAS-2 command consecutively without any other commands between them. The MPC
command must be issued prior to the CAS-2 command.
ACTIVATE Command
The ACTIVATE command must be executed before a READ or WRITE command can be
issued. The ACTIVATE command is issued in two parts: The bank and upper-row ad-
dresses are entered with activate-1 and the lower-row addresses are entered with ACTI-
VATE-2. ACTIVATE-1 and ACTIVATE-2 are executed by strobing CS HIGH while setting
CA[5:0] at valid levels (see Command table) at the rising edge of CK.
The bank addresses (BA[2:0]) are used to select the desired bank. The row addresses
(R[15:0]) are used to determine which row to activate in the selected bank. The ACTI-
VATE-2 command must be applied before any READ or WRITE operation can be execu-
ted. The device can accept a READ or WRITE command at time tRCD after the ACTI-
VATE-2 command is sent. After a bank has been activated, it must be precharged to
close the active row before another ACTIVATE-2 command can be applied to the same
CCM005-554574167-10729

ACTIVATE Command
bank. The bank active and precharge times are defined as tRAS and tRP, respectively.
The minimum time interval between successive ACTIVATE-2 commands to the same
bank is determined by the row cycle time of the device (tRC). The minimum time inter-
val between ACTIVATE-2 commands to different banks is tRRD.
Certain restrictions must be observed for bank ACTIVATE and REFpb operations.
• Four-activate window (tFAW): No more than 4 banks may be activated (or refreshed,
in the case of REFpb) per channel in a rolling tFAW window. Convert to clocks by di-
viding tFAW[ns] by tCK[ns] and rounding up to the next integer value. As an example
of the rolling window, if RU[(tFAW/tCK)] is 64 clocks, and an ACTIVATE command is
issued on clock N, no more than three additional ACTIVATE commands may be is-
sued between clock N + 1 and N + 63. REFpb also counts as bank activation for the
purposes of tFAW.
• 8-bank per channel, precharge all banks (AB) allowance: tRP for a PRECHARGE ALL
BANKS command for an 8-bank device must equal tRPab, which is greater than
tRPpb.
Figure 15: ACTIVATE Command

T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Td0 Td1 Td2 Td3 Td4 Td5
CK_c
CK_t
CKE
CS
RA RA BA0 RA RA RA
CA RA RA RA RA RA RA Valid BA0 CA CA Valid RA
BA0 BA1 BA0
tRRD tRP
tRCD
PRECHARGE ACTIVATE-2 DES DES

Command ACTIVATE-1 ACTIVATE-2 DES ACTIVATE-1 ACTIVATE-2 DES READ1 CAS2 DES per bank DES ACTIVATE-1
tRAS
tRC
Don’t Care
Note: 1. A PRECHARGE command uses tRPab timing for all-bank precharge and tRPpb timing for
single-bank precharge. In this figure, tRP is used to denote either all-bank precharge or
a single-bank precharge. tCCD = MIN, 1.5nCK postamble, 533 MHz < clock frequency ≤
800 MHz, ODT worst timing case.
CCM005-554574167-10729

Read and Write Access Modes
Figure 16: tFAW Timing

T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Td4
CK_c
CK_t
CKE
CS
RA RA RA RA RA
CA RA RA RA RA RA RA RA RA RA RA RA RA RA RA RA
BA0 BA1 BA2 BA3 BA4
Command ACTIVATE-1 ACTIVATE-2 DES ACTIVATE-1 ACTIVATE-2 DES ACTIVATE-1 ACTIVATE-2 DES ACTIVATE-1 ACTIVATE-2 DES DES ACTIVATE-1 ACTIVATE-2
tRRD tRRD tRRD
t FAW
Don’t Care
Note: 1. REFpb may be substituted for one of the ACTIVATE commands for the purposes of tFAW.
Read and Write Access Modes

After a bank has been activated, a READ or WRITE command can be executed. This is
accomplished by asserting CKE asynchronously, with CS and CA[5:0] set to the proper
state (see Command Truth Table) on the rising edge of CK.
The device provides a fast column access operation. A single READ or WRITE command
will initiate a burst READ or WRITE operation, where data is transferred to/from the de-
vice on successive clock cycles. Burst interrupts are not allowed; however, the optimal
burst length may be set on-the-fly (see Command Truth Table).
Preamble and Postamble

The DQS strobe for the device requires a preamble prior to the first latching edge (the
rising edge of DQS_t with data valid), and it requires a postamble after the last latching
edge. The preamble and postamble options are set via MODE REGISTER WRITE com-
mands.
The read preamble is two tCK in length and is either static or has one clock toggle before
the first latching edge. The read preamble option is enabled via MRW to MR1 OP[3] (0 =
Static; 1 = Toggle).
The read postamble has a programmable option to extend the postamble by 1nCK
(tRPSTE). The extended postamble option is enabled via MRW to MR1 OP[7] (0 =
0.5nCK; 1 = 1.5nCK).
CCM005-554574167-10729

Figure 17: DQS Read Preamble and Postamble – Toggling Preamble and 0.5nCK Postamble
T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4
CK_c
CK_t
Command RD-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
RL tDQSCK
tRPRE
DQS_c
DQS_t
tDQSQ tRPST
DQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DMI n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15
Notes: 1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK.

2. DQS and DQ terminated VSSQ.
3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE.
Figure 18: DQS Read Preamble and Postamble – Static Preamble and 1.5nCK Postamble
T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4
CK_c
CK_t
RL tDQSCK
tRPRE
DQS_c
DQS_t
tDQSQ tRPSTE
DQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
Notes: 1. BL = 16, Preamble = Static, Postamble = 1.5nCK (extended).

3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE.
CCM005-554574167-10729

Figure 19: DQS Write Preamble and Postamble – 0.5nCK Postamble

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7
CK_c
CK_t
CKE
CS
CA Valid Valid Valid Valid
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
WL tDQSS
t
WPRE t WPST
DQS_c
DQS_t
tDQS2DQ BL/2
DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
Don’t Care
Notes: 1. BL = 16, Postamble = 0.5nCK.

3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE.
CCM005-554574167-10729

Figure 20: DQS Write Preamble and Postamble – 1.5nCK Postamble

CK_c
CK_t
CKE
CS
WL tDQSS
t t WPST
WPRE
DQS_c
DQS_t
tDQS2DQ BL/2
Don’t Care
Notes: 1. BL = 16, Postamble = 1.5nCK.

3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied,
as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE.
CCM005-554574167-10729

Burst READ Operation

A burst READ command is initiated with CKE, CS, and CA[5:0] asserted to the proper
state on the rising edge of CK, as defined by the Command Truth Table. The command
address bus inputs determine the starting column address for the burst. The two low-
order address bits are not transmitted on the CA bus and are implied to be 0; therefore,
the starting burst address is always a multiple of four (that is, 0x0, 0x4, 0x8, 0xC).
The READ latency (RL) is defined from the last rising edge of the clock that completes a
READ command (for example, the second rising edge of the CAS-2 command) to the
rising edge of the clock from which the tDQSCK delay is measured. The first valid data is
available RL × tCK + tDQSCK + tDQSQ after the rising edge of clock that completes a
READ command.
The data strobe output is driven tRPRE before the first valid rising strobe edge. The first
data bit of the burst is synchronized with the first valid (post-preamble) rising edge of
the data strobe. Each subsequent data-out appears on each DQ pin, edge-aligned with
the data strobe. At the end of a burst, the DQS signals are driven for another half cycle
postamble, or for a 1.5-cycle postamble if the programmable postamble bit is set in the
mode register. The RL is programmed in the mode registers. Pin timings for the data
strobe are measured relative to the cross-point of DQS_t and DQS_c.
Figure 21: Burst Read Timing

T0 T1 T2 T3 T4 T5 T6 T7 T15 T16 T17 T18 T19 T20 T21 T22 T23 T33 T34 T35 T36 T41 T42 T43 T44
CK_c
CK_t
CS
BA0, BA0,
CA BL
CA, AP
CAn CAn BL
CA, AP
CAm CAm
Command READ-1 CAS-2 DES DES DES DES DES READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES
t t DQSCK BL/2 = 8
CCD = 16 RL = 14
RL = 14 t DQSCK
BL/2 = 16
t t RPST
RPRE
DQS_c
DQS_t
tDQSQ tDQSQ
DQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DMI n0 n1 n2 n3 n4 n5 n6 n7 n26 n27 n28 n29 n30 n31 m0 m1 m10 m11 m12 m13 m14 m15
Don’t Care
Notes: 1. BL = 32 for column n, BL = 16 for column m, RL = 14, Preamble = Toggle, Postamble =

0.5nCK, DQ/DQS: VSSQ termination.
2. DOUT n/m = data-out from column n and column m.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
CCM005-554574167-10729

Figure 22: Burst Read Followed by Burst Write or Burst Mask Write
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
CK_c
CK_t
CS
BA0, BA0,
CA BL
CA, AP
CA CA BL
CA, AP
CA CA
Command READ-1 CAS-2 DES DES DES WR-1/MWR-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
RL + RU( tDQSCK(MAX)/ tCK) + BL/2

+ RD( tRPST) - WL + tWPRE WL t DQSS
RL t DQSCK BL/2 = 8
t t
RPRE WPRE
DQS_c
DQS_t
tDQSQ tRPST tDQS2DQ
DQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DMI n0 n9 n10 n11 n12 n13 n14 n15 n0 n9 n10 n11 n12 n13 n14 n15
Don’t Care
Notes: 1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK,
Write postamble = 0.5nCK, DQ/DQS: VSSQ termination.
2. DOUT n = data-out from column n and DIN n = data-in to column n.
these times.
Figure 23: Seamless Burst Read

T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Td0 Td1 Td2 Td3 Te0 Te1 Te2 Te3
CK_c
CK_t
CS
BA0, BA0, BA1,

CA BL
CA, AP
CAn CAn BL
CA, AP
CAm CAm BL
CA, AP
CAn CAn
Command READ-1 CAS-2 DES READ-1 CAS-2 DES READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES
RL t DQSCK
t DQSCK
RL
RL t DQSCK
t
RPRE
DQS_c
DQS_t
tDQSQ tDQSQ tDQSQ tRPST
DQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DMI n0 n1 n10 n11 n12 n13 n14 n15 m0 m1 m10 m11 m12 m13 m14 m15 n0 n1 n10 n11 n12 n13 n14 n15
Bank 0 Bank 1
Don’t Care
Notes: 1. BL = 16, tCCD = 8, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination.
these times.
CCM005-554574167-10729

Read Timing
Figure 24: Read Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3
CK_c
CK_t
t
HZ(DQS)
t
RL DQSCK
t
LZ(DQS) t
RPRE
DQS_c
DQS_t
t t
DQSQ RPST
t
HZ(DQ)
t
LZ(DQ)
DQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
Notes: 1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK.

2. DQS, DQ, and DMI terminated VSSQ.
3. Output driver does not turn on before an endpoint of tLZ(DQS) and tLZ(DQ).
4. Output driver does not turn off before an endpoint of tHZ(DQS) and tHZ(DQ).
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation

tHZ and tLZ transitions occur in the same time window as valid data transitions. These
parameters are referenced to a specific voltage level that specifies when the device out-
put is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and
tLZ(DQ). This section shows a method to calculate the point when the device is no lon-
ger driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by meas-
uring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ),
tHZ(DQS), and tHZ(DQ) are defined as single ended.
CCM005-554574167-10729

tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment)
Figure 25: tLZ(DQS) Method for Calculating Transitions and Endpoint
CK_t – CK_c crossing at the second CAS-2 of READ command
CK_t
CK_c
tLZ(DQS)
VOH DQS_c
VSW2
0.5 x VOH
VSW1
End point: Extrapolated point

0V
Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5.
2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ.
3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device toler-
ances. Use the actual VOH value for tHZ and tLZ measurements.
Figure 26: tHZ(DQS) Method for Calculating Transitions and Endpoint

CK_t
CK_c
tHZ(DQS)
VOH
VSW2
0.5 x VOH
VSW1
0V DQS_c
CCM005-554574167-10729

Table 92: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements
Measured Parameter
Measured Parameter Symbol Vsw1 Vsw2 Unit
DQS_c Low-Z time tLZ(DQS) 0.4 × VOH 0.6 × VOH V
from CK_t, CK_c
DQS_c High-Z time tHZ(DQS) 0.4 × VOH 0.6 × VOH
from CK_t, CK_c
tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment)

Figure 27: tLZ(DQ) Method for Calculating Transitions and Endpoint
CK_t
CK_c
t LZ(DQ)
VOH DQs
VSW2
0.5 x VOH
VSW1

0V
2. Termination condition for DQ and DMI = 50 ohms to VSSQ.
CCM005-554574167-10729

Figure 28: tHZ(DQ) Method for Calculating Transitions and Endpoint

CK_t
CK_c
tHZ(DQ)
VOH
VSW2
0.5 x VOH
VSW1
0V DQs
Table 93: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements
Measured Parameter
DQ Low-Z time tLZ(DQ) 0.4 × VOH 0.6 × VOH V
from CK_t, CK_c
DQ High-Z time tHZ(DQ) 0.4 × VOH 0.6 × VOH
from CK_t, CK_c
CCM005-554574167-10729

Burst WRITE Operation

A burst WRITE command is initiated with CKE, CS, and CA[5:0] asserted to the proper
state at the rising edge of CK, as defined by the Command Truth Table. Column address-
es C[3:2] should be driven LOW for burst WRITE commands, and column addresses
C[1:0] are not transmitted on the CA bus and are assumed to be zero so that the starting
column burst address is always aligned with a 32-byte boundary. The WRITE latency
(WL) is defined from the last rising edge of the clock that completes a WRITE command
(for example, the second rising edge of the CAS-2 command) to the rising edge of the
clock from which tDQSS is measured. The first valid latching edge of DQS must be driv-
en WL × t CK + tDQSS after the rising edge of clock that completes a WRITE command.
The device uses an unmatched DQS DQ path for lower power, so the DQS strobe must
arrive at the SDRAM ball prior to the DQ signal by tDQS2DQ. The DQS strobe output
must be driven tWPRE before the first valid rising strobe edge. The tWPRE preamble is
required to be 2 × tCK at any speed ranges. The DQS strobe must be trained to arrive at
the DQ pad latch center-aligned with the DQ data. The DQ data must be held for
TdiVW, and the DQS must be periodically trained to stay roughly centered in the TdiVW.
Burst data is captured by the SDRAM on successive edges of DQS until the 16- or 32-bit
data burst is complete. The DQS strobe must remain active (toggling) for tWPST (write
postamble) after the completion of the burst WRITE. After a burst WRITE operation,
tWR must be satisfied before a PRECHARGE command to the same bank can be issued.
Signal input timings are measured relative to the cross point of DQS_t and DQS_c.
CCM005-554574167-10729

Figure 29: Burst WRITE Operation

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Tb4 Td5
CK_c
CK_t
CS
CA BA0, BA0,
BL CA, AP CA CA Valid BA0 RA RA RA RA
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES PRECHARGE DES DES DES DES ACT-1 ACT-2
WL BL/2 + 1 Clock tWR tRP
tDQSS (MIN)
tWPRE tDSH
tDSS tWPST
DQS_c
DQS_t
tDQS2DQ
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
DQ
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
tDQSS (Nominal)
tWPRE
DQS_c
DQS_t
tDQS2DQ
DQ
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
tDQSS (MAX)
tWPRE
DQS_c
DQS_t
tDQS2DQ
DQ
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
Don’t Care
Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination.

2. DIN n = data-in to column n.
3. tWR starts at the rising edge of CK after the last latching edge of DQS.
these times.
CCM005-554574167-10729

Figure 30: Burst Write Followed by Burst Read

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10
CK_c
CK_t
CS
CA BA0, BA0,
BL CA, AP CA CA BL CA, AP CA CA
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES READ-1 CAS-2 DES DES DES DES
WL BL/2 + 1 Clock tWTR RL
tDQSS (MIN)
tDSH tDSS
tWPRE
tWPST
DQS_c
DQS_t
tDQS2DQ
DQ
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
Don’t Care

3. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].
t
4. WTR starts at the rising edge of CK after the last latching edge of DQS.
these times.
CCM005-554574167-10729

Write Timing
Figure 31: Write Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5
CK_c
CK_t
CS
CA BA0,
BL CA, AP CA CA
WL
tDQSS (MIN)
tDSH
tDQSS (MIN)
tWPRE
tDSS tWPST
DQS_c
DQS_t
tDQS2DQ
DQ
n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
tDQSS (Nominal)
tDSH
tDQSS (Nominal)
tWPRE
tDSS
DQS_c
DQS_t
tDQS2DQ
DQ
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
tDQSS (MAX)
tDSH
tDQSS (MAX) tWPRE
tDSS
DQS_c
DQS_t
tDQS2DQ tDQSH tDQSL
DQ
n0 n1 n2 n3 n4 n11 n12 n13 n14 n15
Don’t Care
Notes: 1. BL = 16, Write postamble = 0.5nCK.

these times.
CCM005-554574167-10729

tWPRE Calculation for ATE (Automatic Test Equipment)
Figure 32: Method for Calculating tWPRE Transitions and Endpoints
CK_t
Vref(CA)
CK_c
Resulting differential signal
relevant for tWPRE specification
Vsw2
Vsw1
DQS_t - DQS_c 0V
Begin point:
Extrapolated point
tWPRE
Note: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ.
Table 94: Method for Calculating tWPRE Transitions and Endpoints
Measured Parameter
DQS_t, DQS_c tWPRE VIHL_AC × 0.3 VIHL_AC × 0.7 V
differential write preamble
tWPST Calculation for ATE (Automatic Test Equipment)

Figure 33: Method for Calculating tWPST Transitions and Endpoints
CK_t
Vref(CA)
CK_c
Resulting differential signal

relevant for tWPST specification
0V
Vsw2
Vsw1
DQS_t - DQS_c End point:
Extrapolated point
tWPST
Notes: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ.
2. Write postamble: 0.5tCK
3. The method for calculating differential pulse widths for 1.5tCK postamble is same as
0.5tCK postamble.
CCM005-554574167-10729

MASK WRITE Operation
Table 95: Reference Voltage for tWPST Timing Measurements
Measured Parameter
DQS_t, DQS_c tWPST –(VIHL_AC × 0.7) –(VIHL_AC × 0.3) V
differential write postamble

The device requires that WRITE operations that include a byte mask anywhere in the
burst sequence must use the MASK WRITE command. This allows the device to imple-
ment efficient data protection schemes based on larger data blocks. The MASK
WRITE-1 command is used to begin the operation, followed by a CAS-2 command. A
MASKED WRITE command to the same bank cannot be issued until tCCDMW later, to
allow the device to finish the internal READ-MODIFY-WRITE operation. One data-
mask-invert (DMI) pin is provided per byte lane, and the data-mask-invert timings
match data bit (DQ) timing. See Data Mask Invert for more information on the use of
the DMI signal.
Figure 34: MASK WRITE Command – Same Bank

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10
CK_c
CK_t
CS
BA0, BA0,
CA BL CA, AP CA CA BL CA CA
CA, AP
Command MASK WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES MASK WRITE-1 CAS-2 DES DES DES DES
tCCDMW WL
WL tDQSS(MIN)
t
tWPRE WPST
DQS_c
DQS_t
tDQS2DQ
DQ n0 n1 n2 n3 n4 n5 n12 n13 n14 n15
DMI
Don’t Care

3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to
insert only 16-bit wide data for MASKED WRITE operation.
these time.
CCM005-554574167-10729

Figure 35: MASK WRITE Command – Different Bank

T0 T1 T2 T3 T8 T9 T10 T11 T16 T17 T18 T19 T24 T25 T26 T27 T32 T33 T34 T35 T36 T37 T38
CK_c
CK_t
CS
BA0, BA1, BA2, BA3, BA0,

CA BL CA, AP CA CA BL CA, AP CA CA BL CA, AP CA CA BL CA, AP CA CA BL CA CA
CA, AP
Command MASK WRITE-1 CAS-2 DES MASK WRITE-1 CAS-2 DES MASK WRITE-1 CAS-2 DES MASK WRITE-1 CAS-2 DES MASK WRITE-1 CAS-2 DES DES DES
tCCD tCCD tCCD tCCD
tCCDMW
WL tDQSS
tWPRE
DQS_c
DQS_t
tDQS2DQ
DQ
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
DMI n0 n1 n2 n3 n10 n11 n12 n13 n14 n15 n0 n1 n2 n3 n10 n11 n12 n13 n14 n15 n0 n1 n2 n10 n11 n12 n13 n14 n15 n0 n1 n2 n3 n4 n5 n6 n7 n8
Don’t Care
Notes: 1. BL = 16, DQ/DQS/DMI: VSSQ termination.

3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to
insert only 16-bit wide data for MASKED WRITE operation.
these time.
CCM005-554574167-10729

Mask Write Timing Constraints for BL16
Table 96: Same Bank (ODT Disabled)
Next CMD READ WRITE

Current CMD ACTIVE (BL = 16 or 32) (BL = 16 or 32) MASK WRITE PRECHARGE
ACTIVE Illegal RU(tRCD/tCK) RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK)
READ Illegal 81 RL + RL + BL/2 +
(with BL = 16) RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/ MAX{(8,RU(tRTP/
tCK) + BL/2 - WL + tCK) + BL/2 - WL + tCK)} - 8
tWPRE + RD( tRPST) tWPRE + RD( tRPST)
READ Illegal 162 RL + RL + BL/2 +

(with BL = 32) RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/ MAX{(8,RU(tRTP/
tCK) + BL/2 - WL + tCK) + BL/2 - WL + tCK)} - 8
WRITE Illegal WL + 1+ BL/2 + 81 tCCDMW3 WL + 1 + BL/2 +

(with BL = 16) RU(tWTR/tCK) RU(tWR/tCK)
WRITE Illegal WL + 1 + BL/2 + 162 tCCDMW + 84 WL + 1 + BL/2 +
MASK WRITE Illegal WL + 1 + BL/2 + tCCD tCCDMW3 WL + 1 + BL/2 +
RU(tWTR/tCK) RU(tWR/tCK)
PRECHARGE RU(tRP/tCK), Illegal Illegal Illegal 4
RU(tRPab/tCK)
Notes: 1. In the case of BL = 16, tCCD is 8 × tCK.

2. In the case of BL = 32, tCCD is 16 × tCK.
3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16).
4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16.
Table 97: Different Bank (ODT Disabled)
Next CMD READ WRITE

ACTIVE RU(tRRD/tCK) 4 4 4 22
READ 4 81 RL + RL + 22
(with BL = 16) RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/
tCK) + BL/2 - WL + tCK) + BL/2 - WL +
READ 4 162 RL + RL + 22
(with BL = 32) RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/
tCK) + BL/2 - WL + tCK) + BL/2 - WL +
WRITE 4 WL + 1+ BL/2 + 81 81 22
(with BL = 16) RU(tWTR/tCK)
WRITE 4 WL + 1 + BL/2 + 162 162 22
MASK WRITE 4 WL + 1 + BL/2 + 81 81 22
RU(tWTR/tCK)
CCM005-554574167-10729

Table 97: Different Bank (ODT Disabled) (Continued)
Next CMD READ WRITE

PRECHARGE 4 4 4 4 4
Notes: 1. In the case of BL = 16, tCCD is 8 × tCK

2. In the case of BL = 32, tCCD is 16 × tCK
Table 98: Same Bank (ODT Enabled)
Next CMD READ WRITE

ACTIVE Illegal RU(tRCD/tCK) RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK)
READ Illegal 81 RL + RU( RL + RU( BL/2 +
(with BL = 16) tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK) MAX{(8,RU(tRTP/
+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST) tCK)} - 8
- ODTLon - RD( - ODTLon - RD(

tODTon(MIN)/ tCK) tODTon(MIN)/ tCK)
READ Illegal 162 RL + RU( RL + RU( BL/2 +

(with BL = 32) tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK) MAX{(8,RU(tRTP/
+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST) tCK)} - 8

WRITE Illegal WL + 1+ BL/2 + 81 tCCDMW3 WL + 1 + BL/2 +

WRITE Illegal WL + 1 + BL/2 + 162 tCCDMW + 84 WL + 1 + BL/2 +
MASK WRITE Illegal WL + 1 + BL/2 + tCCD tCCDMW3 WL + 1 + BL/2 +
RU(tWTR/tCK) RU(tWR/tCK)
PRECHARGE RU(tRP/tCK), Illegal Illegal Illegal 4
RU(tRPab/tCK)

3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16).
4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16.
Table 99: Different Bank (ODT Enabled)
Next CMD READ WRITE

ACTIVE RU(tRRD/tCK) 4 4 4 22
READ 4 81 RL + RU( RL + RU( 22
(with BL = 16) tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK)
+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST)

CCM005-554574167-10729

Data Mask and Data Bus Inversion (DBI [DC]) Function
Table 99: Different Bank (ODT Enabled) (Continued)
Next CMD READ WRITE

READ 4 162 RL + RU( RL + RU( 22
(with BL = 32) tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK)
+ BL/2 + RD( tRPST) + BL/2 + RD( tRPST)

WRITE 4 WL + 1+ BL/2 + 81 81 22
WRITE 4 WL + 1 + BL/2 + 162 162 22
MASK WRITE 4 WL + 1 + BL/2 + 81 81 22
RU(tWTR/tCK)
PRECHARGE 4 4 4 4 4


Data mask (DM) is supported for WRITE operations and the data bus inversion DBI
(DC) is supported for READ, WRITE, MASK WRITE, MRR, and MRW operations. DM
and DBI (DC) functions are supported with byte granularity. DBI (DC) for READ opera-
tions (READ, MRR) can be enabled or disabled via MR3 OP[6]. DBI (DC) for WRITE op-
erations (WRITE, MASK WRITE, MRW) can be enabled or disabled via MR3 OP[7]. DM
for MASK WRITE operations can be enabled or disabled via MR13 OP[5]. The device has
one data mask inversion (DMI) pin per byte and a total of two DMI pins per channel.
The DMI signal is a bidirectional DDR signal, is sampled with the DQ signals, and is
electrically identical to a DQ signal.
There are eight possible states for the device with the DM and DBI (DC) functions.
Table 100: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations
DMI Signal
During During During During
DM Write DBI Read DBI During MASKED During MPC[WRIT MPC[READ- MPC[READ
Function (DC) (DC) WRITE WRITE READ E-FIFO] FIFO] DQ CAL]
Disabled Disabled Disabled Don't Care1 Illegal1, 3 High-Z2 Don't Care1 High-Z2 High-Z2
Disabled Enabled Disabled DBI (DC)4 Illegal3 High-Z2 Train9 Train10 Train11
Disabled Disabled Enabled Don't Care1 Illegal3 DBI (DC)5 Train9 Train10 Train11
Disabled Enabled Enabled DBI (DC)4 Illegal3 DBI (DC)5 Train9 Train10 Train11
Enabled Disabled Disabled Don't Care6 DM7 High-Z2 Train9 Train10 Train11
Enabled Enabled Disabled DBI (DC)4 DBI (DC)8 High-Z2 Train9 Train10 Train11
Enabled Disabled Enabled Don't Care6 DM7 DBI (DC)5 Train9 Train10 Train11
CCM005-554574167-10729

Table 100: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations
(Continued)
DMI Signal
During During During During
DM Write DBI Read DBI During MASKED During MPC[WRIT MPC[READ- MPC[READ
Function (DC) (DC) WRITE WRITE READ E-FIFO] FIFO] DQ CAL]
Enabled Enabled Enabled DBI (DC)4 DBI (DC)8 DBI (DC)5 Train9 Train10 Train11
Notes: 1. The DMI input signal is "Don’t Care." DMI input receivers are turned off.
2. DMI output drivers are turned off.
3. The MASK WRITE command is not allowed and is considered an illegal command when
the DM function is disabled.
4. The DMI signal is treated as DBI and indicates whether the device needs to invert the
write data received on DQ within a byte. The device inverts write data received on the
DQ inputs if DMI is sampled HIGH and leaves the write data non-inverted if DMI is sam-
pled LOW.
5. The device inverts read data on its DQ outputs associated within a byte and drives the
DMI signal HIGH when more than four data bits = 1 within a given byte lane; otherwise,
the device does not invert the read data and drives DMI signal LOW.
6. The device does not perform a MASK operation when it receives a WRITE (or MRW)
command. During the WRITE burst, the DMI signal must be driven LOW.
7. The device requires an explicit MASKED WRITE command for all MASKED WRITE opera-
tions. The DMI signal is treated as a data mask (DM) and indicates which bytes within a
burst will be masked. When the DMI signal is sampled HIGH, the device masks that beat
of the burst for the given byte lane. All DQ input signals within a byte are "Don't Care"
(either HIGH or LOW) when DMI is HIGH. When the DMI signal is sampled LOW, the de-
vice does not perform a MASK operation and data received on the DQ inputs is written
to the array.
8. The device requires an explicit MASKED WRITE command for all MASKED WRITE opera-
tions. The device masks the write data received on the DQ inputs if five or more data
bits = 1 on DQ[2:7] or DQ[10:15] (for lower byte or upper byte respectively) and the DMI
signal is LOW. Otherwise, the device does not perform the MASK operation and treats it
as a legal DBI pattern. The DMI signal is treated as a DBI signal, and data received on
the DQ input is written to the array.
9. The DMI signal is treated as a training pattern. The device does not perform any MASK
operation and does not invert write data received on the DQ inputs.
10. The DMI signal is treated as a training pattern. The device returns the data pattern writ-
ten to the WRITE-FIFO.
11. The DMI signal is treated as a training pattern. For more information, see the Read DQ
Calibration Training section.
CCM005-554574167-10729

Figure 36: MASKED WRITE Command with Write DBI Enabled; DM Enabled
T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0

CK_c
CK_t
CKE
CS
Command MASK WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES
WL t
DQSS
DQS_c
DQS_t
t
DQS2DQ
t
WPRE
DQ[7:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
N1 I 2 I M3 N I N M N N
DMI[0]
Don’t Care
Notes: 1. N: Input data is written to DRAM cell.

2. I: Input data is inverted, then written to DRAM cell.
3. M: Input data is masked. The total count of 1 data bits on DQ[7:2] is equal to or greater
than five.
4. Data mask (DM) is enable: MR13 OP [5] = 0, Data bus inversion (DBI) write is enable:
MR3 OP[7] = 1.
CCM005-554574167-10729

Figure 37: WRITE Command with Write DBI Enabled; DM Disabled
T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0

CK_c
CK_t
CKE
CS
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES
t
WL DQSS
DQS_c
DQS_t
t
DQS2DQ
t
WPRE
DQ[7:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
N1 N I2 I N N I N N N
DMI[0]
Don’t Care
Notes: 1. N: Input data is written to DRAM cell.

2. I: Input data is inverted, then written to DRAM cell.
3. Data mask (DM) is disable: MR13 OP [5] = 1, Data bus inversion (DBI) write is enable:
MR3 OP[7] = 1.
CCM005-554574167-10729
WRITE and MASKED WRITE Operation DQS Control (WDQS
Control)
WRITE and MASKED WRITE Operation DQS Control (WDQS Control)

The device supports WRITE, MASKED WRITE, and WR-FIFO operations with the fol-
lowing DQS controls. Before and after WRITE, MASKED WRITE, and WR-FIFO opera-
tions, DQS_t, and DQS_c are required to have sufficient voltage gap to make sure the
write buffers operate normally without any risk of meta-stability.
The device is supported by either of the two WDQS control modes below.
• Mode 1: Read-based control
• Mode 2: WDQS_on / WDQS_off definition based control
Regardless of ODT enable/disable, WDQS-related timing described here does not allow
any change of existing command timing constraints for all READ/WRITE operations. In
case of any conflict or ambiguity on the command timing constraints caused by the
specification here, the specification defined in the Timing Constraints for Training
Commands table should have higher priority than WDQS control requirements.
To prevent write preamble related failure, either of the two WDQS controls to the device
should be supported.
WDQS Control Mode 1 – Read-Based Control

The device needs to be guaranteed the differential WDQS, but the differential WDQS
can be controlled as described below. WDQS control requirements here can be ignored
while differential read DQS is operated or while DQS hands over from read to write or
vice versa.
1. When WRITE/MASKED WRITE command is issued, SoC makes the transition
from driving DQS_c HIGH to driving differential DQS_t/DQS_c, followed by nor-
mal differential burst on DQS pins.
2. At the end of post amble of WRITE/MASKED WRITE burst, SoC resumes driving
DQS_c HIGH through the subsequent states except for DQS toggling and DQS
turn around time of WT-RD and RD-WT as long as CKE is HIGH.
3. When CKE is LOW, the state of DQS_t/DQS_c is allowed to be “Don’t Care.”
Figure 38: WDQS Control Mode 1
WT
CMD WT BURST Following states from WT burst
CKE
DQS_c
DQS_t
Don’t Care
WDQS Control Mode 2 – WDQS_On/Off

After WRITE/MASKED WRITE command is issued, DQS_t and DQS_c required to be
differential from WDQS_on, and DQS_t and DQS_c can be “Don’t Care” status from
WDQS_off of WRITE/MASKED WRITE command. When ODT is enabled, WDQS_on
and WDQS_off timing is located in the middle of the operations. When host disables
CCM005-554574167-10729
Control)
ODT, WDQS_on and WDQS_off constraints conflict with tRTW. The timing does not
conflict when ODT is enabled because WDQS_on and WDQS_off timing is covered in
ODTLon and ODTLoff. However, regardless of ODT on/off, WDQS_on/off timing below
does not change any command timing constraints for all read and write operations. To
prevent the conflict, WDQS_on/off requirement can be ignored where WDQS_on/off
timing is overlapped with read operation period including READ burst period and
tRPST or overlapped with turn-around time (RD-WT or WT-RD). In addition, the period
during DQS toggling caused by read and write can be counted as WDQS_on/off.
Parameters
• WDQS_on: The maximum delay from WRITE/MASKED WRITE command to differen-
tial DQS_t and DQS_c
• WDQS_off: The minimum delay for DQS_t and DQS_c differential input after the last
WRITE/MASKED WRITE command
• WDQS_Exception: The period where WDQS_on and WDQS_off timing is overlapped
with READ operation or with DQS turn around (RD-WT, WT-RD)
– WDQS_Exception @ ODT disable = MAX(WL-WDQS_on + tDQSTA - tWPRE - n tCK,
0 tCK) where RD to WT command gap = tRTW(MIN)@ODT disable + n tCK
– WDQS_Exception @ ODT enable = tDQSTA
Table 101: WDQS_On/WDQS_Off Definition
WRITE WDQS_On WDQS_Off Lower Upper

Latency (Max) (Min) Frequency Frequency
Set A Set B nWR nRTP Set A Set B Set A Set B Limit (>) Limit (≤)
4 4 6 8 0 0 15 15 10 266
6 8 10 8 0 0 18 20 266 533
8 12 16 8 0 6 21 25 533 800
10 18 20 8 4 12 24 32 800 1066
12 22 24 10 4 14 27 37 1066 1333
14 26 30 12 6 18 30 42 1333 1600
16 30 34 14 6 20 33 47 1600 1866
18 34 40 16 8 24 36 52 1866 2133
Notes: 1. WDQS_on/off requirement can be ignored when WDQS_on/off timing is overlapped

with READ operation period including READ burst period and tRPST or overlapped with
turn-around time (RD-WT or WT-RD).
2. DQS toggling period caused by read and write can be counted as WDQS_on/off.
Table 102: WDQS_On/WDQS_Off Allowable Variation Range
Min Max Unit

WDQS_on –0.25 0.25 tCK(avg)
WDQS_off –0.25 0.25 tCK(avg)
CCM005-554574167-10729
Control)
Table 103: DQS Turn-Around Parameter
Parameter Description Value Unit Note

tDQSTA Turn-around time RDQS to WDQS for WDQS control case TBD – 1
Note: 1. tDQSTA is only applied to WDQS_exception case when WDQS Control. Except for WDQS
Control, tDQSTA can be ignored.
Figure 39: Burst WRITE Operation

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 Ta13 Ta14 Ta15 Ta16 Ta17 Ta18 Ta19 Ta20 Ta21
CK_c
CK_t
CS
BA0,
CA BL CA,AP CA CA
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
WL
WDQS_off
t DQSS(MIN)
tWPRE t WPST
WDQS_on
DQS_c
DQS_t
t DQS2DQ
DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI
DQ n0 n1
n0 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
t
DQSS(MAX)
t
t WPRE
WPST
DQS_c
DQS_t
t
DQS2DQ
DI
n0 DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI
DQ n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
ODTLon tODTon(MAX)
tODTon(MIN)
DRAM RTT ODT High-Z Transion ODT on Transition ODT High-Z
ODTL off tODToff(MIN)
tODToff(MAX)
Don’t Care
Notes: 1. BL=16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination.

2. DI n = data-in to column n.
these times.
4. DRAM RTT is only applied when ODT is enabled (MR11 OP[2:0] is not 000b).
CCM005-554574167-10729
Control)
Figure 40: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Disable)
T0 T1 T2 T3 T4 T8 T a0 Ta1 T a2 T a3 T a4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 T b7 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
CK_c
CK_t
CS
CA BA0, BA0,
BL CA, AP CA CA BL CA, AP CA CA
Command READ-1 CAS-2 DES DES DES WR-1/MWR-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
t
RL + RU(tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - WL + tWPRE WL DQSS
WDQS_off
WDQS_on WDQS_exception
t
RL DQSCK BL/2 = 8
t t
RPRE WPRE
DQS_c
DQS_t
t
t
DQSQ t
RPST t
DQSTA DQS2DQ
D0 D0 D0 D0 D0 D0 D0 D0 DI DI DI DI DI DI DI DI
DQ n0 n9 n10 n11 n12 n13 n14 n15 n0 n9 n10 n11 n12 n13 n14 n15
Don’t Care
Write postamble = 0.5nCK.
2. DO n = data-out from column n, DI n = data-in to column n.
these times.
4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is
overlapped with READ operation period including READ burst period and tRPST or over-
lapped with turn-around time (RD-WT or WT-RD).
CCM005-554574167-10729

Preamble and Postamble Behavior
Figure 41: Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Enable)
T0 T1 T2 T3 T4 T8 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Td0 Td1 Td2 Td3 Td4 Te0 Te1 Te2 Te3 Te4 Te5 Te6 Tf0 Tf1
CK_c
CK_t
CS
BA0, BA0,
CA BL CA,AP CA CA BL CA,AP CA CA
Command READ-1 CAS-2 DES DES DES WR-1/MWR-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
t
WL DQSS
RL +RU(tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST)
- ODTLon - RD(tODTon(MIN)/ tCK) + 1 WDQS_off
ODTL_off
WDQS_on
ODTLon
t
RL DQSCK BL/2 = 8
t t WPRE
RPRE
DQS_c
DQS_t
tRPST t
t
DQSQ DQSTA t
DQS2DQ
DO DO DO DO DO DO DO DO DI DI DI DI DI DI DI DI
n0 n9 n10 n11 n12 n13 n14 n15 n0 n9 n10 n11 n12 n13 n14 n15
DQ
ODTon,max ODToff,max
ODTon,min
ODToff,min
DRAM RTT ODT High-Z Transion Transition ODT On Transion ODT High-Z
Don’t Care
Write postamble = 0.5nCK, DQ/DQS: VSSQ termination.
2. DO n = data-out from column n, DI n = data-in to column n.
these times.
4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is
overlapped with READ operation period including READ burst period and tRPST or over-
lapped with turn-around time (RD-WT or WT-RD).

Preamble, Postamble Behavior in READ-to-READ Operations
The following illustrations show the behavior of the device's read DQS_t and DQS_c
pins during cases where the preamble, postamble, and/or data clocking overlap.
DQS will be driven with the following priority
1. Data clocking edges will always be driven
2. Postamble
3. Preamble
Essentially the data clocking, preamble, and postamble will be ordered such that all
edges will be driven.
Additional examples of seamless and borderline non-overlapping cases have been in-
cluded for clarity.
CCM005-554574167-10729

READ-to-READ Operations – Seamless
Figure 42: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble
CK_c
CK_t
CS
BA0, BA0,
CA BL CAn CAn BL CAm CAm
CA, AP CA, AP
Command READ-1 CAS-2 DES DES READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
t
t
CCD = 8 RL = 6 DQSCK
t
RL = 6 DQSCK
t
t
RPRE RPST
DQS_c
High-Z High-Z
DQS_t
t
t
DQSQ DQSQ
High-Z High-Z
DMI n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m12 m13 m14 m15
BL/2 = 8 BL/2 = 8
Don’t Care
Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK.

these times.
CCM005-554574167-10729

READ-to-READ Operations – Consecutive
Figure 43: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
Command READ-1 CAS-2 DES DES DES READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES
t
t
t
RL = 6 DQSCK
t
t
RPRE RPST t
RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
High-Z n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15
High-Z m0 m1 m12 m13 m14 m15
High-Z
DMI
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
Figure 44: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t
t
RPRE t
RPRE
RPST t
RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
High-Z High-Z High-Z
BL/2 = 8 BL/2 = 8
Don’t Care

CCM005-554574167-10729

these times.
Figure 45: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t t t
RPRE RPST RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
BL/2 = 8 BL/2 = 8
Don’t Care
Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK.

these times.
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t t t
RPRE RPRE RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
BL/2 = 8 BL/2 = 8
Don’t Care
CCM005-554574167-10729


these times.
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
Command READ-1 CAS-2 DES DES DES DES READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES
t
t
t
RL = 6 DQSCK
t t t t
RPRE RPST RPRE RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
High-Z High-Z m0 m1 m12 m13 m14 m15
High-Z
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CCM005-554574167-10729

CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t t
RPRE t RPRE
RPST t
RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
High-Z
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t t t t
RPRE RPST RPRE RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
High-Z m0 m1 m12 m13 m14 m15
High-Z
DMI
BL/2 = 8 BL/2 = 8
Don’t Care

CCM005-554574167-10729

these times.
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t t
RPRE t
RPST RPRE t
RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
High-Z
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CCM005-554574167-10729

CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
Command READ-1 CAS-2 DES DES DES DES DES READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES
t
t
t
RL = 6 DQSCK
t t t t
RPRE RPST RPRE RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t t
RPRE t
RPRE
RPST t
RPST
DQS_c
DQS_t
t t
DQSQ DQSQ
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CCM005-554574167-10729

CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t t t t
RPRE RPST RPRE RPST
DQS_c
High-Z High-Z
DQS_t
t t
DQSQ DQSQ
High-Z m0 m1 m12 m13 m14 m15
High-Z
DMI
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CK_c
CK_t
CS
BA0, BA0,
CA, AP CA, AP
t
t
t
RL = 6 DQSCK
t
t
RPRE t
RPRE t
RPST RPST
DQS_c
DQS_t
t t
DQSQ DQSQ
High-Z m0 m1 m12 m13 m14 m15
High-Z
DMI
BL/2 = 8 BL/2 = 8
Don’t Care
Notes: 1. BL = 16 for column n and column m; RL = 6, Preamble = Static; Postamble = 0.5nCK

these times.
CCM005-554574167-10729

WRITE-to-WRITE Operations – Seamless
Figure 55: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble

CK_c
CK_t
CS
BA0, BA0,
CA CA
Command WRITE-1 CAS-2 DES DES DES DES WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES
t
CCD = 8 WL = 4
t
DQSS
WL = 4 t
DQSS
t
WPRE t
WPST
DQS_c
DQS_t
t
t
DQS2DQ DQS2DQ
DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
DMI n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m2 m3 m12 m13 m14 m15
BL/2 = 8 BL/2 = 8
Don’t Care

2. DIN n/m = data-in from column n and column m.
3. The minimum number of clock cycles from the burst WRITE command to the burst
WRITE command for any bank is BL/2.
these times.
CCM005-554574167-10729

Figure 56: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency ≤ 800 MHz,
ODT Worst Timing Case
CK_c
CK_t
CS
BA0, BA0,
CA CA
Command WRITE-1 CAS-2 DES DES WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
t
CCD = 8 WL = 12
t
DQSS
WL = 12 t
DQSS
t t
WPRE WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
DMI
t
ODTLon = 6 ODTon(MAX) BL/2 = 8 BL/2 = 8
DRAM RTT ODT High-Z ODT on ODT High-Z
ODTLoff = 22 t
ODToff(MIN)
Don’t Care
Notes: 1. Clock frequency = 800 MHz, tCK(AVG) = 1.25ns.

2. BL = 16, Write postamble = 1.5nCK.
these times.
CCM005-554574167-10729

Figure 57: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble

CK_c
CK_t
CS
BA0, BA0,
CA CA
t
CCD = 8 WL = 14
t
DQSS
WL = 14 t
DQSS
t t
WPRE WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
DMI
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CCM005-554574167-10729

WRITE-to-WRITE Operations – Consecutive
Figure 58: Consecutive WRITE: tCCD = MIN + 1, 0.5nCK Postamble

CK_c
CK_t
CS
BA0, BA0,
CA CA
t
CCD = 9 WL = 12 t
DQSS
WL = 12 t
DQSS
t
WPRE t
WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
DMI n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
BL/2 = 8 BL/2 = 8
Don’t Care

these times.

CK_c
CK_t
CS
BA0, BA0,
CA CA
t
CCD = 9 WL = 12 t
DQSS
WL = 12 t
DQSS
t t
WPRE WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
DMI
BL/2 = 8 BL/2 = 8
Don’t Care

CCM005-554574167-10729

these times.

CK_c
CK_t
CS
BA0, BA0,
CA CA
t
CCD = 10 WL = 12 t
DQSS
WL = 12 t
DQSS
t t
WPRE WPRE t
WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
DMI
BL/2 = 8 BL/2 = 8
Don’t Care

these times.

CK_c
CK_t
CS
BA0, BA0,
CA CA
t
CCD = 10 WL = 12 t
DQSS
WL = 12 t
DQSS
t t t
WPRE WPRE WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
DMI
BL/2 = 8 BL/2 = 8
Don’t Care
CCM005-554574167-10729


these times.

CK_c
CK_t
CS
BA0, BA0,
CA CA
Command WRITE-1 CAS-2 DES DES DES WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES
t
CCD = 11 WL = 12 t
DQSS
WL = 12 t
DQSS
t t
WPRE t
WPST WPRE t
WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN Din DIN DIN
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CCM005-554574167-10729


CK_c
CK_t
CS
BA0, BA0,
CA CA
t
CCD = 11 WL = 12 t
DQSS
WL = 12 t
DQSS
t t t t
WPRE WPST WPRE WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
n0 n1 n2 n13 n14 n15 m0 m1 m2 m13 m14 m15
DMI
BL/2 = 8 BL/2 = 8
Don’t Care

these times.

CK_c
CK_t
CS
BA0, BA0,
CA CA
t
CCD = 12 WL = 12 t
DQSS
WL = 12 t
DQSS
t t t t
WPRE WPST WPRE WPST
DQS_c
DQS_t
t t
DQS2DQ DQS2DQ
BL/2 = 8 BL/2 = 8
Don’t Care

these times.
CCM005-554574167-10729

PRECHARGE Operation
PRECHARGE Operation
The PRECHARGE command is used to precharge or close a bank that has been activa-
ted. The PRECHARGE command is initiated with CKE, CS, and CA[5:0] in the proper
state (see Command Truth Table). The PRECHARGE command can be used to pre-
charge each bank independently or all banks simultaneously. The all banks (AB) flag
and the bank address bit are used to determine which bank(s) to precharge. The pre-
charged bank(s) will be available for subsequent row access tRPab after an all-bank
PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command
is issued.
To ensure that the device can meet the instantaneous current demands, the row pre-
charge time for an all-bank PRECHARGE ( tRPab) is longer than the per-bank precharge
time (tRPpb).
Table 104: Precharge Bank Selection
AB (CA[5], R1) BA2 (CA[2], R2) BA1 (CA[1], R2) BA0 (CA[0], R2) Precharged Bank
0 0 0 0 Bank 0 only
0 0 0 1 Bank 1 only
0 0 1 0 Bank 2 only
0 0 1 1 Bank 3 only
0 1 0 0 Bank 4 only
0 1 0 1 Bank 5 only
0 1 1 0 Bank 6 only
0 1 1 1 Bank 7 only
1 Don't Care Don't Care Don't Care All banks
Burst READ Operation Followed by Precharge

The PRECHARGE command can be issued as early as BL/2 clock cycles after a READ
command, but the PRECHARGE command cannot be issued until after tRAS is satisfied.
A new bank ACTIVATE command can be issued to the same bank after the row pre-
charge time (tRP) has elapsed. The minimum read-to-precharge time must also satisfy a
minimum analog time from the second rising clock edge of the CAS-2 command. tRTP
begins BL/2 - 8 clock cycles after the READ command.
CCM005-554574167-10729

PRECHARGE Operation
Figure 65: Burst READ Followed by Precharge – BL16, Toggling Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Ty Ty+1 Ty+2 Ty+3 Ty+4
CK_c
CK_t
CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
tRTP tRP
Command READ-1 CAS-2 Valid PRECHARGE Valid Valid Valid ACT-1 ACT-2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Valid
Transitioning Data Don’t Care
Figure 66: Burst READ Followed by Precharge – BL32, 2tCK, 0.5nCK Postamble
T0 T1 T2 T3 T4 T5 T10 T11 T12 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Ty Ty+1 Ty+2 Ty+3 Ty+4
CK_c
CK_t
CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
tRTP tRP
Command READ-1 CAS-2 Valid Valid Valid PRECHARGE Valid Valid Valid ACT-1 ACT-2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Valid
Burst WRITE Followed by Precharge

A write recovery time (tWR) must be provided before a PRECHARGE command may be
issued. This delay is referenced from the next rising edge of CK after the last valid DQS
clock of the burst.
Devices write data to the memory array in prefetch multiples (prefetch = 16). An inter-
nal WRITE operation can only begin after a prefetch group has been clocked; therefore,
tWR starts at the prefetch boundaries. The minimum write-to-precharge time for com-
mands to the same bank is WL + BL/2 + 1 + RU( tWR /tCK) clock cycles.
CCM005-554574167-10729

Auto Precharge
Figure 67: Burst WRITE Followed by PRECHARGE – BL16, 2nCK Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Ta Ta+1 Ta+2 Tn Tn+1 Tn+2 Tn+3 Ty Ty+1 Ty+2 Ty+3 Ty+4
CK_c
CK_t
CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
WL
Command WRITE-1 CAS-2 Valid Valid Valid Valid Valid Valid PRECHARGE Valid ACT-1 ACT-2
tDQSS(MAX) tWR tRP
DQS_c
DQS_t
tDQS2DQ
DQ
DMI
Valid
Auto Precharge
Before a new row can be opened in an active bank, the active bank must be precharged
using either the PRECHARGE command or the auto precharge (AP) function. When a
READ or a WRITE command is issued to the device, the AP bit (CA5) can be set to ena-
ble the active bank to automatically begin precharge at the earliest possible moment
during the burst READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, the normal READ or WRITE
burst operation is executed, and the bank remains active at the completion of the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto PRECHARGE
function is engaged. This feature enables the PRECHARGE operation to be partially or
completely hidden during burst READ cycles (dependent upon READ or WRITE laten-
cy), thus improving system performance for random data access.
Burst READ With Auto Precharge

If AP is HIGH when a READ command is issued, the READ with AUTO PRECHARGE
function is engaged. The devices start an AUTO PRECHARGE operation on the rising
edge of the clock at BL/2 after the second beat of the READ w/AP command, or BL/4 - 4
+ RU(tRTP/tCK) clock cycles after the second beat of the READ w/AP command, which-
ever is greater. Following an AUTO PRECHARGE operation, an ACTIVATE command can
be issued to the same bank if the following two conditions are both satisfied:
1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto
precharge began, and
2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
CCM005-554574167-10729

Auto Precharge
Figure 68: Burst READ With Auto Precharge – BL16, Non-Toggling Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Ty Ty+1 Ty+2 Ty+3 Ty+4
CK_c
CK_t
CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
tRTP tRPpb
READ-1
Command w/AP
CAS-2 Valid Valid Valid Valid Valid ACT-1 ACT-2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Valid
Figure 69: Burst READ With Auto Precharge – BL32, Toggling Preamble, 1.5nCK Postamble
T0 T1 T2 T3 T4 T5 T10 T11 T12 T13 T14 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Ty Ty+1 Ty+2 Ty+3 Ty+4
CK_c
CK_t
CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
tRTP tRP
Command READ-1 CAS-2 Valid Valid Valid Valid Valid Valid Valid ACT-1 ACT-2
DQS_t
DQS_c
DQ[15:0]
DMI[1:0]
Valid
Burst WRITE With Auto Precharge

If AP is HIGH when a WRITE command is issued, the WRITE with AUTO PRECHARGE
function is engaged. The device starts an auto precharge on the rising edge tWR cycles
after the completion of the burst WRITE.
Following a WRITE with AUTO PRECHARGE, an ACTIVATE command can be issued to
the same bank if the following conditions are met:
1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto
precharge began, and
CCM005-554574167-10729

Auto Precharge
2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Figure 70: Burst WRITE With Auto Precharge – BL16, 2nCK Preamble, 0.5nCK Postamble
T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Ta Ta+1 Ta+2 Tn Tn+1 Tn+2 Tn+3 Ty Ty+1 Ty+2 Ty+3 Ty+4
CK_c
CK_t
CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
WL
Command WRITE-1 CAS-2 Valid Valid Valid Valid Valid Valid Valid Valid ACT-1 ACT-2
tDQSS (MAX) tWR tRP
DQS_c
DQS_t
tDQS2DQ
DQ[15:0]
DMI[1:0]
Valid
Table 105: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable
Minimum Delay Between

From Command To Command "From Command" and "To Command" Unit Notes
READ PRECHARGE tRTP tCK 1, 6
BL = 16 (to same bank as READ)
PRECHARGE ALL tRTP tCK 1, 6
READ PRECHARGE 8tCK + tRTP tCK 1, 6
BL = 32 (to same bank as READ)
PRECHARGE ALL 8tCK + tRTP tCK 1, 6
READ w/AP PRECHARGE nRTP tCK 1, 10
BL = 16 (to same bank as READ w/AP)
PRECHARGE ALL nRTP tCK 1, 10
ACTIVATE nRTP + tRPpb tCK 1, 8, 10
(to same bank as READ w/AP)
WRITE or WRITE w/AP Illegal –
(same bank)
MASK-WR or MASK-WR w/AP Illegal –
(same bank)
WRITE or WRITE w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 3, 4, 5
(different bank) + RD(tRPST) - WL + tWPRE
MASK-WR or MASK-WR w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 3, 4, 5
READ or READ w/AP Illegal –
(same bank)
READ or READ w/AP BL/2 tCK 3
(different bank)
CCM005-554574167-10729

Auto Precharge
(Continued)

READ w/AP PRECHARGE 8tCK + nRTP tCK 1, 10
BL = 32 (to same bank as READ w/AP)
PRECHARGE ALL 8tCK + nRTP tCK 1, 10
ACTIVATE 8tCK + nRTP + tRPpb tCK 1, 8, 10
(to same bank as READ w/AP)
(same bank)
MASK-WR or MASK-WR w/AP Illegal –
(same bank)
WRITE or WRITE w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 3, 4, 5
MASK-WR or MASK-WR w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 3, 4, 5
(same bank)
READ or READ w/AP BL/2 tCK 3
(different bank)
WRITE PRECHARGE WL + BL/2 + tWR + 1 tCK 1, 7
BL = 16 and 32 (to same bank as WRITE)
PRECHARGE ALL WL + BL/2 + tWR + 1 tCK 1, 7
MASK-WR PRECHARGE WL + BL/2 + tWR +1 tCK 1, 7
BL = 16 (to same bank as MASK-WR)
PRECHARGE ALL WL + BL/2 + tWR + 1 tCK 1, 7
WRITE w/AP PRECHARGE WL + BL/2 + nWR + 1 tCK 1, 11
BL = 16 and 32 (to same bank as WRITE w/AP)
PRECHARGE ALL WL + BL/2 + nWR + 1 tCK 1, 11
ACTIVATE WL + BL/2 + nWR + 1 + tRPpb tCK 1, 8, 11
(to same bank as WRITE w/AP)
(same bank)
(same bank)
WRITE or WRITE w/AP BL/2 tCK 3
(different bank)
MASK-WR or MASK-WR w/AP BL/2 tCK 3
(different bank)
READ or READ w/AP WL + BL/2 + tWTR + 1 tCK 3, 9
(different bank)
CCM005-554574167-10729

Auto Precharge
(Continued)

MASK-WR w/AP PRECHARGE WL + BL/2 + nWR +1 tCK 1, 11
BL = 16 (to same bank as MASK-WR
w/AP)
PRECHARGE ALL WL + BL/2 + nWR + 1 tCK 1, 11
ACTIVATE WL + BL/2 + nWR + 1 + tRPpb tCK 1, 8, 11
(to same bank as MASK-WR
w/AP)
WRITE or WRITE w/AP Illegal – 3
(same bank)
MASK-WR or MASK-WR w/AP Illegal – 3
(same bank)
WRITE or WRITE w/AP BL/2 tCK 3
(different bank)
MASK-WR or MASK-WR w/AP BL/2 tCK 3
(different bank)
READ or READ w/AP Illegal – 3
(same bank)
READ or READ w/AP WL + BL/2 + tWTR + 1 tCK 3, 9
(different bank)
PRECHARGE PRECHARGE 4 tCK 1
(to same bank as PRECHARGE)
PRECHARGE ALL 4 tCK 1
PRECHARGE ALL PRECHARGE 4 tCK 1
PRECHARGE ALL 4 tCK 1
Notes: 1. For a given bank, the precharge period should be counted from the latest PRECHARGE
command, whether per-bank or all-bank, issued to that bank. The precharge period is
satisfied tRP after that latest PRECHARGE command.
2. Any command issued during the minimum delay time as specified in the table above is
illegal.
3. After READ w/AP, seamless READ operations to different banks are supported. After
WRITE w/AP or MASK-WR w/AP, seamless WRITE operations to different banks are sup-
ported. READ, WRITE, and MASK-WR operations may not be truncated or interrupted.
4. tRPST values depend on MR1 OP[7] respectively.
5. tWPRE values depend on MR1 OP[2] respectively.
6. Minimum delay between "from command" and "to command" in clock cycle is calcula-
ted by dividing tRTP (in ns) by tCK (in ns) and rounding up to the next integer: Minimum
delay [cycles] = roundup(tRTP [ns]/tCK [ns]).
ted by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: Minimum
delay [cycles] = roundup(tWR [ns]/tCK [ns]).
CCM005-554574167-10729

Auto Precharge
ted by dividing tRPpb (in ns) by tCK (in ns) and rounding up to the next integer: Mini-
mum delay [cycles] = roundup(tRPpb [ns]/tCK [ns]).
ted by dividing tWTR (in ns) by tCK (in ns) and rounding up to the next integer: Mini-
mum delay [cycles] = roundup(tWTR [ns]/tCK [ns]).
10. For READ w/AP the value is nRTP, which is defined in mode register 2.
11. For WRITE w/AP the value is nWR, which is defined in mode register 1.
Table 106: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Enable

READ w/AP WRITE or WRITE w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 2, 3
BL = 16 (different bank) + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1
MASK-WR or MASK-WR w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 2, 3
(different bank) + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1
READ w/AP WRITE or WRITE w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 2, 3
BL = 32 (different bank) + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1
MASK-WR or MASK-WR w/AP RL + RU(tDQSCK(MAX)/tCK) + BL/2 tCK 2, 3
(different bank) + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1
Notes: 1. The rest of the timing about PRECHARGE and AUTO PRECHARGE is same as DQ ODT is
disable case.
2. After READ w/AP, seamless read operations to different banks are supported. READ,
WRITE, and MASK-WR operations may not be truncated or interrupted.
3. tRPST values depend on MR1 OP[7] respectively.
RAS Lock Function

READ with AUTO PRECHARGE or WRITE/MASK WRITE with AUTO PRECHARGE com-
mands may be issued after tRCD has been satisfied. The LPDDR4 SDRAM RAS lockout
feature will schedule the internal precharge to assure that tRAS is satisfied. tRC needs to
be satisfied prior to issuing subsequent ACTIVATE commands to the same bank.
The figure below shows example of RAS lock function.
CCM005-554574167-10729

Auto Precharge
Figure 71: Command Input Timing with RAS Lock

T0 T1 T2 T3 T4 T19 T20 T21 T22 T23 T24 T25 T31 T32 T38 T39 T47 T48 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5
CK_c
CK_t
CKE
CS
RA RA
CA RA
BA0
RA RA Valid BA0 CA CA RA
BA0
RA RA
Command ACTIVATE-1 ACTIVATE-2 DES DES RDA-1 CAS-2 DES DES DES DES DES DES DES DES DES DES ACTIVATE-1 ACTIVATE-2
tRCD = 20nCK 8nCK nRTP = 8nCK
tRAS
tRC
Don’t Care
Notes: 1. tCK (AVG) = 0.938ns, Data rate = 2133 Mb/s, tRCD(MIN) = MAX(18ns, 4nCK), tRAS(MIN) =
MAX(42ns, 3nCK), nRTP = 8nCK, BL = 32.
2. tRCD = 20nCK comes from roundup(18ns/0.938ns).
these times.
Delay Time From WRITE-to-READ with Auto Precharge

In the case of WRITE command followed by READ with AUTO PRECHARGE, controller
must satisfy tWR for the WRITE command before initiating the device internal auto-pre-
charge. It means that (tWTR + nRTP) should be equal or longer than (tWR) when BL set-
ting is 16, as well as (tWTR + nRTP + 8nCK) should be equal or longer than (tWR) when
BL setting is 32. Refer to the following figure for details.
Figure 72: Delay Time From WRITE-to-READ with Auto Precharge

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Td0 Td1 Td2 Td3 Td4
CK_c
CK_t
CKE
CS
BA0
CA BL
CA
CA CA Valid BA0 CA CA
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES RDA-1 CAS-2 DES DES DES DES DES DES
WL BL/2 + 1 clock tWTR nRTP
tWR
Don’t Care
Notes: 1. Burst length at read = 16.
CCM005-554574167-10729

REFRESH Command
these times.
REFRESH Command
The REFRESH command is initiated with CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3
HIGH and CA4 LOW at the first rising edge of clock. Per-bank REFRESH is initiated with
CA5 LOW at the first rising edge of the clock. The all-bank REFRESH is initiated with
CA5 HIGH at the first rising edge of clock.
A per-bank REFRESH command (REFpb) is performed to the bank address as transfer-
red on CA0, CA1, and CA2 on the second rising edge of the clock. Bank address BA0 is
transferred on CA0, bank address BA1 is transferred on CA1, and bank address BA2 is
transferred on CA2. A per-bank REFRESH command (REFpb) to the eight banks can be
issued in any order. For example, REFpb commands may be issued in the following or-
der: 1-3-0-2-4-7-5-6. After the eight banks have been refreshed using the per-bank RE-
FRESH command, the controller can send another set of per-bank REFRESH com-
mands in the same order or a different order. One possible order can be a sequential
round robin: 0-1-2-3-4-5-6-7. It is illegal to send a per-bank REFRESH command to the
same bank unless all eight banks have been refreshed using the per-bank REFRESH
command. The count of eight REFpb commands starts with the first REFpb command
after a synchronization event.
The bank count is synchronized between the controller and the device by resetting the
bank count to zero. Synchronization can occur upon reset procedure or at every exit
from self refresh. The REFab command also synchronizes the counter between the con-
troller and the device to zero. The device can be placed in self refresh, or a REFab com-
mand can be issued at any time without cycling through all eight banks using per-bank
REFRESH command. After the bank count is synchronized to zero, the controller can
issue per-bank REFRESH commands in any order, as described above.
A REFab command issued when the bank counter is not zero will reset the bank counter
to zero and the device will perform refreshes to all banks as indicated by the row coun-
ter. If another REFRESH command (REFab or REFpb) is issued after the REFab com-
mand then it uses an incremented value of the row counter.
The table below shows examples of both bank and refresh counter increment behavior.
Table 107: Bank and Refresh Counter Increment Behavior
Refresh Bank Ref. Conter #

# Command BA2 BA1 BA0 Bank # Counter # (Row Address #)
0 Reset, SRX, or REFab To 0 –
1 REFpb 0 0 0 0 0 to 1 n
2 REFpb 0 0 1 1 1 to 2
3 REFpb 0 1 0 2 2 to 3
4 REFpb 0 1 1 3 3 to 4
5 REFpb 1 0 0 4 4 to 5
6 REFpb 1 0 1 5 5 to 6
7 REFpb 1 1 0 6 6 to 7
8 REFpb 1 1 1 7 7 to 0
CCM005-554574167-10729

REFRESH Command
Table 107: Bank and Refresh Counter Increment Behavior (Continued)
Refresh Bank Ref. Conter #

# Command BA2 BA1 BA0 Bank # Counter # (Row Address #)
9 REFpb 1 1 0 6 0 to 1 n+1
10 REFpb 1 1 1 7 1 to 2
11 REFpb 0 0 1 1 2 to 3
12 REFpb 0 1 1 3 3 to 4
13 REFpb 1 0 1 5 4 to 5
14 REFpb 0 1 0 2 5 to 6
15 REFpb 0 0 0 0 6 to 7
16 REFpb 1 0 0 4 7 to 0
17 REFpb 0 0 0 0 0 to 1 n+2
18 REFpb 0 0 1 1 1 to 2
19 REFpb 0 1 0 2 2 to 3
20 REFab V V V 0 to 7 To 0 n+2
21 REFpb 1 1 0 6 0 to 1 n+3
22 REFpb 1 1 1 7 1 to 2
Snip
A bank must be idle before it can be refreshed. The controller must track the bank being
refreshed by the per-bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions
have been met:
• tRFCab has been satisfied after the prior REFab command
• tRFCpb has been satisfied after the prior REFpb command
• tRP has been satisfied after the prior PRECHARGE command to that bank
• tRRD has been satisfied after the prior ACTIVATE command (for example, after acti-
vating a row in a different bank than the one affected by the REFpb command)
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb). Howev-
er, other banks within the device are accessible and can be addressed during the cycle.
During the REFpb operation, any of the banks other than the one being refreshed can
be maintained in an active state or accessed by a READ or a WRITE command. When
the per-bank REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, the following conditions must be met:
• tRFCpb must be satisfied before issuing a REFab command
• tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank
• tRRD must be satisfied before issuing an ACTIVATE command to a different bank
• tRFCpb must be satisfied before issuing another REFpb command
An all-bank REFRESH command (REFab) issues a REFRESH command to every bank in

a channel. All banks must be idle when REFab is issued (for example, by issuing a PRE-
CHARGE ALL command prior to issuing an all-bank REFRESH command). The REFab
CCM005-554574167-10729

REFRESH Command
command must not be issued to the device until the following conditions have been
met:
• tRFCab has been satisfied following the prior REFab command
• tRFCpb has been satisfied following the prior REFpb command
• tRP has been satisfied following the prior PRECHARGE command
When an all-bank REFRESH cycle has completed, all banks will be idle. After issuing RE-
Fab:
• RFCab latency must be satisfied before issuing an ACTIVATE command,
• RFCab latency must be satisfied before issuing a REFab or REFpb command
Table 108: REFRESH Command Timing Constraints
Minimum
Symbol Delay From... To Notes
tRFCab REFab REFab
ACTIVATE command to any bank
REFpb
tRFCpb REFpb REFab
ACTIVATE command to same bank as REFpb
REFpb
tRRD REFpb ACTIVATE command to a different bank than REFpb
ACTIVATE REFpb 1
ACTIVATE command to a different bank than the prior ACTIVATE command
Note: 1. A bank must be in the idle state before it is refreshed; therefore, REFab is prohibited
following an ACTIVATE command. REFpb is supported only if it affects a bank that is in
the idle state.
Figure 73: All-Bank REFRESH Operation

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0 Tc1 Tc2 Tc3
CK_c
CK_t
CKE
CS
CA Valid Valid Valid Valid Valid Valid Valid Valid

t t t
RPab RFCab RFCab
Command PRECHARGE DES DES DES DES All bank DES DES DES DES All bank DES DES DES DES Any command DES
ALL bank REFRESH REFRESH
Don’t Care
CCM005-554574167-10729

REFRESH Command
Figure 74: Per-Bank REFRESH Operation

T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6
CK_c
CK_t
CKE
CS
CA Valid Valid Valid BA0 Valid BA1 Valid BA1 Valid Valid
t t t
RPab RFCpb RFCpb
Command PRECHARGE DES DES DES Per bank DES DES DES Per bank DES DES DES ACTIVATE-1 ACTIVATE-2 DES DES
ALL bank REFRESH REFRESH
Don’t Care
Notes: 1. In the beginning of this example, the REFpb bank is pointing to bank 0.
2. Operations to banks other than the bank being refreshed are supported during the
tRFCpb period.
In general, a REFRESH command needs to be issued to the device regularly every tREFI
interval. To allow for improved efficiency in scheduling and switching between tasks,
some flexibility in the absolute refresh interval is provided. A maximum of eight RE-
FRESH commands can be postponed during operation of the device, but at no point in
time are more than a total of eight REFRESH commands allowed to be postponed. And
a maximum number of pulled-in or postponed REF command is dependent on refresh
rate. It is described in the table below. In the case where eight REFRESH commands are
postponed in a row, the resulting maximum interval between the surrounding RE-
FRESH commands is limited to 9 × tREFI. A maximum of eight additional REFRESH
commands can be issued in advance (pulled in), with each one reducing the number of
regular REFRESH commands required later by one. Note that pulling in more than eight
REFRESH commands in advance does not reduce the number of regular REFRESH
commands required later; therefore, the resulting maximum interval between two sur-
rounding REFRESH commands is limited to 9 × tREFI. At any given time, a maximum of
16 REFRESH commands can be issued within 2 × tREFI.
Self refresh mode may be entered with a maximum of eight REFRESH commands being
postponed. After exiting self refresh mode with one or more REFRESH commands post-
poned, additional REFRESH commands may be postponed to the extent that the total
number of postponed REFRESH commands (before and after self refresh) will never ex-
ceed eight. During self refresh mode, the number of postponed or pulled-in REFRESH
commands does not change.
And for per-bank refresh, a maximum of 8 x 8 per-bank REFRESH commands can be
postponed or pulled in for scheduling efficiency. At any given time, a maximum of 2 x 8
x 8 per-bank REFRESH commands can be issued within 2 × tREFI.
CCM005-554574167-10729

REFRESH Command
Table 109: Legacy REFRESH Command Timing Constraints
Max. No. of Max. Interval

MR4 pulled-in or between Max. No. of
OP[2:0] Refresh rate postponed REFab two REFab REFab1 Per-bank REFRESH
000b Low temp. limit N/A N/A N/A N/A
001b 4× tREFI 8 9×4× tREFI 16 1/8 of REFab
010b 2 × tREFI 8 9 × 2 × tREFI 16 1/8 of REFab
011b 1 × tREFI 8 9 × tREFI 16 1/8 of REFab
100b 0.5 × tREFI 8 9 × 0.5 × tREFI 16 1/8 of REFab
111b High temp. limit N/A N/A N/A N/A
Note: 1. Maximum number of REFab within MAX(2 × tREFI × refresh rate multiplier, 16 × tRFC).
Table 110: Modified REFRESH Command Timing Constraints
Max. No. of Max. Interval

MR4 Pulled-in or between Max. No. of
OP[2:0] Refresh Rate Postponed REFab Two REFab REFab1 Per-bank REFRESH
000B Low temp. limit N/A N/A N/A N/A
001B 4 × tREFI 2 3 × 4 × tREFI 4 1/8 of REFab
010B 2 × tREFI 4 5 × 2 × tREFI 8 1/8 of REFab
011B 1× tREFI 8 9× tREFI 16 1/8 of REFab
100B 0.5 × tREFI 8 9 × 0.5 × tREFI 16 1/8 of REFab
111B High temp. limit N/A N/A N/A N/A
Notes: 1. For any thermal transition phase where refresh mode is transitioned to either 2 × tREFI
or 4 × tREFI, LPDDR4 devices will support the previous postponed refresh requirement
provided the number of postponed refreshes is monotonically reduced to meet the new
requirement. However, the pulled-in REFRESH commands in the previous thermal phase
are not applied in the new thermal phase. Entering a new thermal phase, the controller
must count the number of pulled-in REFRESH commands as zero, regardless of the num-
ber of remaining pulled-in REFRESH commands in the previous thermal phase.
2. LPDDR4 devices are refreshed properly if the memory controller issues REFRESH com-
mands with same or shorter refresh period than reported by MR4 OP[2:0]. If a shorter
refresh period is applied, the corresponding requirements from this table apply. For ex-
ample, when MR4 OP[2:0] = 001b, the controller can be in any refresh rate from 4 ×
tREFI to 0.25 × tREFI. When MR4 OP[2:0] = 010b, the only prohibited refresh rate is 4 ×
tREFI.
CCM005-554574167-10729

REFRESH Command
Figure 75: Postponing REFRESH Commands (Example)

tREFI
9 tREFI
t
tRFC
8 REFRESH commands postponed
Figure 76: Pulling in REFRESH Commands (Example)

tREFI
9 tREFI
t
tRFC
8 REFRESH commands pulled in
CCM005-554574167-10729

REFRESH Command
Burst READ Operation Followed by Per-Bank Refresh
Figure 77: Burst READ Operation Followed by Per-Bank Refresh

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2
CK_c
CK_t
CS
CA BA0, Any
BL CA, AP CAn CAn Valid BA0 Valid Bank
Command Per bank Per bank

READ-1 CAS-2 DES DES PRECHARGE DES DES DES DES DES REFRESH DES DES DES DES
t RTP Note 4 t RPpb
RL t DQSCK
t RPRE
tRPST
DQS_c
DQS_t
tDQSQ
DQ n0 n1 n2 n3 n4 n5 n6 n7 n12 n13 n14 n15
Don’t Care
Notes: 1. The per-bank REFRESH command can be issued after tRTP + tRPpb from READ command.
2. BL = 16; Preamble = Toggle; Postamble = 0.5nCK; DQ/DQS: VSSQ termination.
3. DOUT n = data-out from column n.
4. In the case of BL = 32, delay time from read to per-bank precharge is 8nCK + tRTP.
these times.
CCM005-554574167-10729

Refresh Requirement
Figure 78: Burst READ With AUTO PRECHARGE Operation Followed by Per-Bank Refresh
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Tb0 Tb1 Tb2
CK_c
CK_t
CS
CA BA0, Any
BL CA, AP CAn CAn Valid Bank
Command Per bank

READ with AP-1 CAS-2 DES DES DES DES DES DES DES DES DES REFRESH DES DES DES DES
t RC Note 4
RL t DQSCK
tRPST
t RPRE
DQS_c
DQS_t
t DQSQ
DQ n0 n1 n2 n3 n4 n5 n6 n7 n12 n13 n14 n15
Don’t Care
Notes: 1. BL = 16; Preamble = Toggle; Postamble = 0.5nCK; DQ/DQS: VSSQ termination.

2. DOUT n = data-out from column n.
these times.
4. tRC needs to be satisfied prior to issuing a subsequent per-bank REFRESH command.
Refresh Requirement
Between the SRX command and SRE command, at least one extra REFRESH command
is required. After the SELF REFRESH EXIT command, in addition to the normal RE-
FRESH command at tREFI interval, the device requires a minimum of one extra RE-
FRESH command prior to the SELF REFRESH ENTRY command.
Table 111: Refresh Requirement Parameters

Parameter Symbol 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb Unit
Number of banks per channel – 8 –
Refresh window (tREFW): tREFW 32 ms
(1 × Refresh)3
Required number of REFRESH R 8192 –
commands in tREFW window
Average refresh interval REFab tREFI 3.904 µs
(1 × Refresh)3 REFpb tREFIpb 488 ns
CCM005-554574167-10729

SELF REFRESH Operation
Table 111: Refresh Requirement Parameters (Continued)

Parameter Symbol 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb Unit
REFRESH cycle time (all banks) tRFCab 130 180 280 380 ns
REFRESH cycle time (per bank) tRFCpb 60 90 140 190 ns
Per bank refresh to per bank re- tPBR2PBR 60 90 90 90 ns
fresh time (different bank)
Notes: 1. Refresh for each channel is independent of the other channel on the die, or other chan-
nels in a package. Power delivery in the user’s system should be verified to make sure
the DC operating conditions are maintained when multiple channels are refreshed si-
multaneously.
2. Self refresh abort feature is available for higher density devices starting with 6Gb densi-
ty per channel device and tXSR_abort(MIN) is defined as tRFCpb + 17.5ns.
3. Refer to MR4 OP[2:0] for detailed refresh rate and its multipliers.

Self Refresh Entry and Exit
The SELF REFRESH command can be used to retain data in the device without external
REFRESH commands. The device has a built-in timer to accommodate SELF REFRESH
operation. Self refresh is entered by the SELF REFRESH ENTRY command defined by
having CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH, CA4 HIGH, and CA5 valid
(valid meaning that it is at a logic level HIGH or LOW) for the first rising edge, and CS
LOW, CA0 valid, CA1 valid, CA2 valid, CA3 valid, CA4 valid, and CA5 valid at the second
rising edge of clock. The SELF REFRESH command is only allowed when READ DATA
burst is completed and the device is in the idle state.
During self refresh mode, external clock input is needed and all input pins of the device
are activated. The device can accept the following commands: MRR-1, CAS-2, DES, SRX,
MPC, MRW-1, and MRW-2, except PASR bank/segment mask setting and SR abort set-
ting.
The device can operate in self refresh mode within the standard and elevated tempera-
ture ranges. It also manages self refresh power consumption when the operating tem-
perature changes: lower at low temperatures and higher at high temperatures.
For proper SELF REFRESH operation, power supply pins (VDD1, V DD2, and V DDQ) must
be at valid levels. V DDQ can be turned off during self refresh with power-down after
tCKELCK is satisfied. (Refer to the Self Refresh Entry/Exit Timing with Power-Down En-
try/Exit figure.) Prior to exiting self refresh with power-down, V DDQ must be within
specified limits. The minimum time that the device must remain in self refresh mode is
tSR(MIN). After self refresh exit is registered, only MRR-1, CAS-2, DES, MPC, MRW-1,
and MRW-2 except PASR bank/segment mask setting and SR abort setting are allowed
until tXSR is satisfied.
The use of self refresh mode introduces the possibility that an internally timed refresh
event can be missed when self refresh exit is registered. Upon exit from self refresh, it is
required that at least one REFRESH command (8 per-bank or 1 all-bank) is issued be-
fore entry into a subsequent self refresh. This REFRESH command is not included in the
CCM005-554574167-10729

count of regular REFRESH commands required by the tREFI interval, and does not
modify the postponed or pulled-in refresh counts; the REFRESH command does count
toward the maximum refreshes permitted within 2 × tREFI.
Figure 79: Self Refresh Entry/Exit Timing

T0 T1 T2 T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7
CK_c
CK_t
CKE
CS

t SR t XSR
Command DES SELF REFRESH DES DES DES DES DES DES SELF REFRESH DES DES DES DES Any command Any command DES DES
ENTRY EXIT
Enter self refresh Exit self refresh
Don’t Care
Notes: 1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 commands (except PASR bank/
segment mask setting and SR abort setting) are allowed during self refresh.
these times.
Power-Down Entry and Exit During Self Refresh

Entering/exiting power-down mode is allowed during self refresh mode. The related
timing parameters between self refresh entry/exit and power-down entry/exit are
shown below.
CCM005-554574167-10729

Figure 80: Self Refresh Entry/Exit Timing with Power-Down Entry/Exit

T0 T1 T2 T3 Ta0 Tb0 Tb1 Tc0 Td1 Te0 Tf0 Tf1 Tg0 Tg1 Th0 Tk0 Tk1 Tk2 Tk3
CK_c
Note 2
CK_t
CKE
t
t
CKELCK t
CKCKEH
CKE
t
CSCKE tCKELCS t
CSCKEH CKEHCS
t
CS
ESCKE
t
t
CMDCKE XP
t
CA Valid Valid Valid Valid Valid Valid

t SR
Note 3
Command SELFWrite-2
MR REFRESH Any command DES DES DES SELF REFRESH DES
ENTRY EXIT
Enter self refresh Exit self refresh
Don’t Care
segment mask setting and SR abort setting) are allowed during self refresh.
2. Input clock frequency can be changed, or the input clock can be stopped, or floated af-
ter tCKELCK satisfied and during power-down, provided that upon exiting power-down,
the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock
prior to power-down exit and the clock frequency is between the minimum and maxi-
mum specified frequency for the speed grade in use.
3. Two clock command for example.
Command Input Timing After Power-Down Exit

Command input timings after power-down exit during self refresh mode are shown be-
low.
CCM005-554574167-10729

Figure 81: Command Input Timings after Power-Down Exit During Self Refresh
T0 T1 T2 T3 Ta0 Tb0 Tb1 Tc0 Td1 Te0 Tf0 Tf1 Tg0 Tg1 Th0 Tk0 Tk1 Tk2 Tk3
CK_c
Note 2
CK_t
CKE
t
t
CKELCK t
CKCKEH
CKE
t
CSCKE tCKELCS t
CSCKEH CKEHCS
t
CS
ESCKE
t
t
CMDCKE XP
t

t SR
Note 3 Note 3
Command SELFWrite-2
MR REFRESH Any command DES DES DES Any command DES
ENTRY
Enter self refresh
Don’t Care
segment setting) are allowed during self refresh.
2. Input clock frequency can be changed or the input clock can be stopped or floated after
tCKELCK satisfied and during power-down, provided that upon exiting power-down, the
clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior
to power-down exit and the clock frequency is between the minimum and maximum
specified frequency for the speed grade in use.
3. Two clock command for example.
Self Refresh Abort

If MR4 OP[3] is enabled, the device aborts any ongoing refresh during self refresh exit
and does not increment the internal refresh counter. The controller can issue a valid
command after a delay of tXSR_abort instead of tXSR.
The value of tXSR_abort(MIN) is defined as tRFCpb + 17.5ns.
Upon exit from self refresh mode, the device requires a minimum of one extra refresh
(eight per bank or one for the entire bank) before entering a subsequent self refresh
mode. This requirement remains the same irrespective of the setting of the MR bit for
self refresh abort.
Self refresh abort feature is valid for 6Gb density per channel and larger densities only.
MRR, MRW, MPC Commands During tXSR, tRFC

MODE REGISTER READ (MRR), MULTI PURPOSE (MPC), and MODE REGISTER WRITE
(MRW) command except PASR bank/segment mask setting and SR abort setting can be
issued during tXSR period.
CCM005-554574167-10729

Figure 82: MRR, MRW, and MPC Commands Issuing Timing During tXSR
T0 T1 T2 T3 T4 T5 T6 T7 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5
CK_c
CK_t
CKE
CS “H” for case 2
CS
CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
MRD
t
Note 3
Command DES SRX MPC DES DES DES DES MRW-1 MRW-2 DES DES DES DES Any command
(2 clock command)
(Case 1)
t
MRD Note 3
Command DES SRX MPC CAS-2 DES DES MRW-1 MRW-2 DES DES DES DES Any command
(4 clock command)
(Case 2)
XSR Note 2
t
Don’t Care
Notes: 1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is al-
lowed during tXSR period.
2. "Any command" includes MRR, MRW, and all MPC commands.
MRR, MRW, and MPC can be issued during tRFC period.
CCM005-554574167-10729

Figure 83: MRR, MRW, and MPC Commands Issuing Timing During tRFC
T0 T1 T2 T3 T4 T5 T6 T7 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5
CK_c
CK_t
CKE
CS “H” for case 2
CS
CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
MRD
t
Note 3
Command DES REF all bank MPC DES DES DES DES MRW-1 MRW-2 DES DES DES DES Any command
(2 clock command)
(Case 1)
t
MRD Note 3
Command DES REF all bank MPC CAS-2 DES DES MRW-1 MRW-2 DES DES DES DES Any command
(4 clock command)
(Case 2)
RFCab Note 2
t
Don’t Care
Notes: 1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is al-
lowed during tRFCab or tRFCpb period.
2. REFRESH cycle time depends on REFRESH command. In the case of per bank REFRESH
command issued, REFRESH cycle time will be tRFCpb.
3. "Any command" includes MRR, MRW, and all MPC commands.
CCM005-554574167-10729

Power-Down Mode
Power-Down Mode
Power-Down Entry and Exit
Power-down is asynchronously entered when CKE is driven LOW. CKE must not go LOW
while the following operations are in progress:
• Mode register read
• Mode register write
• Read
• Write
• VREF(CA) range and value setting via MRW
• VREF(DQ) range and value setting via MRW
• Command bus training mode entering/exiting via MRW
• VRCG HIGH current mode entering/exiting via MRW
CKE can go LOW while any other operations such as row activation, precharge, auto
precharge, or refresh are in progress. The power-down I DD specification will not be ap-
plied until such operations are complete. Power-down entry and exit are shown below.
Entering power-down deactivates the input and output buffers, excluding CKE and RE-
SET_n. To ensure that there is enough time to account for internal delay on the CKE sig-
nal path, CS input is required stable LOW level and CA input level is "Don’t Care" after
CKE is driven LOW, this timing period is defined as tCKELCS. Clock input is required af-
ter CKE is driven LOW, this timing period is defined as tCKELCK. CKE LOW will result in
deactivation of all input receivers except RESET_n after tCKELCK has expired. In power-
down mode, CKE must be held LOW; all other input signals except RESET_n are "Don't
Care." CKE LOW must be maintained until tCKE(MIN) is satisfied.
VDDQ can be turned off during power-down after tCKELCK is satisfied. Prior to exiting
power-down, V DDQ must be within its minimum/maximum operating range. No RE-
FRESH operations are performed in power-down mode except self refresh power-down.
The maximum duration in non-self-refresh power-down mode is only limited by the re-
fresh requirements outlined in the REFRESH command section.
The power-down state is asynchronously exited when CKE is driven HIGH. CKE HIGH
must be maintained until tCKE(MIN) is satisfied. A valid, executable command can be
applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit laten-
cy is defined in the AC timing parameter table.
Clock frequency change or clock stop is inhibited during tCMDCKE, tCKELCK,
tCKCKEH, tXP, tMRWCKEL, and tZQCKE periods.
If power-down occurs when all banks are idle, this mode is referred to as idle power-
down. if power-down occurs when there is a row active in any bank, this mode is refer-
red to as active power-down. And If power-down occurs when self refresh is in progress,
this mode is referred to as self refresh power-down in which the internal refresh is con-
tinuing in the same way as self refresh mode.
When CA, CK, and/or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or CA-
ODT pad setting, the rank providing ODT will continue to terminate the command bus
in all DRAM states including power-down when V DDQ is stable and within its mini-
mum/maximum operating range.
CCM005-554574167-10729

Power-Down Mode
The LPDDR4 DRAM cannot be placed in power-down state during start DQS interval
oscillator operation.
Figure 84: Basic Power-Down Entry and Exit Timing

T0 T1 Ta0 Tb0 Tb1 Tc0 Tc1 Td0 Te0 Te1 Tf0 Tf1 Tg0 Th0 Th1 Th2 Th3 Tk0 Tk1 Tk2
CK_c
Note 1
CK_t
tCKE t CKE
t CMDCKE t CKELCK t CKCKEH t XP
CKE
t CSCKE t CKELCS t CSCKEH t CKEHCS
CS
Command Valid DES DES DES Valid DES DES
Don’t Care
Note: 1. Input clock frequency can be changed or the input clock can be stopped or floated dur-
ing power-down, provided that upon exiting power-down, the clock is stable and within
specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and
the clock frequency is between the minimum and maximum specified frequency for the
speed grade in use.
Current Generator (VRCG)
CCM005-554574167-10729

Power-Down Mode
Figure 85: Read and Read with Auto Precharge to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1
CK_c
CK_t
CKE
See Note 2
CS
Command READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES
t
RL DQSCK
DQS_c
DQS_t
t
RPST
t
DQ RPRE
DO DO DO DO DO DO
DMI n0 n1 n2 n13 n14 n15
Don’t Care
Notes: 1. CKE must be held HIGH until the end of the burst operation.
2. Minimum delay time from READ command or READ with AUTO PRECHARGE command
to falling edge of CKE signal is as follows:
When read postamble = 0.5nCK (MR1 OP[7] = [0]),
(RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 1tCK
CCM005-554574167-10729

Power-Down Mode
Figure 86: Write and Mask Write to Power-Down Entry

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0 Td1 Td2
CK_c
CK_t
CKE
See Note 2
CS
Command WRITE-1
MASK WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES
t t
WL DQSS WPST
t t t
WPRE DQS2DQ BL/2 WR
DI DI DI DI DI DI
n0 n1 n2 n13 n14 n15
Don’t Care
2. Minimum delay time from WRITE command or MASK WRITE command to falling edge
of CKE signal is as follows:
(WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + tWR
3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0].
4. This timing diagram only applies to the WRITE and MASK WRITE commands without au-
to precharge.
CCM005-554574167-10729

Power-Down Mode
Figure 87: Write With Auto Precharge and Mask Write With Auto Precharge to Power-Down Entry
T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Td0
CK_c
CK_t
CKE
See Note 2
CS
Command WRITE-1
MASK WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES
t t
WL DQSS WPST
t t
WPRE DQS2DQ BL/2
DI DI DI DI DI DI
n0 n1 n2 n13 n14 n15
Don’t Care
2. Delay time from WRITE with AUTO PRECHARGE command or MASK WRITE with AUTO
PRECHARGE command to falling edge of CKE signal is more than
(WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + (nWR × tCK) + (2 × tCK)
3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0].
CCM005-554574167-10729

Power-Down Mode
Figure 88: Refresh Entry to Power-Down Entry

T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10
CK_c
CK_t
CKE
t
CMDCKE
CS
CA Valid Valid
Command REFRESH DES DES
Don’t Care
Note: 1. CKE must be held HIGH until tCMDCKE is satisfied.
Figure 89: ACTIVATE Command to Power-Down Entry

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9
CK_c
CK_t
CKE
t
CMDCKE
CS
Command ACTIVATE-1 ACTIVATE-2 DES DES
Don’t Care
CCM005-554574167-10729

Power-Down Mode
Figure 90: PRECHARGE Command to Power-Down Entry

T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 Tb11
CK_c
CK_t
CKE
t
CMDCKE
CS
CA Valid Valid
Command PRECHARGE DES DES
Don’t Care
CCM005-554574167-10729

Power-Down Mode
Figure 91: Mode Register Read to Power-Down Entry

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1
CK_c
CK_t
CKE
See Note 2
CS
Command MR READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES
t
RL DQSCK
DQS_c
DQS_t
t
RPST
t
DQ RPRE
DO DO DO DO DO DO
DMI n0 n1 n2 n13 n14 n15
Don’t Care
2. Minimum delay time from MODE REGISTER READ command to falling edge of CKE sig-
nal is as follows:
When read postamble = 0.5nCK ( MR1 OP[7] = [0]),
CCM005-554574167-10729

Power-Down Mode
Figure 92: Mode Register Write to Power-Down Entry

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7
CK_c
CK_t
CKE
t
MRWCKEL
CS
Command MR WRITE-1 MR WRITE-2 DES DES DES
Don’t Care
Notes: 1. CKE must be held HIGH until tMRWCKEL is satisfied.

2. This timing is the general definition for power-down entry after MODE REGISTER WRITE
command. When a MODE REGISTER WRITE command changes a parameter or starts an
operation that requires special timing longer than tMRWCKEL, that timing must be satis-
fied before CKE is driven LOW. Changing the VREF(DQ) value is one example, in this case
the appropriate tVREF-SHORT/MIDDLE/LONG must be satisfied.
CCM005-554574167-10729

Power-Down Mode
Figure 93: MULTI PURPOSE Command for ZQCAL Start to Power-Down Entry
T0 T1 T2 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 Tb11
CK_c
CK_t
CKE
t
ZQCKE
CS
CA Valid Valid
MPC
Command [ZQCAL START] DES DES
ZQ Cal Status ZQ calibration progresses

t
ZQCAL
Don’t Care
Note: 1. ZQ calibration continues if CKE goes LOW after tZQCKE is satisfied.
CCM005-554574167-10729

Input Clock Stop and Frequency Change

Clock Frequency Change – CKE LOW
During CKE LOW, the device supports input clock frequency changes under the follow-
ing conditions:
• tCK(abs)min is met for each clock cycle
• Refresh requirements apply during clock frequency change
• During clock frequency change, only REFab or REFpb commands may be executing
• Any ACTIVATE or PRECHARGE commands have completed prior to changing the fre-
quency
• Related timing conditions, tRCD and tRP, have been met prior to changing the fre-
quency
• The initial clock frequency must be maintained for a minimum of tCKELCK after CKE
goes LOW
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE go-
ing HIGH
After the input clock frequency changes and CKE is held HIGH, additional MRW com-
mands may be required to set the WR, RL, and so forth. These settings may require ad-
justment to meet minimum timing requirements at the target clock frequency.
Clock Stop – CKE LOW

During CKE LOW, the device supports clock stop under the following conditions:
• CK_t and CK_c are don't care during clock stop
• Refresh requirements apply during clock stop
• During clock stop, only REFab or REFpb commands may be executing
• Any ACTIVATE or PRECHARGE commands have completed prior to stopping the
clock
• Related timing conditions, tRCD and tRP, have been met prior to stopping the clock
• The initial clock frequency must be maintained for a minimum of tCKELCK after CKE
goes LOW
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE go-
ing HIGH
Clock Frequency Change – CKE HIGH

During CKE HIGH, the device supports input clock frequency change under the follow-
ing conditions:
• tCK(abs)minis met for each clock cycle
• Refresh requirements apply during clock frequency change
• During clock frequency change, only REFab or REFpb commands may be executing
• Any ACTIVATE, READ, WRITE, PRECHARGE, MODE REGISTER WRITE, or MODE
REGISTER READ commands (and any associated data bursts) have completed prior
to changing the frequency
• Related timing conditions (tRCD, tWR, tRP, tMRW, and tMRR) have been met prior to
changing the frequency
CCM005-554574167-10729

• During clock frequency change, CS is held LOW

• The device is ready for normal operation after the clock satisfies tCH(abs) and
tCL(abs) for a minimum of 2 × tCK + tXP
After the input clock frequency is changed, additional MRW commands may be re-
quired to set the WR, RL, and so forth. These settings may need to be adjusted to meet
minimum timing requirements at the target clock frequency.
Clock Stop – CKE HIGH

During CKE HIGH, the device supports clock stop under the following conditions:
• CK_t is held LOW and CK_c is held HIGH during clock stop
• During clock stop, CS is held LOW
• Refresh requirements apply during clock stop
• During clock stop, only REFab or REFpb commands may be executing
• Any ACTIVATE, READ, WRITE, MPC (WRITE-FIFO, READ-FIFO, READ DQ CALIBRA-
TION), PRECHARGE, MODE REGISTER WRITE, or MODE REGISTER READ com-
mands have completed, including any associated data bursts and extra 4 clock cycles
must be provided prior to stopping the clock
• Related timing conditions (tRCD, tWR, tRP, tMRW, tMRR, tZQLAT, and so forth) have
been met prior to stopping the clock
• READ with AUTO PRECHARGE and WRITE with AUTO PRECHARGE commands need
extra 4 clock cycles in addition to the related timing constraints, nWR and nRTP, to
complete the operations
• REFab, REFpb, SRE, SRX, and MPC[ZQCAL START] commands are required to have
extra 4 clock cycles prior to stopping the clock
• The device is ready for normal operation after the clock is restarted and satisfies
tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP
CCM005-554574167-10729

MODE REGISTER READ Operation

The MODE REGISTER READ (MRR) command is used to read configuration and status
data from the device registers. The MRR command is initiated with CS and CA[5:0] in
the proper state as defined by the Command Truth Table. The mode register address
operands (MA[5:0]) enable the user to select one of 64 registers. The mode register con-
tents are available on the first four UI data bits of DQ[7:0] after RL × tCK + tDQSCK +
tDQSQ following the MRR command. Subsequent data bits contain valid but undefined
content. DQS is toggled for the duration of the MODE REGISTER READ burst. The MRR
has a command burst length of 16. MRR operation must not be interrupted.
Table 112: MRR
UI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DQ0 OP0 V
DQ1 OP1 V
DQ2 OP2 V
DQ3 OP3 V
DQ4 OP4 V
DQ5 OP5 V
DQ6 OP6 V
DQ7 OP7 V
DQ8– V
DQ15
DMI0– V
DMI1
Notes: 1. MRR data are extended to the first 4 UIs, allowing the LPDRAM controller to sample da-
ta easily.
2. DBI during MRR depends on mode register setting MR3 OP[6].
3. The read preamble and postamble of MRR are the same as for a normal read.
CCM005-554574167-10729

Figure 94: MODE REGISTER READ Operation

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0 Tc1
CK_c
CK_t
CS
CA Valid MA CAn CAn Valid Valid Valid Valid
Command MR READ-1 CAS-2 DES DES Any command Any command DES DES DES DES DES DES DES DES DES
t
MRR
RL t
DQSCK BL/2 = 8
t
RPRE
DQS_c
DQS_t
t t
DQSQ RPST
Va- Va- Va- Va-
OP Code out
DQ7:0 lid lid lid lid
DQ15:8 Va- Va- Va- Va- Va- Va- Va- Va-

lid lid lid lid lid lid lid lid
DMI1:0
Don’t Care
Notes: 1. Only BL = 16 is supported.

2. Only DESELECT is allowed during tMRR period.
3. There are some exceptions about issuing commands after tMRR. Refer to MRR/MRW
Timing Constraints Table for detail.
4. DBI is disable mode.
5. DES commands except tMRR period are shown for ease of illustration; other commands
may be valid at these times.
6. DQ/DQS: VSSQ termination
MRR After a READ and WRITE Command

After a prior READ command, the MRR command must not be issued earlier than BL/2
clock cycles, in a similar way WL + BL/2 + 1 + RU( tWTR/tCK) clock cycles after a PRIOR
WRITE, WRITE with AP, MASK WRITE, MASK WRITE with AP, and MPC[WRITE-FIFO]
command in order to avoid the collision of READ and WRITE burst data on device inter-
nal data bus.
CCM005-554574167-10729

Figure 95: READ-to-MRR Timing

T0 T1 T2 T3 T4 T15 T16 T17 T18 T19 T20 T21 T33 T34 T35 T36 T37 T43 T44
CK_c
CK_t
CS
CA BA0,
BL CA, AP CAn CAn Valid MA CAn CAn
Command READ-1 CAS-2 DES DES MRR-1 CAS-2 DES DES DES DES DES DES DES DES
RL/2 = 14 t
BL/2 DQSCK BL/2 = 8
RL = 14 t
DQSCK BL/2 = 16
t
RPRE t
RPST
DQS_c
DQS_t
t
t
DQSQ DQSQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT Va- Va-
OP Code out
DQ7:0 n0 n1 n2 n3 n26 n27 n28 n29 n30 n31 lid lid
DQ15:8 DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT Va- Va- Va- Va- Va- Va-
DMI1:0 n0 n1 n2 n3 n26 n27 n28 n29 n30 n31 lid lid lid lid lid lid
Don’t Care
Notes: 1. The minimum number of clock cycles from the burst READ command to the MRR com-
mand is BL/2.
2. Read BL = 32, MRR BL = 16, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DBI = Disa-
ble, DQ/DQS: VSSQ termination.
3. DOUT n = data-out to column n.
CCM005-554574167-10729

Figure 96: WRITE-to-MRR Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5
CK_c
CK_t
CS
BA0,
CA BL CAn CAn Valid MA CAn CAn
CA, AP
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES MRR-1 CAS-2 DES
t
WL BL/2 + 1 clock t
WTR MMR
t
WPRE t
WPST
DQS_c
DQS_t
t
DQS2DQ
DQ DOUT DOUT DOUT DOUT DOUT DOUT
DMI n0 n1 n12 n13 n14 n15
Don’t Care
Notes: 1. Write BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination.

2. Only DES is allowed during tMRR period.
3. DOUT n = data-out to column n.
4. The minimum number of clock cycles from the BURST WRITE command to MRR com-
mand is WL + BL/2 + 1 + RU(tWTR/tCK).
5. tWTR starts at the rising edge of CK after the last latching edge of DQS.
MRR After Power-Down Exit

Following the power-down state, an additional time, tMRRI, is required prior to issuing
the MODE REGISTER READ (MRR) command. This additional time (equivalent to
tRCD) is required in order to maximize power-down current savings by allowing more
power-up time for the MRR data path after exit from power-down mode.
CCM005-554574167-10729

MODE REGISTER WRITE
Figure 97: MRR Following Power-Down

T0 Ta0 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Td9
CK_c
CK_t
t CKCKEH
CKE
t t t
XP MRRI MMR
CS
CA Valid Valid Valid Valid Valid MA CAn CAn
Command DES DES Any command Any command DES DES DES DES MRR-1 CAS-2 DES DES DES
Don't Care
Notes: 1. Only DES is allowed during tMRR period.

MODE REGISTER WRITE

The MODE REGISTER WRITE (MRW) writes configuration data to the mode registers.
The MRW command is initiated with CKE, CS, and CA[5:0] to valid levels at the rising
edge of the clock. The mode register address and the data written to it is contained in
CA[5:0] according to the Command Truth Table. The MRW command period is defined
by tMRW. Mode register WRITEs to read-only registers have no impact on the function-
ality of the device.
Figure 98: MODE REGISTER WRITE Timing

CK_c
CK_t
CS
CA OPn MA OPn OPn OPn MA OPn OPn Valid Valid Valid Valid
tMRW tMRD
Command MRW-1 MRW-2 DES DES MRW-1 MRW-2 DES DES Any command Any command DES DES DES
Don’t Care
CCM005-554574167-10729

MODE REGISTER WRITE
Mode Register Write States

MRW can be issued from either a bank-idle or a bank-active state. Certain restrictions
may apply for MRW from an active state.
Table 113: Truth Table for MRR and MRW
Current State Command Intermediate State Next State

All banks idle MRR Reading mode register, all banks idle All banks idle
MRW Writing mode register, all banks idle All banks idle
Bank(s) active MRR Reading mode register Bank(s) active
MRW Writing mode register Bank(s) active
Table 114: MRR/MRW Timing Constraints: DQ ODT is Disable

MRR MRR tMRR –
RD/RDA tMRR –
WR/WRA/MWR/MWRA RL + RU(tDQSCK(MAX)/tCK) + BL/2 -WL + tWPRE + nCK
RD(tRPST)
MRW RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3 nCK
RD/RDA MRR BL/2 nCK
WR/WRA/MWR/ WL + 1 + BL/2 + RU(tWTR/tCK) nCK
MWRA
MRW tMRD –
POWER-DOWN tXP + tMRRI –
EXIT
MRW RD/RDA tMRD –
WR/WRA/MWR/MWRA tMRD –
MRW tMRW –
RD/ MRW RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK
RD-FIFO/ MAX(RU(7.5ns/tCK), 8nCK)
READ DQ CAL
RD with AUTO RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK
PRECHARGE MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8
WR/ WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) nCK
MWR/
WR-FIFO
WR/MWR with WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK
AUTO PRE-
CHARGE
CCM005-554574167-10729

VREF Current Generator (VRCG)
Table 115: MRR/MRW Timing Constraints: DQ ODT is Enable

MRR MRR tMRR –
RD/RDA tMRR –
WR/WRA/MWR/MWRA RL +RU(tDQSCK(MAX)/tCK) + BL/2 - ODTLon - nCK
RD(tODTon(MIN)/tCK) + RD(tRPST) + 1
MRW RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3 nCK
RD/RDA MRR BL/2 nCK
WR/WRA/MWR/ WL + 1 + BL/2 + RU(tWTR/tCK) nCK
MWRA
MRW tMRD –
POWER-DOWN tXP + tMRRI –
EXIT
MRW RD/RDA tMRD –
WR/WRA/MWR/MWRA tMRD –
MRW tMRW –
RD/ MRW RL + BL/2 +RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK
RD-FIFO/ MAX(RU(7.5ns/tCK), 8nCK)
READ DQ CAL
RD with AUTO RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + nCK
PRECHARGE MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8
WR/ WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) nCK
MWR/
WR-FIFO
WR/MWR with WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK
AUTO PRE-
CHARGE

LPDDR4 SDRAM V REF current generators (VRCG) incorporate a high current mode to
reduce the settling time of the internal V REF(DQ) and V REF(CA) levels during training and
when changing frequency set points during operation. The high current mode is ena-
bled by setting MR13[OP3] = 1. Only DESELECT commands may be issued until
tVRCG_ENABLE is satisfied. tVRCG_ENABLE timing is shown below.
CCM005-554574167-10729

Figure 99: VRCG Enable Timing

T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6
CK_c
CK_t
CKE
CS
CA DES MRW1 MRW1 MRW2 MRW2 DES DES Valid Valid Valid Valid DES DES Valid Valid Valid Valid DES DES
Command DES VRCG enable: MR13 [OP3] = 1 DES DES Valid DES DES Valid DES DES
t
VRCG_ENABLE
VRCG high current mode is disabled by setting MR13[OP3] = 0. Only DESELECT com-
mands may be issued until tVRCG_DISABLE is satisfied. tVRCG_DISABLE timing is
shown below.
Figure 100: VRCG Disable Timing

T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6
CK_c
CK_t
CKE
CS
CA DES Valid Valid Valid Valid DES DES MRW1 MRW1 MRW2 MRW2 DES DES Valid Valid Valid Valid DES DES
Command DES Valid DES DES VRCG disable: MR13 [OP3] = 0 DES DES Valid DES DES
t
VRCG_DISABLE
Note that LPDDR4 SDRAM devices support V FER(CA) and V REF(DQ) range and value
changes without enabling VRCG high current mode.
Table 116: VRCG Enable/Disable Timing

VREF high current mode enable time tVRCG_ENABLE – 200 ns
VREF high current mode disable time tVRCG_DISABLE – 100 ns
CCM005-554574167-10729

VREF Training
VREF Training
VREF(CA) Training
The device's internal V REF(CA) specification parameters are operating voltage range, step
size, V REF step time, V REF full-range step time, and V REF valid level.
The voltage operating range specifies the minimum required V REF setting range for
LPDDR4 devices. The minimum range is defined by V REF,max and V REF,min.
Figure 101: VREF Operating Range (VREF,max, VREF,min)
VDD2
VIN(DC)max
VREF,max
VREF
VREF,min range
VIN(DC)min
VSWING large System variance
VSWING small Total range
The V REF step size is defined as the step size between adjacent steps. However, for a giv-
en design, the device has one value for V REF step size that falls within the given range.
The V REF set tolerance is the variation in the V REF voltage from the ideal setting. This ac-
counts for accumulated error over multiple steps. There are two ranges for V REF set tol-
erance uncertainty. The range of V REF set tolerance uncertainty is a function of the
number of steps n.
The V REF set tolerance is measured with respect to the ideal line that is based on the two
endpoints, where the endpoints are at the minimum and maximum V REF values for a
specified range.
CCM005-554574167-10729

VREF Training
Figure 102: VREF Set-Point Tolerance and Step Size

VREF
level
Actual VREF
output
VREF set-point
tolerance Straight line endpoint fit
VREF
step size
VREF step setting
The V REF increment/decrement step times are defined by tVREF_TIME-SHORT,

tV t
REF_TIME-MIDDLE, and VREF_TIME-LONG. The parameters are defined from TS to
TE as shown below, where TE is referenced to when the V REF voltage is at the final DC
level within the V REF valid tolerance (VREF,val_tol).
The V REF valid level is defined by V REF,val_tol to qualify the step time TE (see the following
figures). This parameter is used to ensure an adequate RC time constant behavior of the
voltage level change after any V REF increment/decrement adjustment. This parameter is
only applicable for LPDDR4 component level validation/characterization.
tV
REF_TIME-SHORT is for a single step size increment/decrement change in the V REF
voltage.
tV
REF_TIME-MIDDLE is at least two stepsizes increment/decrement change within the
same V REF(CA) range in V REF voltage.
tV
REF_TIME-LONG is the time including up to V REF,min to V REF,max or V REF,max to V REF,min
change across the V REF(CA) range in V REF voltage.
TS is referenced to MRW command clock.
TE is referenced to V REF_val_tol.
CCM005-554574167-10729

VREF Training
Figure 103: tVref for Short, Middle, and Long Timing Diagram
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12
CK_c
CK_t
CKE
CS
CA DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES
Command DES VRFF(CA) value/range set DES DES DES DES DES DES DES DES DES DES DES DES DES DES
VREF_time – short/middle/long
Old VREF setting Updating VRFF(CA) setting New VREF setting
TS TE
VREF setting
adjustment
The MRW command to the mode register bits are as follows;

MR12 OP[5:0] : V REF(CA) Setting
MR12 OP[6] : V REF(CA) Range
The minimum time required between two V REF MRW commands is tVREF_TIME-SHORT
for a single step and tVREF_TIME-MIDDLE for a full voltage range step.
Figure 104: VREF(CA) Single-Step Increment
VREF
voltage
VREF(DC)
step size VREF_val_tol
t1
Time
CCM005-554574167-10729

VREF Training
Figure 105: VREF(CA) Single-Step Decrement
VREF
voltage
t1
stepsize VREF_val_tol
VREF(DC)
Time
Figure 106: VREF(CA) Full Step from VREF,min to VREF,max
VREF,max VREF(DC)
VREF
voltage VREF_val_tol
Full range t1
step
VREF,min
Time
Figure 107: VREF(CA) Full Step from VREF,max to VREF,min
VREF VREF,max
voltage
Full range
step t1
VREF_val_tol
VREF,min VREF(DC)
Time
The following table contains the CA internal V REF specification that will be character-
ized at the component level for compliance.
CCM005-554574167-10729

VREF Training
Table 117: Internal VREF(CA) Specifications
Symbol Parameter Min Typ Max Unit Notes

VREF(CA),max_r0 VREF(CA) range-0 MAX operat- – – 44.9% VDDQ 1, 11
ing point
VREF(CA),min_r0 VREF(CA) range-0 MIN operat- 15.0% – – VDDQ 1, 11
ing point
VREF(CA),max_r1 VREF(CA) range-1 MAX operat- – – 62.9% VDDQ 1, 11
ing point
VREF(CA),min_r1 VREF(CA) range-1 MIN operat- 32.9% – – VDDQ 1, 11
ing point
VREF(CA),step VREF(CA) step size 0.50% 0.60% 0.70% VDDQ 2
VREF(CA),set_tol VREF(CA) set tolerance –11 0 11 mV 3, 4, 6
–1.1 0 1.1 mV 3, 5, 7
tV
REF_TIME-SHORT VREF(CA) step time – – 100 ns 8
tV
REF_TIME-MIDDLE – – 200 ns 12
tV
REF_TIME-LONG – – 250 ns 9
tV – – 1 ms 13, 14
REF_time_weak
VREF(CA)_val_tol VREF(CA) valid tolerance –0.10% 0.00% 0.10% VDDQ 10
Notes: 1. VREF(CA) DC voltage referenced to VDDQ(DC).

2. VREF(CA) step size increment/decrement range. VREF(CA) at DC level.
3. VREF(CA),new = VREF(CA),old + n × VREF(CA),step; n = number of steps; if increment, use "+"; if
decrement, use "–".
4. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 11mV. The maximum val-
ue of VREF(CA) setting tolerance = VREF(CA),new + 11mV. For n > 4.
5. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 1.1mV. The maximum
value of VREF(CA) setting tolerance = VREF(CA),new + 1.1mV. For n ≤ 4.
6. Measured by recording the minimum and maximum values of the VREF(CA) output over
the range, drawing a straight line between those points and comparing all other
VREF(CA) output settings to that line.
7. Measured by recording the minimum and maximum values of the VREF(CA) output across
four consecutive steps (n = 4), drawing a straight line between those points and compar-
ing all other VREF(CA) output settings to that line.
8. Time from MRW command to increment or decrement one step size for VREF(CA) .
9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to
VREF,min change across the VREF(CA) range in VREF voltage.
10. Only applicable for DRAM component level test/characterization purposes. Not applica-
ble for normal mode of operation. VREF valid is to qualify the step times which will be
characterized at the component level.
11. DRAM range-0 or range-1 set by MR12 OP[6].
12. Time from MRW command to increment or decrement more than one step size up to a
full range of VREF voltage within the same VREF(CA) range.
13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0b.
14. tVREF_time_weak covers all VREF(CA) range and value change conditions are applied to
tV
REF_TIME-SHORT/MIDDLE/LONG.
CCM005-554574167-10729

VREF Training
VREF(DQ) Training
The device's internal V REF(DQ) specification parameters are operating voltage range, step
size, V REF step tolerance, V REF step time and V REF valid level.
Figure 108: VREF Operating Range (VREF,max, VREF,min)
VDDQ
VIN(DC)max
VREF,max
VREF
VREF,min range
VIN(DC)min
VSWING large System variance
VSWING small Total range
The V REF step size is defined as the step size between adjacent steps. However, for a giv-
en design, the device has one value for V REF step size that falls within the given range.
The V REF set tolerance is the variation in the V REF voltage from the ideal setting. This ac-
counts for accumulated error over multiple steps. There are two ranges for V REF set tol-
erance uncertainty. The range of V REF set tolerance uncertainty is a function of the
number of steps n.
The V REF set tolerance is measured with respect to the ideal line that is based on the two
endpoints, where the endpoints are at the minimum and maximum V REF values for a
specified range.
CCM005-554574167-10729

VREF Training
Figure 109: VREF Set Tolerance and Step Size

VREF
level
Actual VREF
output
VREF set-point
tolerance Straight line endpoint fit
VREF
step size
VREF step setting
The V REF increment/decrement step times are defined by tVREF_TIME-SHORT,

tV t t t
REF_TIME-MIDDLE and VREF_TIME-LONG. The VREF_TIME-SHORT, VREF_TIME-
t
MIDDLE and VREF_TIME-LONG times are defined from TS to TE in the following figure
where TE is referenced to when the V REF voltage is at the final DC level within the V REF
valid tolerance (VREF,VAL_TOL).
The V REF valid level is defined by V REF,VAL_TOL to qualify the step time TE (see the figure
below). This parameter is used to ensure an adequate RC time constant behavior of the
voltage level change after any V REF increment/decrement adjustment. This parameter is
only applicable for DRAM component level validation/characterization.
tV
REF_TIME-SHORT is for a single step size increment/decrement change in the V REF
voltage.
tV
REF_TIME-MIDDLE is at least two step sizes of increment/decrement change in the
VREF(DQ) range in the V REFvoltage.
tV
REF_TIME-LONG is the time including and up to the full range of V REF (MIN to MAX or
MAX to MIN) across the V REF(DQ) range in V REF voltage.
CCM005-554574167-10729

VREF Training
Figure 110: VREF(DQ) Transition Time for Short, Middle, or Long Changes
T0 T1 T2 T3 T4 T5 Ta Ta+1 Ta+2 Ta+3 Ta+4 Ta+5 Ta+6 Ta+7 Ta+8 Ta+9 T+10 T+11 T+12
CK_c
CK_t
CKE
CS
CA[5:0] DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES
Command DES VREF(DQ) value/range set DES DES DES DES DES DES DES DES DES DES DES DES DES DES
VREF_time – short/middle/long
VREF Old VREF setting Updating VREF(DQ) setting New VREF setting
TS TE
VREF setting
adjustment
Notes: 1. TS is referenced to MRW command clock.

2. TE is referenced to VREF,VAL_TOL.
The MRW command to the mode register bits are defined as:
MR14 OP[5:0]: V REF(DQ) setting
MR14 OP[6]: V REF(DQ) range
The minimum time required between two V REF MRW commands is tVREF_TIME-SHORT
for a single step and tVREF_TIME-MIDDLE for a full voltage range step.
Figure 111: VREF(DQ) Single-Step Size Increment
VREF
voltage
VREF(DC)
step size VREF_val_tol
t1
Time
CCM005-554574167-10729

VREF Training
Figure 112: VREF(DQ) Single-Step Size Decrement
VREF
voltage
t1
stepsize VREF_val_tol
VREF(DC)
Time
Figure 113: VREF(DQ) Full Step from VREF,min to VREF,max
VREF,max VREF(DC)
VREF
voltage VREF_val_tol
Full range t1
step
VREF,min
Time
Figure 114: VREF(DQ) Full Step from VREF,max to VREF,min
VREF VREF,max
voltage
Full range
step t1
VREF_val_tol
VREF,min VREF(DC)
Time
The following table contains the DQ internal V REF specification that will be character-
ized at the component level for compliance.
CCM005-554574167-10729

VREF Training
Table 118: Internal VREF(DQ) Specifications

VREF(DQ),max_r0 VREF MAX operating point – – 44.9% VDDQ 1, 11
Range-0
VREF(DQ),min_r0 VREF MIN operating point 15.0% – – VDDQ 1, 11
Range-0
VREF(DQ),max_r1 VREF MAX operating point – – 62.9% VDDQ 1, 11
Range-1
VREF(DQ),min_r1 VREF MIN operating point 32.9% – – VDDQ 1, 11
Range-1
VREF(DQ),step VREF(DQ) step size 0.50% 0.60% 0.70% VDDQ 2
VREF(DQ),set_tol VREF(DQ) set tolerance –11 0 11 mV 3, 4, 6
–1.1 0 1.1 mV 3, 5, 7
tV
REF_TIME-SHORT VREF(DQ) step time – – 100 ns 8
tV
tV
tV – – 1 ms 13, 14
REF_time_weak
VREF(DQ),val_tol VREF(DQ) valid tolerance –0.10% 0.00% 0.10% VDDQ 10
Notes: 1. VREF(DQ) DC voltage referenced to VDDQ(DC).

2. VREF(DQ) step size increment/decrement range. VREF(DQ) at DC level.
3. VREF(DQ),new = VREF(DQ),old + n × VREF(DQ),step; n = number of steps; if increment, use "+"; if
4. The minimum value of VREF(DQ) setting tolerance = VREF(DQ),new - 11mV. The maximum
value of VREF(DQ) setting tolerance = VREF(DQ),new + 11mV. For n > 4.
5. The minimum value of VREF(DQ)setting tolerance = VREF(DQ),new - 1.1mV. The maximum
value of VREF(DQ) setting tolerance = VREF(DQ),new + 1.1mV. For n ≤ 4.
6. Measured by recording the minimum and maximum values of the VREF(DQ) output over
VREF(DQ) output settings to that line.
7. Measured by recording the minimum and maximum values of the VREF(DQ) output across
ing all other VREF(DQ) output settings to that line.
8. Time from MRW command to increment or decrement one step size for VREF(DQ) .
VREF,min change across the VREF(DQ) Range in VREF(DQ) Voltage.
full range of VREF voltage within the same VREF(DQ) range.
13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0.
14. tVREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to
tV
REF_TIME-SHOR/MIDDLE/LONG.
CCM005-554574167-10729

Command Bus Training

Command Bus Training Mode
The command bus must be trained before enabling termination for high-frequency op-
eration. The device provides an internal V REF(CA) that defaults to a level suitable for un-
terminated, low-frequency operation, but the V REF(CA) must be trained to achieve suita-
ble receiver voltage margin for terminated, high-frequency operation.
The training mode described here centers the internal V REF(CA) in the CA data eye and at
the same time allows for timing adjustments of the CS and CA signals to meet setup/
hold requirements. Because it can be difficult to capture commands prior to training
the CA inputs, the training mode described here uses a minimum of external com-
mands to enter, train, and exit the CA bus training mode.
The die has a bond-pad (ODT_CA) but ODT_CA pin is ignored by LPDDR4X devices. CA
ODT is fully controlled through MR11 and MR22. See On-Die Termination for more in-
formation.
The device uses frequency set points to enable multiple operating settings for the die.
The device defaults to FSP-OP[0] at power-up, which has the default settings to operate
in un-terminated, low-frequency environments. Prior to training, the termination
should be enabled for one die in each channel by setting MR13 OP[6] = 1b (FSP-WR[1])
and setting all other mode register bits for FSP-OP[1] to the desired settings for high-
frequency operation. Upon training entry, the device will automatically switch to FSP-
OP[1] and use the high-frequency settings during training (See the Command Bus
Training Entry Timing figure for more information on FSP-OP register sets). Upon train-
ing exit, the device will automatically switch back to FSP-OP[0], returning to a "known-
good" state for unterminated, low-frequency operation.
To enter command bus training mode, issue a MRW-1 command followed by a MRW-2
command to set MR13 OP[0] = 1b (command bus training mode enabled).
After time tMRD, CKE may be set LOW, causing the device to switch to FSP-OP[1], and
completing the entry into command bus training mode.
A status DQS_t, DQS_c, DQ, and DMI are as noted below; the DQ ODT state will be fol-
lowed by FREQUENCY SET POINT function except in the case of output pins.
• DQS_t[0], DQS_c[0] become input pins for capturing DQ[6:0] levels by toggling.
• DQ[5:0] become input pins for setting V REF(CA) level.
• DQ[6] becomes an input pin for setting V REF(CA) range.
• DQ[7] and DMI[0] become input pins, and their input level is valid or floating.
• DQ[13:8] become output pins to feedback, capturing value via the command bus us-
ing the CS signal.
• DQS_t[1], DQS_c[1], DMI[1], and DQ[15:14] become output pins or are disabled,
meaning the device may be driven to a valid level or may be left floating.
At time tCAENT later, the device may change its V REF(CA) range and value using input
signals DQS_t[0], DQS_c[0], and DQ[6:0] from existing value that is set via MR12
OP[6:0]. The mapping between MR12 OP code and DQs is shown below. At least one
VREF(CA) setting is required before proceeding to the next training step.
CCM005-554574167-10729

Table 119: Mapping MR12 Op Code and DQ Numbers
Mapping
MR12 OP code OP6 OP5 OP4 OP3 OP2 OP1 OP0
DQ number DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
The new V REF(CA) value must "settle" for time tVREFCA_Long before attempting to latch
CA information.
Note: If DQ ODT is enabled in MR11-OP[2:0], then the SDRAM will terminate the DQ
lanes during command bus training when entering V REF(CA) range and values on
DQ[6:0].
To verify that the receiver has the correct V REF(CA) setting, and to further train the CA eye
relative to clock (CK), values latched at the receiver on the CA bus are asynchronously
output to the DQ bus.
To exit command bus training mode, drive CKE HIGH, and after time tVREFCA_Long,
issue the MRW-1 command followed by the MRW-2 command to set MR13 OP[0] = 0b.
After time tMRW, the device is ready for normal operation. After training exit, the device
will automatically switch back to the FSP-OP registers that were in use prior to training.
Command bus training (CBT) may be executed from the idle or self refresh state. When
executing CBT within the self refresh state, the device must not be in a power-down
state (for example, CKE must be HIGH prior to training entry). CBT entry and exit is the
same, regardless of the state from which CBT is initiated.
Training Sequence for Single-Rank Systems

The sequence example shown here assumes an initial low-frequency, non-terminating
operating point training a high-frequency, terminating operating point. The bold text
shows high-frequency instructions. Any operating point may be trained from any
known good operating point.
1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or
FSP-OP[0]).
2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels to set up high-frequency
operating parameters.
3. Issue MRW-1 and MRW-2 commands to enter command bus training mode.
4. Drive CKE LOW, and change CK frequency to the high-frequency operating
point.
5. Perform command bus training (VREF(CA), CS, and CA).
6. Exit training by driving CKE HIGH, change CK frequency to the low-frequency
operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven
HIGH, the device will automatically switch back to the FSP-OP registers that were
in use prior to training (trained values are not retained).
7. Write the trained values to FSP-WR[1] (or FSP-WR[0]) by issuing MRW-1 and
MRW-2 commands to the SDRAM and setting all applicable mode register param-
eters.
8. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1]
(or FSP-OP[0]), to turn on termination, and change CK frequency to the high-fre-
quency operating point. At this point the command bus is trained and you may
proceed to other training or normal operation.
CCM005-554574167-10729

Training Sequence for Multiple-Rank Systems

The sequence example shown here is assuming an initial low-frequency operating
point, training a high-frequency operating point. The bold text shows high-frequency
instructions. Any operating point may be trained from any known good operating point.
1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or
FSP-WR[0]).
2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels and ranks to set up
high-frequency operating parameters.
3. Read MR0 OP[7] on all channels and ranks to determine which die are terminat-
ing, signified by MR0 OP[7] = 1b.
4. Issue MRW-1 and MRW-2 commands to enter command bus training mode on
the terminating rank.
5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency
to the high-frequency operating point.
6. Perform command bus training on the terminating rank (VREF(CA), CS, and CA).
7. Exit training by driving CKE HIGH, change CK frequency to the low-frequency
operating point, and issue MRW-1 and MRW-2 commands to write the trained
values to FSP-WR[1] (or FSP-WR[0]). When CKE is driven HIGH, the SDRAM will
automatically switch back to the FSP-OP registers that were in use prior to train-
ing (trained values are not retained by the device).
8. Issue MRW-1 and MRW-2 commands to enter training mode on the non-termi-
nating rank (but keep CKE HIGH).
quency operating point.
10. Drive CKE LOW on the non-terminating (or all) ranks. The non-terminating
rank(s) will now be using FSP-OP[1] (or FSP-OP[0]).
11. Perform command bus training on the non-terminating rank (VREF(CA), CS, and
CA).
12. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-
OP[0] (or FSP-OP[1]) to turn off termination.
13. Exit training by driving CKE HIGH on the non-terminating rank, change CK fre-
quency to the low-frequency operating point, and issue MRW-1 and MRW-2 com-
mands. When CKE is driven HIGH, the device will automatically switch back to
the FSP-OP registers that were in use prior to training (that is, trained values are
not retained by the device).
14. Write the trained values to FSP-WR[1] (or FSP-WR[0]) by issuing MRW-1 and
MRW-2 commands and setting all applicable mode register parameters.
quency operating point. At this point the command bus is trained for both ranks
and the user may proceed to other training or normal operation.
CCM005-554574167-10729

Relation Between CA Input Pin and DQ Output Pin
Table 120: Mapping CA Input Pin and DQ Output Pin
Mapping
CA number CA5 CA4 CA3 CA2 CA1 CA0
DQ number DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
Figure 115: Command Bus Training Mode Entry – CA Training Pattern I/O with VREF(CA) Value Update
T0 T1 T2 T3 T4 T5 Ta Tb Tb+1 Tc See Note 1 Td Te Te+1 Te+2 Tf Tg Th Th+1 Th+2
CK_c
CK_t
tCKPRECS tCKPSTCS
See Note 7
See Note 2
CKE
See Note 3
tMRD tCKELCK tCACD
CS
CA DES MRW1 MRW1 MRW2 MRW2 DES DES DES DES DES Valid Valid
CA training
pattern B
CA training
Command DES Enter command bus training mode DES DES DES DES DES
pattern A
tDQSCKE tCAENT tVREFCA_Long (see Note 5) tADR

See Note 4
DQS0_t
DQS0_c
tDS,train tDH,train
DQ[6:0] Valid
DQ7
DMI0
DQ[13:8] Pattern A
DQ[15:14]
DMI1
DQS1_t
DQS1_c
VREF(CA)
Setting value of MR X (Y) Updating setting from FSP switching Updating setting Temporary setting value
(reference)
tCKELODTon (see Note 6)
ODT_CA
Mode register X (Y) Switching MR Mode register X (Y)
(reference)
Don’t Care
Notes: 1. After tCKELCK, the clock can be stopped or the frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which
disables command decoding).
4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an un-
stable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is
required every for DQS input signal while capturing DQ[6:0] signals. The captured value
of the DQ[6:0] signal level by each DQS edge may be overwritten at any time and the
device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long.
5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1)
The new VREF setting is a single step above or below the old VREF setting; 2) The DQS
pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets
tDS,train/ tDH,train for every DQS pulse applied.
CCM005-554574167-10729

6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate
(non-active) set. For example, if the device is currently using FSP-OP[0], then it will
switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be writ-
ten to the alternate mode registers before entering command bus training to ensure
that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values.
7. When CKE is driven LOW in command bus training mode, the device will change opera-
tion to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode
register.
Figure 116: Consecutive VREF(CA) Value Update

T0 Ta Tb Tb+1 Tc See Note 1 Td Te Te+1 Te+2 Te+3 Te+4 Te+5 Te+6 Te+7 Te+8 Te+9 Te+10 Tf Tf+1 Tf+2 Tf+3
CK_c
CK_t
tCKELCK (see Note 2)
See Note 7
CKE
tCKELCK (see Note 3)
CS
CA DES DES DES DES DES Valid
CA training
Command DES DES DES DES DES
pattern A
tDQSCKE tCAENT tVREFCA_Long (see Note 5) tCS_VREF See Note 4 tVREFCA_Long (see Note 5)
See Note 4
DQS0_t
DQS0_c
tDS,train tDH,train tDS,train tDH,train
DQ[6:0] Valid Valid
DQ7
DMI0
tADR
DQ[13:8] Pattern A
DQ[15:14]
DMI1
DQS1_t
DQS1_c
VREF(CA)
Setting value of MR X (Y) Updating setting from FSP switching Updating setting Temporary setting value Updating setting
(reference)
tCKELODTon (see Note 6)
ODT_CA
Mode register X (Y) Switching MR Mode register X (Y)
(reference)
Don’t Care
Notes: 1. After tCKELCK, the clock can be stopped or the frequency changed any time.
2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS.
3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which
disables command decoding).
4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an un-
stable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is
required every for DQS input signal while capturing DQ[6:0] signals. The captured value
of the DQ[6:0] signal level by each DQS edge may be overwritten at any time and the
device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long.
5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1)
The new VREF setting is a single step above or below the old VREF setting; 2) The DQS
CCM005-554574167-10729

pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets
tDS,train/ tDH,train for every DQS pulse applied.
6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate
(non-active) set. For example, if the device is currently using FSP-OP[0], then it will
switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be writ-
ten to the alternate mode registers before entering command bus training to ensure
that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values.
7. When CKE is driven LOW in command bus training mode, the device will change opera-
tion to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode
register.
Figure 117: Command Bus Training Mode Exit with Valid Command
T0 T1 T2 Ta0 Ta1 Ta2 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 Tf1 Tf2 Tf3 Tf4 Tg0 Tg1 Tg2 Tg3 Tg4 Tg5
CK_c
CK_t
tCKPSTCS
CKE
Note 5
tCACD tCKCKEH Note 1 tXCBT tMRW
CS
CA Valid Valid MRW-1 MRW-1 MRW-2 MRW-2 Valid Valid Valid Valid
Note 2
CA CA Exiting command bus training
Command pattern B pattern C DES DES DES DES DES DES DES Valid DES
mode
tADR tADR tCKEHDQS
DQS_t[0]
DQS_c[0]
DQ[6:0]
DQ[7]
DMI[0]
tMRZ
DQ[13:8] Pattern A Pattern B Pattern C
DQ[15:14]
DMI[1]
DQS_t[1]
DQS_c[1]
Note 4
VREF(CA) Temporary setting value Switching MR Setting value of MR X (Y)
(Reference)
t CKELODToff Note 3
ODT_CA Mode register Y (X) Mode register X (Y)

(Reference) Switching MR
Don’t Care
Notes: 1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must
meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency
must be returned to the original frequency (that is, the frequency corresponding to the
FSP at command bus training mode entry.
2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH.
3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior
to command bus training mode entry, that is, the original frequency set point (FSP-OP,
MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will
switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the device and must be written to the FSP-OP regis-
ter set before returning to operation at the trained frequency. For example, VREF(CA) will
return to the value programmed in the original set point.
CCM005-554574167-10729

5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus
training mode entry.
Figure 118: Command Bus Training Mode Exit with Power-Down Entry
T0 T1 T2 Ta0 Ta1 Ta2 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 Tf1 Tf2 Tf3 Tf4 Tg0 Tg1 Tg2 Tg3 Th0 Tk1
CK_c
CK_t
tCKPSTCS tCKELCK
CKE
Note 5
tCACD tCKCKEH Note 1 tXCBT tMRD tCKELCMD
CS
CA Valid Valid MRW-1 MRW-1 MRW-2 MRW-2 Valid Valid
Note 2
CA CA Exiting command bus training POWER-DOWN
Command pattern B pattern C DES DES DES DES DES DES mode DES ENTRY DES DES
tADR tADR tCKEHDQS
DQS_t[0]
DQS_c[0]
DQ[6:0]
DQ[7]
DMI[0]
tMRZ
DQ[13:8] Pattern A Pattern B Pattern C
DQ[15:14]
DMI[1]
DQS_t[1]
DQS_c[1]
Note 4
VREF(CA) Setting value of MR X (Y)
Temporary setting value Switching MR
(Reference)
tCKELODToff Note 3
ODT_CA Mode register X (Y)

(Reference)
Mode register Y (X) Switching MR
Don’t Care
Notes: 1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must
meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency
must be returned to the original frequency (that is, the frequency corresponding to the
FSP at command bus training mode entry.
2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH.
3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior
to command bus training mode entry, that is, the original frequency set point (FSP-OP,
MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will
switch to FSP-OP[0] when CKE is driven HIGH.
4. Training values are not retained by the device and must be written to the FSP-OP regis-
ter set before returning to operation at the trained frequency. For example, VREF(CA) will
return to the value programmed in the original set point.
5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus
training mode entry.
CCM005-554574167-10729

Write Leveling
Write Leveling
Mode Register Write-WR Leveling Mode
To improve signal-integrity performance, the device provides a write leveling feature to
compensate for CK-to-DQS timing skew, affecting timing parameters such as tDQSS,
tDSS, and tDSH. The memory controller uses the write leveling feature to receive feed-
back from the device, enabling it to adjust the clock-to-data strobe signal relationship
for each DQS_t/DQS_c signal pair. The device samples the clock state with the rising
edge of DQS signals and asynchronously feeds back to the memory controller. The
memory controller references this feedback to adjust the clock-to-data strobe signal re-
lationship for each DQS_t/DQS_c signal pair.
All data bits (DQ[7:0] for DQS[0] and DQ[15:8] for DQS[1]) carry the training feedback to
the controller. Both DQS signals in each channel must be leveled independently. Write
leveling entry/exit is independent between channels for dual-channel devices.
The device enters write leveling mode when mode register MR2-OP[7] is set HIGH.
When entering write leveling mode, the state of the DQ pins is undefined. During write
leveling mode, only DESELECT commands, or a MRW command to exit the WRITE
LEVELING operation, are allowed. Depending on the absolute values of tQSL and tQSH
in the application, the value of tDQSS may have to be better than the limits provided in
the AC Timing Parameters section in order to satisfy the tDSS and tDSH specifications.
Upon completion of the WRITE LEVELING operation, the device exits write leveling
mode when MR2-OP[7] is reset LOW.
Write leveling should be performed before write training (DQS2DQ training).
Write Leveling Procedure

1. Enter write leveling mode by setting MR2-OP[7]=1.
2. Once in write leveling mode, DQS_t must be driven LOW and DQS_c HIGH after a
delay of tWLDQSEN.
3. Wait for a time tWLDQSEN before providing the first DQS signal input. The delay
time tWLMRD(MAX) is controller-dependent.
4. The device may or may not capture the first rising edge of DQS_t due to an unsta-
ble first rising edge; therefore, at least two consecutive pulses of DQS signal input
is required for every DQS input signal during write training mode. The captured
clock level for each DQS edge is overwritten, and the device provides asynchro-
nous feedback on all DQ bits after time tWLO.
5. The feedback provided by the device is referenced by the controller to increment
or decrement the DQS_t and/or DQS_c delay settings.
6. Repeat steps 4 and 5 until the proper DQS_t/DQS_c delay is established.
7. Exit write leveling mode by setting MR2-OP[7] = 0.
CCM005-554574167-10729

Write Leveling
Figure 119: Write Leveling Timing – tDQSL(MAX)

T0 T1 T2 T3 T4 Ta Ta1 Tb Tb1 Tc Tc1 Td Td1 Td2 Td3 Te Te1 Tf Tf1 Tf2 Tf3 Tf4 Tg Tg1 Tg2 Tg3 Tg4
CK_c
CK_t
CA[5:0] MRW MRW MRW MRW DES DES DES DES DES DES DES DES DES DES DES DES DES DES MRW MRW MRW MRW DES DES Valid Valid Valid Valid
MA MA OP OP MA MA OP OP
MRW-1 MRW-2 MRW-1 WR MRW-2 WR

Command WR LEVELING WR LEVELING
DES DES DES DES DES DES DES
LEVELING exit LEVELING exit
DES Valid Valid
tWLDQSEN tDQSH
tDQSL
tWLWPRE
DQS_c
DQS_t
tWLMRD tWLO tWLO tMRD
tWLO tWLO
DQ[15:0]
DMI[1:0]
Don’t Care
Note: 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH).
However, a stable clock prior to sampling is required to ensure timing accuracy.
Figure 120: Write Leveling Timing – tDQSL(MIN)

T0 T1 T2 T3 T4 Ta Ta1 Tb Tb1 Tc Tc1 Td Td1 Td2 Td3 Te Te1 Tf Tf1 Tf2 Tf3 Tf4 Tg Tg1 Tg2 Tg3
CK_c
CK_t
CA[5:0] MRW MRW MRW MRW DES DES DES DES DES DES DES DES DES DES DES DES DES DES MRW MRW MRW MRW DES DES Valid Valid Valid Valid
MA MA OP OP MA MA OP OP
MRW-1 MRW-2 MRW1 WR MRW-2 WR

Command WR LEVELING WR LEVELING DES DES DES DES DES DES DES LEVELING exit LEVELING exit DES Valid Valid
tDQSH tDQSL
tWLDQSEN tWLWPRE
DQS_c
DQS_t
tWLMRD tWLO tWLO tMRD
tWLO
DQ[15:0]
DMI[1:0]
Don’t Care
Note: 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH).
However, a stable clock prior to sampling is required to ensure timing accuracy.
Input Clock Frequency Stop and Change

The input clock frequency can be stopped or changed from one stable clock rate to an-
other stable clock rate during write leveling mode. The frequency stop or change timing
is shown below.
CCM005-554574167-10729

Write Leveling
Figure 121: Clock Stop and Timing During Write Leveling

T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tc0 Td0 Te0 Te1 Te2 Te3 Te4 Tf0 Tf1 Tf2 Tf3
CK_c
CK_t
t CKPSTDQS t CKPRDQS
CS
CKE
MRW MRW MRW MRW

CA MA MA OP OP DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
MRW-1 MRW-2
Command WR LEVELING WR LEVELING DESELECT DESELECT DESELECT DESELECT DESELECT DESELECT DESELECT DESELECT
t WLDQSEN t WLWPRE t DQSH

t DQSL
DQS_t
DQS_c
t WLMRD t WLO t WLO
t WLO t WLO
DQ
DMI
Don’t Care
Notes: 1. CK_t is held LOW and CK_c is held HIGH during clock stop.
2. CS will be held LOW during clock stop.
Table 121: Write Leveling Timing Parameters
Parameter Symbol Min/Max Value Units

DQS_t/DQS_c delay after write leveling mode is tWLDQSEN MIN 20 tCK
programmed MAX –
Write preamble for write leveling tWLWPRE MIN 20 tCK
MAX –
First DQS_t/DQS_c edge after write leveling tWLMRD MIN 40 tCK
mode is programmed MAX –

Write leveling output delay tWLO MIN 0 ns
MAX 20
MODE REGISTER SET command delay tMRD Refer to Mode Register Timing Parameter Table
Valid clock requirement before DQS toggle tCKPRDQS MIN MAX(7.5ns, 4nCK) –
MAX –
Valid clock requirement after DQS toggle tCKPSTDQS MIN MAX(7.5ns, 4nCK) –
MAX –
Table 122: Write Leveling Setup and Hold Timing
Data Rate
Parameter Symbol Min/Max 1600 2400 3200 3733 4267 Unit
Write leveling hold time tWLH MIN 150 100 75 62.5 50 ps
Write leveling setup time tWLS MIN 150 100 75 62.5 50 ps
CCM005-554574167-10729

Write Leveling
Table 122: Write Leveling Setup and Hold Timing (Continued)
Data Rate
Parameter Symbol Min/Max 1600 2400 3200 3733 4267 Unit
Write leveling input valid tWLIVW MIN 240 160 120 105 90 ps
window
Notes: 1. In addition to the traditional setup and hold time specifications, there is value in an in-
valid window-based specification for write leveling training. As the training is based on
each device, worst-case process skews for setup and hold do not make sense to close
timing between CK and DQS.
2. tWLIVW is defined in a similar manner to TdIVW_total, except that here it is a DQS inva-
lid window with respect to CK. This would need to account for all voltage and tempera-
ture (VT) drift terms between CK and DQS within the device that affect the write level-
ing invalid window.
The figure below shows the DQS input mask for timing with respect to CK. The “total”
mask (tWLIVW) defines the time the input signal must not encroach in order for the
DQS input to be successfully captured by CK. The mask is a receiver property and it is
not the valid data-eye.
Figure 122: DQS_t/DQS_c to CK_t/CK_c Timings at the Pins Referenced from the Internal Latch
Internal composite DQS eye
center aligned to CK
CK_c
CK_t
DQ_diff =
DQS_t–DQS_c tWLIVW
CCM005-554574167-10729

MULTIPURPOSE Operation
The device uses the MULTIPURPOSE command to issue a NO OPERATION (NOP) com-
mand and to access various training modes. The MPC command is initiated with CS,
and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Com-
mand Truth Table. The MPC command has seven operands (OP[6:0]) that are decoded
to execute specific commands in the SDRAM. OP[6] is a special bit that is decoded on
the first rising CK edge of the MPC command. When OP[6] = 0, the device executes a
NOP command, and when OP[6] = 1, the device further decodes one of several training
commands.
When OP[6] = 1 and the training command includes a READ or WRITE operation, the
MPC command must be followed immediately by a CAS-2 command. For training com-
mands that read or write, READ latency (RL) and WRITE latency (WL) are counted from
the second rising CK edge of the CAS-2 command with the same timing relationship as
a typical READ or WRITE command. The operands of the CAS-2 command following a
MPC READ/WRITE command must be driven LOW. The following MPC commands
must be followed by a CAS-2 command:
• WRITE-FIFO
• READ-FIFO
• READ DQ CALIBRATION
All other MPC commands do not require a CAS-2 command, including the following:
• NOP
• START DQS INTERVAL OSCILLATOR
• STOP DQS INTERVAL OSCILLATOR
• ZQCAL START (ZQ CALIBRATION START)
• ZQCAL LATCH (ZQ CALIBRATION LATCH)
Table 123: MPC Command Definition
SDR Command Pins SDR CA Pins

CKE
CK_t CK_t
SDR Command (n-1) CK_t(n) CS CA0 CA1 CA2 CA3 CA4 CA5 Edge Notes
MPC H H H L L L L L OP6 1 1, 2
(Train, NOP) L OP0 OP1 OP2 OP3 OP4 OP5 2
Notes: 1. See the Command Truth Table for more information.

2. MPC commands for READ or WRITE TRAINING operations must be immediately followed
by the CAS-2 command, consecutively, without any other commands in between. The
MPC command must be issued before issuing the CAS-2 command.
CCM005-554574167-10729

Table 124: MPC Commands
Function Operand Data

Training Modes OP[6:0] 0XXXXXXb: NOP
1000001b: READ-FIFO: READ-FIFO supports only BL16 operation
1000011b: READ DQ CALIBRATION (MR32/MR40)
1000101b: RFU
1000111b: WRITE-FIFO: WRITE-FIFO supports only BL16 operation
1001001b: RFU
1001011b: START DQS OSCILLATOR
1001101b: STOP DQS OSCILLATOR
1001111b: ZQCAL START
1010001b: ZQCAL LATCH
All Others: Reserved
Notes: 1. See command truth table for more information.

2. MPC commands for READ or WRITE TRAINING operations must be immediately followed
by CAS-2 command consecutively without any other commands in-between. MPC com-
mand must be issued first before issuing the CAS-2 command.
3. WRITE-FIFO and READ-FIFO commands will only operate as BL16, ignoring the burst
length selected by MR1 OP[1:0].
Figure 123: WRITE-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 Te2 Tf0 Tf1 Tg0 Tg1 Tg2 Tg3
CK_c
CK_t
CS
BA0,
CA BL
CA
CAn CAn Valid Valid Valid Valid Valid Valid Valid Valid
MPC MPC
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES
[WRITE-FIFO]
CAS-2 DES DES
[WRITE-FIFO]
CAS-2 DES DES DES DES DES DES DES DES DES DES
t WRWTR tCCD =8 WL
WL WL
tDQSS tDQSS tDQSS
t WPRE WPRE t WPST
t WPST
DQS_c
DQS_t
tDQS2DQ tDQS2DQ tDQS2DQ
DQ[15:0]
n0 n13 n14 n15 n0 n13 n14 n15 n0 n13 n14 n15
DMI[1:0]
Don’t Care
Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during
refresh or during self refresh, with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Tim-
ing from Write-1 to MPC[WRITE-FIFO] is tWRWTR.
3. Seamless MPC[WRITE-FIFO] commands may be executed by repeating the command ev-
ery tCCD time.
4. MPC[WRITE-FIFO] uses the same command-to-data timing relationship (WL, tDQSS,
tDQS2DQ) as a WRITE-1 command.
5. A maximum of five MPC[WRITE-FIFO] commands may be executed consecutively without

corrupting FIFO data. The sixth MPC[WRITE-FIFO] command will overwrite the FIFO data
CCM005-554574167-10729

from the first command. If fewer than five MPC[WRITE-FIFO] commands are executed,
then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driv-
en LOW.
7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow
MPC[WRITE-FIFO]/CAS-2 without any other commands in-between. See Write Training
section for more information on FIFO pointer behavior.
Figure 124: READ-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK, tRPRE = Toggling, tRPST = 1.5nCK
T0 T1 T2 T3 T4 Ta Ta+1 Ta+2 Ta+3 Tb Tb+1 Tb+2 Tb+3 Tb+4 Tb+5 Tc+2 Tc+3 Tc+4 Tc+5 Tc+6 Tc+7 Td Td+1 Td+2 Td+3 Td+4 Td+5 Te Te+1 Tf Tf+1 Tf+2 Tf+3 Tf+4
CK_c
CK_t
tCCD
CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
WL RL
MPC MPC MPC

Command [WRITE-FIFO]
CAS-2 Valid Valid Valid
[READ-FIFO]
CAS-2 Valid
[READ-FIFO]
CAS-2 Valid Valid Valid Valid Valid Valid Valid
tDQSS tWTR tDQSCK
DQS_t
DQS_c
tDQS2DQ tRPRE tRPST
DQ[15:0] D0 D1 D12 D13 D14 D15 D0 D1 D2 D13 D14 D15 D0 D11 D12 D13 D14 D15
DMI[1:0]
Don’t Care
refresh or during self refresh with CKE HIGH.
2. Seamless MPC[READ-FIFO] commands may be executed by repeating the command ev-
ery tCCD time.
3. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a
READ-1 command.
4. Data may be continuously read from the FIFO without any data corruption. After five
MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and con-
tinue advancing. If fewer than five MPC[WRITE-FIFO] commands were executed, then
the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See
Write Training for more information on the FIFO pointer behavior.
5. For the CAS-2 command immediately following an MPC command, the CAS-2 operands
must be driven LOW.
6. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode regis-
ters. See Write Training for more information on DMI behavior.
CCM005-554574167-10729

Figure 125: READ-FIFO – tRPRE = Toggling, tRPST = 1.5nCK

T0 T1 T2 T3 T4 Ta Ta+1 Ta+2 Ta+3 Ta+4 Tb Tb+1 Tc Tc+1 Tc+2 Tc+3 Tc+4 Tc+5 Td Td+1 Td+2 Td+3 Te Te+1 Te+2 Te+3 Te+4 Te+5
CK_c
CK_t
tRTRRD
CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
RL RL
MPC
Command [READ-FIFO]
CAS-2 Valid Valid Valid Valid Valid READ-1 CAS-2 Valid Valid Valid Valid Valid Valid
tDQSCK tDQSCK
DQS_t
DQS_c
tRPRE tRPST tRPRE tRPST
DQ[15:0] D0 D1 D2 D13 D14 D15 D0 D1 D12 D13 D14 D15

DMI[1:0]
Don’t Care
2. MPC[READ-FIFO] to READ-1 operation is shown as an example of command-to-com-
mand timing for MPC. Timing from MPC[READ-FIFO] command to read is tRTRRD.
ery tCCD time.
4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a
READ-1 command.
tinue advancing. If fewer than five MPC[WRITE-FIFO] commands are executed, then the
MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See
must be driven LOW.
Table 125: Timing Constraints for Training Commands
Previous Com-
mand Next Command Minimum Delay Unit Notes
WR/MWR MPC[WRITE-FIFO] tWRWTR nCK 1
MPC[READ-FIFO] Not allowed – 2
MPC[READ DQ CALIBRATION] WL + RU(tDQSS(MAX)/tCK) + nCK
BL/2 + RU(tWTR/tCK)
RD/MRR MPC[WRITE-FIFO] tRTRRD nCK 3
MPC[READ DQ CALIBRATION] tRTRRD nCK 3
CCM005-554574167-10729

Table 125: Timing Constraints for Training Commands (Continued)
Previous Com-
mand Next Command Minimum Delay Unit Notes
MPC[WRITE-FIFO] WR/MWR Not allowed – 2
MPC[WRITE-FIFO] tCCD nCK
RD/MRR Not allowed – 2
MPC[READ-FIFO] WL + RU(tDQSS(MAX)/tCK) + nCK
BL/2 + RU(tWTR/tCK)
MPC[READ DQ CALIBRATION] Not allowed – 2
MPC[READ-FIFO] WR/MWR tRTRRD nCK 3
MPC[WRITE-FIFO] tRTW nCK 4
RD/MRR tRTRRD nCK 3
MPC[READ-FIFO] tCCD nCK
MPC[READ DQ CALIBRATION] tRTRRD nCK 3
MPC[READ DQ CALI- WR/MWR tRTRRD nCK 3
BRATION] MPC[WRITE-FIFO] tRTRRD nCK 3
RD/MRR tRTRRD nCK 3
MPC[READ DQ CALIBRATION] tCCD nCK
Notes: 1. tWRWTR = WL + BL/2 + RU(tDQSS(MAX)/tCK) + MAX(RU(7.5ns/tCK), 8nCK).

2. No commands are allowed between MPC[WRITE-FIFO] and MPC[READ-FIFO] except the
MRW commands related to training parameters.
3. tRTRRD = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK).
4. In case of DQ ODT disable MR11 OP[2:0] = 000b,
tRTW = RL + RU(tDQSCK(MAX)/tCK) + BL/2 - WL + tWPRE + RD(tRPST).
In case of DQ ODT enable MR11 OP[2:0] ≠ 000b,
tRTW = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK)
+ 1.
CCM005-554574167-10729

Read DQ Calibration Training

The READ DQ CALIBRATION TRAINING function outputs a 16-bit, user-defined pat-
tern on the DQ pins. Read DQ calibration is initiated by issuing a MPC[READ DQ CALI-
BRATION] command followed by a CAS-2 command, which causes the device to drive
the contents of MR32, followed by the contents of MR40 on each of DQ[15:0] and
DMI[1:0]. The pattern can be inverted on selected DQ pins according to user-defined
invert masks written to MR15 and MR20.
Read DQ Calibration Training Procedure

1. Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits),
MR15 (eight-bit invert mask for byte 0), and MR20 (eight-bit invert mask for byte
1).
In the alternative, this step could be replaced with the default pattern:
• MR32 default = 5Ah
• MR40 default = 3Ch
• MR15 default = 55h
• MR20 default = 55h
2. Issue an MPC command, followed immediately by a CAS-2 command.
• Each time an MPC command followed by a CAS-2 is received by the device, a
16-bit data burst will drive the eight bits programmed in MR32 followed by the
eight bits programmed in MR40 on all I/O pins after the currently-set RL.
• The data pattern will be inverted for I/O pins with a 1 programmed in the corre-
sponding invert mask mode register bit (see table below).
• The pattern is driven on the DMI pins, but no DATA BUS INVERSION function is
enabled, even if read DBI is enabled in the mode register.
• The MPC command can be issued every tCCD seamlessly, and tRTRRD delay is
required between ARRAY READ command and the MPC command as well the
delay required between the MPC command and an ARRAY READ.
• The operands received with the CAS-2 command must be driven LOW.
3. DQ
Read DQ calibration training can be performed with any or no banks active during
Table 126: Invert Mask Assignments
DQ pin 0 1 2 3 DMI0 4 5 6 7
MR15 bit 0 1 2 3 N/A 4 5 6 7
DQ pin 8 9 10 11 DMI1 12 13 14 15
MR20 bit 0 1 2 3 N/A 4 5 6 7
CCM005-554574167-10729

Figure 126: Read DQ Calibration Training Timing: Read-to-Read DQ Calibration

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Td1 Td2 Td3 Td4 Td5 Td6 Te0 Te1 Te2 Te3
CK_c
CK_t
CS
BA0,
CA BL
CA
CAn CAn Valid Valid Valid Valid
MPC
Command READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES
[RD DQ CAL]
CAS-2 DES DES DES DES DES DES DES DES DES DES DES
tRTRRD t
RL DQSCK
RL t
DQSCK
t RPST
t RPRE t RPRE
t RPST
DQS_c
High-Z High-Z
DQS_t
tDQSQ tDQSQ
DQ
High-Z n0 n13 n14 n15 High-Z n0 n13 n14 n15
DMI
Don’t Care
Notes: 1. Read-1 to MPC operation is shown as an example of command-to-command timing. Tim-

ing from Read-1 to MPC command is tRTRRD.
2. MPC uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a
Read-1 command.
3. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK.
these times.
Figure 127: Read DQ Calibration Training Timing: Read DQ Calibration to Read DQ Calibration/Read
T0 T1 T2 T3 T8 T9 T10 T11 T12 T13 T14 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Te0 Te1
CK_c
CK_t
CS
BA0,
CA Valid Valid Valid Valid Valid Valid Valid Valid BL CA CAn CAn
MPC MPC
Command [RD DQ CAL]
CAS-2 DES
[RD DQ CAL]
CAS-2 DES DES DES DES DES DES DES DES DES DES READ-1 CAS-2 DES DES DES DES DES DES DES DES
t CCD tDQSCK
tRTRRD RL
RL tDQSCK
RL tDQSCK
t RPST t RPST
t RPRE t RPRE
DQS_c
High-Z High-Z
DQS_t
tDQSQ t DQSQ tDQSQ
DQ
High-Z n0 n9 n10 n11 n12 n13 n14 n15 n0 n13 n14 n15 High-Z n0 n13 n14 n15
DMI
Don’t Care
Notes: 1. MPC[READ DQ CALIBRATION] to MPC[READ DQ CALIBRATION] operation is shown as an

example of command-to-command timing.
2. MPC[READ DQ CALIBRATION] to READ-1 operation is shown as an example of com-
mand-to-command timing.
3. MPC[READ DQ CALIBRATION] uses the same command-to-data timing relationship (RL,
tDQSCK, tDQSQ) as a READ-1 command.
4. Seamless MPC[READ DQ CALIBRATION] commands may be executed by repeating the

command every tCCD time.
5. Timing from MPC[READ DQ CALIBRATION] command to READ-1 is tRTRRD.
CCM005-554574167-10729

6. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK.

these times.
Read DQ Calibration Training Example

An example of read DQ calibration training output is shown in table below. This shows
the 16-bit data pattern that will be driven on each DQ in byte 0 when one READ DQ
CALIBRATION TRAINING command is executed. This output assumes the following
mode register values are used:
• MR32 = 1CH
• MR40 = 59H
• MR15 = 55H
• MR20 = 55H
Table 127: Read DQ Calibration Bit Ordering and Inversion Example
Bit Sequence →
Pin Invert 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DQ0 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ1 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DQ2 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ3 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DMI0 Never 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DQ4 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ5 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DQ6 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ7 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DQ8 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ9 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DQ10 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ11 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DMI1 Never 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DQ12 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ13 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
DQ14 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1
DQ15 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0
Notes: 1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0]
when read DQ calibration is initiated via a MPC[READ DQ CALIBRATION] command. The
pattern transmitted serially on each data lane, organized little endian such that the low-
order bit in a byte is transmitted first. If the data pattern is 27H, then the first bit trans-
mitted with be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111 →.
2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins.
3. DMI [1:0] outputs status follows MR Setting vs. DMI Status table.
CCM005-554574167-10729

Write Training
DBI is enabled in MR3-OP[6].
Table 128: MR Setting vs. DMI Status
DM Function WRITE DBIdc Function READ DBIdc Function

Status
MR13 OP[5] MR3 OP[7] MR3 OP[6] DMI
1: Disable 0: Disable 0: Disable High-Z
1: Disable 1: Enable 0: Disable The data pattern is transmitted
1: Disable 0: Disable 1: Enable The data pattern is transmitted
1: Disable 1: Enable 1: Enable The data pattern is transmitted
0: Enable 0: Disable 0: Disable The data pattern is transmitted
0: Enable 1: Enable 0: Disable The data pattern is transmitted
0: Enable 0: Disable 1: Enable The data pattern is transmitted
0: Enable 1: Enable 1: Enable The data pattern is transmitted
MPC[READ DQ CALIBRATION] After Power-Down Exit

Following the power-down state, an additional time, tMRRI, is required prior to issuing
the MPC[READ DQ CALIBRATION] command. This additional time (equivalent to
tRCD) is required in order to be able to maximize power-down current savings by allow-
ing more power-up time for the read DQ data in MR32 and MR40 data path after exit
from standby, power-down mode.
Figure 128: MPC[READ DQ CALIBRATION] Following Power-Down State

CK_c
CK_t
t CKCKEH
CKE
t XP t MRRI
CS
Command MPC
DES DES DES DES DES DES DES DES DES DES [READ DQ CAL] CAS-2 DES DES DES
Don’t Care
Write Training
The device uses an unmatched DQS-DQ path to enable high-speed performance and
save power. As a result, the DQS strobe must be trained to arrive at the DQ latch center-
aligned with the data eye. The DQ receiver is located at the DQ pad and has a shorter
internal delay than the DQS signal. The DQ receiver will latch the data present on the
CCM005-554574167-10729

Write Training
DQ bus when DQS reaches the latch, and training is accomplished by delaying the DQ
signals relative to DQS such that the data eye arrives at the receiver latch centered on
the DQS transition.
Two modes of training are available:
• Command-based FIFO WR/RD with user patterns
• An internal DQS clock-tree oscillator, which determines the need for, and the magni-
tude of, required training
The command-based FIFO WR/RD uses the MPC command with operands to enable
this special mode of operation. When issuing the MPC command, if CA[5] is set LOW
(OP[6] = 0), then the device will perform a NOP command. When CA[5] is set HIGH, the
CA[4:0] pins enable training functions or are reserved for future use (RFU). MPC com-
mands that initiate a read or write to the device must be followed immediately by a
CAS-2 command. See the MPC Operation section for more information.
To perform write training, the controller can issue an MPC[WRITE-FIFO] command
with OP[6:0] set, followed immediately by a CAS-2 command (CAS-2 operands should
be driven LOW) to initiate a WRITE-FIFO. Timings for MPC[WRITE-FIFO] are identical
to WRITE commands, with WL timed from the second rising clock edge of the CAS-2
command. Up to five consecutive MPC[WRITE-FIFO] commands with user-defined
patterns may be issued to the device, which will store up to 80 values (BL16 × 5) per pin
that can be read back via the MPC[READ-FIFO] command. (The WRITE/READ-FIFO
POINTER operation is described in a different section.
After writing data with the MPC[WRITE-FIFO] command, the data can be read back
with the MPC[READ-FIFO] command and results can be compared with "expected" da-
ta to determine whether further training (DQ delay) is needed. MPC[READ-FIFO] is ini-
tiated by issuing an MPC command, as described in the MPC Operation section, fol-
lowed immediately by a CAS-2 command (CAS-2 operands must be driven LOW). Tim-
ings for the MPC[READ-FIFO] command are identical to READ commands, with RL
timed from the second rising clock edge of the CAS-2 command.
READ-FIFO is nondestructive to the data captured in the FIFO; data may be read con-
tinuously until it is disturbed by another command, such as a READ, WRITE, or another
MPC[WRITE-FIFO]. If fewer than five WRITE-FIFO commands are executed, unwritten
registers will have undefined (but valid) data when read back.
For example, if five WRITE-FIFO commands are executed sequentially, then a series of
READ-FIFO commands will read valid data from FIFO[0], FIFO[1]….FIFO[4] and then
wrap back to FIFO[0] on the next READ-FIFO. However, if fewer than five WRITE-FIFO
commands are executed sequentially (example = 3), then a series of READ-FIFO com-
mands will return valid data for FIFO[0], FIFO[1], and FIFO[2], but the next two READ-
FIFO commands will return undefined data for FIFO[3] and FIFO[4] before wrapping
back to the valid data in FIFO[0].
The READ-FIFO pointer and WRITE-FIFO pointer are reset under the following condi-
tions:
• Power-up initialization
• RESET_n asserted
• Power-down entry
• Self refresh power-down entry
CCM005-554574167-10729

Write Training
The MPC[WRITE-FIFO] command advances the WRITE-FIFO pointer, and the

MPC[READ-FIFO] advances the READ-FIFO pointer. Also any normal (non-FIFO) READ
operation (RD, RDA) advances both WRITE-FIFO pointer and READ-FIFO pointer. Issu-
ing (non-FIFO) READ operation command is inhibited during write training period. To
keep the pointers aligned, the SoC memory controller must adhere to the following re-
striction at the end of Write training period:
b = a + (n × c)
Where:
'a' is the number of MPC[WRITE-FIFO] commands
'b' is the number of MPC[READ-FIFO] commands
'c' is the FIFO depth (= 5 for LPDDR4)
'n' is a positive integer, ≥0
Figure 129: WRITE-to-MPC[WRITE-FIFO] Operation Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 Te2 Tf0 Tf1 Tg0 Tg1 Tg2 Tg3
CK_c
CK_t
CS
BA0,
CA BL
CA
MPC MPC
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES
[WRITE-FIFO]
CAS-2 DES DES
[WRITE-FIFO]
CAS-2 DES DES DES DES DES DES DES DES DES DES
t WRWTR tCCD =8 WL
WL WL
tDQSS tDQSS tDQSS
t WPRE WPRE t WPST
t WPST
DQS_c
DQS_t
tDQS2DQ tDQS2DQ tDQS2DQ
DQ[15:0]
n0 n13 n14 n15 n0 n13 n14 n15 n0 n13 n14 n15
DMI[1:0]
Don’t Care
Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during
REFRESH or during SELF REFRESH with CKE HIGH.
2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Tim-
ing from Write-1 to MPC[WRITE-FIFO] is tWRWTR.
3. Seamless MPC[WR-FIFO] commands may be executed by repeating the command every
tCCD time.
4. MPC[WRITE-FIFO] uses the same command-to-data timing relationship (WL, tDQSS,

tDQS2DQ) as a WRITE-1 command.
5. A maximum of five MPC[WRITE-FIFO] commands may be executed consecutively without

corrupting FIFO data. The sixth MPC[WRITE-FIFO] command will overwrite the FIFO data
from the first command. If fewer than five MPC[WRITE-FIFO] commands are executed,
then the remaining FIFO locations will contain undefined data.
6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driv-
en LOW.
7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow
MPC[WRITE-FIFO]/CAS-2 without any other commands disturbing FIFO pointers in be-
tween. FIFO pointers are disturbed by CKE LOW, WRITE, MASKED WRITE, READ, READ
DQ CALIBRATION, and MRR.
these times.
CCM005-554574167-10729

Write Training
Figure 130: MPC[WRITE-FIFO]-to-MPC[READ-FIFO] Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 Te2 Te3 Tf0 Tf1 Tg0 Tg1
CK_c
CK_t
CS
BA0,
CA BL
CA
MPC MPC MPC

CAS-2 DES DES DES DES DES DES DES DES
[READ-FIFO]
CAS-2 DES DES
[READ-FIFO]
CAS-2 DES DES DES DES DES DES DES DES DES
tWTR tCCD =8
WL BL/2 + 1 clock
RL tDQSCK
tDQSS
t WPRE t RPRE
t WPST t RPST
DQS_c
DQS_t
tDQS2DQ tDQSQ
DQ
n0 n13 n14 n15 n0 n13 n14 n15 n0 n13 n14 n15
DMI
Don’t Care
Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during re-
fresh or during self refresh with CKE HIGH.
2. MPC[WRITE-FIFO] to MPC[READ-FIFO] is shown as an example of command-to-command
timing for MPC. Timing from MPC[WRITE-FIFO] to MPC[READ-FIFO] is specified in the
command-to-command timing table.
ery tCCD time.
4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK,
tDQSQ ) as a READ-1 command.
must be driven LOW.
ters. See Write Training section for more information on DMI behavior.
8. BL = 16, Write postamble = 0.5nCK, Read preamble: Toggle, Read postamble: 0.5nCK.
these times.
CCM005-554574167-10729

Write Training
Figure 131: MPC[READ-FIFO] to Read Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Td1 Td2 Td3 Td4 Td5 Td6 Te0 Te1 Te2 Te3
CK_c
CK_t
CS
CA Valid Valid CAn CAn BL BA0, CAn CAn

CA
MPC
Command RAD FIFO
CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES READ-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES
tRTRRD t
RL DQSCK
RL t
DQSCK
t RPRE t RPRE
t RPST t RPST
DQS_c
DQS_t
tDQSQ tDQSQ
DQ
n0 n13 n14 n15 n0 n13 n14 n15
DMI
Don’t Care
2. MPC[READ-FIFO] to READ-1 operation is shown as an example of command-to-com-
mand timing for MPC. Timing from MPC[READ-FIFO] command to READ is tRTRRD.
ery tCCD time.
4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK,
tDQSQ ) as a READ-1 command.
must be driven LOW.
8. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK
these times.
CCM005-554574167-10729

Write Training
Figure 132: MPC[WRITE-FIFO] with DQ ODT Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6
CK_c
CK_t
CS
MPC
CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
WL
tDQSS
t WPRE
t WPST
DQS_c
DQS_t
tDQS2DQ
DQ
n0 n1 n2 n13 n14 n15
DMI
t
ODTLon ODTon(MAX)
t
ODTon(MIN)
DRAM RTT ODT High-Z Transition ODT On Transition ODT High-Z
ODTLoff t
ODToff(MIN)
t
ODToff(MAX)
Don’t Care
2. MPC[WRITE-FIFO] uses the same command-to-data/ODT timing relationship (RL, tDQSCK,
tDQS2DQ, ODTLon, ODTLoff, tODTon, tODToff) as a WRITE-1 command.
must be driven LOW.
these times.
CCM005-554574167-10729

Write Training
Figure 133: Power-Down Exit to MPC[WRITE-FIFO] Timing

CK_c
CK_t
t
CKCKEH
CKE
t
t
XP MPCWR (= t RCD + 3nCK) WL
CS
Note 1
DES DES MPC
Command DES DES Any command Any command DES DES [WRITE-FIFO] CAS-2 DES DES DES
Don’t Care
Notes: 1. Any commands except MPC[WRITE-FIFO] and other exception commands defined other
section in this document (for example. MPC[READ DQ CALIBRATION]).
these times.
Table 129: MPC[WRITE-FIFO] AC Timing
Parameter Symbol MIN/MAX Value Unit

Additional time after tXP
has expired until tMPCWR MIN tRCD + 3nCK –
MPC[WRITE-FIFO] command may be issued
Internal Interval Timer

As voltage and temperature change on the device, the DQS clock-tree delay will shift,
requiring retraining. The device includes an internal DQS clock-tree oscillator to meas-
ure the amount of delay over a given time interval (determined by the controller), allow-
ing the controller to compare the trained delay value to the delay value seen at a later
time. The DQS oscillator will provide the controller with important information regard-
ing the need to retrain and the magnitude of potential error.
The DQS interval oscillator is started by issuing an MPC command with OP[6:0] set as
described in MPC Operation, which will start an internal ring oscillator that counts the
number of time a signal propagates through a copy of the DQS clock tree.
The DQS oscillator may be stopped by issuing an MPC[STOP DQS OSCILLATOR] com-
mand with OP[6:0] set as described in MPC Operation, or the controller may instruct
the SDRAM to count for a specific number of clocks and then stop automatically (See
MR23 for more information). If MR23 is set to automatically stop the DQS oscillator,
then the MPC[STOP DQS OSCILLATOR] command should not be used (illegal). When
the DQS oscillator is stopped by either method, the result of the oscillator counter is au-
tomatically stored in MR18 and MR19.
The controller may adjust the accuracy of the result by running the DQS interval oscilla-
tor for shorter (less accurate) or longer (more accurate) duration. The accuracy of the
CCM005-554574167-10729

Write Training
result for a given temperature and voltage is determined by the following equation,
where run time = total time between START and STOP commands and DQS delay = the
value of the DQS clock tree delay (tDQS2DQ(MIN)/(MAX)):
2 x (DQS delay)
DQS oscillator granularity error =
run time
Additional matching error must be included, which is the difference between DQS
training circuit and the actual DQS clock tree across voltage and temperature. The
matching error is vendor specific. Therefore, the total accuracy of the DQS oscillator
counter is given by:
DQS oscillator accuracy = 1 - granularity error - matching error
For example, if the total time between START and STOP commands is 100ns, and the
maximum DQS clock tree delay is 800ps (tDQS2DQ(MAX)), then the DQS oscillator
granularity error is:
2 x (0.8ns)
DQS oscillator granularity error = = 1.6%
100ns
This equates to a granularity timing error of 12.8ps. Assuming a circuit matching error
of 5.5ps across voltage and temperature, the accuracy is:
12.8 + 5.5
DQS oscillator accuracy = 1 - = 97.7%
800
For example, running the DQS oscillator for a longer period improves the accuracy. If
the total time between START and STOP commands is 500ns, and the maximum DQS
clock tree delay is 800ps (tDQS2DQ(MAX)), then the DQS oscillator granularity error is:
2 x (0.8ns)
DQS oscillator granularity error = = 0.32%
500ns
This equates to a granularity timing error or 2.56ps. Assuming a circuit matching error
of 5.5ps across voltage and temperature, the accuracy is:
2.56 + 5.5
DQS oscillator accuracy = 1 - = 99.0%
800
The result of the DQS interval oscillator is defined as the number of DQS clock tree de-
lays that can be counted within the run time, determined by the controller. The result is
stored in MR18-OP[7:0] and MR19-OP[7:0].
MR18 contains the least significant bits (LSB) of the result, and MR19 contains the most
significant bits (MSB) of the result. MR18 and MR19 are overwritten by the SDRAM
when a MPC[STOP DQS OSCILLATOR] command is received.
The SDRAM counter will count to its maximum value (= 2^16) and stop. If the maxi-
mum value is read from the mode registers, the memory controller must assume that
the counter overflowed the register and therefore discard the result. The longest run
time for the oscillator that will not overflow the counter registers can be calculated as
follows:
Longest runtime interval = 216 x tDQS2DQ(MIN) = 216 × 0.2ns = 13.1µs
CCM005-554574167-10729

Write Training
DQS Interval Oscillator Matching Error

The interval oscillator matching error is defined as the difference between the DQS
training ckt (interval oscillator) and the actual DQS clock tree across voltage and tem-
perature.
Parameters:
tDQS2DQ: Actual DQS clock tree delay
tDQS
OSC: Training ckt (interval oscillator) delay
OSCOffset: Average delay difference over voltage and temperature (shown below)
OSCMatch: DQS oscillator matching error
Figure 134: Interval Oscillator Offset – OSCoffset
Offset 2
tDQS2DQ
tDQS
OSC
Time
(ps)
OSC offset = AVG(offset1, offset2)
Offset 1 (at end point) = tDQS2DQ(V,T) – tDQSOSC(V,T)

Offset 2 (at end point) = tDQS2DQ(V,T) – tDQSOSC(V,T)
Offset 1
Temperature(T)/Voltage(V)
OSCMatch :
OSCMatch = [ tDQS2DQ(V,T) - tDQSOSC (V,T) - OSCoffset ]
tDQS
OSC:
tDQS
Runtime
OSC(V,T) = [ ]
2 × Count
Table 130: DQS Oscillator Matching Error Specification
Parameter Symbol MIN MAX Unit Notes

DQS oscillator matching error OSCMatch –20 20 ps 1, 2, 3, 4,
5, 6, 7, 8
DQS oscillator offset OSCoffset –100 100 ps 2, 4. 7
Notes: 1. The OSCMatch is the matching error per between the actual DQS and DQS interval oscilla-
tor over voltage and temperature.
CCM005-554574167-10729

Write Training
2. This parameter will be characterized or guaranteed by design.

3. The OSCMatch is defined as the following:
OSCMatch = [ tDQS2DQ(V, T) - tDQSOSC(V, T) - OSCoffset ]

Where tDQS2DQ(V,T) and tDQSOSC(V,T) are determined over the same voltage and tem-
perature conditions.
4. The runtime of the oscillator must be at least 200ns for determining tDQSOSC(V,T).
tDQS
Runtime
OSC(V,T) = [ ]
2 × Count
5. The input stimulus for tDQS2DQ will be consistent over voltage and temperature condi-
tions.
6. The OSCoffset is the average difference of the endpoints across voltage and temperature.
7. These parameters are defined per channel.
8. tDQS2DQ(V,T) delay will be the average of DQS-to-DQ delay over the runtime period.
OSC Count Readout Time

OSC Stop to its counting value readout timing is shown in following figures.
Figure 135: In Case of DQS Interval Oscillator is Stopped by MPC Command

T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6
CK_c
CK_t
CKE
CS
Command MPC :START MPC :STOP MRR-1

DES MROSCILLATOR
DQS Write-2 DES DES DES DES DQS OSCILLATOR DES DES DES DES MR18/MR19 CAS-2
t OSCO
Don’t Care
Note: 1. DQS interval timer run time setting :MR23 OP[7:0] = 00000000b.
CCM005-554574167-10729

Write Training
Figure 136: In Case of DQS Interval Oscillator is Stopped by DQS Interval Timer
T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6
CK_c
CK_t
CKE
CS
Command MPC :START MRR-1

DES MROSCILLATOR
DQS Write-2 DES DES DES DES DES DES DES DES DES DES MR18/MR19 CAS-2
See Note 2 t OSCO
Don’t Care
Notes: 1. DQS interval timer run time setting: MR23 OP[7:0] ≠ 00000000b.
2. Setting counts of MR23.
Table 131: DQS Interval Oscillator AC Timing
Parameter Symbol MIN/MAX Value Unit

Delay time from OSC stop to mode regis- tOSCO MIN MAX(40ns, ns
ter readout 8nCK)
Note: 1. START DQS OSCILLATOR command is prohibited until tOSCO(MIN) is satisfied.
CCM005-554574167-10729

Thermal Offset
Thermal Offset
Because of tight thermal coupling, hot spots on an SOC can induce thermal gradients
across the device. Because these hot spots may not be located near the thermal sensor,
the temperature compensated self refresh (TCSR) circuit may not generate enough re-
fresh cycles to guarantee memory retention. To address this shortcoming, the controller
can provide a thermal offset that the memory can use to adjust its TCSR circuit to en-
sure reliable operation.
This thermal offset is provided through MR4 OP[6:5] to either or both channels (dual-
channel devices). This temperature offset may modify refresh behaviour for the channel
to which the offset is provided. It will take a maximum of 200µs to have the change re-
flected in MR4 OP[2:0] for the channel to which the offset is provided. If the induced
thermal gradient from the device temperature sensor location to the hot spot location
of the controller is greater than 15°C, self refresh mode will not reliably maintain memo-
ry contents.
To accurately determine the temperature gradient between the memory thermal sensor
and the induced hot spot, the memory thermal sensor location must be provided to the
controller.
Temperature Sensor
The device has a temperature sensor that can be read from MR4. This sensor can be
used to determine the appropriate refresh rate, to determine whether AC timing de-rat-
ing is required at an elevated temperature range, and to monitor the operating tempera-
ture. Either the temperature sensor or the device T OPER can be used to determine if op-
erating temperature requirements are being met.
The device monitors device temperature and updates MR4 according to tTSI. Upon exit-
ing self refresh or power-down, the device temperature status bits shall be no older than
tTSI.
When using the temperature sensor, the actual device case temperature may be higher
than the T OPER specification that applies to standard or elevated temperature ranges.
For example, T CASE may be above 85°C when MR4[2:0] = b011. The device enables a 2°C
temperature margin between the point when the device updates the MR4 value and the
point when the controller reconfigures the system accordingly. When performing tight
thermal coupling of the device to external hot spots, the maximum device temperature
may be higher than indicated by MR4.
To ensure proper operation when using the temperature sensor, consider the following:
• TempGradient is the maximum temperature gradient experienced by the device at the
temperature of interest over a range of 2°C.
• ReadInterval is the time period between MR4 reads from the system.
• TempSensorInterval (tTSI) is the maximum delay between the internal updates of
MR4.
• SysRespDelay is the maximum time between a read of MR4 and a response from the
system.
In order to determine the required frequency of polling MR4, the system uses the Temp-
Gradient and the maximum response time of the system in the following equation:
TempGradient × (ReadInterval + tTSI + SysRespDelay) ≤ 2°C
CCM005-554574167-10729

ZQ Calibration
Table 132: Temperature Sensor
Parameter Symbol Max/Min Value Unit

System temperature gradient TempGradient MAX System Dependent °C/s
MR4 read interval ReadInterval MAX System Dependent ms
Temperature sensor interval tTSI MAX 32 ms
System response delay SysRespDelay MAX System Dependent ms
Device temperature margin TempMargin MAX 2 °C
For example, if TempGradient is 10°C/s and the SysRespDelay is 1ms:

(10°C/s) x (ReadInterval + 32ms + 1ms) ≤ 2°C
In this case, ReadInterval shall be no greater than 167ms.
Figure 137: Temperature Sensor Timing

Temperature
< [tTSI + ReadInterval + SysRespDelay]

Device
temperature
margin
ient
2° p Grad
Tem
MR4
trip level
tTSI
MR4 = 0x03 MR4 = 0x06 MR4 = 0x06 MR4 = 0x06 MR4 = 0x06 MR4 = 0x06
Time
Temperature
sensor
update
ReadInterval SysRespDelay
Host
MR4 read MRR MR4 = 0x06 MRR MR4 = 0x06
ZQ Calibration
The MPC command is used to initiate ZQ calibration, which calibrates the output driver
impedance and CA/DQ ODT impedance across process, temperature, and voltage. ZQ
calibration occurs in the background of device operation and is designed to eliminate
any need for coordination between channels (that is, it allows for channel independ-
ence). ZQ calibration is required each time that the PU-Cal value (MR3-OP[0]) is
changed. Additional ZQ CALIBRATION commands may be required as the voltage and
temperature change in the system environment. CA ODT values (MR11-OP[6:4]) and
DQ ODT values (MR11-OP[2:0]) may be changed without performing ZQ calibration, as
long as the PU-Cal value doesn’t change.
CCM005-554574167-10729

ZQ Calibration
There are two ZQ calibration modes initiated with the MPC command: ZQCAL START
and ZQCAL LATCH. ZQCAL START initiates the calibration procedure, and ZQCAL
LATCH captures the result and loads it into the drivers.
A ZQCAL START command may be issued anytime the device is not in a power-down
state. A ZQCAL LATCH command may be issued anytime outside of power-down after
tZQCAL has expired and all DQ bus operations have completed. The CA bus must main-
tain a deselect state during tZQLAT to allow CA ODT calibration settings to be updated.
The DQ calibration value will not be updated until ZQCAL LATCH is performed and
tZQLAT has been met. The following mode register fields that modify I/O parameters
cannot be changed following a ZQCAL START command and before tZQCAL has ex-
pired:
• PU-Cal (pull-up calibration V OH point)
• PDDS (pull-down drive strength and Rx termination)
• DQ ODT (DQ ODT value)
• CA ODT (CA ODT value)
ZQCAL Reset
The ZQCAL RESET command resets the output impedance calibration to a default ac-
curacy of ±30% across process, voltage, and temperature. This command is used to en-
sure output impedance accuracy to ±30% when ZQCAL START and ZQCAL LATCH com-
mands are not used.
The ZQCAL RESET command is executed by writing MR10-OP[0] = 1B.
Table 133: ZQ Calibration Parameters
Parameter Symbol Min/Max Value Unit

ZQCAL START to ZQCAL LATCH command interval tZQCAL MIN 1 µs
ZQCAL LATCH to next valid command interval tZQLAT MIN MAX(30ns, 8nCK) ns
ZQCAL RESET to next valid command interval tZQRESET MIN MAX(50ns, 3nCK) ns
Figure 138: ZQCAL Timing

T0 T1 T2 T3 T4 T5 T6 T7 T8 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6
CK_c
CK_t
tZQCAL tZQLAT
CA ZQCAL ZQCAL WR WR CAS CAS ZQCAL ZQCAL Valid Valid

START START LATCH LATCH
WL
MPC MPC
Command TRAIN/CAL
DES DES WRITE CAS2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES
TRAIN/CAL
DES DES DES DES PRECHARGE DES DES
tDQSS
DQS_t
DQS_c
tWPRE tWPST
tDQS2DQ
DQ[15:0]
Notes: 1. WRITE and PRECHARGE operations are shown for illustrative purposes. Any single or
multiple valid commands may be executed within the tZQCAL time and prior to latching
the results.
CCM005-554574167-10729

ZQ Calibration
2. Before the ZQCAL LATCH command can be executed, any prior commands that utilize
the DQ bus must have completed. WRITE commands with DQ termination must be given
enough time to turn off the DQ ODT before issuing the ZQCAL LATCH command. See
the ODT section for ODT timing.
Multichannel Considerations
The device includes a single ZQ pin and associated ZQ calibration circuitry. Calibration
values from this circuit will be used by both channels according to the following proto-
col:
• The ZQCAL START command can be issued to either or both channels.
• The ZQCAL START command can be issued when either or both channels are execut-
ing other commands, and other commands can be issued during tZQCAL.
• The ZQCAL START command can be issued to both channels simultaneously.
• The ZQCAL START command will begin the calibration unless a previously requested
ZQ calibration is in progress.
• If the ZQCAL START command is received while a ZQ calibration is in progress, the
command will be ignored and the in-progress calibration will not be interrupted.
• The ZQCAL LATCH command is required for each channel.
• The ZQCAL LATCH command can be issued to both channels simultaneously.
• The ZQCAL LATCH command will latch results of the most recent ZQCAL START
command provided tZQCAL has been met.
• ZQCAL LATCH commands that do not meet tZQCAL will latch the results of the most
recently completed ZQ calibration.
• The ZQRESET MRW commands will only reset the calibration values for the channel
issuing the command.
In compliance with complete channel independence, either channel may issue ZQCAL
START and ZQCAL LATCH commands as needed without regard to the state of the other
channel.
ZQ External Resistor, Tolerance, and Capacitive Loading

To use the ZQ CALIBRATION function, a 240 ohms, ±1% tolerance external resistor must
be connected between the ZQ pin and V DDQ.
If the system configuration shares the CA bus to form a x32 (or wider) channel, the ZQ
pin of each die’s x16 channel must use a separate ZQCAL resistor.
If the system configuration has more than one rank, and if the ZQ pins of both ranks are
attached to a single resistor, then the SDRAM controller must ensure that the ZQCAL's
don’t overlap.
The total capacitive loading on the ZQ pin must be limited to 25pF. For example, if a sys-
tem configuration shares a CA bus between n channels to form an n x16 wide bus, and
no means are available to control the ZQCAL separately for each channel (that is, sepa-
rate CS, CKE, or CK), then each x16 channel must have a separate ZQCAL resistor. For a
x32, two-rank system, each x16 channel must have its own ZQCAL resistor, but the
ZQCAL resistor can be shared between ranks on each x16 channel. In this configuration,
the CS signal can be used to ensure that the ZQCAL commands for Rank[0] and Rank[1]
don’t overlap.
CCM005-554574167-10729

Frequency Set Points

Frequency set points enable the CA bus to be switched between two differing operating
frequencies with changes in voltage swings and termination values, without ever being
in an untrained state, which could result in a loss of communication to the device. This
is accomplished by duplicating all CA bus mode register parameters, as well as other
mode register parameters commonly changed with operating frequency.
These duplicated registers form two sets that use the same mode register addresses,
with read/write access controlled by MR bit FSP-WR (frequency set point write/read)
and the operating point controlled by MR bit FSP-OP (FREQUENCY SET POINT opera-
tion). Changing the FSP-WR bit enables MR parameters to be changed for an alternate
frequency set point without affecting the current operation.
Once all necessary parameters have been written to the alternate set point, changing
the FSP-OP bit will switch operation to use all of the new parameters simultaneously
(within tFC), eliminating the possibility of a loss of communication that could be
caused by a partial configuration change.
Parameters that have two physical registers controlled by FSP-WR and FSP-OP include
those in the following table.
Table 134: Mode Register Function With Two Physical Registers
MR Number Operand Function Notes

MR1 OP[2] WR-PRE (Write preamble length)
OP[3] RD-PRE (Read preamble type)
OP[6:4] nWR (Write-recovery for AUTO PRECHARGE command)
OP[7] RD-PST (Read postamble length)
MR2 OP[2:0] RL (READ latency)
OP[5:3] WL (WRITE latency)
OP[6] WLS (WRITE latency set)
MR3 OP[0] PU-CAL (Pull-up calibration point) 1
OP[1] WR-PST(Write postamble length)
OP[5:3] PDDS (Pull-down drive strength)
OP[6] DBI-RD (DBI-read enable)
OP[7] DBI-WR (DBI-write enable)
MR11 OP[2:0] DQ ODT (DQ bus receiver on-die termination)
OP[6:4] CA ODT (CA bus receiver on-die termination)
MR12 OP[5:0] VREF(CA) (VREF(CA) setting)
OP[6] VRCA (VREF(CA) range)
MR14 OP[5:0] VREF(DQ) (VREF(DQ) setting)
OP[6] VRDQ (VREF(DQ) range)
CCM005-554574167-10729

Table 134: Mode Register Function With Two Physical Registers (Continued)
MR Number Operand Function Notes

MR22 OP[2:0] SOC ODT (Controller ODT value for VOH calibration)
OP[3] ODTE-CK (CK ODT enabled for non-terminating rank)
OP[4] ODTE-CS (CS ODT enable for non-terminating rank)
OP[5] ODTD-CA (CA ODT termination disable)
Note: 1. For dual-channel devices, PU-CAL setting is required as the same value for both Ch.A
and Ch.B before issuing ZQCAL START command. See Mode Register Definition section
for more details.
The table below shows how the two mode registers for each of the parameters in the
previous table can be modified by setting the appropriate FSP-WR value and how device
operation can be switched between operating points by setting the appropriate FSP-OP
value. The FSP-WR and FSP-OP functions operate completely independently.
Table 135: Relation Between MR Setting and DRAM Operation
MR# and Op-

Function erand Data Operation Notes
FSP-WR MR13 OP[6] 0 (default) Data write to mode register N for FSP-OP[0] by MRW command. 1
Data read from mode register N for FSP-OP[0] by MRR command.
1 Data write to mode register N for FSP-OP[1] by MRW command.
Data read from mode register N for FSP-OP[1] by MRR command.
FSP-OP MR13 OP[7] 0 (default) DRAM operates with mode register N for FSP-OP[0] setting. 2
1 DRAM operates with mode register N for FSP-OP[1] setting.
Notes: 1. FSP-WR stands for frequency set point write/read.

2. FSP-OP stands for frequency set point operating point.
Frequency Set Point Update Timing

The frequency set point update timing is shown below. When changing the frequency
set point via MR13 OP[7], the V RCG setting: MR13 OP[3] have to be changed into V REF
fast response (high current) mode at the same time. After frequency change time (tFC) is
satisfied. V RCG can be changed into normal operation mode via MR13 OP[3].
CCM005-554574167-10729

Figure 139: Frequency Set Point Switching Timing

T0 T1 T2 T3 T4 T5 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6
CK_c
CK_t
tCKFSPE Note 1 tCKFSPX tVRCG_DISABLE
Frequency
change
CKE
CS
CA DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES DES MRW-1 MRW-1 MRW-2 MRW-2 DES
FSP changes from 0 to 1 VRCG changes

Command DES VRCG changes from normal to HIGH current DES DES DES DES DES
from HIGH current to normal
DES
tFC_short/middle/long
Applicable
Mode register for FSP-OP0 Switching mode register Mode register for FSP-OP1
mode register
Don’t Care
Note: 1. For frequency change during frequency set point switching, refer to Input Clock Stop
and Frequency Change section.
Table 136: Frequency Set Point AC Timing
Min/ Data Rate

Parameter Symbol Max 1600 3200 3733 4267 Unit Notes
Frequency set point switching time tFC_short MIN 200 ns 1
tFC_middle MIN 200 ns
tFC_long MIN 250 ns
Valid clock requirement after enter- tCKFSPE MIN MAX(7.5ns, 4nCK) –
ing FSP change
Valid clock requirement before first tCKFSPX MIN MAX(7.5ns, 4nCK) –
valid command after FSP change
Note: 1. Frequency set point switching time depends on value of VREF(CA) setting: MR12 OP[5:0]
and VREF(CA) range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in table below.
Additionally change of frequency set point may affect VREF(DQ) setting. Settling time of
VREF(DQ) level is the same as VREF(CA) level.
Table 137: tFC Value Mapping
Applica- Step Size Range

tion From FSP-OP0 To FSP-OP1 From FSP -OP0 To FSP-OP1
tFC_short Base A single step size incre- Base No change
ment/decrement
tFC_middle Base Two or more step size in- Base No change
crement/decrement
CCM005-554574167-10729

Table 137: tFC Value Mapping (Continued)
Applica- Step Size Range

tion From FSP-OP0 To FSP-OP1 From FSP -OP0 To FSP-OP1
tFC_long – – Base Change
Note: 1. As well as change from FSP-OP1 to FSP-OP0.
Table 138: tFC Value Mapping: Example
FSP-OP: VREF(CA) Setting: VREF(CA) Range:

Case From/To MR13 OP[7] MR12: OP[5:0] MR12 OP[6] Application Notes
1 From 0 001100 0 tFC_short 1
To 1 001101 0
2 From 0 001100 0 tFC_middle 2
To 1 001110 0
3 From 0 Don't Care 0 tFC_long 3
To 1 Don't Care 1
Notes: 1. A single step size increment/decrement for VREF(CA) setting value.

2. Two or more step size increment/decrement for VREF(CA) setting value.
3. VREF(CA) range is changed. In this case, changing VREF(CA) setting doesn’t affect tFC value.
The LPDDR4 SDRAM defaults to FSP-OP[0] at power-up. Both set points default to set-
tings needed to operate in un-terminated, low-frequency environments. To enable the
device to operate at higher frequencies, Command bus training mode should be utiliz-
ed to train the alternate frequency set point. See Command Bus Training section for
more details on this training mode.
CCM005-554574167-10729

Figure 140: Training for Two Frequency Set Points
Power-up/ Prepare for CA bus CA bus training,

Initialization training of FSP1 for FSP-OP1
FSP-OP = 0 high frequency FSP-WR = 1
FSP-WR = 0 FSP-OP = 0 CKE High to Low Freq. = High
Freq. = Boot FSP-WR = 1
Freq. = Boot
CKE LOW to HIGH
Exit CA bus Switch to high- Prepare for CA bus

training speed mode training of FSP0 for
FSP-OP = 0 FSP-OP = 1 medium frequency
FSP-WR = 1 FSP-WR = 1 FSP-OP = 1
Freq. = Boot Freq. = High FSP-WR = 0
Freq. = High
CKE HIGH to LOW
CA bus training, Exit CA bus

FSP-OP0 training
FSP-WR = 0 FSP-OP = 1 Operate at
Freq. = Medium FSP-WR = 0 high speed
CKE LOW to HIGH
Freq. = High
Once both of the frequency set points have been trained, switching between points can
be performed with a single MRW followed by waiting for time tFC.
Figure 141: Example of Switching Between Two Trained Frequency Set Points
State n-1:
FSP-OP = 1
Operate at MRW command Operate at
high speed State n: FSP-OP = 0 tFC medium speed
State n-1:
FSP-OP = 0
MRW command Operate at
State n: FSP-OP = 1 tFC high speed
Switching to a third (or more) set point can be accomplished if the memory controller
has stored the previously-trained values (in particular the V REF(CA) calibration value)
and rewrites these to the alternate set point before switching FSP-OP.
CCM005-554574167-10729

Pull-Up and Pull-Down Characteristics and Calibration
Figure 142: Example of Switching to a Third Trained Frequency Set Point
State n-1: MRW command

FSP-WR = 1 {VREF(CA)
Operate at MRW command
high speed tFC CA ODT, DQ ODT,
State n: FSP-WR = 0 RL, WL, VREF(DQ),
ODTD-CA...}
State n-1:
FSP-OP = 1
MRW command Operate at
State n: FSP-OP = 0 tFC third speed
Pull-Up and Pull-Down Characteristics and Calibration
Table 139: Pull-Down Driver Characteristics – ZQ Calibration
RONPD,nom Register Min Nom Max Unit

40 ohms RON40PD 0.90 1.0 1.10 RZQ/6
48 ohms RON48PD 0.90 1.0 1.10 RZQ/5
60 ohms RON60PD 0.90 1.0 1.10 RZQ/4
80 ohms RON80PD 0.90 1.0 1.10 RZQ/3
120 ohms RON120PD 0.90 1.0 1.10 RZQ/2
240 ohms RON240PD 0.90 1.0 1.10 RZQ/1
Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%.
Table 140: Pull-Up Characteristics – ZQ Calibration
VOHPU,nom VOH,nom Min Nom Max Unit

VDDQ × 0.5 300 0.90 1.0 1.10 VOH,nom
VDDQ × 0.6 360 0.90 1.0 1.10 VOH,nom
Notes: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%.
2. VOH,nom (mV) values are based on a nominal VDDQ = 0.6V.
Table 141: Valid Calibration Points
ODT Value
VOHPU 240 120 80 60 48 40
VDDQ × 0.5 Valid Valid Valid Valid Valid Valid
CCM005-554574167-10729

On-Die Termination for the Command/Address Bus
Table 141: Valid Calibration Points (Continued)
ODT Value
VOHPU 240 120 80 60 48 40
VDDQ × 0.6 DNU Valid DNU Valid DNU DNU
Notes: 1. After the output is calibrated for a given VOH,nom calibration point, the ODT value may
be changed without recalibration.
2. If the VOH,nom calibration point is changed, then recalibration is required.
3. DNU = Do not use.

The on-die termination (ODT) feature allows the device to turn on/off termination re-
sistance for CK_t, CK_c, CS, and CA[5:0] signals without the ODT control pin. The ODT
feature is designed to improve signal integrity of the memory channel by allowing the
DRAM controller to turn on and off termination resistance for any target DRAM devices
via the mode register setting.
A simple functional representation of the DRAM ODT feature is shown below.
Figure 143: ODT for CA
RTT = VOUT
|IOUT|
VDD2
To other
circuitry ODT
like RCV, ...
CA
IOUT
RTT VOUT
VSS
ODT Mode Register and ODT State Table

ODT termination values are set and enabled via MR11. The CA bus (CK_t, CK_c, CS,
CA[5:0]) ODT resistance values are set by MR11 OP[6:4]. The default state for the CA is
ODT disabled.
ODT is applied on the CA bus to the CK_t, CK_c, CS, and CA signals. Generally only one
termination load will be present even if multiple devices are sharing the command sig-
nals. In contrast to LPDDR4 where the ODT_CA input is used in combination with
mode registers, LPDDR4X uses mode registers exclusively to enable CA termination. Be-
CCM005-554574167-10729

fore enabling CA termination via MR11, all ranks should have appropriate MR22 termi-
nation settings programmed. In a multi rank system, the terminating rank should be
trained first, followed by the non-terminating rank(s).
Table 142: Command Bus ODT State
CA ODT ODTD-CA ODTE-CK ODTE-CS ODT State ODT State ODT State
MR11[6:4] MR22 OP[5] MR22 OP[3] MR22 OP[4] for CA for CK for CS
Disabled1 Valid2 Valid2 Valid2 Off Off Off
Valid 2 0 0 0 On On On
Valid 2 0 0 1 On On Off
Valid 2 0 1 0 On Off On
Valid 2 0 1 1 On Off Off
Valid 2 1 0 0 Off On On
Valid 2 1 0 1 Off On Off
Valid 2 1 1 0 Off Off On
Valid 2 1 1 1 Off Off Off
Notes: 1. Default value

2. Valid = 0 or 1
ODT Mode Register and ODT Characteristics
Table 143: ODT DC Electrical Characteristics for Command/Address Bus

RZQ = 240Ω ±1% over entire operating range after calibration
MR11 OP[6:4] RTT VOUT Min Nom Max Unit Notes
001b 240Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
010b 120Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
011b 80Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/3 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
100b 60Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
101b 48Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
CCM005-554574167-10729

DQ On-Die Termination
Table 143: ODT DC Electrical Characteristics for Command/Address Bus (Continued)

110b 40Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/6 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
Mismatch CA-to-CA within clock 0.50 × VDDQ – – 2 % 1, 2, 3
group
Notes: 1. The tolerance limits are specified after calibration with stable temperature and voltage.
To understand the behavior of the tolerance limits when voltage or temperature
changes after calibration, see the section on voltage and temperature sensitivity.
2. Pull-down ODT resistors are recommended to be calibrated at 0.50 × VDDQ. Other cali-
bration points may be used to achieve the linearity specification shown above; for ex-
ample, calibration at 0.75 × VDDQ and 0.20 × VDDQ.
3. CA to CA mismatch within clock group variation for a given component including CK_t,
CK_c ,and CS (characterized).
CA-to-CA mismatch = RODT (MAX) - RODT (MIN)

RODT (AVG)
ODT for CA Update Time
Figure 144: ODT for CA Setting Update Timing in 4-Clock Cycle Command
T0 T1 T2 T3 T4 T5 Ta Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8
CK_c
CK_t
CKE
CS_n
Command DES MRW1 MRW1 MRW2 MRW2 DES DES DES DES DES Valid 1 Valid 1 Valid 1 Valid 1 Valid
CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid
CA ODT Old setting value Updating setting New setting value
tODTUP
Don’t Care
On-die termination (ODT) is a feature that allows the device to turn on/off termination
resistance for each DQ, DQS, and DMI signal without the ODT control pin. The ODT
CCM005-554574167-10729

during WRITE or MASK WRITE operation.
The ODT feature is off and cannot be supported in power-down and self refresh modes.
The switch is enabled by the internal ODT control logic, which uses the WRITE-1 or
MASK WRITE-1 command and other mode register control information. The value of
RTT is determined by the MR bits.
RTT = VOUT
|IOUT|
Figure 145: Functional Representation of DQ ODT
VDDQ
To other
circuitry ODT
like RCV, ...
DQ
IOUT
RTT VOUT
VSSQ
Table 144: ODT DC Electrical Characteristics for DQ Bus

001b 240Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
010b 120Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
011b 80Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/3 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
100b 60Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
101b 48Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
CCM005-554574167-10729

Table 144: ODT DC Electrical Characteristics for DQ Bus (Continued)

110b 40Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/6 1, 2
VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3
Mismatch DQ-to-DQ within 0.50 × VDDQ – – 2 % 1, 2, 3
clock group
Notes: 1. The ODT tolerance limits are specified after calibration with stable temperature and
voltage. To understand the behavior of the tolerance limits when voltage or tempera-
ture changes after calibration, see the following section on voltage and temperature
sensitivity.
bration points may be used to achieve the linearity specification shown above, for ex-
ample, calibration at 0.75 × VDDQ and 0.20 × VDDQ.
3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (char-
acterized).
DQ-to-DQ mismatch= RODT (MAX) - RODT (MIN)

RODT (AVG)
Output Driver and Termination Register Temperature and Voltage Sensitivity

When temperature and/or voltage change after calibration, the tolerance limits are wi-
den according to the tables below.
Table 145: Output Driver and Termination Register Sensitivity Definition
Definition
Resistor Point Min Max Unit Notes
RONPD 0.50 × VDDQ 90 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) % 1, 2
VOHPU 0.50 × VDDQ 90 - (dVOHdT × |ΔT|) - (dVOHdV × |ΔV|) 110 + (dVOHdT × |ΔT|) + (dVOHdV × |ΔV|) 1, 2
RTT(I/O) 0.50 × VDDQ 90 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) 1, 2, 3
RTT(IN) 0.50 × VDD2 90 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) 1, 2, 4
Notes: 1. ΔT = T - T(@calibration), ΔV = V - V(@calibration)

2. dRONdT, dRONdV, dVOHdT, dVOHdV, dRTTdV, and dRTTdT are not subject to production test
but are verified by design and characterization.
3. This parameter applies to input/output pin such as DQS, DQ, and DMI.
4. This parameter applies to input pin such as CK, CA, and CS.
5. Refer to Pull-Up/Pull-Down Driver Characteristics for VOHPU.
Table 146: Output Driver and Termination Register Temperature and Voltage Sensitivity
Symbol Parameter Min Max Unit

dRONdT RON temperature sensitivity 0 0.75 %/˚C
dRONdV RON voltage sensitivity 0 0.20 %/mV
CCM005-554574167-10729

Table 146: Output Driver and Termination Register Temperature and Voltage Sensitivity (Contin-
ued)

dVOHdT VOH temperature sensitivity 0 0.75 %/˚C
dVOHdV VOH voltage sensitivity 0 0.35 %/mV
dRTTdT RTT temperature sensitivity 0 0.75 %/˚C
dRTTdV RTT voltage sensitivity 0 0.20 %/mV
ODT Mode Register

The ODT mode is enabled if MR11 OP[2:0] are non-zero. In this case, the value of RTT is
determined by the settings of those bits. The ODT mode is disabled if MR11 OP[2:0] = 0.
Asynchronous ODT
When ODT mode is enabled in MR11 OP[2:0], DRAM ODT is always High-Z. The DRAM
ODT feature is automatically turned ON asynchronously after a WRITE-1, MASK
WRITE-1, or MPC[WRITE-FIFO] command. After the burst write is complete, the DRAM
ODT turns OFF asynchronously. The DQ bus ODT control is automatic and will turn the
ODT resistance on/off if DQ ODT is enabled in the mode register.
The following timing parameters apply when the DQ bus ODT is enabled:
• ODTLon, tODTon(MIN), tODTon(MAX)
• ODTLoff, tODToff(MIN), tODToff(MAX)
ODTLON is a synchronous parameter and is the latency from a CAS-2 command to the
tODTon reference. ODTL
ON latency is a fixed latency value for each speed bin. Each
speed bin has a different ODTLON latency.
Minimum RTT turn-on time ( tODTon(MIN)) is the point in time when the device termi-
nation circuit leaves High-Z and ODT resistance begins to turn on.
Maximum RTT turn on time ( tODTon(MAX)) is the point in time when the ODT resist-
ance is fully on.
tODTon(MIN) and tODTon(MAX) are measured after ODTL
ON latency is satisfied from
CAS-2 command.
ODTLOFF is a synchronous parameter and it is the latency from CAS-2 command to
tODToff reference. ODTL
OFF latency is a fixed latency value for each speed bin. Each
speed bin has a different ODTLOFF latency.
Minimum RTT turn-off time ( tODToff(MIN)) is the point in time when the device termi-
nation circuit starts to turn off the ODT resistance.
Maximum ODT turn off time ( tODToff(MAX)) is the point in time when the on-die ter-
mination has reached High-Z.
tODToff(MIN)
and tODToff(MAX) are measured after ODTLOFF latency is satisfied from
CAS-2 command.
CCM005-554574167-10729

Table 147: ODTLON and ODTLOFF Latency Values
ODTLON Latency1
Lower Upper
tWPRE = 2tCK ODTLOFF Latency2 Frequency Limit Frequency Limit
WL Set A (nCK) WL Set B (nCK) WL Set A (nCK) WL Set B (nCK) (>) (MHz) (≤) (MHz)
N/A N/A N/A N/A 10 266
N/A N/A N/A N/A 266 533
N/A 6 N/A 22 533 800
4 12 20 28 800 1066
4 14 22 32 1066 1333
6 18 24 36 1333 1600
6 20 26 40 1600 1866
8 24 28 44 1866 2133
Notes: 1. ODTLON is referenced from CAS-2 command.

2. ODTLOFF as shown in table assumes BL = 16. For BL32, 8 tCK should be added.
Figure 146: Asynchronous ODTon/ODToff Timing

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 Ta13 Ta14 Ta15 Ta16 Ta17 Ta18 Ta19 Ta20 Ta21
CK_c
CK_t
CS
BA0,
CA BL CAn CAn
CA, AP
Command WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES
t
WL DQSS(MIN)
t t
WPRE WPST
DQS_c
DQS_t
t
DQS2DQ
DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
t
DQSS(MAX)
t t
WPRE WPST
DQS_c
DQS_t
t
DQS2DQ
DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
ODTLon t
ODTon(MAX) t
ODToff(MAX)
t t
ODTon(MIN) ODToff(MIN)
DRAM RTT ODT High-Z Transition ODTL On Transition ODT High-Z
ODTLoff
Don’t Care

CCM005-554574167-10729

Target Row Refresh Mode
these times.
DQ ODT During Power-Down and Self Refresh Modes

DQ bus ODT will be disabled in power-down mode. In self refresh mode, the ODT will
be turned off when CKE is LOW but will be enabled if CKE is HIGH and DQ ODT is ena-
bled in the mode register.
ODT During Write Leveling Mode

If ODT is enabled in MR11 OP[2:0] in write leveling mode, the device always provides
the termination on DQS signals. DQ termination is always off in write leveling mode.
Table 148: Termination State in Write Leveling Mode
DQ[15:0]/DMI[1:0]
ODT State in MR11 OP[2:0] DQS Termination Termination
Disabled Off Off
Enabled On Off

The device limits the number of times that a given row can be accessed within a refresh
period (tREFW × 2) prior to requiring adjacent rows to be refreshed. The maximum acti-
vate count (MAC) is the maximum number of activates that a single row can sustain
within a refresh period before the adjacent rows need to be refreshed. The row receiving
the excessive actives is the target row (TRn), the adjacent rows to be refreshed are the
victim rows. When the MAC limit is reached on TRn, either the device receives all (R × 2)
REFRESH commands before another row activate is issued, or the device should be
placed into targeted row refresh (TRR) mode. The TRR mode will refresh the rows adja-
cent to the TRn that encountered tMAC limit.
If the device supports unlimited MAC value: MR24 OP[2:0] = 000 and MR24 OP[3] = 1,
TARGET ROW REFRESH operation is not required. Even though the device allows to set
MR24 OP[7] = 1: TRR mode enable, in this case the device behavior is vendor specific.
For example, a certain device may ignore MRW command for entering/exiting TRR
mode or a certain device may support commands related TRR mode. See vendor device
data sheets for details about TRR mode definition at supporting unlimited MAC value
case.
There could be a maximum of two target rows to a victim row in a bank. The cumulative
value of the activates from the two target rows on a victim row in a bank should not ex-
ceed MAC value.
MR24 fields are required to support the new TRR settings. Setting MR24 OP[7] = 1 ena-
bles TRR mode and setting MR24 OP[7] = 0 disables TRR mode. MR24 OP[6:4] defines
which bank (BAn) the target row is located in (refer to MR24 table for details).
The TRR mode must be disabled during initialization as well as any other device cali-
bration modes. The TRR mode is entered from a DRAM idle state, once TRR mode has
been entered, no other mode register commands are allowed until TRR mode is com-
CCM005-554574167-10729

pleted; however, setting MR24 OP[7] = 0 to interrupt and reissue the TRR mode is al-
lowed.
When enabled, TRR mode is self-clearing. The mode will be disabled automatically af-
ter the completion of defined TRR flow (after the third BAn precharge has completed
plus tMRD). Optionally, the TRR mode can also be exited via another MRS command at
the completion of TRR by setting MR24 OP[7] = 0. If the TRR is exited via another MRS
command, the value written to MR24 OP[6:4] are "Don’t Care."
TRR Mode Operation

1. The timing diagram depicts TRR mode. The following steps must be performed
when TRR mode is enabled. This mode requires all three ACT (ACT1, ACT2, and
ACT3) and three corresponding PRE commands (PRE1, PRE2, and PRE3) to com-
plete TRR mode. PRECHARGE All (PREA) commands issued while the device is in
TRR mode will also perform precharge to BAn and counts towards PREn com-
mand.
2. Prior to issuing the MRW command to enter TRR mode, the device should be in
the idle state. MRW command must be issued with MR24 OP[7] = 1 and MR24
OP[6:4] defining the bank in which the targeted row is located. All other MR24 bits
should remain unchanged.
3. No activity is to occur with the device until tMRD has been satisfied. When tMRD
has been satisfied, the only commands allowed BAn, until TRR mode has comple-
ted, are ACT and PRE.
4. The first ACT to the BAn with the TRn address can now be applied; no other com-
mand is allowed at this point. All other banks must remain inactive from when the
first BAn ACT command is issued until [(1.5 x tRAS) + tRP] is satisfied.
5. After the first ACT to the BAn with the TRn address is issued, PRE to BAn is to be
issued (1.5 × tRAS) later; and then followed tRP later by the second ACT to the BAn
with the TRn address.
6. After the second ACT to the BAn with the TRn address is issued, PRE to BAn is to
be issued tRAS later and then followed tRP later by the third ACT to the BAn with
the TRn address.
7. After the third ACT to the BAn with the TRn address is issued, PRE to BAn would
be issued tRAS later. TRR mode is completed once tRP plus tMRD is satisfied.
8. TRR mode must be completed as specified to guarantee that adjacent rows are re-
freshed. Anytime the TRR mode is interrupted and not completed, the interrupted
TRR mode must be cleared and then subsequently performed again. To clear an
interrupted TRR mode, MR24 change is required with setting MR24 OP[7] = 0,
MR24 OP[6:4] are "Don’t Care," followed by three PRE to BAn, with tRP time in be-
tween each PRE command. The complete TRR sequence (steps 2–7) must be then
reissued and completed to guarantee that the adjacent rows are refreshed.
9. A REFRESH command to the device, or entering self refresh mode, is not allowed
while the device is in TRR mode.
CCM005-554574167-10729

Post-Package Repair
Figure 147: Target Row Refresh Mode

T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Td0 Td1 Td2 Td3 Te0 Te1 Tf0 Tf1 Tf2 Tf3 Tg0 Tg1 Tg2 Tg3 Th0 Th1 Th2 Th3 Tk0 Tk1 Tk2 Tm0 Tm1 Tm2 Tm3 Tm4 Tm5
CK_c
CK_t
CKE
CS
ACT1 PRE1 ACT2 PRE2 ACT3 PRE3
Command MRW-1 MRW-2 DES ACT-1 ACT-2 DES PRE DES ACT-1 ACT-2 DES CMD-1 CMD-2 DES PRE DES CMD-1 CMD-2 DES ACT-1 ACT-2 DES CMD-1 CMD-2 DES PRE DES DES CMD-1 CMD-2 DES
TRR entry 1st ACT 1st PRE 2nd ACT 2nd PRE 3rd ACT 3rd PRE
Bank Non Non Non Any
N/A N/A N/A N/A N/A BAn N/A N/A N/A BAn N/A BAn N/A N/A V V V N/A BAn V V V N/A BAn N/A N/A V V V N/A BAn V V V
Address BAn BAn BAn BAn
Address OP MA OP OP TRn TRn TRn TRn N/A N/A TRn TRn TRn TRn V V V V N/A N/A V V V V TRn TRn TRn TRn V V V V N/A N/A V V V V
tMRD 1.5 × tRAS tRP tRAS t RP tRAS tRP + tMRD
Non BAn No activity allowed Activity

Non BAn in idle No activity allowed in other banks (Banks closed) Activity allowed
(may have bank(s) open) allowed
BAn 9 Activity
BAn in idle
No activity allowed (Banks closed) BAn TRR operation allowed allowed
Don’t Care
Notes: 1. TRn is the targeted row.

2. Bank BAn represents the bank in which the targeted row is located.
3. TRR mode self-clears after tMRD + tRP measured from the third BAn precharge PRE3 at
clock edge Th4.
4. TRR mode or any other activity can be re-engaged after tRP + tMRD from the third BAn
precharge PRE3. PRE_ALL also counts if it is issued instead of PREn. TRR mode is cleared
by the device after PRE3 to the BAn bank.
5. ACTIVATE commands to BAn during TRR mode do not provide refresh support (the re-
fresh counter is unaffected).
6. The device must restore the degraded row(s) caused by excessive activation of the targe-
ted row (TRn) necessary to meet refresh requirements.
7. A new TRR mode must wait tMRD + tRP time after the third precharge.
8. BAn may not be used with any other command.
9. ACT and PRE are the only allowed commands to BAn during TRR mode.
10. REFRESH commands are not allowed during TRR mode.
11. All timings are to be met by DRAM during TRR mode, such as tFAW. Issuing ACT1, ACT2,
and ACT3 counts towards tFAW budget.
Post-Package Repair
The device has fail row address repair as an optional post-package repair (PPR) feature
and it is readable through MR25 OP[7:0].
PPR provides simple and easy repair method in the system and fail row address can be
repaired by the electrical programming of Electrical-fuse scheme. The device can cor-
rect one row per bank with PPR.
Electrical-fuse cannot be switched back to un-fused states once it is programmed. The
controller should prevent unintended PPR mode entry and repair.
Failed Row Address Repair

1. Before entering PPR mode, all banks must be precharged.
2. Enable PPR using MR4 OP[4] = 1 and wait tMRD.
3. Issue ACT command with fail row address.
4. Wait tPGM to allow the device repair target row address internally then issue PRE-
CHARGE
CCM005-554574167-10729

Post-Package Repair
5. Wait tPGM_EXIT after PRECHARGE, which allows the device to recognize repaired
row address RAn.
6. Exit PPR mode with setting MR4 OP[4] = 0.
7. The device is ready for any valid command after tPGMPST.
8. In more than one fail address repair case, repeat step 2 to 7.
Once PPR mode is exited, to confirm whether the target row has correctly repaired, the
host can verify the repair by writing data into the target row and reading it back after
PPR exit with MR4 OP[4] = 0 and tPGMPST.
The following timing diagram shows PPR operation.
Figure 148: Post-Package Repair Timing

T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5
CK_c
CK_t
CKE
CS
Any Any
Command DES MR WRITE-1 MR WRITE-2 DES ACT-1 ACT-2 DES DES PRE DES MR WRITE-1 MR WRITE-2 DES command command
BA N/A N/A N/A N/A Valid BA Valid Valid Valid Valid N/A N/A N/A N/A Valid Valid Valid Valid
Address OP MA OP OP RAn RAn RAn RAn Valid Valid OP MA OP OP Valid Valid Valid Valid
PPR Normal mode Move to PPR mode Move to PPR mode Normal
(All banks must be idle) PPR repair PPR recognition mode
staus
t MRD t PGM t PGM_Exit t PGMPST
Don’t Care
Notes: 1. During tPGM, any other commands (including refresh) are not allowed on each die.
2. With one PPR command, only one row can be repaired at one time per die.
3. When PPR procedure completes, reset procedure is required before normal operation.
4. During PPR, memory contents are not refreshed and may be lost.
Table 149: Post-Package Repair Timing Parameters
Parameter Symbol Min Max Units

PPR programming time tPGM 1000 – ms
PPR exit time tPGM_EXIT 15 – ns
New address setting time tPGMPST 50 – µs
CCM005-554574167-10729

Read Preamble Training
Read Preamble Training

Read preamble training is supported through the MPC function.
This mode can be used to train or read level the DQS receivers. After read preamble
training is enabled by MR13 OP[1] = 1, the device will drive DQS_t LOW and DQS_c
HIGH within tSDO and remain at these levels until an MPC[READ DQ CALIBRATION]
command is issued.
During read preamble training, the DQS preamble provided during normal operation
will not be driven by the device. After the MPC[READ DQ CALIBRATION] command is
issued, the device will drive DQS_t/DQS_c and DQ like a normal READ burst after RL
and tDQSCK. Prior to the MPC[READ DQ CALIBRATION] command, the device may or
may not drive DQ[15:0] in this mode.
While in read preamble training mode, only READ DQ CALIBRATION commands may
be issued.
• Issue an MPC[READ DQ CALIBRATION] command followed immediately by a CAS-2
command.
• Each time an MPC[READ DQ CALIBRATION] command followed by a CAS-2 is re-
ceived by the device, a 16-bit data burst will, after the currently set RL, drive the eight
bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O
pins.
• The data pattern will be inverted for I/O pins with a 1 programmed in the corre-
sponding invert mask mode register bit.
• Note that the pattern is driven on the DMI pins, but no DATA BUS INVERSION func-
tion is enabled, even if read DBI is enabled in the DRAM mode register.
• This command can be issued every tCCD seamlessly.
• The operands received with the CAS-2 command must be driven LOW.
Read preamble training is exited within tSDO after setting MR13 OP[1] = 0.
Figure 149: Read Preamble Training

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1
CK_c
CK_t
CS
MPC MPC
Command MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES [RD DQ CAL] [RD DQ CAL] CAS-2 CAS-2 DES DES DES DES DES DES DES DES DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES
tSDO RL tDQSCK tSDO
Read preamble training mode = Read preamble training mode =

Enable: MR13[OP1] = 1 Enable: MR13[OP1] = 0
DQS_c
DQS_t
t
DQSQ
DQ DOUT DOUT DOUT DOUT DOUT DOUT
DMI DQ (High-Z or Driven ) n0 n1 n12 n13 n14 n15 DQ (High-Z or Driven )
Don’t Care
Note: 1. Read DQ calibration supports only BL16 operation.
CCM005-554574167-10729

Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed in the table below may cause permanent damage to
the device. This is a stress rating only, and functional operation of the device at these
conditions, or any other conditions outside those indicated in the operational sections
of this document, is not implied. Exposure to absolute maximum rating conditions for
extended periods may adversely affect reliability.
Table 150: Absolute Maximum DC Ratings
Parameter Symbol Min Max Unit Notes

VDD1 supply voltage relative to VSS VDD1 –0.4 2.1 V 1
VDD2 supply voltage relative to VSS VDD2 –0.4 1.5 V 1
VDDQ supply voltage relative to VSS VDDQ –0.4 1.5 V 1
Voltage on any ball relative to VSS VIN, VOUT –0.4 1.5 V
Storage temperature TSTG –55 125 ˚C 2
Notes: 1. For information about relationships between power supplies, see the Voltage Ramp and
Device Initialization section.
2. Storage temperature is the case surface temperature on the center/top side of the de-
vice. For measurement conditions, refer to the JESD51-2 standard.
AC and DC Operating Conditions

Operation or timing that is not specified is illegal. To ensure proper operation, the de-
vice must be initialized properly.
Table 151: Recommended DC Operating Conditions
Symbol Min Typ Max DRAM Unit Notes

VDD1 1.7 1.8 1.95 Core 1 power V 1, 2
VDD2 1.06 1.1 1.17 Core 2 power/Input buffer power V 1, 2, 3
VDDQ 0.57 0.60 0.65 I/O buffer power V 2, 3
Notes: 1. VDD1 uses significantly less power than VDD2.

2. The voltage range is for DC voltage only. DC voltage is the voltage supplied at the
DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball.
3. The voltage noise tolerance from DC to 20 MHz exceeding a peak-to-peak tolerance of
45mV at the DRAM ball is not included in the TdIVW.
Table 152: Input Leakage Current
Parameter/Condition Symbol Min Max Unit Notes

Input leakage current IL –4 4 μA 1, 2
Notes: 1. For CK_t, CK_c, CKE, CS, CA, ODT_CA and RESET_n. Any input 0V ≤ VIN ≤ VDD2. All other
pins not under test = 0V.
CCM005-554574167-10729

AC and DC Operating Conditions
2. CA ODT is disabled for CK_t, CK_c, CS, and CA.
Table 153: Input/Output Leakage Current
Parameter/Condition Symbol Min Max Unit Notes

Input/Output leakage current IOZ –5 5 μA 1, 2
Notes: 1. For DQ, DQS_t, DQS_c and DMI. Any I/O 0V ≤ VOUT ≤ VDDQ.
2. I/Os status are disabled: High impedance and ODT off.
Table 154: Operating Temperature Range
Parameter/Condition Symbol Min Max Unit

Standard TOPER Note 4 85 ˚C
Elevated 85 95 ˚C
Automotive 95 105 ˚C
Ultra 105 125 ˚C
Notes: 1. Operating temperature is the case surface temperature at the center of the top side of
the device. For measurement conditions, refer to the JESD51-2 standard.
2. When using the device in the elevated temperature range, some derating may be re-
quired. See Mode Registers for vendor-specific derating.
3. Either the device case temperature rating or the temperature sensor can be used to set
an appropriate refresh rate, determine the need for AC timing derating, and/or monitor
the operating temperature (see Temperature Sensor). When using the temperature sen-
sor, the actual device case temperature may be higher than the TOPER rating that applies
for the standard or elevated temperature range. For example, TCASE could be above
+85˚C when the temperature sensor indicates a temperature of less than +85˚C.
4. Refer to operating temperature range on top page.
CCM005-554574167-10729

AC and DC Input Measurement Levels

Input Levels for CKE
Table 155: Input Levels

Input HIGH level (AC) VIH(AC) 0.75 × VDD2 VDD2 + 0.2 V 1
Input LOW level (AC) VIL(AC) –0.2 0.25 × VDD2 V 1
Input HIGH level (DC) VIH(DC) 0.65 × VDD2 VDD2 + 0.2 V
Input LOW level (DC) VIL(DC) –0.2 0.35 × VDD2 V
Note: 1. See the AC Overshoot and Undershoot section.
Figure 150: Input Timing Definition for CKE
VIH(AC) VIH(DC)
Input
level
VIL(AC) VIL(DC)
Don’t Care
Input Levels for RESET_n
Table 156: Input Levels

Input HIGH level VIH 0.80 × VDD2 VDD2 + 0.2 V 1
Input LOW level VIL –0.2 0.20 × VDD2 V 1
Note: 1. See the AC Overshoot and Undershoot section.
Figure 151: Input Timing Definition for RESET_n
VIH VIH
Input
level
VIL VIL
Don’t Care
Differential Input Voltage for CK

The minimum input voltage needs to satisfy both V indiff_CK and V indiff_CK/2 specification
at input receiver and their measurement period is 1tCK. V indiff_CK is the peak-to-peak
CCM005-554574167-10729

voltage centered on 0 volts differential and V indiff_CK/2 is maximum and minimum peak
voltage from 0 volts.
Figure 152: CK Differential Input Voltage
Peak
voltage
Differential Input Voltage : CK_t - CK_c
Vindiff_CK/2
Vindiff_CK
0.0
Vindiff_CK/2
Peak
voltage
Time
Table 157: CK Differential Input Voltage
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Parameter Symbol Min Max Min Max Min Max Unit Note
CK differential input voltage Vindiff_CK 420 – 380 – 360 – mV 1
Note: 1. The peak voltage of differential CK signals is calculated in a following equation.

• Vindiff_CK = (Maximum peak voltage) - (Minimum peak voltage)
• Maximum peak voltage = MAX(f(t))
• Minimum peak voltage = MIN(f(t))
• f(t) = VCK_t - VCK_c
Peak Voltage Calculation Method

The peak voltage of differential clock signals are calculated in a following equation.
• VIH.DIFF.peak voltage = MAX(f(t))
• VIL.DIFF.peak voltage = MIN(f(t))
• f(t) = V CK_t - V CK_c
CCM005-554574167-10729

Figure 153: Definition of Differential Clock Peak Voltage
CK_t
Single Ended Input Voltage Min(f(t)) Max(f(t))
VREF(CA)
CK_c
Time
Note: 1. VREF(CA) is device internal setting value by VREF training.
Single-Ended Input Voltage for Clock

The minimum input voltage need to satisfy V inse_CK, V inse_CK_HIGH, and V inse_CK_LOW
specification at input receiver.
Figure 154: Clock Single-Ended Input Voltage
CK_t
Vinse_CK_HIGH
Vinse_CK_HIGH
Single Ended Input Voltage
Vinse_CK
Vinse_CK
VREF(CA)
Vinse_CK_LOW
Vinse_CK_LOW
CK_c
Time
Note: 1. VREF(CA) is device internal setting value by VREF training.
CCM005-554574167-10729

Table 158: Clock Single-Ended Input Voltage
1600/1867 2133/2400/3200 3733/4267

Parameter Symbol Min Max Min Max Min Max Unit
Clock single-ended Vinse_CK 210 – 190 – 180 – mV
input voltage
Clock single-ended input Vinse_CK_HIGH 105 – 95 – 90 – mV
voltage HIGH from VREF(CA)
Clock single-ended input Vinse_CK_LOW 105 – 95 – 90 – mV
voltage LOW from VREF(CA)
Differential Input Slew Rate Definition for Clock

Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown
below in figure and the tables.
Figure 155: Differential Input Slew Rate Definition for CK_t, CK_c
Peak
Differential Input Voltage : f(t) = CK_t - CK_c
Voltage
VIHdiff_CK
0.0
VILdiff_CK
Peak
Voltage
Delta TFdiff Delta TRdiff
Time
Notes: 1. Differential signal rising edge from VILdiff_CK to VIHdiff_CK must be monotonic slope.
2. Differential signal falling edge from VIHdiff_CK to VILdiff_CK must be monotonic slope.
Table 159: Differential Input Slew Rate Definition for CK_t, CK_c
Description From To Defined by

Differential input slew rate for VILdiff_CK VIHdiff_CK |VILdiff_CK - VIHdiff_CK|/ΔTRdiff
rising edge (CK_t - CK_c)
Differential input slew rate for VIHdiff_CK VILdiff_CK |VILdiff_CK - VIHdiff_CK|/ΔTFdiff
falling edge (CK_t - CK_c)
CCM005-554574167-10729

Table 160: Differential Input Level for CK_t, CK_c
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Differential Input HIGH VIHdiff_CK 175 – 155 – 145 – mV
Differential Input LOW VILdiff_CK – –175 – –155 – –145 mV
Table 161: Differential Input Slew Rate for CK_t, CK_c
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Differential input SRIdiff_CK 2 14 2 14 2 14 V/ns
slew rate for clock
Differential Input Cross-Point Voltage

The cross-point voltage of differential input signals (CK_t, CK_c) must meet the require-
ments in table below. The differential input cross-point voltage V IX is measured from
the actual cross-point of true and complement signals to the mid level that is V REF(CA).
Figure 156: Vix Definition (Clock)
VDD
CK_t
Single-Ended Input Voltage
Max(f(t))
ViX_CK_FR ViX_CK_RF
VREF(CA)
ViX_CK_RF ViX_CK_FR
Min(f(t))
CK_c
VSS
Time
Note: 1. The base levels of Vix_CK_FR and Vix_CK_RF are VREF(CA) that is device internal setting value
by VREF training.
CCM005-554574167-10729

Table 162: Cross-Point Voltage for Differential Input Signals (Clock)

Notes 1 and 2 apply to entire table
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Clock differential input Vix_CK_ratio – 25 – 25 – 25 %
cross-point voltage ratio
Notes: 1. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_FR/|MIN(f(t))|

2. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_RF/MAX(f(t))
Differential Input Voltage for DQS

The minimum input voltage needs to satisfy both V indiff_DQS and V indiff_DQS/2 specifica-
tion at input receiver and their measurement period is 1UI (tCK/2). V indiff_DQS is the
peak to peak voltage centered on 0 volts differential and V indiff_DQS/2 is maximum and
minimum peak voltage from 0 volts.
Figure 157: DQS Differential Input Voltage
Peak
voltage
Differential Input Voltage : DQS_t - DQS_c
Vindiff_DQS /2
Vindiff_DQS
0.0
Vindiff_DQS /2
Peak
voltage
Time
Table 163: DQS Differential Input Voltage
1600/1867 2133/2400/3200 3733/4267

Parameter Symbol Min Max Min Max Min Max Unit Note
DQS differential input voltage Vindiff_DQS 360 – 360 – 340 – mV 1
Note: 1. The peak voltage of differential DQS signals is calculated in a following equation.
• Vindiff_DQS = (Maximum peak voltage) - (Minimum peak voltage)
• Maximum peak voltage = MAX(f(t))
• Minimum peak voltage = MIN(f(t))
• f(t) = VDQS_t - VDQS_c
Peak Voltage Calculation Method

The peak voltage of differential DQS signals are calculated in a following equation.
CCM005-554574167-10729

• VIH.DIFF.peak voltage = MAX(f(t))

• VIL.DIFF.peak voltage = MIN(f(t))
• f(t) = V DQS_t - V DQS_c
Figure 158: Definition of Differential DQS Peak Voltage
DQS_t
Min(f(t)) Max(f(t))
VREF(DQ)
DQS_c
Time
Note: 1. VREF(DQ) is device internal setting value by VREF training.
Single-Ended Input Voltage for DQS

The minimum input voltage need to satisfy V inse_DQS, V inse_DQS_HIGH, and V inse_DQS_LOW
specification at input receiver.
Figure 159: DQS Single-Ended Input Voltage
DQS_t
Vinse_DQS_HIGH
Vinse_DQS_HIGH
Vinse_DQS
Vinse_DQS
VREF(DQ)
Vinse_DQS_LOW
Vinse_DQS_LOW
DQS_c
Time
Note: 1. VREF(DQ) is device internal setting value by VREF training.
CCM005-554574167-10729

Table 164: DQS Single-Ended Input Voltage
1600/1867 2133/2400/3200 3733/4267

DQS single-ended Vinse_DQS 180 – 180 – 170 – mV
input voltage
DQS single-ended input Vinse_DQS_HIGH 90 – 90 – 85 – mV
voltage HIGH from VREF(DQ)
DQS single-ended input Vinse_DQS_LOW 90 – 90 – 85 – mV
voltage LOW from VREF(DQ)
Differential Input Slew Rate Definition for DQS

Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as
shown below in figure and the tables.
Figure 160: Differential Input Slew Rate Definition for DQS_t, DQS_c
Peak
Differential Input Voltage : f(t) = CK_t - CK_c
Voltage
VIHdiff_CK
0.0
VILdiff_CK
Peak
Voltage
Delta TFdiff Delta TRdiff
Time
Notes: 1. Differential signal rising edge from VILdiff_DQS to VIHdiff_DQS must be monotonic slope.
2. Differential signal falling edge from VIHdiff_DQS to VILdiff_DQS must be monotonic slope.
Table 165: Differential Input Slew Rate Definition for DQS_t, DQS_c
Description From To Defined by

Differential input slew rate for VILdiff_DQS VIHdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/ΔTRdiff
rising edge (DQS_t - DQS_c)
Differential input slew rate for VIHdiff_DQS VILdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/ΔTFdiff
falling edge (DQS_t - DQS_c)
CCM005-554574167-10729

Table 166: Differential Input Level for DQS_t, DQS_c
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Differential Input HIGH VIHdiff_DQS 140 – 140 – 120 – mV
Differential Input LOW VILdiff_DQS – –140 – –140 – –120 mV
Table 167: Differential Input Slew Rate for DQS_t, DQS_c
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Differential input slew rate SRIdiff 2 14 2 14 2 14 V/ns
Differential Input Cross-Point Voltage

The cross-point voltage of differential input signals (DQS_t, DQS_c) must meet the re-
quirements in table below. The differential input cross-point voltage V IX is measured
from the actual cross-point of true and complement signals to the mid level that is
VREF(DQ).
Figure 161: Vix Definition (DQS)
VDDQ
DQS_t
Single-Ended Input Voltage
Max(f(t))
ViX_DQS_FR ViX_DQS_RF
VREF(DQ)
ViX_DQS_RF ViX_DQS_FR
Min(f(t))
DQS_c
VSSQ
Time
Note: 1. The base levels of Vix_DQS_FR and Vix_DQS_RF are VREF(DQ) that is device internal setting val-
ue by VREF training.
CCM005-554574167-10729

Output Slew Rate and Overshoot/Undershoot specifications
Table 168: Cross-Point Voltage for Differential Input Signals (DQS)

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DQS differential input Vix_DQS_ratio – 20 – 20 – 20 %
cross-point voltage ratio
Notes: 1. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_FR/|MIN(f(t))|

2. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_RF/MAX(f(t))
Input Levels for ODT_CA
Table 169: Input Levels for ODT_CA

ODT input HIGH level VIHODT 0.75 × VDD2 VDD2 + 0.2 V
ODT input LOW level VILODT –0.2 0.25 × VDD2 V

Single-Ended Output Slew Rate
Table 170: Single-Ended Output Slew Rate

Note 1-5 applies to entire table
Value
Single-ended output slew rate (VOH = VDDQ x 0.5) SRQse 3.0 9.0 V/ns
Output slew rate matching ratio (rise to fall) – 0.8 1.2 –
Notes: 1. SR = Slew rate; Q = Query output; se = Single-ended signal.

2. Measured with output reference load.
3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and
voltage, over the entire temperature and voltage range. For a given output, it repre-
sents the maximum difference between pull-up and pull-down drivers due to process
variation.
4. The output slew rate for falling and rising edges is defined and measured between
VOL(AC) = 0.2 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).
5. Slew rates are measured under average SSO conditions with 50% of the DQ signals per
data byte switching.
CCM005-554574167-10729

Figure 162: Single-Ended Output Slew Rate Definition
∆TRSE
Single-Ended Output Voltage (DQ)

VOH(AC)
VCENT
VOL(AC)
∆TFSE
Time
Differential Output Slew Rate
Table 171: Differential Output Slew Rate

Value
Differential output slew rate (VOH = VDDQ x 0.5) SRQdiff 6 18 V/ns
Notes: 1. SR = Slew rate; Q = Query output; se = Differential signal.

VOL(AC) = –0.8 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).
Figure 163: Differential Output Slew Rate Definition
∆TRdiff
Differential Output Voltage (DQ)
∆TFdiff
Time
CCM005-554574167-10729

Driver Output Timing Reference Load
Overshoot and Undershoot Specifications
Table 172: AC Overshoot/Undershoot Specifications
Parameter 1600 1866 3200 3733 4267 Unit

Maximum peak amplitude provided for over- MAX 0.3 0.3 0.3 0.3 0.3 V
shoot area
Maximum peak amplitude provided for un- MAX 0.3 0.3 0.3 0.3 0.3 V
dershoot area
Maximum area above VDD/ VDDQ MAX 0.1 0.1 0.1 0.1 0.1 V-ns
Maximum area below VSS/ VSSQ MAX 0.1 0.1 0.1 0.1 0.1 V-ns
Notes: 1. VDD stands for VDD2 for CA[5:0], CK_t, CS_n, CKE, and ODT. VDD stands for VDDQ for DQ,
DMI, DQS_t, and DQS_c.
2. VSS stands for VSS for CA[5:0], CK_t, CK_c, CS_n, CKE, and ODT. VSS stands for VSSQ for
DQ, DMI, DQS_t, and DQS_c.
3. Maximum peak amplitude values are referenced from actual VDD and VSS values.
4. Maximum area values are referenced from maximum VDD and VSS values.
Table 173: Overshoot/Undershoot Specification for CKE and RESET
Parameter Specification
Maximum peak amplitude provided for overshoot area 0.35V
Maximum peak amplitude provided for undershoot area 0.35V
Maximum area above VDD 0.8 V-ns
Maximum area below VSS 0.8 V-ns
Figure 164: Overshoot and Undershoot Definition

Maximum amplitude
Overshoot area
Volts (V)
VDD
Time (ns)
VSS
Undershoot area
Maximum amplitude
Driver Output Timing Reference Load

Timing reference loads are not intended as a precise representation of any particular
system environment or depiction of an actual load presented by a production tester.
System designers should use IBIS or other simulation tools to correlate the timing refer-
ence load to a system environment. Manufacturers correlate to their production test
conditions, generally one or more coaxial transmission lines terminated at the tester
electronics.
CCM005-554574167-10729

LVSTL I/O System
Figure 165: Driver Output Timing Reference Load
DRAM
50 ohms
Note: 1. All output timing parameter values are reported with respect to this reference load; this
reference load is also used to report slew rate.
LVSTL I/O System

LVSTL I/O cells are comprised of a driver pull-up and pull-down and a terminator.
Figure 166: LVSTL I/O Cell

VDDQ
Pull-Up
DQ
ODT
Pull-Down Enabled when receiving
VSSQ VSSQ
To ensure that the target impedance is achieved, calibrate the LVSTL I/O cell as follow-
ing example:
1. Calibrate the pull-down device against a 240 ohm resistor to V DDQ via the ZQ pin.
• Set strength control to minimum setting
• Increase drive strength until comparator detects data bit is less than V DDQ/2
• NMOS pull-down device is calibrated to 240 ohms
2. Calibrate the pull-up device against the calibrated pull-down device.
• Set V OH target and NMOS controller ODT replica via MRS (VOH can be automatically
controlled by ODT MRS)
CCM005-554574167-10729

Input/Output Capacitance

• Increase drive strength until comparator detects data bit is greater than V OH target
• NMOS pull-up device is calibrated to V OH target
Figure 167: Pull-Up Calibration

VDDQ
N
Strength contol [N-1:0]
Comparator
VOH target
Calibrated NMOS PD Controller ODT replica could be

control + ODT information 60 ohms, 120 ohms, ... via MRS setting
VSSQ
Input/Output Capacitance
Table 174: Input/Output Capacitance

Input capacitance, CK_t and CK_c CCK 0.5 0.9
Input capacitance delta, CK_t and CK_c CDCK 0 0.09 3
Input capacitance, all other input-only pins CI 0.5 0.9 4
Input capacitance delta, all other input-only pins CDI –0.1 0.1 5
pF
Input/output capacitance, DQ, DMI, DQS_t, DQS_c CIO 0.7 1.3 6
Input/output capacitance delta, DQS_t, DQS_c CDDQS 0 0.1 7
Input/output capacitance delta, DQ, DMI CDIO –0.1 0.1 8
Input/output capacitance, ZQ pin CZQ 0 5.0
Notes: 1. This parameter applies to LPDDR4 die only (does not include package capacitance).
2. This parameter is not subject to production testing; It is verified by design and character-
ization. The capacitance is measured according to JEP147 (procedure for measuring in-
put capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, and VSS ap-
plied; All other pins are left floating.
3. Absolute value of CCK_t – CCK_c.
4. CI applies to CS, CKE, and CA[5:0].
5. CDI = CI – 0.5 × (CCK_t + CCK_c); It does not apply to CKE.
6. DMI loading matches DQ and DQS.
7. Absolute value of CDQS_t and CDQS_c.
CCM005-554574167-10729

IDD Specification Parameters and Test Conditions
8. CDIO = CIO – Average(CDQn, CDMI, CDQS_t, CDQS_c) in byte-lane.
Table 175: IDD Measurement Conditions
Switching for CA
CK_t edge R1 R2 R3 R4 R5 R6 R7 R8
CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
CS LOW LOW LOW LOW LOW LOW LOW LOW
CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH
CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH
Notes: 1. LOW = VIN ≤ VIL(DC) MAX.

HIGH = VIN ≥ VIH(DC) MIN.
STABLE = Inputs are stable at a HIGH or LOW level.
2. CS must always be driven LOW.
3. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.
4. The pattern is used continuously during IDD measurement for IDD values that require
switching on the CA bus.
Table 176: CA Pattern for IDD4R for BL = 16
Clock Cycle
Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5
N HIGH HIGH READ-1 L H L L L L
N+1 HIGH LOW L H L L L L
N+2 HIGH HIGH CAS-2 L H L L H L
N+3 HIGH LOW L L L L L L
N+4 HIGH LOW DES L L L L L L
N+8 HIGH HIGH READ-1 L H L L L L
N+9 HIGH LOW L H L L H L
N+10 HIGH HIGH CAS-2 L H L L H H
N+11 HIGH LOW H H H H H H
CCM005-554574167-10729

Table 176: CA Pattern for IDD4R for BL = 16 (Continued)
Clock Cycle
Notes: 1. BA[2:0] = 010; C[9:4] = 000000 or 111111; Burst order C[3:2] = 00 or 11 (same as LPDDR3
IDDR4R specification).
2. CA pins are kept LOW with DES command to reduce ODT current (different from
LPDDR3 IDDR4R specification).
Table 177: CA Pattern for IDD4W for BL = 16
Clock Cycle
N HIGH HIGH WRITE-1 L L H L L L
N+8 HIGH HIGH WRITE-1 L L H L L L
N+11 HIGH LOW L L H H H H
Notes: 1. BA[2:0] = 010; C[9:4] = 000000 or 111111 (same as LPDDR3 IDDR4W specification).
2. No burst ordering (different from LPDDR3 IDDR4W specification).
3. CA pins are kept LOW with DES command to reduce ODT current (different from
LPDDR3 IDDR4W specification).
Table 178: Data Pattern for IDD4W (DBI Off) for BL = 16
DBI Off Case

DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s
BL0 1 1 1 1 1 1 1 1 0 8
BL1 1 1 1 1 0 0 0 0 0 4
BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
CCM005-554574167-10729

Table 178: Data Pattern for IDD4W (DBI Off) for BL = 16 (Continued)
DBI Off Case

BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
BL6 1 1 1 1 1 1 0 0 0 6
BL7 1 1 1 1 0 0 0 0 0 4
BL8 1 1 1 1 1 1 1 1 0 8
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 1 1 1 1 1 1 0 0 0 6
BL15 1 1 1 1 0 0 0 0 0 4
BL16 1 1 1 1 1 1 0 0 0 6
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 1 1 0 2
BL19 0 0 0 0 1 1 1 1 0 4
BL20 0 0 0 0 0 0 0 0 0 0
BL21 0 0 0 0 1 1 1 1 0 4
BL22 1 1 1 1 1 1 1 1 0 8
BL23 1 1 1 1 0 0 0 0 0 4
BL24 0 0 0 0 0 0 1 1 0 2
BL25 0 0 0 0 1 1 1 1 0 4
BL26 1 1 1 1 1 1 0 0 0 6
BL27 1 1 1 1 0 0 0 0 0 4
BL28 1 1 1 1 1 1 1 1 0 8
BL29 1 1 1 1 0 0 0 0 0 4
BL30 0 0 0 0 0 0 0 0 0 0
BL31 0 0 0 0 1 1 1 1 0 4
# of 1s 16 16 16 16 16 16 16 16
Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to
reduce complexity for IDD4W pattern programming.
Table 179: Data Pattern for IDD4R (DBI Off) for BL = 16
DBI Off Case

BL0 1 1 1 1 1 1 1 1 0 8
CCM005-554574167-10729

Table 179: Data Pattern for IDD4R (DBI Off) for BL = 16 (Continued)
DBI Off Case

BL1 1 1 1 1 0 0 0 0 0 4
BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
BL6 1 1 1 1 1 1 0 0 0 6
BL7 1 1 1 1 0 0 0 0 0 4
BL8 1 1 1 1 1 1 1 1 0 8
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 1 1 1 1 1 1 0 0 0 6
BL15 1 1 1 1 0 0 0 0 0 4
BL16 1 1 1 1 1 1 1 1 0 8
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 0 0 0 0
BL19 0 0 0 0 1 1 1 1 0 4
BL20 1 1 1 1 1 1 0 0 0 6
BL21 1 1 1 1 0 0 0 0 0 4
BL22 0 0 0 0 0 0 1 1 0 2
BL23 0 0 0 0 1 1 1 1 0 4
BL24 0 0 0 0 0 0 0 0 0 0
BL25 0 0 0 0 1 1 1 1 0 4
BL26 1 1 1 1 1 1 1 1 0 8
BL27 1 1 1 1 0 0 0 0 0 4
BL28 0 0 0 0 0 0 1 1 0 2
BL29 0 0 0 0 1 1 1 1 0 4
BL30 1 1 1 1 1 1 0 0 0 6
BL31 1 1 1 1 0 0 0 0 0 4
# of 1s 16 16 16 16 16 16 16 16
reduce complexity for IDD4R pattern programming.
CCM005-554574167-10729

Table 180: Data Pattern for IDD4W (DBI On) for BL = 16
DBI On Case
BL0 0 0 0 0 0 0 0 0 1 1
BL1 1 1 1 1 0 0 0 0 0 4
BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
BL6 0 0 0 0 0 0 1 1 1 3
BL7 1 1 1 1 0 0 0 0 0 4
BL8 0 0 0 0 0 0 0 0 1 1
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 0 0 0 0 0 0 1 1 1 3
BL15 1 1 1 1 0 0 0 0 0 4
BL16 0 0 0 0 0 0 1 1 1 3
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 1 1 0 2
BL19 0 0 0 0 1 1 1 1 0 4
BL20 0 0 0 0 0 0 0 0 0 0
BL21 0 0 0 0 1 1 1 1 0 4
BL22 0 0 0 0 0 0 0 0 1 1
BL23 1 1 1 1 0 0 0 0 0 4
BL24 0 0 0 0 0 0 1 1 0 2
BL25 0 0 0 0 1 1 1 1 0 4
BL26 0 0 0 0 0 0 1 1 1 3
BL27 1 1 1 1 0 0 0 0 0 4
BL28 0 0 0 0 0 0 0 0 1 1
BL29 1 1 1 1 0 0 0 0 0 4
BL30 0 0 0 0 0 0 0 0 0 0
BL31 0 0 0 0 1 1 1 1 0 4
# of 1s 8 8 8 8 8 8 16 16 8
Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, and BL28.
CCM005-554574167-10729

Table 181: Data Pattern for IDD4R (DBI On) for BL = 16
DBI On Case
BL0 0 0 0 0 0 0 0 0 1 1
BL1 1 1 1 1 0 0 0 0 0 4
BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
BL6 0 0 0 0 0 0 1 1 1 3
BL7 1 1 1 1 0 0 0 0 0 4
BL8 0 0 0 0 0 0 0 0 1 1
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 0 0 0 0 0 0 1 1 1 3
BL15 1 1 1 1 0 0 0 0 0 4
BL16 0 0 0 0 0 0 0 0 1 1
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 0 0 0 0
BL19 0 0 0 0 1 1 1 1 0 4
BL20 0 0 0 0 0 0 1 1 1 3
BL21 1 1 1 1 0 0 0 0 0 4
BL22 0 0 0 0 0 0 1 1 0 2
BL23 0 0 0 0 1 1 1 1 0 4
BL24 0 0 0 0 0 0 0 0 0 0
BL25 0 0 0 0 1 1 1 1 0 4
BL26 0 0 0 0 0 0 0 0 1 1
BL27 1 1 1 1 0 0 0 0 0 4
BL28 0 0 0 0 0 0 1 1 0 2
BL29 0 0 0 0 1 1 1 1 0 4
BL30 0 0 0 0 0 0 1 1 1 3
BL31 1 1 1 1 0 0 0 0 0 4
# of 1s 8 8 8 8 8 8 16 16 8
Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL20, BL26, and BL30.
CCM005-554574167-10729

Table 182: CA Pattern for IDD4R for BL = 32
Clock Cycle
N HIGH HIGH READ-1 L H L L L L
N+16 HIGH HIGH READ-1 L H L L L L
N+19 HIGH LOW H H L H H H
Note: 1. BA[2:0] = 010, C[9:5] = 00000 or 11111, Burst order C[4:2] = 000 or 111.
CCM005-554574167-10729

Table 183: CA Pattern for IDD4W for BL = 32
Clock Cycle
N HIGH HIGH WRITE-1 L L H L L L
N+16 HIGH HIGH WRITE-1 L L H L L L
N+19 HIGH LOW L L L H H H
Note: 1. BA[2:0] = 010, C[9:5] = 00000 or 11111.
CCM005-554574167-10729

Table 184: Data Pattern for IDD4W (DBI Off) for BL = 32
DBI Off Case

BL0 1 1 1 1 1 1 1 1 0 8
BL1 1 1 1 1 0 0 0 0 0 4
BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
BL6 1 1 1 1 1 1 0 0 0 6
BL7 1 1 1 1 0 0 0 0 0 4
BL8 1 1 1 1 1 1 1 1 0 8
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 1 1 1 1 1 1 0 0 0 6
BL15 1 1 1 1 0 0 0 0 0 4
BL16 1 1 1 1 1 1 0 0 0 6
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 1 1 0 2
BL19 0 0 0 0 1 1 1 1 0 4
BL20 0 0 0 0 0 0 0 0 0 0
BL21 0 0 0 0 1 1 1 1 0 4
BL22 1 1 1 1 1 1 1 1 0 8
BL23 1 1 1 1 0 0 0 0 0 4
BL24 0 0 0 0 0 0 1 1 0 2
BL25 0 0 0 0 1 1 1 1 0 4
BL26 1 1 1 1 1 1 0 0 0 6
BL27 1 1 1 1 0 0 0 0 0 4
BL28 1 1 1 1 1 1 1 1 0 8
BL29 1 1 1 1 0 0 0 0 0 4
BL30 0 0 0 0 0 0 0 0 0 0
BL31 0 0 0 0 1 1 1 1 0 4
BL32 1 1 1 1 1 1 1 1 0 8
BL33 1 1 1 1 0 0 0 0 0 4
BL34 0 0 0 0 0 0 0 0 0 0
BL35 0 0 0 0 1 1 1 1 0 4
BL36 0 0 0 0 0 0 1 1 0 2
CCM005-554574167-10729

Table 184: Data Pattern for IDD4W (DBI Off) for BL = 32 (Continued)
DBI Off Case

BL37 0 0 0 0 1 1 1 1 0 4
BL38 1 1 1 1 1 1 0 0 0 6
BL39 1 1 1 1 0 0 0 0 0 4
BL40 1 1 1 1 1 1 1 1 0 8
BL41 1 1 1 1 0 0 0 0 0 4
BL42 0 0 0 0 0 0 0 0 0 0
BL43 0 0 0 0 1 1 1 1 0 4
BL44 0 0 0 0 0 0 1 1 0 2
BL45 0 0 0 0 1 1 1 1 0 4
BL46 1 1 1 1 1 1 0 0 0 6
BL47 1 1 1 1 0 0 0 0 0 4
BL48 1 1 1 1 1 1 0 0 0 6
BL49 1 1 1 1 0 0 0 0 0 4
BL50 0 0 0 0 0 0 1 1 0 2
BL51 0 0 0 0 1 1 1 1 0 4
BL52 0 0 0 0 0 0 0 0 0 0
BL53 0 0 0 0 1 1 1 1 0 4
BL54 1 1 1 1 1 1 1 1 0 8
BL55 1 1 1 1 0 0 0 0 0 4
BL56 0 0 0 0 0 0 1 1 0 2
BL57 0 0 0 0 1 1 1 1 0 4
BL58 1 1 1 1 1 1 0 0 0 6
BL59 1 1 1 1 0 0 0 0 0 4
BL60 1 1 1 1 1 1 1 1 0 8
BL61 1 1 1 1 0 0 0 0 0 4
BL62 0 0 0 0 0 0 0 0 0 0
BL63 0 0 0 0 1 1 1 1 0 4
# of 1s 32 32 32 32 32 32 32 32
reduce complexity for IDD4W pattern programming.
Table 185: Data Pattern for IDD4R (DBI Off) for BL = 32
DBI Off Case

BL0 1 1 1 1 1 1 1 1 0 8
BL1 1 1 1 1 0 0 0 0 0 4
CCM005-554574167-10729

DBI Off Case

BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
BL6 1 1 1 1 1 1 0 0 0 6
BL7 1 1 1 1 0 0 0 0 0 4
BL8 1 1 1 1 1 1 1 1 0 8
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 1 1 1 1 1 1 0 0 0 6
BL15 1 1 1 1 0 0 0 0 0 4
BL16 1 1 1 1 1 1 0 0 0 6
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 1 1 0 2
BL19 0 0 0 0 1 1 1 1 0 4
BL20 0 0 0 0 0 0 0 0 0 0
BL21 0 0 0 0 1 1 1 1 0 4
BL22 1 1 1 1 1 1 1 1 0 8
BL23 1 1 1 1 0 0 0 0 0 4
BL24 0 0 0 0 0 0 1 1 0 2
BL25 0 0 0 0 1 1 1 1 0 4
BL26 1 1 1 1 1 1 0 0 0 6
BL27 1 1 1 1 0 0 0 0 0 4
BL28 1 1 1 1 1 1 1 1 0 8
BL29 1 1 1 1 0 0 0 0 0 4
BL30 0 0 0 0 0 0 0 0 0 0
BL31 0 0 0 0 1 1 1 1 0 4
BL32 0 0 0 0 0 0 1 1 0 2
BL33 0 0 0 0 1 1 1 1 0 4
BL34 1 1 1 1 1 1 0 0 0 6
BL35 1 1 1 1 0 0 0 0 0 4
BL36 1 1 1 1 1 1 1 1 0 8
BL37 1 1 1 1 0 0 0 0 0 4
BL38 0 0 0 0 0 0 0 0 0 0
CCM005-554574167-10729

DBI Off Case

BL39 0 0 0 0 1 1 1 1 0 4
BL40 0 0 0 0 0 0 1 1 0 2
BL41 0 0 0 0 1 1 1 1 0 4
BL42 1 1 1 1 1 1 0 0 0 6
BL43 1 1 1 1 0 0 0 0 0 4
BL44 1 1 1 1 1 1 1 1 0 8
BL45 1 1 1 1 0 0 0 0 0 4
BL46 0 0 0 0 0 0 0 0 0 0
BL47 0 0 0 0 1 1 1 1 0 4
BL48 1 1 1 1 1 1 1 1 0 8
BL49 1 1 1 1 0 0 0 0 0 4
BL50 0 0 0 0 0 0 0 0 0 0
BL51 0 0 0 0 1 1 1 1 0 4
BL52 1 1 1 1 1 1 0 0 0 6
BL53 1 1 1 1 0 0 0 0 0 4
BL54 0 0 0 0 0 0 1 1 0 2
BL55 0 0 0 0 1 1 1 1 0 4
BL56 0 0 0 0 0 0 0 0 0 0
BL57 0 0 0 0 1 1 1 1 0 4
BL58 1 1 1 1 1 1 1 1 0 8
BL59 1 1 1 1 0 0 0 0 0 4
BL60 0 0 0 0 0 0 1 1 0 2
BL61 0 0 0 0 1 1 1 1 0 4
BL62 1 1 1 1 1 1 0 0 0 6
BL63 1 1 1 1 0 0 0 0 0 4
# of 1s 32 32 32 32 32 32 32 32
reduce complexity for IDD4R pattern programming.
Table 186: Data Pattern for IDD4W (DBI On) for BL = 32
DBI On Case
BL0 0 0 0 0 0 0 0 0 1 1
BL1 1 1 1 1 0 0 0 0 0 4
BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
CCM005-554574167-10729

Table 186: Data Pattern for IDD4W (DBI On) for BL = 32 (Continued)
DBI On Case
BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
BL6 0 0 0 0 0 0 1 1 1 3
BL7 1 1 1 1 0 0 0 0 0 4
BL8 0 0 0 0 0 0 0 0 1 1
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 0 0 0 0 0 0 1 1 1 3
BL15 1 1 1 1 0 0 0 0 0 4
BL16 0 0 0 0 0 0 1 1 1 3
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 1 1 0 2
BL19 0 0 0 0 1 1 1 1 0 4
BL20 0 0 0 0 0 0 0 0 0 0
BL21 0 0 0 0 1 1 1 1 0 4
BL22 0 0 0 0 0 0 0 0 1 1
BL23 1 1 1 1 0 0 0 0 0 4
BL24 0 0 0 0 0 0 1 1 0 2
BL25 0 0 0 0 1 1 1 1 0 4
BL26 0 0 0 0 0 0 1 1 1 3
BL27 1 1 1 1 0 0 0 0 0 4
BL28 0 0 0 0 0 0 0 0 1 1
BL29 1 1 1 1 0 0 0 0 0 4
BL30 0 0 0 0 0 0 0 0 0 0
BL31 0 0 0 0 1 1 1 1 0 4
BL32 0 0 0 0 0 0 0 0 1 1
BL33 1 1 1 1 0 0 0 0 0 4
BL34 0 0 0 0 0 0 0 0 0 0
BL35 0 0 0 0 1 1 1 1 0 4
BL36 0 0 0 0 0 0 1 1 0 2
BL37 0 0 0 0 1 1 1 1 0 4
BL38 0 0 0 0 0 0 1 1 1 3
BL39 1 1 1 1 0 0 0 0 0 4
BL40 0 0 0 0 0 0 0 0 1 1
CCM005-554574167-10729

Table 186: Data Pattern for IDD4W (DBI On) for BL = 32 (Continued)
DBI On Case
BL41 1 1 1 1 0 0 0 0 0 4
BL42 0 0 0 0 0 0 0 0 0 0
BL43 0 0 0 0 1 1 1 1 0 4
BL44 0 0 0 0 0 0 1 1 0 2
BL45 0 0 0 0 1 1 1 1 0 4
BL46 0 0 0 0 0 0 1 1 1 3
BL47 1 1 1 1 0 0 0 0 0 4
BL48 0 0 0 0 0 0 1 1 1 3
BL49 1 1 1 1 0 0 0 0 0 4
BL50 0 0 0 0 0 0 1 1 0 2
BL51 0 0 0 0 1 1 1 1 0 4
BL52 0 0 0 0 0 0 0 0 0 0
BL53 0 0 0 0 1 1 1 1 0 4
BL54 0 0 0 0 0 0 0 0 1 1
BL55 1 1 1 1 0 0 0 0 0 4
BL56 0 0 0 0 0 0 1 1 0 2
BL57 0 0 0 0 1 1 1 1 0 4
BL58 0 0 0 0 0 0 1 1 1 3
BL59 1 1 1 1 0 0 0 0 0 4
BL60 0 0 0 0 0 0 0 0 1 1
BL61 1 1 1 1 0 0 0 0 0 4
BL62 0 0 0 0 0 0 0 0 0 0
BL63 0 0 0 0 1 1 1 1 0 4
# of 1s 16 16 16 16 16 16 32 32 16
Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, BL28, BL32, BL38, BL40, BL46,
BL48, BL54, BL58, and BL60.
Table 187: Data Pattern for IDD4R (DBI On) for BL = 32
DBI On Case
BL0 0 0 0 0 0 0 0 0 1 1
BL1 1 1 1 1 0 0 0 0 0 4
BL2 0 0 0 0 0 0 0 0 0 0
BL3 0 0 0 0 1 1 1 1 0 4
BL4 0 0 0 0 0 0 1 1 0 2
BL5 0 0 0 0 1 1 1 1 0 4
CCM005-554574167-10729

Table 187: Data Pattern for IDD4R (DBI On) for BL = 32 (Continued)
DBI On Case
BL6 0 0 0 0 0 0 1 1 1 3
BL7 1 1 1 1 0 0 0 0 0 4
BL8 0 0 0 0 0 0 0 0 1 1
BL9 1 1 1 1 0 0 0 0 0 4
BL10 0 0 0 0 0 0 0 0 0 0
BL11 0 0 0 0 1 1 1 1 0 4
BL12 0 0 0 0 0 0 1 1 0 2
BL13 0 0 0 0 1 1 1 1 0 4
BL14 0 0 0 0 0 0 1 1 1 3
BL15 1 1 1 1 0 0 0 0 0 4
BL16 0 0 0 0 0 0 1 1 1 3
BL17 1 1 1 1 0 0 0 0 0 4
BL18 0 0 0 0 0 0 1 1 0 2
BL19 0 0 0 0 1 1 1 1 0 4
BL20 0 0 0 0 0 0 0 0 0 0
BL21 0 0 0 0 1 1 1 1 0 4
BL22 0 0 0 0 0 0 0 0 1 1
BL23 1 1 1 1 0 0 0 0 0 4
BL24 0 0 0 0 0 0 1 1 0 2
BL25 0 0 0 0 1 1 1 1 0 4
BL26 0 0 0 0 0 0 1 1 1 3
BL27 1 1 1 1 0 0 0 0 0 4
BL28 0 0 0 0 0 0 0 0 1 1
BL29 1 1 1 1 0 0 0 0 0 4
BL30 0 0 0 0 0 0 0 0 0 0
BL31 0 0 0 0 1 1 1 1 0 4
BL32 0 0 0 0 0 0 1 1 0 2
BL33 0 0 0 0 1 1 1 1 0 4
BL34 0 0 0 0 0 0 1 1 1 3
BL35 1 1 1 1 0 0 0 0 0 4
BL36 0 0 0 0 0 0 0 0 1 1
BL37 1 1 1 1 0 0 0 0 0 4
BL38 0 0 0 0 0 0 0 0 0 0
BL39 0 0 0 0 1 1 1 1 0 4
BL40 0 0 0 0 0 0 1 1 0 2
BL41 0 0 0 0 1 1 1 1 0 4
BL42 0 0 0 0 0 0 1 1 1 3
CCM005-554574167-10729

Table 187: Data Pattern for IDD4R (DBI On) for BL = 32 (Continued)
DBI On Case
BL43 1 1 1 1 0 0 0 0 0 4
BL44 0 0 0 0 0 0 0 0 1 1
BL45 1 1 1 1 0 0 0 0 0 4
BL46 0 0 0 0 0 0 0 0 0 0
BL47 0 0 0 0 1 1 1 1 0 4
BL48 0 0 0 0 0 0 0 0 1 1
BL49 1 1 1 1 0 0 0 0 0 4
BL50 0 0 0 0 0 0 0 0 0 0
BL51 0 0 0 0 1 1 1 1 0 4
BL52 0 0 0 0 0 0 1 1 1 3
BL53 1 1 1 1 0 0 0 0 0 4
BL54 0 0 0 0 0 0 1 1 0 2
BL55 0 0 0 0 1 1 1 1 0 4
BL56 0 0 0 0 0 0 0 0 0 0
BL57 0 0 0 0 1 1 1 1 0 4
BL58 0 0 0 0 0 0 0 0 1 1
BL59 1 1 1 1 0 0 0 0 0 4
BL60 0 0 0 0 0 0 1 1 0 2
BL61 0 0 0 0 1 1 1 1 0 4
BL62 0 0 0 0 0 0 1 1 1 3
BL63 1 1 1 1 0 0 0 0 0 4
# of 1s 16 16 16 16 16 16 32 32 16
Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, BL28, BL34, BL36, BL42, BL44,
BL48, BL52, BL58, and BL62.
CCM005-554574167-10729

IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire
standard temperature range.
Table 188: IDD Specification Parameters and Operating Conditions

LPDDR4: VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V
LPDDR4X: VDD2= 1.06–1.17V; VDDQ = 0.57–0.65V; VDD1 = 1.70–1.95V
Power
Parameter/Condition Symbol Supply Notes
Operating one bank active-precharge current: = tCK tCK IDD01 VDD1
(MIN); tRC = tRC (MIN); CKE is HIGH; CS is LOW between valid com- IDD02 VDD2
mands; CA bus inputs are switching; Data bus inputs are stable;
IDD0Q VDDQ 2
ODT is disabled
Idle power-down standby current: tCK = tCK (MIN); CKE is IDD2P1 VDD1
LOW; CS is LOW; All banks are idle; CA bus inputs are switching; IDD2P2 VDD2
Data bus inputs are stable; ODT is disabled
IDD2PQ VDDQ 2
Idle power-down standby current with clock stop: CK_t = IDD2PS1 VDD1
LOW, CK_c = HIGH; CKE is LOW; CS is LOW; All banks are idle; CA IDD2PS2 VDD2
bus inputs are stable; Data bus inputs are stable; ODT is disabled
IDD2PSQ VDDQ 2
Idle non-power-down standby current: = (MIN); CKE is tCK tCK IDD2N1 VDD1
HIGH; CS is LOW; All banks are idle; CA bus inputs are switching; IDD2N2 VDD2
IDD2NQ VDDQ 2
Idle non-power-down standby current with clock stopped: IDD2NS1 VDD1
CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS is LOW; All banks are IDD2NS2 VDD2
idle; CA bus inputs are stable; Data bus inputs are stable; ODT is
IDD2NSQ VDDQ 2
disabled
Active power-down standby current: tCK = tCK (MIN); CKE is IDD3P1 VDD1
LOW; CS is LOW; One bank is active; CA bus inputs are switching; IDD3P2 VDD2
IDD3PQ VDDQ 2
Active power-down standby current with clock stop: CK_t = IDD3PS1 VDD1
LOW, CK_c = HIGH; CKE is LOW; CS is LOW; One bank is active; CA IDD3PS2 VDD2
bus inputs are stable; Data bus inputs are stable; ODT is disabled
IDD3PSQ VDDQ 3
Active non-power-down standby current: = (MIN); tCK tCK IDD3N1 VDD1
CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are IDD3N2 VDD2
switching; Data bus inputs are stable; ODT is disabled
IDD3NQ VDDQ 3
Active non-power-down standby current with clock stop- IDD3NS1 VDD1
ped: CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS is LOW; One bank IDD3NS2 VDD2
is active; CA bus inputs are stable; Data bus inputs are stable; ODT
IDD3NSQ VDDQ 3
is disabled
Operating burst READ current: tCK = tCK (MIN); CS is LOW be- IDD4R1 VDD1
tween valid commands; One bank is active; BL = 16 or 32; RL = RL IDD4R2 VDD2
(MIN); CA bus inputs are switching; 50% data change each burst
IDD4RQ VDDQ 4
transfer; ODT is disabled
CCM005-554574167-10729

Table 188: IDD Specification Parameters and Operating Conditions (Continued)

LPDDR4: VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V
LPDDR4X: VDD2= 1.06–1.17V; VDDQ = 0.57–0.65V; VDD1 = 1.70–1.95V
Power
Parameter/Condition Symbol Supply Notes
Operating burst WRITE current: tCK = tCK (MIN); CS is LOW be- IDD4W1 VDD1
tween valid commands; One bank is active; BL = 16 or 32; WL = IDD4W2 VDD2
WL (MIN); CA bus inputs are switching; 50% data change each
IDD4WQ VDDQ 3
burst transfer; ODT is disabled
All-bank REFRESH burst current: tCK = tCK (MIN); CKE is HIGH IDD51 VDD1
between valid commands; tRC = tRFCab (MIN); Burst refresh; CA IDD52 VDD2
bus inputs are switching; Data bus inputs are stable; ODT is disa-
IDD5Q VDDQ 3
bled
All-bank REFRESH average current: tCK = tCK (MIN); CKE is IDD5AB1 VDD1
HIGH between valid commands; tRC = tREFI; CA bus inputs are IDD5AB2 VDD2
IDD5ABQ VDDQ 3
Per-bank REFRESH average current: = (MIN); CKE is tCK tCK IDD5PB1 VDD1
HIGH between valid commands; tRC = tREFI/8; CA bus inputs are IDD5PB2 VDD2
IDD5PBQ VDDQ 3
Power-down self refresh current: CK_t = LOW, CK_c = HIGH; IDD61 VDD1 5, 6
CKE is LOW; CA bus inputs are stable; Data bus inputs are stable; IDD62 VDD2 5, 6
Maximum 1x self refresh rate; ODT is disabled
IDD6Q VDDQ 3, 5, 6
Notes: 1. ODT disabled: MR11[2:0] = 000b.

2. IDD current specifications are tested after the device is properly initialized.
3. Measured currents are the summation of VDDQ and VDD2.
4. Guaranteed by design with output load = 5pF and RON = 40 ohm.
5. The 1x self refresh rate is the rate at which the device is refreshed internally during self
refresh before going into the elevated temperature range.
6. This is the general definition that applies to full-array self refresh.
7. For all IDD measurements, VIHCKE = 0.8 × VDD2; VILCKE = 0.2 × VDD2.
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AC Timing
AC Timing
Table 189: Clock Timing
Min/ Data Rate

Parameter Symbol Max 1600 3200 3733 4267 Unit
Average clock period tCK(AVG) Min 1250 625 535 468 ps
Max 100 100 100 100 ns
Min 0.46
Average HIGH pulse width tCH(AVG) tCK(AVG)
Max 0.54
Min 0.46
Average LOW pulse width tCL(AVG) tCK(AVG)
Max 0.54
Absolute clock period tCK(ABS) Min tCK(AVG)min + tJIT(per)min ps
Min 0.43
Absolute clock HIGH pulse width tCH(ABS) tCK(AVG)
Max 0.57
Min 0.43
Absolute clock LOW pulse width tCL(ABS) tCK(AVG)
Max 0.57
tJIT(per)al- Min –70 –40 –34 –30
Clock period jitter ps
lowed Max 70 40 34 30
Maximum clock jitter between two
consecutive clock cycles (includes tJIT(cc)allowed Max 140 80 68 60 ps
clock period jitter)
Table 190: Read Output Timing
Min/ Data Rate

Parameter Symbol Max 533 1066 1600 2133 2667 3200 3733 4267 Unit Notes
DQS output access time Min 1500
tDQSCK ps 1
from CK_t/CK_c Max 3500
DQS output access time tDQSCK_
from CK_t/CK_c - voltage Max 7 ps/mV 2
VOLT
variation
DQS output access time tDQSCK_
from CK_t/CK_c - temper- Max 4 ps/°C 3
TEMP
ature variation
CK to DQS rank to rank tDQSCK_r
Max 1.0 ns 4, 5
variation ank2rank
DQS_t, DQS_c to DQ skew
total, per group, per ac- tDQSQ Max 0.18 UI 6
cess (DBI Disabled)
DQ output hold time to-
tal from DQS_t, DQS_c tQH Min MIN(tQSH, tQSL) ps 6
(DBI Disabled)
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AC Timing
Table 190: Read Output Timing (Continued)
Min/ Data Rate

Data output valid win- tQW_to-
dow time total, per pin Min 0.75 0.73 0.70 UI 6, 11
tal
(DBI-Disabled)
DQS_t, DQS_c to DQ skew tDQSQ_D
total, per group, per ac- Max 0.18 UI 6
BI
cess (DBI-Enabled)
DQ output hold time to-
tal from DQS_t, DQS_c tQH_DBI Min MIN(tQSH_DBI, tQSL_DBI) ps 6
(DBI-Enabled)
Data output valid win- tQW_to-
dow time total, per pin Min 0.75 0.73 0.70 UI 6, 11
tal_DBI
(DBI-Enabled)
DQS_t, DQS_c differential
output LOW time (DBI- tQSL Min tCL(ABS) - 0.05 tCK(AVG) 9, 11
Disabled)
output HIGH time (DBI- tQSH Min tCH(ABS) - 0.05 tCK(AVG) 10, 11
Disabled)
output LOW time (DBI- tQSL-DBI Min tCL(ABS) - 0.045 tCK(AVG) 9, 11
Enabled)
output HIGH time (DBI- tQSH-DBI Min tCH(ABS) - 0.045 tCK(AVG) 10, 11
Enabled)
Read preamble tRPRE Min 1.8 tCK(AVG)
Read postamble tRPST Min 0.4 (or 1.4 if extra postamble is programmed in MR) tCK(AVG)
DQS Low-Z from clock tLZ(DQS) Min (RL × tCK) + tDQSCK(MIN) - (tRPRE(MAX) × tCK) - 200ps ps
DQ Low-Z from clock tLZ(DQ) Min (RL × tCK) + tDQSCK(MIN) - 200ps ps
(RL × tCK) + tDQSCK(MAX)+(BL/2 × tCK) + (tRPST(MAX) ×
DQS High-Z from clock tHZ(DQS) Max ps
tCK) - 100ps
tHZ(DQ) (RL × tCK) + tDQSCK(MAX) + tDQSQ(MAX) + (BL/2 × tCK)

DQ High-Z from clock Max ps
- 100ps
Notes: 1. This parameter includes DRAM process, voltage, and temperature variation. It also in-
cludes the AC noise impact for frequencies >20 MHz and a max voltage of 45mV peak-
to-peak from DC-20 MHz at a fixed temperature on the package. The voltage supply
noise must comply with the component MIN/MAX DC operating conditions.
2. tDQSCK_volt max delay variation as a function of DC voltage variation for VDDQ and
VDD2. The voltage supply noise must comply with the component MIN/MAX DC operat-
ing conditions. The voltage variation is defined as the MAX[ABS(tDQSCK(MIN)@V1 -
tDQSCK(MAX)@V2), ABS(tDQSCK(MAX)@V1 - tDQSCK(MIN)@V2)]/ABS(V1 - V2).
3. tDQSCK_temp MAX delay variation as a function of temperature.

4. The same voltage and temperature are applied to tDQSCK_rank2rank.
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AC Timing
5. tDQSCK_rank2rank parameter is applied to multi-ranks per byte lane within a package

consisting of the same design die.
6. DQ-to-DQS differential jitter where the total includes the sum of deterministic and ran-
dom timing terms for a specified BER.
7. The deterministic component of the total timing.
8. This parameter will be characterized and guaranteed by design.
9. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c,
as measured from one falling edge to the next consecutive rising edge.
10. tQSH describes the instantaneous differential output high pulse width on DQS_t -
DQS_c, as measured from one falling edge to the next consecutive rising edge.
11. This parameter is a function of input clock jitter. These values assume MIN tCH(ABS) and
tCL(ABS). When the input clock jitter MIN tCH(ABS) and tCL(ABS) is 0.44 or greater than
tCK(AVG), the minimum value of tQSL will be tCL(ABS) - 0.04 and tQSH will be tCH(ABS) -
0.04.
Table 191: Write Timing

Note UI = tCK(AVG)(MIN)/2
Min/ Data Rate
Rx timing window total TdIVW_t
Max 0.22 0.25 UI 1, 2, 3
at VdIVW voltage levels otal
DQ and DMI input pulse
TdIPW Min 0.45 UI 7
width (at VCENT_DQ)
Min 200
DQ-to-DQS offset tDQS2DQ ps 6
Max 800
DQ-to-DQ offset tDQDQ Max 30 ps 7
DQ-to-DQS offset temper- tDQS2DQ
Max 0.6 ps/°C 8
ature variation _temp
DQ-to-DQS offset voltage tDQS2DQ
Max 33 ps/50mV 9
variation _volt
tDQS2DQ
DQ-to-DQS offset rank to
_rank2ra Max 200 ps 10, 11
rank variation
nk
WRITE command to first Min 0.75
tDQSS tCK(AVG)
DQS transition Max 1.25
DQS input HIGH-level tDQSH tCK(AVG)
Min 0.4
width
DQS input LOW-level tDQSL tCK(AVG)
Min 0.4
width
DQS falling edge to CK tDSS tCK(AVG)
Min 0.2
setup time
DQS falling edge from CK tDSH tCK(AVG)
Min 0.2
hold time
Write postamble tWPST Min 0.4 (or 1.4 if extra postamble is programmed in MR) tCK(AVG)
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AC Timing
Table 191: Write Timing (Continued)

Min/ Data Rate
Write preamble tWPRE Min 1.8 tCK(AVG)
Notes: 1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM
DQ-to-DQS voltage AC noise impact for frequencies >20 MHz with a maximum voltage
of 45mV peak-to-peak at a fixed temperature on the package. The voltage supply noise
must comply to the component MIN/MAX DC operating conditions.
2. Rx differential DQ-to-DQS jitter total timing window at the VdIVW voltage levels.
3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the in-
ternal VREF(DQ) range irrespective of the input signal common mode.
4. Rx mask defined for one pin toggling with other DQ signals in a steady state.
5. DQ-only minimum input pulse width defined at the VCENT_DQ(pin_mid).
6. DQ-to-DQS offset is within byte from DRAM pin to DRAM internal latch. Includes all
DRAM process, voltage, and temperature variations.
7. DQ-to-DQ offset defined within byte from DRAM pin to DRAM internal latch for a given
component.
8. tDQS2DQ(MAX) delay variation as a function of temperature.
9. tDQS2DQ(MAX) delay variation as a function of the DC voltage variation for VDDQ and
VDD2. It includes the VDDQ and VDD2 AC noise impact for frequencies >20 MHz and MAX
voltage of 45mV peak-to-peak from DC-20 MHz at a fixed temperature on the package.
10. The same voltage and temperature are applied to tDQS2DQ_rank2rank.
11. tDQS2DQ_rank2rank parameter is applied to multi-ranks per byte lane within a package
consisting of the same design die.
Table 192: CKE Input Timing
Min/ Data Rate

CKE minimum pulse width (HIGH tCKE Min MAX(7.5ns, 4nCK) ns 1
and LOW pulse width)
Delay from valid command to CKE tCMDCKE Min MAX(1.75ns, 3nCK) ns 1
input LOW
Valid clock requirement after CKE tCKELCK Min MAX(5ns, 5nCK) ns 1
input LOW
Valid CS requirement before CKE tCSCKE Min 1.75 ns
input LOW
Valid CS requirement after CKE in- tCKELCS Min MAX(5ns, 5nCK) ns 1
put LOW
Valid Clock requirement before tCKCKEH Min MAX(1.75ns, 3nCK) ns 1
CKE Input HIGH
Exit power-down to next valid tXP Min MAX(7.5ns, 5nCK) ns 1
command delay
Valid CS requirement before CKE tCSCKEH Min 1.75 ns
input HIGH
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AC Timing
Table 192: CKE Input Timing (Continued)
Min/ Data Rate

Valid CS requirement after CKE in- tCKEHCS Min MAX(7.5ns, 5nCK) ns 1
put HIGH
Valid clock and CS requirement
after CKE input LOW after MRW tMRWCKEL Min MAX(14ns, 10nCK) ns 1
command
Valid clock and CS requirement
after CKE input LOW after ZQCAL tZQCKE Min MAX(1.75ns, 3nCK) ns 1
START command
Note: 1. Delay time has to satisfy both analog time(ns) and clock count (nCK). For example,
tCMDCKE will not expire until CK has toggled through at least 3 full cycles (3tCK) and
3.75ns has transpired. The case that 3nCK is applied to is shown below.
Figure 168: tCMDCKE Timing
T-1 T0 T1 T2 T3 T4
CK_c
CK_t
tCMDCKE
CKE
CS
CA Valid Valid
Command Valid DES
Don’t Care
Table 193: Command Address Input Timing
Min/ Data Rate

Command/address valid
window (referenced from tcIVW Min 0.3 tCK(AVG) 1, 2, 3
CA VIL/VIH to CK VIX)
Address and control input
pulse width (referenced tcIPW Min 0.55 0.55 0.55 0.6 0.6 0.6 0.6 0.6 tCK(AVG) 4
to VREF)
Notes: 1. CA Rx mask timing parameters at the pin including voltage and temperature drift.
2. Rx differential CA to CK jitter total timing window at the VcIVW voltage levels.
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AC Timing
3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the in-
ternal VREF(CA) range irrespective of the input signal common mode.
4. CA only minimum input pulse width defined at the VCENT_CA(pin mid).
Table 194: Boot Timing Parameters (10–55 MHz)
Min/
Parameter Symbol Max Value Unit
Min 18
Clock cycle time tCKb ns
Max 100
DQS output data acess time Min 1.0
tDQSCKb ns
from CK Max 10.0
DQS edge to output data tDQSQb Max 1.2 ns
edge
Table 195: Mode Register Timing Parameters
Min/ Data Rate

MODE REGISTER WRITE (MRW) com- tMRW Min MAX(10ns, 10nCK) ns
mand period
MODE REGISTER SET command delay tMRD Min MAX(14ns, 10nCK) ns
MODE REGISTER READ (MRR) com- tMRR tCK(AVG)
Min 8
mand period
Additional time after tXP has expired
until the MRR command may be is- tMRRI Min tRCD(MIN) + 3nCK ns
sued
Delay from MRW command to DQS tSDO Max MAX(12nCK, 20ns) ns
driven out
Table 196: Core Timing Parameters

Refresh rate is determined by the value in MR4 OP[2:0]
Min/ Data Rate
READ latency (DBI disa- tCK(AVG)
RL-A Min 6 10 14 20 24 28 32 36
bled)
READ latency (DBI ena- tCK(AVG)
RL-B Min 6 12 16 22 28 32 36 40
bled)
WRITE latency (Set A) WL-A Min 4 6 8 10 12 14 16 18 tCK(AVG)
WRITE latency (Set B) WL-B Min 4 8 12 18 22 26 30 34 tCK(AVG)
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AC Timing
Table 196: Core Timing Parameters (Continued)

Refresh rate is determined by the value in MR4 OP[2:0]
Min/ Data Rate
tRAS + tRPab
ACTIVATE-to-ACTIVATE
tRC (with all-bank precharge)
command period (same Min tRAS + tRPpb ns
bank)
(with per-bank precharge)
Minimum self refresh tSR Min MAX(15ns, 3nCK) ns
time (entry to exit)
Self refresh exit to next tXSR Min MAX(tRFCab + 7.5ns, 2nCK) ns
valid command delay
CAS-to-CAS delay tCCD Min 8 tCK(AVG)
CAS-to-CAS delay masked tCCDMW tCK(AVG)

Min 32
write
Internal READ-to-PRE- tRTP Min MAX(7.5ns, 8nCK) ns
CHARGE command delay
RAS-to-CAS delay tRCD Min MAX(18ns, 4nCK) ns
Row precharge time (sin- tRPpb Min MAX(18ns, 3nCK) ns
gle bank)
Row precharge time (all tRPab Min MAX(21ns, 3nCK) ns
banks)
Min MAX(42ns, 3nCK) ns
Row active time tRAS
Max MIN(9 × tREFI × Refresh Rate, 70.2) µs
Write recovery time tWR Min MAX(18ns, 4nCK) ns
Write-to-read delay tWTR Min MAX(10ns, 8nCK) ns
MAX(
Active bank A to active tRRD Min MAX(10ns, 4nCK) 7.5ns, ns 1
bank B
4nCK)
Precharge-to-precharge tPPD tCK(AVG)
Min 4 2
delay
Four-bank activate win- tFAW Min 40 30 ns 1
dow
Delay from SRE command tESCKE Min MAX(1.75ns, 3nCK) – 3
to CKE input LOW
Notes: 1. 4267 Mb/s timing value is supported at lower data rates if the device is supporting 4266
Mb/s speed grade.
2. Precharge to precharge timing restriction does not apply to AUTO PRECHARGE com-
mands.
3. Delay time has to satisfy both analog time (ns) and clock count (nCK). It means that
tESCKE will not expire until CK has toggled through at least three full cycles (3 tCK) and
1.75ns has transpired. The case which 3nCK is applied to is shown below.
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AC Timing
Figure 169: tESCKE Timing
T-1 T0 T1 T2 T3 T4
CK_c
CK_t
t ESCKE
CKE
CS
CA Valid Valid
Command SELF Entry

REFRESH
DES
Don’t Care
Table 197: CA Bus ODT Timing
Min/ Data Rate

Parameter Symbol Max 533-4267
CA ODT value update time tODTUP Min RU(20ns/tCK(AVG))
Table 198: CA Bus Training Parameters
Min/ Data Rate

Valid clock requirement after CKE in- tCKELCK tCK
Min MAX(5ns, 5nCK)
put LOW
Data setup for VREF training mode tDStrain Min 2 ns
Data hold for VREF training mode tDHtrain Min 2 ns
Asynchronous data read tADR Max 20 ns
CA BUS TRAINING command-to-com- tCACD Min RU(tADR/tCK) tCK 1
mand delay
Valid strobe requirement before CKE tDQSCKE Min 10 ns
LOW
First CA BUS TRAINING command fol- tCAENT Min 250 ns
lowing CKE LOW
VREF step time – multiple steps tVREFca_LONG Max 250 ns
VREF step time – one step tVREFca_SHORT Max 80 ns
Valid clock requirement before CS tCKPRECS Min 2tCK + tXP –
HIGH
Valid clock requirement after CS tCKPSTCS Min MAX(7.5ns, 5nCK) –
HIGH
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AC Timing
Table 198: CA Bus Training Parameters (Continued)
Min/ Data Rate

Minimum delay from CS to DQS tog- tCS_VREF tCK
Min 2
gle in command bus training
Minimum delay from CKE HIGH to tCKEHDQS Min 10 ns
strobe High-Z
CA bus training CKE HIGH to DQ tri- tMRZ Min 1.5 ns
state
ODT turn-on latency from CKE tCKELODTon Min 20 ns
ODT turn-off latency from CKE tCKEHODToff Min 20 ns
tXCBT_Short Min MAX(200ns, 5nCK) – 2
Exit command bus training mode to tXCBT_Middle Min MAX(200ns, 5nCK) – 2
next valid command delay
tXCBT_Long Min MAX(250ns, 5nCK) – 2
Notes: 1. If tCACD is violated, the data for samples which violate tCACD will not be available, ex-
cept for the last sample (where tCACD after this sample is met). Valid data for the last
sample will be available after tADR.
2. Exit command bus training mode to next valid command delay time depends on value
of VREF(CA) setting: MR12 OP[5:0] and VREF(CA) range: MR12 OP[6] of FSP-OP 0 and 1. The
details are shown in tFC value mapping table. Additionally exit command bus training
mode to next valid command delay time may affect VREF(DQ) setting. Settling time of
VREF(DQ) level is same as VREF(CA) level.
Table 199: Asynchronous ODT Turn On and Turn Off Timing
Symbol 800–2133 MHz Unit

tODTon(MIN) 1.5 ns
tODTon(MAX) 3.5 ns
tODToff(MIN) 1.5 ns
tODToff(MAX) 3.5 ns
Table 200: Temperature Derating Parameters
Min/ Data Rate

DQS output access time from CK_t/CK_c tDQSCKd Max 3600 ps
(derated)
RAS-to-CAS delay (derated) tRCDd Min tRCD + 1.875 ns
ACTIVATE-to-ACTIVATE command period tRCd tRC
Min + 3.75 ns
(same bank, derated)
Row active time (derated) tRASd Min tRAS + 1.875 ns
Row precharge time (derated) tRPd Min tRP + 1.875 ns
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CA Rx Voltage and Timing
Table 200: Temperature Derating Parameters (Continued)
Min/ Data Rate

Active bank A to active bank B (derated) tRRDd Min tRRD + 1.875 ns
Note: 1. At higher temperatures (>85°C), AC timing derating may be required. If derating is re-
quired the device will set MR4 OP[2:0] = 110b.

The command and address (CA), including CS input receiver compliance mask for volt-
age and timing, is shown in the CA Receiver (Rx) Mask figure below. All CA and CS sig-
nals apply the same compliance mask and operate in single data rate mode.
The CA input Rx mask for voltage and timing is applied across all pins, as shown in the
figure below. The Rx mask defines the area that the input signal must not encroach if
the DRAM input receiver is expected to successfully capture a valid input signal; it is not
the valid data eye.
Figure 170: CA Receiver (Rx) Mask

tcIVW_total
Rx Mask
VcIVW VCENT_CA(pin mid)
Figure 171: Across Pin VREF (CA) Voltage Variation
CAx CAy CAz
VCENT_CAz
VCENT_CAx
VCENT_CAy
VREF variation
(component)
VCENT_CA(pin mid) is defined as the midpoint between the largest V CENT_CA voltage level
and the smallest V CENT_CA voltage level across all CA and CS pins for a given DRAM
component. Each CA V CENT level is defined by the center, which is, the widest opening
of the cumulative data input eye, as depicted in the figure above. This clarifies that any
CCM005-554574167-10729

DRAM component level variation must be accounted for within the CA Rx mask. The
component-level V REF will be set by the system to account for RON and ODT settings.
Figure 172: CA Timings at the DRAM Pins
CK, CK Data-in at DRAM Pin

Minimum CA eye center aligned
CK_c
CK_t
Rx mask
VcIVW
CA
DRAM pin
tcIVW
TcIVW for all CA signals is defined as centered on

the CK_t/CK_c crossing at the DRAM pin.
Note: 1. All of the timing terms in above figure are measured from the CK_t/CK_c to the center
(midpoint) of the TcIVW window taken at the VcIVW_total voltage levels centered
around VCENT_CA(pin mid).
Figure 173: CA tcIPW and SRIN_cIVW Definition (for Each Input Pulse)
tr tf
Rx Mask
VCENT_CA(pin mid) VcIVW
tcIPW
Note: 1. SRIN_cIVW = VdIVW_total/(tr or tf); signal must be monotonic within tr and tf range.
Figure 174: CA VIHL_AC Definition (for Each Input Pulse)
VIHL(AC)min/2
VCENT_CA
Rx Mask Rx Mask Rx Mask VcIVW
VIHL(AC)min/2
CCM005-554574167-10729

Table 201: DRAM CMD/ADR, CS

UI = tCK(AVG)MIN
DQ – DQ –
DQ – 13337 1600/1867 3200/3733 DQ – 4267
Symbol Parameter Min Max Min Max Min Max Min Max Unit Notes
VclVW Rx mask voltage peak-to- – 175 – 175 – 155 – 145 mV 1, 2, 3
peak
VIHL(AC) CA AC input pulse ampli- 210 – 210 – 190 – 180 – mV 4, 6
tude peak-to-peak
SRIN_clVW Input slew rate over VclVW 1 7 1 7 1 7 1 7 V/ns 5
Notes: 1. CA Rx mask voltage and timing parameters at the pin, including voltage and tempera-
ture drift.
2. Rx mask voltage VcIVW total(MAX) must be centered around VCENT_CA(pin mid).
3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the in-
ternal VREF(CA) range irrespective of the input signal common mode.
4. CA-only input pulse signal amplitude into the receiver must meet or exceed VIHL(AC) at
any point over the total UI. No timing requirement above level. VIHL(AC) is the peak-to-
peak voltage centered around VCENT_CA(pin mid), such that VIHL(AC)/2 (MIN) must be met
both above and below VCENT_CA.
5. Input slew rate over VcIVW mask is centered at VCENT_CA(pin mid).
6. VIHL(AC) does not have to be met when no transitions are occurring.
7. The Rx voltage and absolute timing requirements apply for DQ operating frequencies at
or below 1333 for all speed bins. For example the tcIVW (ps) = 450ps at or below 1333
operating frequencies.
CCM005-554574167-10729

DQ Tx Voltage and Timing
DQ Tx Voltage and Timing

DRAM Data Timing
Figure 175: Read Data Timing Definitions – tQH and tDQSQ Across DQ Signals per DQS Group
tQSH(DQS_t) tQSL(DQS_t)
DQS_c
DQS_t
tQH
tDQSQ
Associated
DQ pins
DQS_c
DQS_t
tQW
DQx
tQW
DQy
tQW
DQz
CCM005-554574167-10729

DQ Rx Voltage and Timing

The DQ input receiver mask for voltage and timing is applied per pin, as shown in the
DQ Receiver (Rx) Mask figure below. The total mask (V dIVW_total, TdIVW_total) defines
the area that the input signal must not encroach in order for the DQ input receiver to
successfully capture an input signal. The mask is a receiver property, and it is not the
valid data eye.
Figure 176: DQ Receiver (Rx) Mask

TdIVW_total
Rx Mask
VdIVW VCENT_DQ(pin mid)
Figure 177: Across Pin VREF DQ Voltage Variation
DQx DQy DQz
VCENT_DQz
VCENT_DQx
VCENT_DQy
VREF variation
(component)
VCENT_DQ(pin_mid) is defined as the midpoint between the largest V CENT_DQ voltage level
and the smallest V CENT_DQ voltage level across all DQ pins for a given DRAM compo-
nent. Each V CENT_DQ is defined by the center, which is the widest opening of the cumu-
lative data input eye as shown in the figure above. This clarifies that any DRAM compo-
nent level variation must be accounted for within the DRAM Rx mask. The component-
level V REF will be set by the system to account for RON and ODT settings.
CCM005-554574167-10729

Figure 178: DQ-to-DQS tDQS2DQ and tDQDQ
DQ, DQS Data-in at DRAM Latch DQS, DQs Data-in Skews at DRAM
Internal componsite data-eye center aligned to DQS Nonminimum data-eye/maximum Rx mask
DQS_c DQS_c
DQS_t DQS_t
tDQS2DQ2
VdIVW_total
DQx, y, z DQx Rx mask
DRAM pin
tDQS2DQy2
All DQ signals center aligned to the
strobe at the device internal latch
VdIVW_total
DQy Rx mask
DRAM pin
tDQS2DQz2
VdIVW_total
DQz Rx mask
DRAM pin
tDQDQ
Notes: 1. These timings at the DRAM pins are referenced from the internal latch.
2. tDQS2DQ is measured at the center (midpoint) of the TdIVW window.
3. DQz represents the MAX tDQS2DQ in this example.
4. DQy represents the MIN tDQS2DQ in this example.
All of the timing terms in DQ to DQS_t are measured from the DQS_t/DQS_c to the cen-
ter (midpoint) of the TdIVW window taken at the V dIVW_total voltage levels centered
around V CENT_DQ(pin_mid). In figure above, the timings at the pins are referenced with re-
spect to all DQ signals center-aligned to the DRAM internal latch. The data-to-data off-
set is defined as the difference between the MIN and MAX tDQS2DQ for a given compo-
nent.
CCM005-554574167-10729

Figure 179: DQ tDIPW and SRIN_dIVW Definition for Each Input Pulse
UI = tCK(AVG) MIN/2
tr tf
Rx Mask
VCENT_DQ(pin mid) VDIVW_total
tDIPW
Note: 1. SRIN_dIVW = VdIVW_total/(tr or tf) signal must be monotonic within tr and tf range.
Figure 180: DQ VIHL(AC) Definition (for Each Input Pulse)
VIHL(AC)min/2
VCENT_DQ VdIVW_total
Rx Mask Rx Mask Rx Mask
VIHL(AC)min/2
Table 202: DQs In Receive Mode

1600/1867 2133/2400 3200/3733 4267
Symbol Parameter Min Max Min Max Min Max Min Max Unit Notes
VdIVW_total Rx mask voltage – peak-to- – 140 – 140 – 140 – 120 mV 1, 2, 3
peak
VIHL(AC) DQ AC input pulse ampli- 180 – 180 – 180 – 170 – mV 5, 7
tude peak-to-peak
SRIN_dIVW Input slew rate over 1 7 1 7 1 7 1 7 V/ns 6
VdIVW_total
Notes: 1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM
DQ-to-DQS voltage AC noise impact for frequencies >20 MHz with a maximum voltage
of 45mV peak-to-peak at a fixed temperature on the package. The voltage supply noise
must comply to the component MIN/MAX DC operating conditions.
2. Rx mask voltage VdIVW_total(MAX) must be centered around VCENT_DQ(pin_mid).
3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the in-
ternal VREF DQ range irrespective of the input signal common mode.
4. Deterministic component of the total Rx mask voltage or timing. Parameter will be char-
acterized and guaranteed by design.
5. DQ-only input pulse amplitude into the receiver must meet or exceed VIHL(AC) at any
point over the total UI. No timing requirement above level. VIHL(AC) is the peak-to-peak
voltage centered around VCENT_DQ(pin_mid), such that VIHL(AC)/2 (MIN) must be met both
above and below VCENT_DQ.
6. Input slew rate over VdIVW mask centered at VCENT_DQ(pin_mid).
CCM005-554574167-10729

Clock Specification
7. VIHL(AC) does not have to be met when no transitions are occurring.
Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks vio-
lating minimum or maximum values may result in device malfunction.
Table 203: Definitions and Calculations
Symbol Description Calculation Notes

tCK(avg) and The average clock period across any consecutive N
nCK 200-cycle window. Each clock period is calculated tCK(avg) = Σ tCK j /N

j=1
from rising clock edge to rising clock edge.
Where N = 200
Unit tCK(avg) represents the actual clock average
tCK(avg) of the input clock under operation. Unit
nCK represents one clock cycle of the input clock,

counting from actual clock edge to actual clock
edge.
tCK(avg) can change no more than ±1% within a
100-clock-cycle window, provided that all jitter
and timing specifications are met.
tCK(abs) The absolute clock period, as measured from one 1
rising clock edge to the next consecutive rising
clock edge.
tCH(avg) The average HIGH pulse width, as calculated N
across any 200 consecutive HIGH pulses. tCH(avg) = Σ tCH j /(N × tCK(avg))
j=1
Where N = 200
tCL(avg) The average LOW pulse width, as calculated N
across any 200 consecutive LOW pulses. tCL(avg) = Σ tCL j /(N × tCK(avg))
j=1
Where N = 200
tJIT(per) The single-period jitter defined as the largest de- 1
tJIT(per) = min/max of tCK – tCK(avg)
viation of any signal tCK from tCK(avg). i
Where i = 1 to 200
tJIT(per),act The actual clock jitter for a given system.
tJIT(per), The specified clock period jitter allowance.
allowed
tJIT(cc) The absolute difference in clock periods between 1
tJIT(cc) = max of tCK t
two consecutive clock cycles. tJIT(cc) defines the i + 1 – CKi
cycle-to-cycle jitter.
tERR(nper) The cumulative error across n multiple consecu- i+n–1 1
tive cycles from tCK(avg). tERR(nper) = Σ tCK – (n × tCK(avg))
j
j=i
tERR(nper),act The actual clock jitter over n cycles for a given

system.
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Clock Period Jitter
Table 203: Definitions and Calculations (Continued)
Symbol Description Calculation Notes

tERR(nper), The specified clock jitter allowance over n cycles.
allowed
tERR(nper),min The minimum tERR(nper). tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min 2
tERR(nper),max The maximum tERR(nper). tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max 2
tJIT(duty) Defined with absolute and average specifications tJIT(duty),min =
for tCH and tCL, respectively. MIN((tCH(abs),min – tCH(avg),min),
(tCL(abs),min – tCL(avg),min)) × tCK(avg)
tJIT(duty),max =
MAX((tCH(abs),max – tCH(avg),max),
(tCL(abs),max – tCL(avg),max)) × tCK(avg)
Notes: 1. Not subject to production testing.

2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
tCK(abs), tCH(abs), and tCL(abs)

These parameters are specified with their average values; however, the relationship be-
tween the average timing and the absolute instantaneous timing (defined in the follow-
ing table) is applicable at all times.
Table 204: tCK(abs), tCH(abs), and tCL(abs) Definitions
Parameter Symbol Minimum Unit

Absolute clock period tCK(abs) tCK(avg),min + tJIT(per),min ps1
Absolute clock HIGH pulse width tCH(abs) tCH(avg),min + tJIT(duty),min2/tCK(avg),min tCK(avg)
Absolute clock LOW pulse width tCL(abs) tCL(avg),min + tJIT(duty),min2/tCK(avg),min tCK(avg)
Notes: 1. tCK(avg),min is expressed in ps for this table.

2. tJIT(duty),min is a negative value.
Clock Period Jitter

LPDDR4 devices can tolerate some clock period jitter without core timing parameter
derating. This section describes device timing requirements with clock period jitter
(tJIT(per)) in excess of the values found in the AC Timing table. Calculating cycle time
derating and clock cycle derating are also described.
Clock Period Jitter Effects on Core Timing Parameters

Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) ex-
tend across multiple clock cycles. Clock period jitter impacts these parameters when
measured in numbers of clock cycles. Within the specification limits, the device is char-
acterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device op-
eration where clock jitter is outside specification limits, the number of clocks, or
tCK(avg), may need to be increased based on the values for each core timing parameter.
CCM005-554574167-10729

Clock Period Jitter
Cycle Time Derating for Core Timing Parameters

For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed
tERR(tnPARAM),allowed, cycle time derating may be required for core timing parame-
ters.
t t t t t
CycleTimeDerating = max PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tCK(avg) , 0
tnPARAM
Cycle time derating analysis should be conducted for each core timing parameter. The
amount of cycle time derating required is the maximum of the cycle time deratings de-
termined for each individual core timing parameter.
Clock Cycle Derating for Core Timing Parameters

For each core timing parameter and a given number of clocks (tnPARAM), clock cycle
derating should be specified with tJIT(per).
For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) ex-
ceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the
equation below results in a positive value for a core timing parameter (tCORE), the re-
quired clock cycle derating will be that positive value (in clocks).
t t t t t
ClockCycleDerating = RU PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tnPARAM
tCK(avg)
Cycle-time derating analysis should be conducted for each core timing parameter.
Clock Jitter Effects on Command/Address Timing Parameters

Command/address timing parameters (tIS, tIH, tISb, tIHb) are measured from a com-
mand/address signal (CS or CA[5:0]) transition edge to its respective clock signal (CK_t/
CK_c) crossing. The specification values are not affected by the tJIT(per) applied, be-
cause the setup and hold times are relative to the clock signal crossing that latches the
command/address. Regardless of clock jitter values, these values must be met.
Clock Jitter Effects on READ Timing Parameters

tRPRE
When the device is operated with input clock jitter, tRPRE must be derated by the
tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output derat-
ings are relative to the input clock:
tRPRE(min,derated) = 0.9 – tJIT(per),act,max – tJIT(per),allowed,max

tCK(avg)
For example, if the measured jitter into a LPDDR4 device has tCK(avg) = 625ps,
tJIT(per),act,min = –xx, and tJIT(per),act,max = +xx ps, then tRPRE,min,derated = 0.9 -
(tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (xx - xx)/xx = yy tCK(avg).
CCM005-554574167-10729

Clock Period Jitter
tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
These parameters are measured from a specific clock edge to a data signal transition
(DMn or DQm, where: n = 0,1; and m = 0–15, and specified timings must be met with
respect to that clock edge. Therefore, they are not affected by tJIT(per).
tQSH, tQSL
These parameters are affected by duty cycle jitter, represented by tCH(abs)min and
tCL(abs)min. These parameters determine the absolute data-valid window at the device
pin. The absolute minimum data-valid window at the device pin = MIN {( tQSH(abs)min
- tDQSQmax), (tQSL(abs)min - tDQSQmax)}. This minimum data valid window must be
met at the target frequency regardless of clock jitter.
tRPST
tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min

can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.
Clock Jitter Effects on WRITE Timing Parameters

tDS, tDH
These parameters are measured from a data signal (DMIn or DQm, where n = 0, 1 and m
= 0–15) transition edge to its respective data strobe signal (DQSn_t, DQSn_c: n = 0,1)
crossing. The specification values are not affected by the amount of tJIT(per) applied,
because the setup and hold times are relative to the data strobe signal crossing that
latches the command/address. Regardless of clock jitter values, these values must be
met.
tDSS, tDSH
These parameters are measured from a data signal (DQS_t, DQSn_c) crossing to its re-
spective clock signal (CK_t, CK_c) crossing. When the device is operated with input
clock jitter, this parameter needs to be derated by the actual tJIT(per)act of the input clock
in excess of the allowed period jitter tJIT(per)allowed.
tDQSS
tDQSS is measured from a data strobe signal (DQSn_t, DQSn_c) crossing to its respec-
tive clock signal (CK_t, CK_c) crossing. When the device is operated with input clock jit-
ter, this parameter must be derated by the actual tJIT(per),act of the input clock in ex-
cess of tJIT(per)allowed.
tDQSS(min,derated) = 0.75 - tJIT(per),act,min – tJIT(per),allowed, min

tCK(avg)
tDQSS(max,derated) = 1.25 – tJIT(per),act,max – tJIT(per),allowed, max

tCK(avg)
For example, if the measured jitter into an LPDDR4 device has tCK(avg) = 625ps,
tJIT(per),act,min = -xxps, and tJIT(per),act,max = +xx ps, then:
tDQSS,(min,derated) = 0.75 - (-xx + yy)/625 = xxxx tCK(avg)
tDQSS,(max,derated) = 1.25 - (xx – yy)/625 = xxxx tCK(avg)
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
LPDDR4 1.10V VDDQ

This section defines LPDDR4 specifications to enable 1.10 V DDQ operation of LPDDR4
devices.
Power-Up and Initialization - LPDDR4

To ensure proper functionality for power-up and reset initialization, default values for
the MR settings are provided in the table below.
Table 205: Mode Register Default Settings
Item Mode Register Setting Default Setting Description

FSP-OP/WR MR13 OP[7:6] 00b FSP-OP/WR[0] are enabled
WLS MR2 OP[6] 0b WRITE latency set A is selected
WL MR2 OP[5:3] 000b WL = 4
RL MR2 OP[2:0] 000b RL = 6, nRTP = 8
nWR MR1 OP[6:4] 000b nWR = 6
DBI-WR/RD MR3 OP[7:6] 00b Write and read DBI are disa-
bled
CA ODT MR11 OP[6:4] 000b CA ODT is disabled
DQ ODT MR11 OP[2:0] 000b DQ ODT is disabled
VREF(CA) setting MR12 OP[6] 1b VREF(CA) range[1] is enabled
VREF(CA) value MR12 OP[5:0] 001101b Range1: 27.2% of VDD2
VREF(DQ) setting MR14 OP[6] 1b VREF(DQ) range[1] enabled
VREF(DQ) value MR14 OP[5:0] 001101b Range1: 27.2% of VDDQ
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Mode Register Definition - LPDDR4

Mode register definitions are provided in the Mode Register Assignments table. In the
access column of the table, R indicates read-only; W indicates write-only; R/W indicates
read- or write-capable or enabled. The MRR command is used to read from a register.
The MRW command is used to write to a register.
Table 206: Mode Register Assignments

0 00h Device info R CATR RFU RFU RZQI RFU Latency REF
mode
1 01h Device feature 1 W RD-PST nWR (for AP) RD-PRE WR-PRE BL
2 02h Device feature 2 W WR Lev WLS WL RL
3 03h I/O config-1 W DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL
4 04h Refresh and R /W TUF Thermal offset PPRE SR abort Refresh rate
training
5 05h Basic config-1 R Manufacturer ID
8 08h Basic config-4 R I/O width Density Type
9 09h Test mode W Vendor-specific test mode
10 0Ah I/O calibration W RFU ZQ RST
11 0Bh ODT W RFU CA ODT RFU DQ ODT
12 0Ch VREF(CA) R/W RFU VRCA VREF(CA)
13 0Dh Register control W FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT
14 0Eh VREF(DQ) R/W RFU VRDQ VREF(DQ)
15 0Fh DQI-LB W Lower-byte invert register for DQ calibration
16 10h PASR_Bank W PASR bank mask
17 11h PASR_Seg W PASR segment mask
18 12h IT-LSB R DQS oscillator count – LSB
19 13h IT-MSB R DQS oscillator count – MSB
20 14h DQI-UB W Upper-byte invert register for DQ calibration
21 15h Vendor use W RFU
22 16h ODT feature 2 W ODTD for x8_2ch ODTD- ODTE-CS ODTE- SoC ODT
CA CK
23 17h DQS oscillator W DQS oscillator run-time setting
stop
24 18h TRR control R/W TRR TRR mode BAn Unltd MAC value
mode MAC
25 19h PPR resources R B7 B6 B5 B4 B3 B2 B1 B0
26–29 1Ah~1D – – Reserved for future use
h
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Table 206: Mode Register Assignments (Continued)

30 1Eh Reserved for W SDRAM will ignore
test
31 1Fh – – Reserved for future use
pattern A
33–38 21h≈26h Do not use – Do not use
39 27h Reserved for W SDRAM will ignore
test
pattern B
41–47 29h≈2Fh Do not use – Do not use
48–63 30h≈3Fh Reserved – Reserved for future use
Notes: 1. RFU bits must be set to 0 during MRW commands.

2. RFU bits are read as 0 during MRR commands.
3. All mode registers that are specified as RFU or write-only shall return undefined data
when read via an MRR command.
4. RFU mode registers must not be written.
5. Writes to read-only registers will not affect the functionality of the device.

CATR RFU RZQI RFU Latency mode REF

Refresh mode Read OP[0] 0b: Both legacy and modified refresh mode supported
only 1b: Only modified refresh mode supported
Latency mode Read OP[1] 0b: Device supports normal latency 5, 6
only 1b: Device supports byte mode latency
Built-in self-test for RZQ in- Read OP[4:3] 00b: RZQ self-test not supported 1–4
formation only 01b: ZQ may connect to VSSQ or float
10b: ZQ may short to VDDQ
11b: ZQ pin self-test completed, no error condition de-
tected (ZQ may not connect to VSSQ, float, or short to
VDDQ)
CCM005-554574167-10729

LPDDR4 1.10V VDDQ

CA terminating rank Read OP[7] 0b: CA for this rank is not terminated 7
only 1b: CA for this rank is terminated
Notes: 1. RZQI MR value, if supported, will be valid after the following sequence:
• Completion of MPC[ZQCAL START] command to either channel
• Completion of MPC[ZQCAL LATCH] command to either channel then tZQLAT is satis-
fied
RZQI value will be lost after reset.
2. If ZQ is connected to VSSQ to set default calibration, OP[4:3] must be set to 01b. If ZQ is
not connected to VSSQ, either OP[4:3] = 01b or OP[4:3] = 10b might indicate a ZQ pin as-
sembly error. It is recommended that the assembly error be corrected.
3. In the case of possible assembly error, the device will default to factory trim settings for
RON, and will ignore ZQ CALIBRATION commands. In either case, the device may not
function as intended.
4. If the ZQ pin self-test returns OP[4:3] = 11b, the device has detected a resistor connected
to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or
that the ZQ resistor meets the specified limits (that is, 240Ω ±1%).
5. See byte mode addendum spec for byte mode latency details.
6. Byte mode latency for 2Ch. x16 device is only allowed when it is stacked in a same pack-
age with byte mode device.
7. CATR indicates whether CA for the rank will be terminated or not as a result of ODTCA
pad connection and MR22 OP[5] settings for x16 devices, MR22 OP[7:5] settings for byte
mode devices.
Table 209: MR3 I/O Configuration 1 (MA[5:0] = 03h)

DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL
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LPDDR4 1.10V VDDQ

PU-CAL OP[0] 0b: VDDQ/2.5 1-4
(Pull-up calibration point) 1b: VDDQ/3 (default)
WR-PST (WR postamble length) OP[1] 0b: WR postamble = 0.5 × tCK (default) 2, 3, 5
1b: WR postamble = 1.5 × tCK
PPRP (Post-package repair protec- OP[2] 0b: PPR protection disabled (default) 6
tion) 1b: PPR protection enabled
PDDS 000b: RFU 1, 2, 3
(Pull-down drive strength) 001b: RZQ/1
010b: RZQ/2
Write-only
011b: RZQ/3
OP[5:3]
100b: RZQ/4
101b: RZQ/5
110b:RZQ/6 (default)
111b: Reserved
DBI-RD OP[6] 0b: Disabled (default) 2, 3
(DBI-read enable) 1b: Enabled
DBI-WR OP[7] 0b: Disabled (default) 2, 3
(DBI-write enable) 1b: Enabled
ance for a given voltage and temperature. Recalibration may be required as voltage and
temperature vary.
2. There are two physical registers assigned to each bit of this MR parameter, designated
set point 0 and set point 1.The device will operate only according to the values stored in
the registers for the active set point, for example, the set point determined by the state
of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will
be determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers
for the inactive set point will be ignored by the device, and may be changed without
affecting device operation.
4. For dual channel device, PU‐CAL (MR3‐OP[0]) must be set the same for both channels on
a die. The SDRAM will read the value of only one register (Ch.A or Ch.B), vendor-specif-
ic, so both channels must be set the same.
5. 1.5 × tCK apply > 1.6 GHz clock.
6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a
sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR
mode. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4
OP[4].
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Table 211: MR12 Register Information (MA[5:0] = 0Ch)

RFU VRCA VREF(CA)

VREF(CA) Read/ OP[5:0] 000000b–110010b: See VREF Settings Table 1–3, 5, 6
VREF(CA) settings Write All others: Reserved
VRCA Read/ OP[6] 0b: VREF(CA) range[0] enabled 1, 2, 4, 5,
VREF(CA) range Write 1b: VREF(CA) range[1] enabled (default) 6
Notes: 1. This register controls the VREF(CA) levels for frequency set point[1:0]. Values from either
VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately.
2. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ
will be set to 0. See the MRR Operation section.
3. A write to MR12 OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6] = 0b
or sets the internal VREF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for
VREF(CA) to reach the set level depends on the step size from the current level to the new
level. See the VREF(CA) training section.
4. A write to MR12 OP[6] switches the device between two internal VREF(CA) ranges. The
range (range[0] or range[1]) must be selected when setting the VREF(CA) register. The val-
ue, once set, will be retained until overwritten or until the next power‐on or reset
event.
ation.
Table 213: Mode Register 14 (MA[5:0] = 0Eh)

RFU VRDQ VREF(DQ)
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LPDDR4 1.10V VDDQ

VREF(DQ) Read/ OP[5:0] 000000b–110010b: See VREF Settings table 1–3, 5, 6
VREF(DQ) setting Write All others: Reserved
VRDQ OP[6] 0b: VREF(DQ) range[0] enabled 1, 2, 4–6
VREF(DQ) range 1b: VREF(DQ) range[1] enabled (default)
Notes: 1. This register controls the VREF(DQ) levels for frequency set point[1:0]. Values from either
VRDQ [vendor defined] or VRDQ [vendor defined] may be selected by setting OP[6] ap-
propriately.
2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and
unused DQ will be set to 0. See the MRR Operation section.
3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or
sets FSP[1] when MR13 OP[6] = 1b. The time required for VREF(DQ) to reach the set level
depends on the step size from the current level to the new level. See the VREF(DQ) train-
ing section.
4. A write to OP[6] switches the device between two internal VREF(DQ) ranges. The range
(range[0] or range[1]) must be selected when setting the VREF(DQ) register. The value,
once set, will be retained until overwritten, or until the next power‐on or reset event.
set point 0, and set point 1. The device will operate only according to the values stored
ation.
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LPDDR4 1.10V VDDQ
Table 215: VREF Setting for Range[0] and Range[1]

Range[0] Values Range[1] Values
VREF(CA) (% of VDD2 ) VREF(CA) (% of VDD2 )
Function OP VREF(DQ) (% of VDDQ ) VREF(DQ) (% of VDDQ )

VREF setting OP[5:0] 000000b: 10.0% 011010b: 20.4% 000000b: 22.0% 011010b: 32.4%
for MR12 000001b: 10.4% 011011b: 20.8% 000001b: 22.4% 011011b: 32.8%
and MR14
000010b: 10.8% 011100b: 21.2% 000010b: 22.8% 011100b: 33.2%
000011b: 11.2% 011101b: 21.6% 000011b: 23.2% 011101b: 33.6%
000100b: 11.6% 011110b: 22.0% 000100b: 23.6% 011110b: 34.0%
000101b: 12.0% 011111b: 22.4% 000101b: 24.0% 011111b: 34.4%
000110b: 12.4% 100000b: 22.8% 000110b: 24.4% 100000b: 34.8%
000111b: 12.8% 100001b: 23.2% 000111b: 24.8% 100001b: 35.2%
001000b: 13.2% 100010b: 23.6% 001000b: 25.2% 100010b: 35.6%
001001b: 13.6% 100011b: 24.0% 001001b: 25.6% 100011b: 36.0%
001010b: 14.0% 100100b: 24.4% 001010b: 26.0% 100100b: 36.4%
001011b: 14.4% 100101b: 24.8% 001011b: 26.4% 100101b: 36.8%
001100b: 14.8% 100110b: 25.2% 001100b: 26.8% 100110b: 37.2%
001101b: 15.2% 100111b: 25.6% 001101b: 27.2% de- 100111b: 37.6%
fault
001110b: 15.6% 101000b: 26.0% 001110b: 27.6% 101000b: 38.0%
001111b: 16.0% 101001b: 26.4% 001111b: 28.0% 101001b: 38.4%
010000b: 16.4% 101010b: 26.8% 010000b: 28.4% 101010b: 38.8%
010001b: 16.8% 101011b: 27.2% 010001b: 28.8% 101011b: 39.2%
010010b: 17.2% 101100b: 27.6% 010010b: 29.2% 101100b: 39.6%
010011b: 17.6% 101101b: 28.0% 010011b: 29.6% 101101b: 40.0%
010100b: 18.0% 101110b: 28.4% 010100b: 30.0% 101110b: 40.4%
010101b: 18.4% 101111b: 28.8% 010101b: 30.4% 101111b: 40.8%
010110b: 18.8% 110000b: 29.2% 010110b: 30.8% 110000b: 41.2%
010111b: 19.2% 110001b: 29.6% 010111b: 31.2% 110001b: 41.6%
011000b: 19.6% 110010b: 30.0% 011000b: 31.6% 110010b: 42.0%
011001b: 20.0% All others: Reserved 011001b: 32.0% All others: Reserved
Notes: 1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or
VREF(DQ) levels in the device.
2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] ap-
propriately.
3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set
points each for CA and DQ are provided to allow for faster switching between termina-
ted and unterminated operation or between different high‐frequency settings, which
may use different terminations values.
CCM005-554574167-10729

LPDDR4 1.10V VDDQ

ODTD for x8_2ch ODTD-CA ODTE-CS ODTE-CK SOC ODT

SOC ODT (controller ODT val- Write-only OP[2:0] 000b: Disable (default) 1, 2, 3
ue for VOH calibration) 001b: RZQ/1
010b: RZQ/2
011b: RZQ/3
100b: RZQ/4
101b: RZQ/5
110b: RZQ/6
111b: RFU
ODTE-CK (CK ODT enabled Write-only OP[3] 0b: ODT-CK override disabled (default) 2, 3, 4, 6, 8
for non-terminating rank) 1b: ODT-CK override enabled
ODTE-CS (CS ODT enabled for Write-only OP[4] 0b: ODT-CS override disabled (default) 2, 3, 5, 6, 8
non-terminating rank) 1b: ODT-CS override enabled
ODTD-CA (CA ODT termina- Write-only OP[5] 0b: CA ODT obeys ODT_CA bond pad (default) 2, 3, 6, 7, 8
tion disable) 1b: CA ODT disabled
ODTD for x8_2ch (Byte) mode Write-only OP[7:6] See Byte Mode section
Notes: 1. All values are typical.

of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command or read from
with an MRR command to this address.
in the registers for the active set point determined by the state of the FSP-OP bit (MR13
OP[7]). The values in the registers for the inactive set point will be ignored by the device
and may be changed without affecting device operation.
4. When OP[3] = 1 the CK signals will be terminated to the value set by MR11 OP[6:4] re-
gardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for
configurations where CA is shared by two or more devices but CK is not, enabling CK to
terminate on all devices.
5. When OP[4] = 1 the CS signal will be terminated to the value set by MR11 OP[6:4] re-
gardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for
configurations where CA is shared by two or more devices but CS is not, enabling CS to
terminate on all devices.
6. For system configurations where the CK, CS, and CA signals are shared between pack-
ages, the package design should provide for the ODT_CA ball to be bonded on the sys-
tem board outside of the memory package. This provides the necessary control of the
ODT function for all die with shared command bus signals.
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
7. When OP[5] = 0, CA[5:0] will terminate when the ODT_CA bond pad is HIGH and MR11
OP[6:4] is valid and disable termination when ODT_CA is LOW or MR11 OP[6:4] is disa-
bled. When OP[5] = 1, termination for CA[5:0] is disabled regardless of the state of the
ODT_CA bond pad or MR11 OP[6:4].
8. To ensure proper operation in a multi-rank configuration, when CA, CK or CS ODT is en-
abled via MR11 OP[6:4] and also via MR22 or ODT_CA pad setting, the rank providing
ODT will continue to terminate the command bus in all DRAM states including Active,
Self-refresh, Self-refresh Power-down, Active Power-down and Precharge Power-down.
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Burst READ Operation - LPDDR4 ATE Condition

tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation
tHZ and tLZ transitions occur in the same time window as valid data transitions. These
parameters are referenced to a specific voltage level that specifies when the device out-
put is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and
tLZ(DQ). This section shows a method to calculate the point when the device is no lon-
ger driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by meas-
uring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ),
tHZ(DQS), and tHZ(DQ) are defined as single ended.
tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment)
Figure 181: tLZ(DQS) Method for Calculating Transitions and Endpoint

CK_t
CK_c
tLZ(DQS)
VOH DQS_c
VSW2
0.5 x VOH
VSW1

0V
Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3.
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Figure 182: tHZ(DQS) Method for Calculating Transitions and Endpoint

CK_t
CK_c
tHZ(DQS)
VOH
VSW2
0.5 x VOH
VSW1
0V DQS_c
Table 218: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements
Measured Parameter
DQS_c Low-Z time tLZ(DQS) 0.4 × VOH 0.6 × VOH V
from CK_t, CK_c
DQS_c High-Z time tHZ(DQS) 0.4 × VOH 0.6 × VOH
from CK_t, CK_c
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment)
Figure 183: tLZ(DQ) Method for Calculating Transitions and Endpoint

CK_t
CK_c
t LZ(DQ)
VOH DQs
VSW2
0.5 x VOH
VSW1

0V
Figure 184: tHZ(DQ) Method for Calculating Transitions and Endpoint

CK_t
CK_c
tHZ(DQ)
VOH
VSW2
0.5 x VOH
VSW1
0V DQs
CCM005-554574167-10729

LPDDR4 1.10V VDDQ

Table 219: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements
Measured Parameter
DQ Low-Z time tLZ(DQ) 0.4 × VOH 0.6 × VOH V
from CK_t, CK_c
DQ High-Z time tHZ(DQ) 0.4 × VOH 0.6 × VOH
from CK_t, CK_c
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LPDDR4 1.10V VDDQ
VREF Specifications - LPDDR4

Internal VREF(CA) Specifications
The device's internal V REF(CA) specification parameters are operating voltage range, step
size, V REF step time, V REF full-range step time, and V REF valid level.
Table 220: Internal VREF(CA) Specifications

VREF(CA),max_r0 VREF(CA) range-0 MAX operat- – – 30% VDD2 1, 11
ing point
VREF(CA),min_r0 VREF(CA) range-0 MIN operat- 10% – – VDD2 1, 11
ing point
VREF(CA),max_r1 VREF(CA) range-1 MAX operat- – – 42% VDD2 1, 11
ing point
VREF(CA),min_r1 VREF(CA) range-1 MIN operat- 22% – – VDD2 1, 11
ing point
VREF(CA),step VREF(CA) step size 0.30% 0.40% 0.50% VDD2 2
VREF(CA),set_tol VREF(CA) set tolerance –1.00% 0.00% 1.00% VDD2 3, 4, 6
–0.10% 0.00% 0.10% VDD2 3, 5, 7
tV
REF_TIME-SHORT VREF(CA) step time – – 100 ns 8
tV
tV
tV – – 1 ms 13, 14
REF_time_weak
VREF(CA)_val_tol VREF(CA) valid tolerance –0.10% 0.00% 0.10% VDD2 10
Notes: 1. VREF(CA) DC voltage referenced to VDD2(DC).

2. VREF(CA) step size increment/decrement range. VREF(CA) at DC level.
3. VREF(CA),new = VREF(CA),old + n × VREF(CA),step; n = number of steps; if increment, use "+"; if
4. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 1.0% × VDD2. The maxi-
mum value of VREF(CA) setting tolerance = VREF(CA),new + 1.0% × VDD2. For n > 4.
5. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 0.10% × VDD2. The maxi-
mum value of VREF(CA) setting tolerance = VREF(CA),new + 0.10% × VDD2. For n < 4.
6. Measured by recording the minimum and maximum values of the VREF(CA) output over
VREF(CA) output settings to that line.
7. Measured by recording the minimum and maximum values of the VREF(CA) output across
ing all other VREF(CA) output settings to that line.
8. Time from MRW command to increment or decrement one step size for VREF(CA) .
VREF,min change across the VREF(CA) range in VREF voltage.
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LPDDR4 1.10V VDDQ

full range of VREF voltage within the same VREF(CA) range.
13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0b.
14. tVREF_time_weak covers all VREF(CA) range and value change conditions are applied to
tV
REF_TIME-SHORT/MIDDLE/LONG.
Internal VREF(DQ) Specifications

The device's internal V REF(DQ) specification parameters are operating voltage range, step
size, V REF step tolerance, V REF step time and V REF valid level.
Table 221: Internal VREF(DQ) Specifications

VREF(DQ),max_r0 VREF MAX operating point – – 30% VDDQ 1, 11
Range-0
VREF(DQ),min_r0 VREF MIN operating point 10% – – VDDQ 1, 11
Range-0
VREF(DQ),max_r1 VREF MAX operating point – – 42% VDDQ 1, 11
Range-1
VREF(DQ),min_r1 VREF MIN operating point 22% – – VDDQ 1, 11
Range-1
VREF(DQ),step VREF(DQ) step size 0.30% 0.40% 0.50% VDDQ 2
VREF(DQ),set_tol VREF(DQ) set tolerance –1.00% 0.00% 1.00% VDDQ 3, 4, 6
–0.10% 0.00% 0.10% VDDQ 3, 5, 7
tV
REF_TIME-SHORT VREF(DQ) step time – – 100 ns 8
tV
tV
tV – – 1 ms 13, 14
REF_time_weak
VREF(DQ),val_tol VREF(DQ) valid tolerance –0.10% 0.00% 0.10% VDDQ 10
Notes: 1. VREF(DQ) DC voltage referenced to VDDQ(DC).

2. VREF(DQ) step size increment/decrement range. VREF(DQ) at DC level.
3. VREF(DQ),new = VREF(DQ),old + n × VREF(DQ),step; n = number of steps; if increment, use "+"; if
4. The minimum value of VREF(DQ) setting tolerance = VREF(DQ),new - 1.0% × VDDQ. The maxi-
mum value of VREF(DQ) setting tolerance = VREF(DQ),new + 1.0% × VDDQ. For n > 4.
5. The minimum value of VREF(DQ)setting tolerance = VREF(DQ),new - 0.10% × VDDQ. The maxi-
mum value of VREF(DQ) setting tolerance = VREF(DQ),new + 0.10% × VDDQ. For n < 4.
6. Measured by recording the minimum and maximum values of the VREF(DQ) output over
VREF(DQ) output settings to that line.
7. Measured by recording the minimum and maximum values of the VREF(DQ) output across
ing all other VREF(DQ) output settings to that line.
8. Time from MRW command to increment or decrement one step size for VREF(DQ) .
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LPDDR4 1.10V VDDQ

VREF,min change across the VREF(DQ) Range in VREF(DQ) Voltage.
full range of VREF voltage within the same VREF(DQ) range.
13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0.
14. tVREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to
tV
REF_TIME-SHOR/MIDDLE/LONG.
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Command Definitions and Timing Diagrams - LPDDR4

Pull Up/Pull Down Driver Characteristics and Calibration
Table 222: Pull-Down Driver Characteristics – ZQ Calibration
RONPD,nom Register Min Nom Max Unit

40 ohms RON40PD 0.90 1.0 1.10 RZQ/6
48 ohms RON48PD 0.90 1.0 1.10 RZQ/5
60 ohms RON60PD 0.90 1.0 1.10 RZQ/4
80 ohms RON80PD 0.90 1.0 1.10 RZQ/3
120 ohms RON120PD 0.90 1.0 1.10 RZQ/2
240 ohms RON240PD 0.90 1.0 1.10 RZQ/1
Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%.
Table 223: Pull-Up Characteristics – ZQ Calibration
VOHPU,nom VOH,nom Min Nom Max Unit

VDDQ/2.5 440 0.90 1.0 1.10 VOH,nom
VDDQ/3 367 0.90 1.0 1.10 VOH,nom
Notes: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%.
2. VOH,nom (mV) values are based on a nominal VDDQ = 1.1V.
Table 224: Terminated Valid Calibration Points
ODT Value
VOHPU 240 120 80 60 48 40
VDDQ/2.5 Valid Valid Valid DNU DNU DNU
VDDQ/3 Valid Valid Valid Valid Valid Valid
Notes: 1. Once the output is calibrated for a given VOH(nom) calibration point, the ODT value may
be changed without recalibration.
2. If the VOH(nom) calibration point is changed, then recalibration is required.
3. DNU = Do not use.

The on-die termination (ODT) feature allows the device to turn on/off termination re-
sistance for CK_t, CK_c, CS, and CA[5:0] signals without the ODT control pin. The ODT
via the mode register setting.
A simple functional representation of the DRAM ODT feature is shown below.
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Figure 185: ODT for CA
RTT = VOUT
|IOUT|
VDD2
To other
circuitry ODT
like RCV, ...
CA
IOUT
RTT VOUT
VSS
ODT Mode Register and ODT State Table

ODT termination values are set and enabled via MR11. The CA bus (CK_t, CK_c, CS,
CA[5:0]) ODT resistance values are set by MR11 OP[6:4]. The default state for the CA is
ODT disabled.
ODT is applied on the CA bus to the CK_t, CK_c, CS, and CA signals. The CA ODT of the
device is designed to enable one rank to terminate the entire command bus in a multi-
rank system, so only one termination load will be present even if multiple devices are
sharing the command signals. For this reason, CA ODT remains on, even when the de-
vice is in the power-down or self refresh power-down state.
The die has a bond pad (ODT_CA) for multirank operations. When the ODT_CA pad is
LOW, the die will not terminate the CA bus regardless of the state of the mode register
CA ODT bits (MR11 OP[6:4]). If, however, the ODT_CA bond pad is HIGH and the mode
register CA ODT bits are enabled, the die will terminate the CA bus with the ODT values
found in MR11 OP[6:4]. In a multirank system, the terminating rank should be trained
first, followed by the non-terminating rank(s).
Table 225: Command Bus ODT State
CA ODT ODT_CA ODTD-CA ODTE-CK ODTE-CS ODT State ODT State ODT State
MR11[6:4] Bond Pad MR22 OP[5] MR22 OP[3] MR22 OP[4] for CA for CK for CS
Disabled1 Valid2 Valid3 Valid3 Valid3 Off Off Off
Valid 3 0 Valid3 0 0 Off Off Off
Valid 3 0 Valid3 0 1 Off Off On
Valid 3 0 Valid3 1 0 Off On Off
Valid 3 0 Valid3 1 1 Off On On
Valid 3 1 0 Valid3 Valid3 On On On
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LPDDR4 1.10V VDDQ
Table 225: Command Bus ODT State (Continued)
CA ODT ODT_CA ODTD-CA ODTE-CK ODTE-CS ODT State ODT State ODT State
MR11[6:4] Bond Pad MR22 OP[5] MR22 OP[3] MR22 OP[4] for CA for CK for CS
Valid 3 1 1 Valid3 Valid3 Off On On
Notes: 1. Default value.

2. Valid = H or L (a defined logic level)
3. Valid = 0 or 1.
4. The state of ODT_CA is not changed when the device enters power-down mode. This
maintains termination for alternate ranks in multirank systems.
ODT Mode Register and ODT Characteristics
Table 226: ODT DC Electrical Characteristics for Command/Address Bus – up to 3200 Mb/s
001b 240Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/1 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2
010b 120Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/2 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2
011b 80Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/3 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2
100b 60Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/4 1, 2
V OM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2
101b 48Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/5 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2
110b 40Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/6 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2
Mismatch, CA -CA within clock 0.33 × VDD2 – – 2 % 1, 2, 3
group
2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other cali-
bration points may be required to achieve the linearity specification shown above, for
example, calibration at 0.5 × VDD2 and 0.1 × VDD2.
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LPDDR4 1.10V VDDQ

RODT (AVG)
Table 227: ODT DC Electrical Characteristics for Command/Address Bus – Beyond 3200 Mb/s
001b 240Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/1 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3
010b 120Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/2 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3
011b 80Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/3 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3
100b 60Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/4 1, 2
V OM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3
101b 48Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/5 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3
110b 40Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/6 1, 2
VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1
VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3
Mismatch, CA -CA within clock 0.33 × VDD2 – – 2 % 1, 2, 3
group
2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other cali-
bration points may be required to achieve the linearity specification shown above, e.g.
calibration at 0.5 × VDD2 and 0.1 × VDD2.

RODT (AVG)
On-die termination (ODT) is a feature that allows the device to turn on/off termination
resistance for each DQ, DQS, and DMI signal without the ODT control pin. The ODT
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LPDDR4 1.10V VDDQ
during WRITE or MASK WRITE operation.
The ODT feature is off and cannot be supported in power-down and self refresh modes.
The switch is enabled by the internal ODT control logic, which uses the WRITE-1 or
MASK WRITE-1 command and other mode register control information. The value of
RTT is determined by the MR bits.
RTT = VOUT
|IOUT|
Figure 186: Functional Representation of DQ ODT
VDDQ
To other
circuitry ODT
like RCV, ...
DQ
IOUT
RTT VOUT
VSSQ
Table 228: ODT DC Electrical Characteristics for DQ Bus– up to 3200 Mb/s

001b 240Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2
010b 120Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2
011b 80Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/3 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2
100b 60Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2
V OM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Table 228: ODT DC Electrical Characteristics for DQ Bus– up to 3200 Mb/s (Continued)
101b 48Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2
110b 40Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/6 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2
Mismatch error, DQ-to-DQ with- 0.33 × VDDQ – – 2 % 1, 2, 3
in a channel
sensitivity.
bration points may be required to achieve the linearity specification shown above, (for
example, calibration at 0.5 × VDDQ and –0.1 × VDDQ.
acterized).

RODT (AVG)
Table 229: ODT DC Electrical Characteristics for DQ Bus – Beyond 3200 Mb/s
001b 240Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3
010b 120Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3
011b 80Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/3 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3
100b 60Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2
V OM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3
101b 48Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Table 229: ODT DC Electrical Characteristics for DQ Bus – Beyond 3200 Mb/s (Continued)
110b 40Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/6 1, 2
VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1
VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3
Mismatch error, DQ-to-DQ with- 0.33 × VDDQ – – 2 % 1, 2, 3
in a channel
sensitivity.
bration points may be required to achieve the linearity specification shown above, for
example, calibration at 0.5 × VDDQ and –0.1 × VDDQ.
acterized).

RODT (AVG)
Output Driver and Termination Register Temperature and Voltage Sensitivity

When temperature and/or voltage change after calibration, the tolerance limits are wi-
den according to the tables below.
Table 230: Output Driver and Termination Register Sensitivity Definition
Definition
Resistor Point Min Max Unit Notes
RONPD 0.33 × VDDQ 90 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) % 1, 2
VOHPU 0.33 × VDDQ 90 - (dVOHdT × |ΔT|) - (dVOHdV × |ΔV|) 110 + (dVOHdT × |ΔT|) + (dVOHdV × |ΔV|) 1, 2, 5
RTT(I/O) 0.33 × VDDQ 90 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) 1, 2, 3
RTT(IN) 0.33 × VDD2 90 - (dRONdT × |ΔT|) - (dRONdV× |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) 1, 2, 4
Notes: 1. ΔT = T - T(@calibration), ΔV = V - V(@calibration)

2. dRONdT, dRONdV, dVOHdT, dVOHdV, dRTTdV, and dRTTdT are not subject to production test
but are verified by design and characterization.
3. This parameter applies to input/output pin such as DQS, DQ, and DMI.
4. This parameter applies to input pin such as CK, CA, and CS.
5. Refer to Pull-up/Pull-down Driver Characteristics for VOHPU.
Table 231: Output Driver and Termination Register Temperature and Voltage Sensitivity

dRONdT RON temperature sensitivity 0 0.75 %/˚C
dRONdV RON voltage sensitivity 0 0.20 %/mV
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Table 231: Output Driver and Termination Register Temperature and Voltage Sensitivity (Contin-
ued)

dVOHdT VOH temperature sensitivity 0 0.75 %/˚C
dVOHdV VOH voltage sensitivity 0 0.35 %/mV
dRTTdT RTT temperature sensitivity 0 0.75 %/˚C
dRTTdV RTT voltage sensitivity 0 0.20 %/mV
AC and DC Operating Conditions - LPDDR4

Recommended DC Operating Conditions
Operation or timing that is not specified is illegal. To ensure proper operation, the de-
vice must be initialized properly.
Table 232: Recommended DC Operating Conditions
Symbol Min Typ Max DRAM Unit Notes

VDD1 1.7 1.8 1.95 Core 1 power V 1, 2
VDD2 1.06 1.1 1.17 Core 2 power/Input buffer power V 1, 2, 3
VDDQ 1.06 1.1 1.17 I/O buffer power V 2, 3
Notes: 1. VDD1 uses significantly less power than VDD2.

2. The voltage range is for DC voltage only. DC voltage is the voltage supplied at the
DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball.
3. The voltage noise tolerance from DC to 20 MHz exceeding a peak-to-peak tolerance of
45mV at the DRAM ball is not included in the TdIVW.
Output Slew Rate and Overshoot/Undershoot specifications - LPDDR4

Single-Ended Output Slew Rate
Table 233: Single-Ended Output Slew Rate

Value
Single-ended output slew rate (VOH = VDDQ/3) SRQse 3.5 9.0 V/ns
Output slew rate matching ratio (rise to fall) – 0.8 1.2 –
Notes: 1. SR = Slew rate; Q = Query output; se = Single-ended signal

3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and
voltage, over the entire temperature and voltage range. For a given output, it repre-
sents the maximum difference between pull-up and pull-down drivers due to process
variation.
VOL(AC) = 0.2 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Figure 187: Single-Ended Output Slew Rate Definition
∆TRSE
Single-Ended Output Voltage (DQ)
VOH(AC)
VCENT
VOL(AC)
∆TFSE
Time
Differential Output Slew Rate
Table 234: Differential Output Slew Rate

Value
Differential output slew rate (VOH = VDDQ/3) SRQdiff 7 18 V/ns
Notes: 1. SR = Slew rate; Q = Query output; se = Differential signal

VOL(AC) = –0.8 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC).
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
Figure 188: Differential Output Slew Rate Definition
∆TRdiff
Differential Output Voltage (DQ)
∆TFdiff
Time
LVSTL I/O System - LPDDR4

LVSTL I/O cells are comprised of a driver pull-up and pull-down and a terminator.
Figure 189: LVSTL I/O Cell

VDDQ
Pull-Up
DQ
ODT
Pull-Down Enabled when receiving
VSSQ VSSQ
To ensure that the target impedance is achieved, calibrate the LVSTL I/O cell as follow-
ing example:
1. Calibrate the pull-down device against a 240 ohm resistor to V DDQ via the ZQ pin.
• Increase drive strength until comparator detects data bit is less than V DDQ/3
• NMOS pull-down device is calibrated to 120 ohms
2. Calibrate the pull-up device against the calibrated pull-down device.
CCM005-554574167-10729

LPDDR4 1.10V VDDQ
• Set V OH target and NMOS controller ODT replica via MRS (VOH can be automatically
controlled by ODT MRS)
• Increase drive strength until comparator detects data bit is greater than V OH target
• NMOS pull-up device is calibrated to V OH target
Figure 190: Pull-Up Calibration

VDDQ
N
Strength contol [N-1:0]
Comparator
VOH target
Calibrated NMOS PD Controller ODT replica could be

control + ODT information 60 ohms, 120 ohms, ... via MRS setting
VSSQ
CCM005-554574167-10729

Revision History
Revision History
Rev. F – 12/2020
• Updated footnotes for the LPDDR4 and LPDDR4X IDD6 self refresh current tables
Rev. E – 12/2020
• Updated legal status of package code FW and DE to Production
Rev. D – 3/2020
• Updated MR24 table notes
Rev. C – 2/2020
• Updated legal status to Production: MT53E2G32D4DT-046 AIT:A,
MT53E2G32D4DT-046 AAT:A
• Added AUT device with preliminary IDD specification: MT53E1G32D2FW-046 AUT:A
• Added solder joint reliability (SJR) improved package: Package code FW and code DE
Rev. B – 11/2019
• Updated IDD6 PASR specification
Rev. A – 8/2019
• Initial Preliminary release based on JESD209-4B, JESD209-4-1
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
CCM005-554574167-10729

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200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Automotive LPDDR4/LPDDR4X SDRAM

Features Options Marking

Table 1: Key Timing Parameters

Speed Clock Rate Data Rate WRITE Latency READ Latency

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Table 2: Device Configuration

1G16 1G32 2G32

Refresh Requirement Parameters

Table 3: Refresh Requirement Parameters

Parameter Symbol 16Gb Single-Channel Die Unit

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Part Number and Part Marking Information

Figure 1: Part Number Chart

Micron Technology Design Revision

Automotive Certification (option)

Table 4: Part Number List

Part Number Total Density Data Rate per Pin

FBGA Part Marking Decoder

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Burst WRITE Operation .................................................................................................................................. 83

MASK WRITE Operation ................................................................................................................................. 88

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Burst READ With Auto Precharge ............................................................................................................... 118

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

ZQ External Resistor, Tolerance, and Capacitive Loading ............................................................................. 202

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Clock Period Jitter .......................................................................................................................................... 272

VREF Specifications - LPDDR4 .................................................................................................................... 289

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Figure 154: Clock Single-Ended Input Voltage ................................................................................................ 225

Figure 169: tESCKE Timing ........................................................................................................................... 262

Figure 170: CA Receiver (Rx) Mask ................................................................................................................ 264

Figure 185: ODT for CA ................................................................................................................................. 293

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Table 51: Mode Register 14 (MA[5:0] = 0Eh) .................................................................................................... 58

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Table 103: DQS Turn-Around Parameter ......................................................................................................... 98

Table 138: tFC Value Mapping: Example ........................................................................................................ 206

Table 139: Pull-Down Driver Characteristics – ZQ Calibration ........................................................................ 208

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Table 155: Input Levels ................................................................................................................................. 223

Table 205: Mode Register Default Settings ..................................................................................................... 275

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Table 207: MR0 Device Feature 0 (MA[5:0] = 00h) ........................................................................................... 277

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Important Notes and Warnings

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM

Package Block Diagrams

Figure 2: Single-Die, Single-Channel, Single-Rank Package Block Diagram (x16 I/O)

VDD1 VDD2 VSS VDDQ

Figure 3: Dual-Die, Dual-Channel, Single-Rank Package Block Diagram (x32 I/O)

200b: x16/x32 Automotive LPDDR4/LPDDR4X SDRAM