BY MR. AKETCH - A TVET TRAINER - KENYA COAST NATIONAL POLYTECNIC MOMBASA.

DATE 05/04/2019
COMPILED BY MR. AKETCH - A TVET TRAINER - KENYA COAST NATIONAL POLYTECHNIC. DATE 05/04/2019
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TOPIC FOUR
MICROCONTROLLER INTERFACING TECHNIQUES
Microcontrollers are useful to the extent that they communicate with other devices, such as sensors,
motors, switches, keypads, displays, memory and even other micro-controllers.

Many interface methods have been developed over the years to solve the complex problem of
balancing circuit design criteria such as features, cost, size, weight, power consumption, reliability,
availability, manufacturability.

Many microcontroller designs typically mix multiple interfacing methods. In a very simplistic form,
a microcontroller system can be viewed as a system that reads from (monitors) inputs, performs
processing and writes to (controls) outputs.

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Microcontroller Interfaces

Input / Output ports

In order that the microcontroller is of any use, it has to be connected to additional electronics, i.e.
peripherals. For that reason, each microcontroller has one or more registers (called “port” in this
case) connected to the microcontroller pins. Why input/output? Because you can change the pin’s
function as you wish.
For example, suppose you want your device to turn on and off three signal LEDs and simultaneously
monitor logic state of five sensors or push buttons. In accordance with that, some of ports should
be configured so that there are three outputs (connected to LEDs) and five inputs (connected to
sensors). It is simply performed by software, which means that pin’s function can be changed during
operation.

Usually, each I/O port is under control of a S p e c i a l F u n c t i o n R e g i s t e r SFR, which means that
each bit of that register determines state of the corresponding microcontroller pin. For example, by
writing logic one (1) to one bit of that control register SFR, the appropriate port pin is automatically
configured as input. It means that voltage brought to that pin can be read as logic 0 or 1. Otherwise, by
writing zero to the SFR, the appropriate port pin is configured as output. Its voltage (0V or 5V)
corresponds to the state of the appropriate bit of the port register.
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Digital I/O
Digital I/O, or, to be more general, the ability to directly monitor and control hardware, is the main
characteristic of microcontrollers. As a consequence, practically all microcontrollers have at least 1-
2 digital I/O pins that can be directly connected to hardware (within the electrical limits of the
controller). In general, you can find 8-32 pins on most controllers, and some even have a lot more
than that (like Motorola’s HCS12 with over 90 I/O pins).
I/O pins are generally grouped into ports of 8 pins, which can be accessed with a single byte
access. Pins can either be input only, output only, or —most commonly, — bidirectional, that is,
capable of both input and output. Apart from their digital I/O capabilities, most pins have one or
more alternate functions to save pins and keep the chip small. All other modules of the controller
which require I/O pins, like the analog module or the timer, use in fact alternate functions of the
digital I/O pins.

The application programmer can select which function should be used for the pin by enabling the
functionality within the appropriate module. Of course, if a pin is used for the analog module, then it
is lost for digital I/O and vice versa, so the hardware designer must choose carefully which pins to use
for which functions. In this section, we will concentrate on the digital I/O capability of pins
First, let me explain what we mean by “digital”: When we read the voltage level of a pin with a
voltmeter (with respect to GND), we will see an analog voltage. However, the microcontroller
digitizes this voltage by mapping it to one of two states, logical 0 or logical 1. So when i talk about
digital I/O, i mean that the value of the pin, from the controller’s perspective, is either 1 or 0. Note that
in positive-logic, 1 corresponds to the “high” state (the more positive resp. less negative state) of the
line, whereas 0 corresponds to the “low” state (the less positive resp. more negative state). In
negative-logic, 1 corresponds to “low” and 0 to “high”. Microcontrollers generally use positive-logic.
As far as digital I/O is concerned, three registers control the behavior of the pins:
Data Direction Register (DDR): Each bidirectional port has its own DDR, which contains one bit for
each pin of the port. The functionality of a pin (input or output) is determined by clearing or
setting its bit in the DDR. Different pins of a port may be configured differently, so it is
perfectly okay to have three pins configured to output and use the other five as inputs. After a
reset, the DDR bits are generally initialized to input. Reading the register returns its value.
Port Register (PORT): This register is used to control the voltage level of output pins. Assuming a
pin has been configured to output, and then if its bit in the PORT register is set, the pin will be
high; if the bit is cleared, the pin will be low. To avoid overwriting the other bits in the port
when setting a particular bit, it is generally best to use the controller’s bit operations.
Otherwise, you must use a read-modify-write access and hence must ensure that this access is
not interrupted.
For output pins, reading the register returns the value you have written. For input pins, the
functionality depends on the controller. Some controllers allow you to read the state of input
pins through the port register. Other controllers, e.g. the ATmega16, use the port bits for other
purposes if the corresponding pins are set to input, so here you will read back the value you
have written to the register.
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Port Input Register (PIN): The PIN register is generally read-only and contains the current state
(high or low) of all pins, whether they are configured as output or as input. It is used to read
the state of input pins, but it can also be used to read the state of output pins to verify that the
output was taken over correctly. A write to this register generally has no effect.

The digital input functionality is used whenever the monitored signal should be interpreted digitally,
that is, when it only changes between the two states “high” (corresponding to logic 1) and “low”
(corresponding to 0). Whether a given signal should be interpreted as high or low depends on its
voltage level, which must conform to the controller’s specifications, which in turn depend on the
operating voltage of the controller. For example, the operating voltage V CC of the ATmega16 must be
within the interval [4.5, 5.5] V, its input low voltage must be within [-0.5, 0.2VCC] V, and its input high
voltage must be within [0.6VCC, VCC+0.5] V. This leaves the interval (0.2VCC, 0.6VCC) within
which the signal is said to be undefined.
Advantages
On/OFF control and monitoring.
- Simple interface
- Lowest-cost implementation
- High speed
- Low programming overhead

Disadvantages
- Only on/off controlling or monitoring
- Short distance, few feet maximum
- Single device control/monitoring

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Digital Input Example: Keypad Interface

Analog I/O
In the previous section, I have covered digital I/O. There, analog signals were mapped to two
discrete values 0 and 1. Although this is already very useful, there are situations in which the actual
voltage of the line transports information, for example when using a photo transistor as light sensor:
The voltage drop it produces at its output is directly proportional to the amount of light falling on the
transistor, and to adequately evaluate the sensor output, the microcontroller must deal with the analog
value.
On the other hand, the microcontroller is inherently digital, so we need appropriate ways of
converting analog signals into the digital world and back again. This problem is addressed by the
analog module of the microcontroller.

Advantages
- Simple interface
- Low Cost for low-resolutions
- Low Programming overhead
Disadvantages
- High cost for higher resolutions
- Not all microcontrollers have analog inputs/outputs built-in
- Complicates the circuit design when external ADC or DAC are needed.
- Short distance, few feet maximum.
Voltage type: Typical ranges

 0 to 2.5V
 0 to 4V
 0 to 5V
 +/- 2.5V
 +/- 4V
 +/- 5V

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Current type: Typical ranges

 0-20mA
 4-20Ma

Serial Communications
It refers to any digital signal where data is transferred a single bit at a time. Common examples
include USB (Universal Serial Bus), digital telephone lines, telegraphs, RS232 (commonly called
the serial port on computers), Ethernet and the list continues.

There are three serial communications peripherals on the ATMega644p: SPI (Serial Peripheral
Interface), USART (Universal Synchronous/Asynchronous
2
Receiver Transmitter) and TWI (2-
wire Serial Interface) also known as I C (pronounced I-squared C or I-two C).

USART
The USART (Universal Synchronous/Asynchronous Receiver Transmitter) is the peripheral most
often used for communications to and from a computer or another microcontroller. This is because
it is very simply converted into a signal using the RS232 standard with the use of another IC. This
second IC’s purpose is to ensure the voltage level of the signal is within the plus or minus 3 to 15
volts, protect the microcontroller from shorts and grounds, and provide the signals for the other
pins in the RS232 standard.

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the
serial communications subsystem of a computer. UART is also a common integrated feature in most
microcontrollers. The UART takes bytes of data and transmits the individual bits in a sequential
fashion. At the destination, a second UART re-assembles the bits into complete bytes. Serial
transmission of digital information (bits) through a single wire or other medium is much more cost
effective than parallel transmission through multiple wires. Communication can be “full duplex” (both
send and receive at the same time) or “half duplex” (devices take turns transmitting and receiving).

Generally it uses a three-wire setup to communicate with other devices such as microcontrollers
and RS232 transceivers. Two of this wire is for the actual communications (one for each direction)
and the third wire is ground. If the data transfer only requires one direction, the second data line
can be left off. The use of separate data lines for each direction does allow for full duplex
communications (data is sent and received simultaneously), however this is not required.
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Whenever we want to communicate between PC and MCU or between two MCUs, the simplest way to
achieve that is using UART. UART communication basically uses 2 pins for Data transfer and these
are:

1. TxD (or Tx) – which is the Transmit Data Pin used to send data
2. RxD (or Rx) – which is the Receive Data Pin used to get data
UART sends & receives data in form of chunks or packets. These chunks or packets are also referred to
as ‘transmission characters’. The structure of data packets is as shown below:

UART data packet begins with a ‘0’. This bit is also called as “Start Bit” which signifies incoming data.
Next comes the actual data which can be 5 to 8 bits in length. After the data an optional parity bit can
be used for error checking. Lastly comes the “Stop Bit(s)” which is a ‘1’ and this signifies end of
current data packet. Note that either 1 or 2 stop bits can be used and the parity bit can be : Even , Odd ,
forced to 1 i.e. Mark parity , forced to 0 i.e. Space parity or None. (In UART/RS232 context a MARK
means 1 and SPACE means 0, hence marking state means a stream (series) of 1s and Spacing state
means a stream of 0s)

As mentioned before, the UART essentially acts as an intermediary between parallel and serial
interfaces. On one end of the UART is a bus of eight-or-so data lines (plus some control pins), on the
other is the two serial wires - RX and TX.

Super-simplified UART interface. Parallel on one end, serial on the other.

UARTs do exist as stand-alone ICs, but they’re more commonly found inside microcontrollers.
As the Rx and Tx in the acronym dictate, UARTs are responsible for both sending and receiving serial
data. On the transmit side, a UART must create the data packet - appending sync and parity bits - and
send that packet out the TX line with precise timing (according to the set baud rate). On the receive
end, the UART has to sample the RX line at rates according to the expected baud rate, pick out the sync
bits, and spit out the data.

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Fig-Internal UART block diagram

More advanced UARTs may throw their received data into a buffer, where it can stay until the
microcontroller comes to get it. UARTs will usually release their buffered data on a first-in-first-out
(FIFO) basis. Buffers can be as small as a few bits, or as large as thousands of bytes.

RS232
RS232 is an asynchronous serial communication protocol widely used in computers and digital
systems. It is called asynchronous because there is no separate synchronizing clock signal as there are
in other serial protocols like SPI and I2C. The protocol is such that it automatically synchronizes itself.

We can use RS232 to easily create a data link between our Micro-controller based projects and standard
PC. Excellent example is a commercial Serial PC mouse. You can make a data loggers that reads
analog value(such as temperatures or light using proper sensors) using the ADC and send them to PC
where a special program written by you shows the data using nice graphs and charts etc

RS-232 stands for Recommend Standard number 232 and C is the latest revision of the standard. The
serial ports on most computers use a subset of the RS-232C standard. The full RS-232C standard
specifies a 25-pin "D" connector of which 22 pins are used. Most of these pins are not needed for
normal PC communications, and indeed, most new PCs are equipped with male D type connectors
having only 9 pins.

The RS232 serial communications standard is used by the port commonly labeled the ”Serial Port”
on desktop or laptop computers, using a 25 pin D-sub connector. Of these 25 pins only 10 are used
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by the standards, and only two actually carry the data being transferred. The two devices
communicating under this standard are classified as “Data Terminal Equipment” (DTE) or
as”DATA Communication Equipment” (DCE). When communicating with a desktop computer,
the computer will be the DTE and the microcontroller will be the DCE. Table below lists the pins
used by RS232 and their assignments.

Name Purpose Brie Pin

Data Terminal Tells DCE that DTE is ready DTf #
2
Ready to be connected R 0
Data Carrier Tells DTE that DCE is DC 8
DataDetect
Set Ready Tells DTEconnected
that DCE is ready D
DS 6
to
receive R
Ring Indicator Tells DTE that DCE has RI 2
detected
a ring signal on telephone 2
Request to Send Tells DCElineto prepare to RTS 4
data accept
from DTE
Clear to Send Allows DTE to transmit 5
Transmitted Data Data line from DTE to DCE TxD 2
Received Data Data line from DCE to DTE RxD 3
Common Ground GN 7
Protective Ground D
PG 1

The pin description for the RS-232 pins is as follows:

 DTR (data terminal ready): When terminal is turned on, it sends out signal DTR to indicate
that it is ready for communication.
 DSR (data set ready): When DCE is turned on and has gone through the self-test, it assert
DSR to indicate that it is ready to communicate.
 RTS (request to send): When the DTE device has byte to transmit, it assert RTS to signal the
modem that it has a byte of data to transmit.
 CTS (clear to send): When the modem has room for storing the data it is to receive, it sends
out signal CTS to DTE to indicate that it can receive the data now.
 DCD (data carrier detect): The modem asserts signal DCD to inform the DTE that a valid
carrier has been detected and that contact between it and the other modem is established.
 RI (ring indicator): An output from the modem and an input to a PC indicates that the
telephone is ringing. It goes on and off in synchronous with the ringing sound.
 RxD (Received data): The RxD pin is the Data Receive pin. This is the pin where the receiver
receives data.
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 TxD (Transmitted data): The TxD pin is the Data Transmit pin. This is the pin through which
data is transmitted to the receiver.
 GND: Ground pin.
In RS232 there are two data lines RX and TX. TX is the wire in which data is sent out to other device.
RX is the line in which other device put the data it needs to sent to the device.

Fig RS232 transmission.

The arrows indicate the direction of data transfer. In addition to RX/TX lines there is a third line i.e.
Ground (GND) or Common.
We know that a HIGH =+5v and LOW=0v in TTL / MCU circuits but in RS232 a HIGH=-12V and
LOW=+12V. Yes this is bit weird but it increases the range and reliability of data transfer. Now you
must be wondering how to interface this to MCUs who understand only 0 and 5v? But you will be very
happy to know that there is a very popular IC which can do this for you! It is MAX232 from Maxim
Semiconductors. It converts signals from a TIA-232 (RS-232) serial port to signals suitable for use
in TTL-compatible digital logic circuits. The MAX232 is a dual driver/receiver and typically converts
the RX, TX, CTS and RTS.

The MAX232 IC is used to convert the TTL/CMOS logic levels to RS232 logic levels during serial
communication of microcontrollers with PC. The controller operates at TTL logic level (0-5V) whereas
the serial communication in PC works on RS232 standards (-25 V to + 25V). This makes it difficult to
establish a direct link between them to communicate with each other.
The intermediate link is provided through MAX232. It is a dual driver/receiver that includes a
capacitive voltage generator to supply RS232 voltage levels from a single 5V supply. Each receiver
converts RS232 inputs to 5V TTL/CMOS levels.

As there is no "clock" line so for synchronization accurate timing is required so transmissions are
carried out with certain standard speeds. The speeds are measured in bits per second. Number of bits
transmitted is also known as baud rate. Some standard baud rates are

 1200
 2400
 4800
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 9600
 19200
 38400
 57600
 115200
 … etc

Transmission
1. When there is no transmission the TX line sits HIGH (-12V) ( STOP CONDITION )
2. When the device needs to send data it pulls the TX line low for 104uS (This is the start bit
which is always 0)
3. then it send each bits with duration = 104uS
4. Finally it sets TX lines to HIGH for at least 104uS (This is stop bits and is always 1). I said "at
least" because after you send the stop bit you can either start new transmission by sending a start
bit or you let the TX line remain HIGH till next transmission begin in this case the last bit is
more than 104uS.

Fig- Data Transmission on RS232 line.

Reception
1. The receiving device is waiting for the start bit i.e. the RX line to go LOW (+12V).
2. When it gets start bit it waits for half bit time i.e. 104/2 = 51uS now it is in middle of start bit it
reads it again to make sure it is a valid start bit not a spike.
3. Then it waits for 104uS and now it is in middle of first bit it now reads the value of RX line.
4. In same way it reads all 8 bits
5. Now the receiver has the data.

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RS-422
The RS-422 standard is also designed for point-to-point communication, just like the RS-232. How-
ever, it uses differential lines (both RXD and TXD consist of twisted-pair wires) for transmission.
Hence, it does not need a common GND wire. The RS-422 can be used instead of the RS-232 to
extend the transmission range of the UART. It is also the better choice in noisy environments.

RS485
RS232, RS422, RS423 and RS485 are serial communication methods for computers and devices.
RS232 is without doubt the best known interface, because this serial interface is implemented on almost
all computers available today. But some of the other interfaces are certainly interesting because they
can be used in situations where RS232 is not appropriate.

RS485 is the most versatile communication standard in the standard series defined by the EIA, as it
performs well on all four points. That is why RS485 is currently a widely used communication interface
in data acquisition and control applications where multiple nodes communicate with each other.

RS-485 allows multiple devices (up to 32) to communicate at half-duplex on a single pair of wires, plus
a ground wire (more on that later), at distances up to 1200 meters (4000 feet). Both the length of the
network and the number of nodes can easily be extended using a variety of repeater products on the
market. Data is transmitted differentially on two wires twisted together, referred to as a "twisted pair."
The properties of differential signals provide high noise immunity and long distance capabilities.

RS485 Network Topology: Any station can communicate with any other station, but not at the
same time.

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Ethernet
Ethernet is the ubiquitous (meaning present, appearing, or found everywhere) communication platform
for computer networking in the home and enterprise. The simplicity, performance and cost
effectiveness has made Ethernet technology a viable choice for transport networks as well.

Traditionally, Ethernet nodes were running asynchronously to each other, with defined ±100 ppm
accuracy to the nominal frequency. Consequently, most of the traffic carried over Ethernet was
asynchronous and “bursty” in nature. Synchronization in its strictest sense was not required because of
the nature of the traffic passing through. The transceiver buffers were used to take care of the
unexpected variations in the data flow. Moreover, the protocol layer implemented flow control using
“Pause Frames” which halted the transmission for a specific period of time.

As Ethernet started to carry real time voice and video, the traffic patterns changed. Such services
demanded Constant Bit Rate or Variable Bit Rate but contiguous traffic, which demanded all nodes in a
network from source to destination to have same average frequency. The timing and synchronization
techniques that were applied to the traditional circuit switched networks became relevant to the
Ethernet networks as well. The equipment based on Ethernet networks that support synchronous timing
are described as Synchronous Ethernet (SyncE) networks.
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Advantages
- Very high speed (10Mbit to 100Mbit/s)
- Very long distance, hundreds of feet can be achieved, more with hubs and switches
- Immune to noise
- Widely used in industrial automation due to noise immunity
Disadvantages
- Cost
- More suitable for systems to system communications, not so much for chip to chip sensor
- Requires Ethernet chipset, transformer, jack and special cabling that add to system cost
- Complicated to implement
- High code footprint

I2C (Inter Integrated Circuit bus)

The I2C bus pronounced I-squared-C was designed by Philips in the early ’80s to allow easy
communication between components which reside on the same circuit board. Philips Semiconductors
migrated to NXP in 2006. The name I2C translates into “Inter IC”. Sometimes the bus is called IIC or
I²C bus. It is quite a bit more complex than SPI and Microwire, which results in a larger silicon area
and therefore slightly more expensive devices. It is 2-wire interface with one master and multiple slaves
(multi-master configurations possible).
Typical application to connect:
• Some intelligent control, usually a single-chip microcontroller
• General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM, EEPROM,
real-time clocks or A/D and D/A converters
• Application-oriented circuits such as digital tuning and signal processing circuits for
radio and video systems, temperature sensors, and smart cards
It was originated by Philips Semiconductor in the early 80’s to connect a microcontroller to peripheral
devices in TV sets.

In addition Philips is collecting licensing fees for I2C implementations from competitors, adding to the
cost of I2C devices.

To start the communications, the bus master (typically a microcontroller) places the address of
the device with which it intends to communicate (the slave) on the bus. All slave devices monitor
the bus to determine if the master device is sending their address. Only the device with the
correct address communicates with the master. By definition, I2C is 5V.

I2C – Most significant features

• Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
• Each device connected to the bus is software addressable by a unique address and simple
master/slave relationships exist at all times; masters can operate as master transmitters or as
master-receivers.
• It is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the
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Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4

Mbit/s in the High-speed mode.
• Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast mode • On-chip
filtering rejects spikes on the bus data line to preserve data integrity.
• The number of ICs that can be connected to the same bus is limited only by a maximum bus
capacitance. More capacitance may be allowed under some conditions.
I C – Typical Setup
2

Advantages
- Multiple slave devices can be accessed with only 3 wires
- Low-cost to implement
- Implemented in hardware or software
- Easy to implement
- Supports multi-master configuration
Disadvantages
• The assignment of slave addresses is one weakness of I²C. Seven bits is too few to prevent
address collisions between the many thousands of available devices.
• 10-bit I²C addresses are not yet widely used
• Automatic bus configuration is a related issue. A given address may be used by a number of
different protocol-incompatible devices in various systems, and hardly any device types can be
detected at runtime. For example, 0x51 may be used by a 24LC02 or 24C32 EEPROM
EEPROM, with incompatible addressing; or by a PCF8563 RTC, which cannot reliably be
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distinguished from
• I²C supports a limited range of speeds.
• Devices are allowed to stretch clock cycles to suit their particular needs, which can starve
bandwidth needed by faster devices and increase latencies when talking to other device
addresses.
• Because I²C is a shared bus, there is the potential for any device to have a fault and hang the
entire bus. For example, if any device holds the SDA or SCL line low, it prevents the master
from sending START or STOP commands to reset the bus. Thus it is common for designs to
include a reset signal that provides an external method of resetting the bus devices.
• Because of these limits (address management, bus configuration, potential faults, speed), few
I²C bus segments have even a dozen devices. It is common for systems to have several such
segments.
Asynchronous versus synchronous communications
Asynchronous communications means that information can be sent whenever its ready, and the
receiver cannot expect a transmission to arrive at specific times. The transmission allows data to
be transmitted without the sender having to send a clock signal to the receiver. In this case, the sender
and receiver must agree on timing parameters (Baud Rate) prior transmission and special bits are added
to each word to synchronize the sending and receiving units. In asynchronous transmission, the sender
sends a Start bit, 5 to 8 data bits (LSB first), an optional Parity bit, and then 1, 1.5 or 2 Stop bits.

Synchronous communications means that both the transmitter and receiver know exactly when
each byte will start and stop. This requires that data be continually transmitted to keep the two
devices in sync. When there is no data to be sent, the ASCII ”SYN” character is generally used as
padding. Unless the required data transfer rate is very high in comparison to the maximum possible
data rate, using asynchronous communications is often a better choice as it is somewhat more
robust and easier to maintain.

In an asynchronous serial interface (SCI), data is transmitted in well-defined frames. A frame is a

complete and no divisible packet of bits. The frame includes both information (e.g., data)
and overhead (e.g. control bits).
In asynchronous serial protocols the frame often consists of a single start bit, seven or eight data bits,
parity bits, and sometimes a stop bit. A representative timing diagram for a frame that might be used
by an SCI interface is shown in figure 4. In this figure, the frame has one start bit, seven data bits, one
parity bit, and one stop bit. Most of the bits in this frame are self-explanatory. The start bit is used to
signal the beginning of a frame and the stop bit signals the end of the frame. The parity bit is a special
bit that is used to detect transmission errors.

Figure 4: RS-232 Frame (1 start bit, 7 data bits, 1 parity bits, and 2 stop bits)

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In an asynchronous serial interface, the reading of the data line is initiated by detecting the start bit.
Upon detecting the start bit, the receiver then begins reading the "data" bits from the line at regular
intervals determined by the receiver's clock. This means, of course, that the transmitter and receiver
must have a prior agreement on the rate at which data is to be transmitted.

Synchronous Serial Interface

In a synchronous serial interface, the receiver has no internal clock. This means that the receiver
cannot independently synchronize its reading of the data line with the transmitter's transmission rate.
The receiver needs some help and that help comes in the form of a clock signal that is shared by the
transmitter and receiver. The clock signal acts a control line that tells the receiver when to read from the
data line. What this means is that the transmitter and receiver must synchronize their access to the data
line in order to successfully transmit data.

Examples of synchronous interfaces are: SPI (Serial Peripheral Interface), developed by Motorola,
MICROWIRE developed by National Semiconductor, I2C (Inter Integrated Circuit) developed by
Philips/Signetics, and USART (Universal Synchronous &
Asynchronous Receiver Transmitter) - as the name suggests a USART can either be used in a
synchronous or asynchronous mode, so it falls into both categories.
Synchronous interfaces were designed mainly to connect peripheral devices on the same circuit
board, like external EEPROMS, A/D converters, display drivers and sensors to microcontrollers. They
are only suitable

Character Framing
When using a USART, each character is a separate transmission, with a configurable number of
bits per character. The characters transmitted via a USART c a n be anywhere from 5 bits to 9 bits
long with 7bits (ASCII character) or 8 bits (1 byte) being the most common. Each character is
preceded by a single start bit (logical low) and followed by one or two stop bits (logical high),
and may contain a single parity bit after the final data bit and before the stop bit(s), the total length
of a transmission can range from 7 bits to 13 bits. It is vital that both devices are configured to use
the same options of character length (5-9), parity (none, even, odd), number of stop bits (1 or 2)
and data rate, otherwise errors will arise and if any characters are actually accepted by the receiver,
they will likely be gibberish.

Communications Errors
There are several possible errors that can be detected if a problem occurs during
transmission or reception
 Overrun Error: Occurs when data is received before the previously
received data can be processed. Different devices have different buffer
sizes to store received data in, and if the buffer fills up this error is
triggered. The ATMega644p can only buffer a single character, so it is
important to read that character as soon as possible after it arrives and

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either use it, ignore it, or (most likely) store it until it can be used.
 Under run Error: Occurs when the transmit buffer is empty and the
USART has completed transmitting the previous character. In general,
this is treated as an indication that nothing is being transmitted as in
asynchronous communications data does not need to be continually
transmit- ted. This error can indicate a problem in synchronous
communications as under run is more serious there.
 Framing Error: Occurs when the start and stop bits do not align
properly. If the receiver does not find the stop bit(s) where they are
expected, this error is triggered indicating something went wrong with
the transmission. If this occurs regularly it could indicate that the two
devices are configured for different character frames.
 Parity Error: Occurs when the parity calculation does not match the
parity bit. When parity is enabled and set to even, the parity bit
should be logical high when an even number of bits in the character
are logical high, or when the number of logical high bits is odd and
parity is set to odd. If this bit does not match the receiver’s
calculations a parity error is thrown indicating that there was an error
in the received data. If the transmission lines are particularly noisy
and two bit errors occur, they can cancel each other out in the parity
calculation and the parity calculations will be correct, even if the data
is incorrect.

Serial Peripheral Interface (SPI)

The Serial Peripheral Interface bus (SPI) is a synchronous serial communication interface specification
used for short distance communication, primarily in embedded systems. The interface was developed
by Motorola in the late 1980s and has become a de facto standard. Typical applications include Secure
Digital cards and liquid crystal displays.

SPI devices communicate in full duplex mode using a master-slave architecture with a single master.
The master device originates the frame for reading and writing. Multiple slave devices are supported
through selection with individual slave select (SS) lines.

Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses.
The SPI may be accurately described as a synchronous serial interface, but it is different from the
Synchronous Serial Interface (SSI) protocol, which is also a four-wire synchronous serial
communication protocol. SSI Protocol employs differential signaling and provides only a single
simplex communication channel.

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Figure 5: Independent/daisy chain configuration

SPI Bus
Figure 7.1 below gives an example of a setup where there are three slaves connected to a single
master via SPI. The six wires are:
 SCK: System Clock. This is a clock signal that the transmission uses. It
is generated by the master and is not required to be a constant
frequency. While often generated by a hardware clock in the master, it
is possible to manually control the line via software in extraordinary
situations. Also called SCLK or CLK.
 MOSI: Master Out Slave In. This is the line for transmission from the
master to the slaves and is unidirectional. Also called SIMO, SDO, DO,
SO.
 MISO: Master In Slave Out. This is the line for transmission from a slave
to the master and is also unidirectional. Also called SOMI, SDI, DI, SI.
 SSn: Slave Select n. In single slave situations this is just SS or Slave Select.
This line connects the master to only a single slave device and is used
to tell that device to pay attention to the transmissions. Only a single
slave select should be pulled low at a given time, otherwise the slaves
transmissions may interfere with each other. Also called nCS, CSB, CSN,
STE, nSS.
Operation
During times at which the master is not specifically communicating with one of the slaves, all of
the pins are dormant. SCK is held at either logical high or low depending on the configuration of
CPOL, all nSS lines are held at logical high and the MISO and MOSI lines can be anything (often
tri-state, see below). Once the SS for a given device is pulled low, one of two thinks will happen
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depending on the clock phase configuration (CPHA). If the phase is set to 0 both the master and
slave immediately pull their respective out lines to the correct level for the first bit to be
transmitted. For one or the other this is often logical low, though does not have to be. Half a cycle
later the clock switches high to low or low to high (depending on CPOL) and both master and
slave sample their input lines. On the trailing edge of the cycle (half a cycle later, when the clock
returns to its original value), data is propagated and the MISO and MOSI values change. This
continues until the clock is stopped and returned to its idle value. After that the SS pin can be
returned to a high value and MISO

Figure 7.1: 3 devices connected to a microcontroller using SPI.

and MOSI return to being uncared about. Because communication only occurs while the master is
driving the clock, if the master is expecting some response from the slave after transmitting, the
master must continue operating the clock, and most likely transmitting zeros, until the slave has
finished transmitting. In the case where CPHA is set to 1, data is propagated on the leading clock
edges and sampled on the trailing, rather than vice versa.
Figure 7.2 shows the states of each data line at each clock cycle four configurations of CPOL and
CPHA. The long vertical lines indicate the leading clock edges. Here is a brief explanation of each
of the four possible configurations, including the commonly used mode numbers for each:

Figure 7.2: The four modes of SPI clock polarity and phase.

CPOL=0 (base clock value is 0)

 CPHA=0: Data is captured on rising edge and propagated on
falling edge. (Mode 0)
 CPHA=1: Data is propagated on rising edge and captured on
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falling edge. (Mode 1)

CPOL=1 (base clock value is 1)
 CPHA=0: Data is captured on falling edge and propagated on
rising edge. (Mode 2)
 CPHA=1: Data is propagated on falling edge and captured on
rising edge. (Mode 3)

It was mentioned that MISO and MOSI are often set to tri-state when not in use. Tri-state is a
special third state in binary logic which is obtained by connecting the line through a large
resistor (such as 50kΩ) to ground to prevent it from affecting the level of the line. The large
resistor is designed to be enough to prevent it from reducing the voltage on the line any great
amount, while at the same time preventing the device from sourcing a Voltage on the line.
This is also called a high-impedance state.

SPI Communications Example

The following program can be used to setup and read the 4-byte counter register from an LS7366R
32-bit quadrature counter. This is a device used for counting ticks on an encoder (see chapter 9). It
is somewhat longer than the USART example as both the SPI peripheral on the ATmega644p must
be configured to the requirements of the LS7366R as well as the LS7366R needing configuration.
Once they are both configured and started, the program waits for one second and then reads the
current count.
This operation requires transmitting five bytes. The first byte is the actual command, telling the
LS7366R what register is being read. The following four transmitted bytes are all ignored by the
LS7366R as it is transmitting the counter value. This transmitted data is read from the same
register as the transmitted data was written to. This program saves the incoming data byte by byte
into an array of chars.

Daisy-Chaining SPI devices

Due to hardware or layout limitations, there are times that using a separate slave select line for
each SPI device is not feasible. In this case it may be possible to daisy chain the devices
together and use a single slave select line for all of them.

A daisy chain is formed by connecting the output of one device into the input of the next; thereby
connecting the devices in series rather than in parallel (see

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Figure 7.6: 3 devices daisy-chained to a microcontroller using SPI.

figure 7.6). Whenever the clock pulses, the registers in each of the devices shifts one, causing the
highest bit of each device to shift into the lowest bit of the next device. Therefore, when sending
a command to each of the devices, the command for the last device on the chain must be sent
first. Once all the commands are shifted into the devices, the slave select line is driven high and all
the devices read their instructions. Reading data back on the MISO line works similarly, in that the
appropriate number of bytes must be clocked out to shift the results from all the devices back
around to the microcontroller.

Limitations of a daisy-chain
There are several limitations which cause daisy chains to be less useful than they might
otherwise be.
 All devices must be daisy-chain compatible. Not all devices that use
SPI are set up to be able to daisy-chain. Any device that is not must
be controlled using its own slave select l i n e .
 All devices must use the same clock mode. If two devices use
different clock operational modes (CPOL or CPHA are different),
then they cannot be daisy-chained together as they will be operating
out of sync with each other.
 All devices are controlled simultaneously. Whenever a command is
sent to one device, all of them receive some form of command. If the
programmer is not careful to send a sequence that is known to be
ignored by other devices, unexpected behaviors may occur.
Over all, daisy-chains can be useful in certain circumstances, especially when all the devices being
controlled are identical. They do suffer serious limitations that reduce their usability, so take
care when attempting to daisy-chain SPI devices.

Microwire
Microwire is a close cousin of the SPI often spelled μWire, is essentially a predecessor of SPI and a
trademark of National Semiconductor. It's a strict subset of SPI: half-duplex and using SPI mode 0.
Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz.
Some Microwire chips also support a three-wire mode, which fits neatly with the restriction to half-
duplex.

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Two-Wire Interface (TWI)

The final type of serial communications peripheral on the ATMega644p is the Two-Wire Interface
serial. Other common names include TWI, I2 C (I-squared C), I2C (I-two C) or Inter-Integrated
Circuit). This is again a master-slave configuration, though multiple masters can exist. With only
two wires, one for data and one for the clock, it is only half-duplex meaning data can only be sent
in one direction at any given time.

Figure 7.7: 3 devices connected to a microcontroller using TWI.

Operation
As TWI is not limited to two devices, and as there is no slave select line as there was for SPI, each
device on the bus must have a unique address. When the master (or any of them in a multi-master
setup) is ready to begin transmitting, it begins with a low start bit, followed by the 7-bit address of
the slave to which the master is talking. The clock (SCL) then begins timing the transmission after
the start bit has been set, and before the address. Unlike SPI, where the data was read and
propagated on the rising and falling edges of the clock, in TWI SDA is set while the clock is low
and read while the clock is high.

After the address is sent, the master indicates with a single bit whether it will be reading from (1)
or writing to (0) the addressed slave. If there is a slave with that address on the bus, it will respond
with a single ACK bit (logical low), and then the master or slave will transmit the data, depending
on the read/write bit. If the master wants to transmit several bytes in succession to the same
slave, it can do so, though the slave will send ACK bits between each byte sent. Likewise, if
receiving multiple bytes the master must send ACK bits after every byte received except for the
final byte. Finally, once all the data has-been transmitted the master can send a stop bit,
indicating that it has finished, or another start bit indicating a new message to a new slave.

Advantages
• Full duplex communication is the default version of this protocol.
• Push-pull drivers (as opposed to open drain) provide good signal integrity and high speed
• Higher throughput than I²C or SMBus (The SMBus controller enables simple, two wire
communication between the motherboard and key system components. Short for "system management
bus.). Not limited to any maximum clock speed, enabling potentially high speed
• Complete protocol flexibility for the bits transferred
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• Not limited to 8-bit words

• Arbitrary choice of message size, content, and purpose
• Extremely simple hardware interfacing
• Typically lower power requirements than I²C or SMBus due to less circuitry (including pull up
resistors)
• No arbitration or associated failure modes
• Slaves use the master's clock and do not need precision oscillators
• Slaves do not need a unique address — unlike I²C or GPIB or SCSI
• Transceivers are not needed
• Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than
parallel interfaces
• At most one unique bus signal per device (chip select); all others are shared
• Signals are unidirectional allowing for easy Galvanic isolation
• Simple software implementation
Disadvantages
• Requires more pins on IC packages than I²C, even in the three-wire variant
• No in-band addressing; out-of-band chip select signals are required on shared buses
• No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer
rate)
• No hardware slave acknowledgment (the master could be transmitting to nowhere and not know it)
• Typically supports only one master device (depends on device's hardware implementation)
• No error-checking protocol is defined
• Without a formal standard, validating conformance is not possible
• Only handles short distances compared to RS-232, RS-485, or CAN-bus. (can be extended with use of
transceivers like RS-422)
• Many existing variations, making it difficult to find development tools like host adapters that support
those variations
• SPI does not support hot swapping (dynamically adding nodes).
• Interrupts must either be implemented with out-of-band signals or be faked by using periodic polling
similarly to USB 1.1 and 2.0
• Some variants like Multi I/O SPI and three-wire serial buses are half-duplex.

SPI Applications
• Sensors: temperature, pressure, ADC, touch screens, video game controllers
• Control devices: audio codecs, digital potentiometers, DAC
• Camera lenses: Canon EF lens mount
• Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4, IEEE 802.11, handheld video
games
• Memory: flash and EEPROM
• Real-time clocks
• LCD, sometimes even for managing image data
• Any MMC or SD card

Comparing TWI and SPI

Many devices will support both TWI and SPI. In such a case, one must examine the needs versus
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the capabilities of each.

Speed
SPI has a major benefit here as it is full-duplex, meaning twice the data can flow over the lines.
This is not fully utilized as it is uncommon for master and slave to be transmitting data
simultaneously. Another major speed advantage that SPI has is the lack of addresses. For any
message this increases the overhead, thereby decreasing the available time to transmit data. This
can get especially bad when sending many short m e s s a g e s .

Flexibility
Here each has benefits over the other. SPI has more configurable options, how- ever this can often
lead to confusion and problems. On the other hand it is somewhat easier to use once set up. TWI is
more consistent from device to device as to levels and clock phase and also has the ability to hot-
swap devices on and off the bus, however does have a severe drawback. Slave devices, such as
sensors, DACs and ADCs, can run into problems with overlapping addresses if several identical
devices are used on the same bus. Careful attention must be paid while designing the system to
how many is possible on a single bus and how to set their a d d r e s s e s .

Complexity
Again, SPI takes the lead here. While TWI has less physical complexity, the added complexity in
the code is vast and often more than makes up for the extra pair of wires required. SPI also does
not require the step of ensuring every device has a separate address.

Overall, when given choice between TWI and SPI, and the requirements of the system don’t
indicate one choice is particularly better, the best choice is most likely the one that is more
comfortable for the developers to reduce the likely hood of errors and the costly debugging
process.

1-wire
1-Wire is a device communications bus system designed by Dallas Semiconductor Corp. that
provides low-speed data, signaling, and power over a single conductor.

1-Wire is similar in concept to I²C, but with lower data rates and longer range. It is typically used
to communicate with small inexpensive devices such as digital thermometers and weather
instruments. A network of 1-Wire devices with an associated master device is called a MicroLAN.

One distinctive feature of the bus is the possibility of using only two wires: data and ground. To
accomplish this, 1-Wire devices include an 800 pF capacitor to store charge, and to power the
device during periods when the data line is active.

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Communication
In any MicroLan, there is always one master in overall charge. The master initiates activity on the
bus, simplifying the avoidance of collisions on the bus. Protocols are built into the software to
detect collisions. After a collision, the master retries the required communication

Many devices can share the same bus. Each device on the bus has a unique 64-bit serial number.
The least significant byte of the serial number is an 8-bit number that tells the type of the device.
The most significant byte is a standard (for the 1-wire bus) 8-bit CRC.

There are several standard broadcast commands, as well as commands used to address a particular
device. The master can send a selection command, then the address of a particular device. The
next command is executed only by the addressed device.

Advantages
- Multi slave devices can be accessed with only 2 wires
- Low-cost
- Implemented I hardware or software
- Easy to implement
- Relatively long distance. Theoretically 300 metres but this is limited in practice due to
noise and cable capacitance
Disadvantages
- Slow speed
- 1- wire slave devices typically has come from one source: Dallas Semiconductor
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Conclusion
There are several additional serial communications protocols, however the three discussed above
(RS232, SPI and TWI) that are primarily found on microcontrollers.

Parallel Interface
Parallel Bus
A parallel interface refers to a multiline channel, each line capable of transmitting several bits of data
simultaneously. Most commonly, personal computers (PCs) have at least one parallel interface for
connecting a printer using a parallel port. In contrast, a "serial interface" uses a serial port, a single line
capable of only transmitting one bit of data at a time; a computer mouse connection is a good example.
Here, multiple bits (usually 8 bits or a byte/character) are sent simultaneously on different channels
(wires, frequency channels) within the same cable, or radio path, and synchronized to a clock. Parallel
devices have a wider data bus than serial devices and can therefore transfer data in words of one or
more bytes at a time. As a result, there is a speedup in parallel transmission bit rate over serial
transmission bit rate. However, this speedup is a tradeoff versus cost since multiple wires cost more
than a single wire, and as a parallel cable gets longer, the synchronization timing between multiple
channels becomes more sensitive to distance.
The timing for parallel transmission is provided by a constant clocking signal sent over a separate wire
within the parallel cable; thus parallel transmission is considered synchronous.

The most common types:

 4-bit
 8-bit ( e.g. Getronics )
 16-bit ( e.g. ISA )
 32-bit ( e.g. PCI )
A parallel port is a parallel communication physical interface. It is also known as a printer
port or Centronics port. It was an industry de facto standard for many years. Today, the parallel port
interface is virtually non-existent because of the rise of Universal Serial Bus (USB) devices, along with
network printing using Ethernet and Wi-Fi connected printers.

Parallel communication is and always has been widely used within integrated circuits,
in peripheral buses, and in memory devices such as RAM. Computer system buses, on the other hand,
have evolved over time: parallel communication was commonly used in earlier system buses, whereas
serial communications are prevalent in modern computers.

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In computer architecture, a bus or buss is a communication system that transfers data between
components inside a computer, or between computers. This expression covers all related hardware
components (wire, optical fiber, etc.) and software, including communication protocols.
Early computer buses were parallel electrical wires with multiple connections, but the term is now used
for any physical arrangement that provides the same logical function as a parallel electrical bus.
Modern computer buses can use both parallel and bit serial connections, and can be wired in either
a multidrop (electrical parallel) or daisy chain topology(an interconnection of computer devices,
peripherals, or network nodes in series, one after another), or connected by switched hubs, as in the
case of USB.

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Advantages
- High speed
- High throughput: Several bits transmitted on each clock pulse
- Low-cost
Disadvantages
- Large number of microcontroller pins needed for implementing the parallel bus.

Example: LCD Interface

4-bit LCD Interface

Terminology
Before we get into the individual interface details, we should define several terms:
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 In an asynchronous bus, data is sent without a timing clock. A synchronous bus sends data
with a timing clock.
 Full-duplex means data can be sent and received simultaneously. Half-duplex is when data
can be sent or received, but not at the same time.
 Master/slave describes a bus where one device is the master and others are slaves.
Master/slave buses are usually synchronous, as the master often supplies the timing clock
for data being sent along in both directions.
 A multi-master bus is a master/slave bus that may have more than one master. These buses
must have an arbitration scheme that can settle conflicts when more than one master wants
to control the bus at the same time.
 Point-to-point or peer interfaces are where two devices have a peer relation to each other;
there are no masters or slaves. Peer interfaces are most often asynchronous.
 The term multi-drop describes an interface in which there are several receivers and one
transmitter.
 Multi-point describes a bus in which there are more than two peer transceivers. This is
different from a multi-drop interface as it allows bidirectional communication over the
same set of wires.

PIC microcontrollers
How to make the right choice?
Ok, you are a beginner and you have made decision to let yourself go on an adventure of working
with the microcontrollers. Congratulations on the choice! However, it is not so easy to choose the
right microcontroller as it looks like at first sight. The problem is not a small range of devices, but the
opposite!
Before you start designing some device based on the microcontroller, think of the following:
i) How many input/output lines it is necessary for operation,
ii) Should it perform some other operations than to turn relay on/off,
iii) Does it need some specialized module such as serial communication, A/D converter
etc.
When you create a clear picture of what you need, the selection range is considerably reduced, and it
is time to think of price. Is your plan to have several same devices? Several hundred? A million?
Anyway, you catch the point.
If you think of all these things for the very first time then everything seems a bit confusing. For that
reason, go step by step. First of all, select the manufacturer, i.e. the family of the microcontrollers
you can easily provide. After that, study one particular model. Learn as much as you need, do not go
into details. Solve a specific problem and something incredible will happen- you will be able to
handle any model belonging to that family.

PCI Microcontrollers:
Low-cost computers-in-chip; they allow electronics designers and hobbyist add intelligence and
functions that mimic big computers for almost any electronic products or projects.
These microcontrollers designed by Microchip® Technology are likely the right choice for you if you

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are the beginner. Here is why...

The real name of this microcontroller is PICmicro (Peripheral Interface Controller), but it is better
known as PIC. Its first ancestor was designed in 1975 by General Instruments. This chip called
PIC1650 was meant for totally different purposes. Not longer than ten years after, by adding
EEPROM memory, this circuit was transformed into a real PIC microcontroller. Nowadays,
Microchip Technology announces a manufacturing of the 5 billionth samples.
All PIC microcontrollers use Harvard architecture, which means that their program memory is
connected to CPU via more than 8 lines. Depending on the bus width, there are 12-, 14- and 16-bit
microcontrollers. The table above shows the main features of these three categories.
As seen in the table on the previous page, excepting “16-bit monsters”- PIC 24FXXX and PIC
24HXXX- all PIC microcontrollers have 8-bit Harvard architecture and belong to one out of
three large groups. Therefore, depending on the size of a program word there are first, second and
third category, i.e. 12-, 14- or 16-bit microcontrollers. Having similar 8- bit core, all of them use the
same instruction set and the basic hardware ‘skeleton’ connected to more or less peripheral units.
So far we have gone through an overall overview of the microcontrollers in general and PIC
microcontrollers in specific.

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