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8086 – 16 Bit Microprocessor

8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed
by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines
that provides up to 1MB storage. It consists of powerful instruction set, which provides
operations like multiplication and division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum
mode is suitable for system having multiple processors and Minimum mode is suitable
for system havinga single processor.

Features of 8086
The most prominent features of a 8086 microprocessor are as follows −

1. The 8086 is a 16-bit microprocessor. The term "16-bit" means that its arithmetic logic
unit, internal registers and most of its instructions are designed to work with 16-bit binary
words.
2. The 8086 has a 16-bit data bus, so it can read data from or write data to memory and
ports either 16 bits or 8 bits at a time.
3. The 8086 has a 20-bit address bus, so it can directly access 220 or 10,48,576 (1Mb)
memory locations. Each of the 10, 48, 576 memory locations is byte(8-bit) wide. Therefore,
a sixteen-bit words are stored in two consecutive memory locations.
4. The 8086 can generate 16-bit I/0 address, hence it can access 216 = 65536 I/0 ports.
5. The 8086 provides fourteen 16-bit registers.
6. The 8086 has multiplexed address and data bus which reduces the number of pins
needed, but does slow down the transfer of data.
7. The 8086 is possible to perform bit, byte, word and block operations in 8086. It performs
the arithmetic and logical operations on bit, byte, word and decimal numbers including
multiply and divide.
8. The Intel 8086 is designed to operate in two modes, namely the minimum mode and the
maximum mode. When only one 8086 CPU is to be used in a microcomputer system, the
8086 is used in the minimum mode of operation. In multiprocessor (more than one
processor in the system) system 8086
operates in maximum mode.
9. An interesting feature of the 8086 is that it fetches up to six instruction bytes from
memory and queue stores them in order to speed up instruction execution.
10. The 8086 provides powerful instruction set with the following addressing modes
Register, immediate, direct, indirect through an index or base, indirect through the sum of
a base and an index register, relative and implied.

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8086 Pin Description

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package)
chip. Letus now discuss in detail the pin configuration of a 8086 Microprocessor.

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Let us now discuss the signals in detail −

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.

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Clock signal

Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Itsfrequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after thatit carries 16-bit data.
Address/status bus

A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it
carries 4-bit address and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer
of datausing data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.

Read($\overline{RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready
to transfer data. When it is low, it indicates wait state.
RESET

It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.
INTR

It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an
interrupt or not.
NMI

It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered

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input, whichcauses an interrupt request to the microprocessor.

$\overline{TEST}$

This signal is like wait state and is available at pin 23. When this signal is high,
then theprocessor has to wait for IDLE state, else the execution continues.
MN/$\overline{MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processoris to operate in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
ALE

It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a
valid address on the address/data lines.
DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data from the address/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out
and vice-a-versa.

M/IO

This signal is used to distinguish between memory and I/O operations. When it is
high, itindicates I/O operation and when it is low indicates the memory operation. It is
available at pin28.
WR

It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
HLDA

It stands for Hold Acknowledgement signal and is available at pin 30. This signal

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acknowledges the HOLD signal.

HOLD

This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide
the status of instruction queue. Their conditions are shown in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2

These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26,
27, and
28. Following is the table showing their status −

S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

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LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to leave
the system bus. It is activated using the LOCK prefix on any instruction and is available at
pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the
CPU to release the system bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

Architecture of 8086 (Block Diagram)

The following diagram depicts the architecture of a 8086 Microprocessor −

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8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU
(Bus Interface Unit).

EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then
decode and execute those instructions. Its function is to control operations on data using
the instruction decoder & ALU. EU has no direct connection with system buses as shown
in the above figure, it performs operations over data through BIU.
Let us now discuss the functional parts of 8086 microprocessors.

ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the
result stored in the accumulator. It has 9 flags and they are divided into 2 groups −
Conditional Flags and Control Flags.

Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is
the list of conditional flags −

Carry flag − This flag indicates an overflow condition for arithmetic operations.

Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow

from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set,
i.e. carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform
binary to BCD conversion.
Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower
order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For
odd number of 1’s, the Parity Flag is reset.
Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is
zero elseit is set to 0.
Sign flag − This flag holds the sign of the result, i.e. when the result of the operation
is negative, then the sign flag is set to 1 else set to 0.
Overflow flag − This flag represents the result when the system capacity is exceeded.

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Control Flags
Control flags controls the operations of the execution unit. Following is the list of control
flags −

Trap flag − It is used for single step control and allows the user to execute one
instruction ata time for debugging. If it is set, then the program can be run in a single
step mode.
Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and
set to 0 forinterrupt disabled condition.
Direction flag − It is used in string operation. As the name suggests when it is set
then string bytes are accessed from the higher memory address to the lower
memory address and vice-a-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store
16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It
is referred to the AX, BX, CX, and DX respectively.
AX register − It is also known as accumulator register. It is used to store
operands forarithmetic operations.
BX register − It is used as a base register. It is used to store the starting base
address ofthe memory area within the data segment.

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CX register − It is referred to as counter. It is used in loop instruction to store

the loopcounter.
DX register − This register is used to hold I/O port address for I/O instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to the
memory location, where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the
memory as well as writing data to the ports and the memory. EU has no direction
connection with System Buses so this is possible with the BIU. EU and BIU are connected
with the Internal Bus.
It has the following functional parts −
Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of
next instructions and stores them in the instruction queue. When EU executes
instructions and is ready for its next instruction, then it simply reads the instruction
from this instruction queue resulting in increased execution speed.
Fetching the next instruction while the current instruction executes is called
pipelining.

Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the
addresses of instructions and data in memory, which are used by the processor to
access memory locations. It also contains 1 pointer register IP, which holds the
address of the next instruction to executed by the EU.

CS − It stands for Code Segment. It is used for addressing a memory location in

the code segment of the memory, where the executable program is stored.
DS − It stands for Data Segment. It consists of data used by the program andis
accessed in the data segment by an offset address or the content of other
register that holds the offset address.
SS − It stands for Stack Segment. It handles memory to store data and
addresses during execution.
ES − It stands for Extra Segment. ES is additional data segment, which is used
by the string to hold the extra destination data.

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Instruction pointer − It is a 16-bit register used to hold the address of the next
instructionto be executed.

1. In 8086, pipelining is the technique of overlapping instruction fetch

and execution mechanism.
2. To speed up program execution, the BIU fetches as many as six
instruction bytes ahead of time from memory. The size of instruction
prefetching queue in 8086 is 6 bytes.
3. While executing one instruction other instruction can be fetched.
Thus it avoids the waiting time for execution unit to receive other
instruction.
4. BIU stores the fetched instructions in a 6 level deep FIFO . The BIU can
be fetching instructions bytes while the EU is decoding an instruction
or executing an instruction which does not require use of the buses.
5. When the EU is ready for its next instruction, it simply reads the
instruction from the queue in the BIU.
6. This is much faster than sending out an address to the system
memory and waiting for memory to send back the next instruction
byte or bytes.
7. This improves overall speed of the processor

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Advantages of pipelining:
1. The execution unit always reads the next instruction byte from the
2. queue in BIU. This is faster than sending out an address to the
memory and waiting for the next instruction byte to come.
3. More efficient use of processor.
4. Quicker time of execution of large number of instruction.
5. In short pipelining eliminates the waiting time of EU and speeds up
the processing. -The 8086 BIU will not initiate a fetch unless and until
there are two empty bytes in its queue. 8086 BIU normally obtains
two instruction bytes per fetch.

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Memory Segmentation in 8086 microprocessor

Segmentation is the process in which the main memory of the computer is logically
divided into different segments and each segment has its own base address. It is
basically used to enhance the speed of execution of the computer system, so that
the processor is able to fetch and execute the data from the memory easily and
fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.
 Code segment register (CS): is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
 Data segment register (DS): points to the data segment of the memory where
the data is stored.
 Extra Segment Register (ES): also refers to a segment in the memory which is
another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack segment of the
memory. The stack segment is that segment of memory which is used to store
stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as
to access one of the 1MB memory locations. The four segment registers actually
contain the upper 16 bits of the starting addresses of the four memory segments of
64 KB each with which the 8086 is working at that instant of time. A segment is a
logical unit of memory that may be up to 64 kilobytes long. Each segment is made
up of contiguous memory locations. It is an independent, separately addressable
unit. Starting address will always be changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time.
However, it works only with four 64KB segments within the whole 1MB memory.

Below is the one way of positioning four 64 kilobyte segments within the 1M byte
memory space of an 8086.

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Rules of Segmentation Segmentation process follows some rules as follows:

 The starting address of a segment should be such that it can be evenly divided
by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Advantages of the Segmentation The main advantages of segmentation are as

follows:
 It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in different
segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.

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 It allows to extend the address ability of the processor, i.e. segmentation

allows the use of 16 bit registers to give an addressing capability of 1
Megabytes. Without segmentation, it would require 20 bit registers.
 It is possible to enhance the memory size of code data or stack segments
beyond 64 KB by allotting more than one segment for each area.

Example:
Calculate physical address if CS = 2308H and IP = 76A9H

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Difference between 8085 and 8086

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