Analog System Lab 2024

EE2019 ANALOG SYSTEMS LAB
EE2019 Analog Systems Lab
Last updated on: 16 February 2023 at 12:26 PM
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Department of Electrical Engineering, Indian Institute of Technology Madras
Table of Contents
Chapter 1 Analog Systems Lab Overview ............................................................................................... 5
Objective ............................................................................................................................................. 5
Learning Outcome............................................................................................................................... 5
Brief Description ................................................................................................................................. 5
Evaluation ........................................................................................................................................... 6
Important Instruction ......................................................................................................................... 6
Chapter 2 DC-DC Converter Based LED Driver ........................................................................................ 7
Introduction ........................................................................................................................................ 7
Working Principle ................................................................................................................................ 7
Building Blocks .................................................................................................................................... 8
1. Low Pass Filter......................................................................................................................... 8
2. Compensator......................................................................................................................... 10
3. PWM Modulator ................................................................................................................... 12
4. Power Stage .......................................................................................................................... 12
References: ....................................................................................................................................... 15
EXPERIMENT-1: RAMP GENERATOR AND PWM MODULATOR ........................................................ 16
Circuit Diagram ............................................................................................................................. 16
Specifications ................................................................................................................................ 16
List of Components ....................................................................................................................... 17
List of Measurements ................................................................................................................... 17
Pre-Lab Exercises .......................................................................................................................... 17
EXPERIMENT-2: POWER STAGE AND LPF.......................................................................................... 18
Circuit Diagram ............................................................................................................................. 18
Specifications ................................................................................................................................ 18
Pre-Lab Exercises .......................................................................................................................... 19
EXPERIMENT-3: COMPENSATOR AND MDODULE INTEGRATION ..................................................... 20
Circuit Diagram ............................................................................................................................. 20
Generating VREF ............................................................................................................................. 20
Stability Analysis ........................................................................................................................... 20
Specifications ................................................................................................................................ 23
Pre-Lab Exercise ............................................................................................................................ 24
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Chapter 3 Class-D Audio Amplifier ........................................................................................................ 25

References: ................................................................................................................................... 25
List of Difference between EE3703 and EE2019 Class-d Amplifier: .............................................. 25
EXPERIMENT-4: SINGLE ENDED-TO-DIFFERENTIAL INPUT CONVERTER AND PWM MODULATOR .. 26
Circuit Diagram: ............................................................................................................................ 26
Specifications ................................................................................................................................ 27
Pre-Lab Exercise ............................................................................................................................ 27
EXPERIMENT-5: H-BRIDGE DRIVER AND INTEGRATION.................................................................... 28
Circuit Diagram: ............................................................................................................................ 28
Specifications ................................................................................................................................ 30
Pre-Lab Exercise ............................................................................................................................ 30
Chapter 4 Analog Filter, Adder and Peak Detector............................................................................... 31
Introduction and Circuit Diagrams .................................................................................................... 31
EXPERIMENT-6: BANDPASS FILTER ................................................................................................... 33
Specifications ................................................................................................................................ 33
Pre-Lab Exercise ............................................................................................................................ 34
EXPERIMENT-7: ADDER and PEAK DETECTOR................................................................................... 35
Specifications ................................................................................................................................ 35
Pre-Lab Exercise ............................................................................................................................ 36
Chapter 5 Top Level Integration ........................................................................................................... 37
Integration Guidelines ...................................................................................................................... 38
Final Demo ........................................................................................................................................ 38
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List of Figures
Figure 1-1 System Block diagram of the synchronized light and sound system ..................................... 6
Figure 2-1 Voltage Vs Current Characteristic of LED............................................................................... 7
Figure 2-2 Block diagram of a switching regulator ................................................................................. 8
Figure 2-3 An ideal LC Low-pass Filter .................................................................................................... 8
Figure 2-4 A non-ideal LC Low-pass Filter ............................................................................................... 9
Figure 2-5 A non-ideal LC Low-pass Filter with resistive load ROUT ......................................................... 9
Figure 2-6 Inductor ripple current and output ripple voltage of LC Low-pass Filter with PWM input . 10
Figure 2-7 Fist order opamp-RC filter as type-1 compensator ............................................................. 11
Figure 2-8 Opamp-RC integrator as type-1 compensator..................................................................... 11
Figure 2-9 Opamp-RC integrator as type-1 compensator..................................................................... 12
Figure 2-10 PWM Modulator ................................................................................................................ 12
Figure 2-11 Power Stage with Non-overlap Clock Generator and Gate Driver .................................... 13
Figure 2-12 Circuit diagram of a dc-dc converter based LED driver using Type-I compensator........... 14
Figure 2-13 Circuit diagram of a dc-dc converter based LED driver using Type-III Compensator ........ 14
Figure 2-14 Ramp Generator Circuit ..................................................................................................... 16
Figure 2-15 Power stage and LPF .......................................................................................................... 18
Figure 2-16 Type-I (Integral) Compensator........................................................................................... 20
Figure 2-17 Complete LED Driver .......................................................................................................... 20
Figure 2-18 Continuous time model of siwtching LED driver with Type-I compensator ...................... 21
Figure 2-19 Breaking the loop for stability analysis .............................................................................. 22
Figure 2-20 Breaking the loop using L and C......................................................................................... 22
Figure 2-21 Phase Margin of a feedback system .................................................................................. 23
Figure 3-1 Block diagram of single ended-to-differential converter and PWM modulator ................. 26
Figure 3-2 Circuit diagram of single ended-to-differential converter using op-amp............................ 26
Figure 3-3 Half-bridge speaker driver ................................................................................................... 28
Figure 3-4 Non-overlap clock generator ............................................................................................... 28
Figure 3-5 Electrical model of a speaker ............................................................................................... 29
Figure 3-6 Circuit diagram of the complete class-d amplifier ............................................................... 29
Figure 4-1 A second order bandpass filter ............................................................................................ 31
Figure 4-2 An opamp based adder ........................................................................................................ 31
Figure 4-3 A basic peak detector curcuit .............................................................................................. 32
Figure 4-4 Op-amp based peak detector curcuit .................................................................................. 32
Figure 4-5 Modified op-amp based peak detector curcuit ................................................................... 33
Figure 4-6 Bandpass Filters ................................................................................................................... 33
Figure 4-7 Adder and Peak Detector..................................................................................................... 35
Figure 5-1 Block diagram of the complete system after integration .................................................... 37
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Chapter 1 Analog Systems Lab Overview
Objective
Design of a composite analog system for synchronized light and sound.
Learning Outcome
At the end of this lab, students should be understand following topics with their application
in real world.
• Feedback theory
• Open and closed loop system
• Stability of a closed loop system
• Compensating an unstable system
• Voltage and Current regulation
• Opamp-RC Integrator
• Schmitt Trigger and Oscillator
• Active-RC Filters
• Summing Amplifier (Adder)
• Peak Detector
• Audio Amplifier
Brief Description
The system consists of following three main modules
1. DC-DC Converter based LED Driver
2. Bandpass Filters
3. Adder
4. Peak Detector
5. Class-D Audio Amplifier
When these 3 modules are connected together, it can synchronized light with sound by
changing the brightness of LED (Light Emitting Diode) with sound level. Sound can be heard
over speaker driven by class-D amplifier. Typically, heart beat and lung sound is used as an
input which is derived from stethoscope and processed in electronic stethoscope module.
However, alternate audio signal such as fixed frequency tone from audio source or functional
generator can also be used.
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DC-DC Converter VOUT

Based LED Driver
LED
VREF VFB
RSENSE
Speaker Peak
Detector
Bandapss Audio
Filter Signal
Class-D Audio Bandapss

Amplifier Filter
Figure 1-1 System Block diagram of the synchronized light and sound system
Evaluation
• Weekly pre-lab exercise, schematic and simulation: 25%
• Weekly module demo: 25%
• Final system demo: 25%
• Final exam: 25%
Important Instruction
• Pre-lab exercise and simulation results must be demonstrated and submitted before starting
the lab experiment.
• Use LTSpice for pre-lab simulations. Information about cad tools can be found at
http://www.ee.iitm.ac.in/~nagendra/cadinfo.html
• All lab experiments are carried in a group of two but pre-lab exercises, schematic design and
simulations should be performed individually.
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Chapter 2 DC-DC Converter Based LED Driver
Introduction
LEDs are designed to operate with a constant current and brightness is usually proportional to the
current. Since the V-I characteristic of LED as shown in Figure is exponential, a small change in voltage
can cause a significant change in LED current. Since current higher than rated LED current may damage
LED, it requires constant voltage over varying operation conditions. Accurate and constant voltage is
achieved by voltage regulation (linear or switching). Switching regulator or dc-dc converter is often
preferred over linear regulator due to higher efficiency.
Figure 2-1 Voltage Vs Current Characteristic of LED
Figure 2-2 shows the block diagram of a switching dc-dc converter.
Working Principle
Switching regulator works on the principle of Pulse Width Modulation (PWM) and output voltage, VOUT
is expressed as:
Equation 2-1 VOUT = D ∙ VIN
Where D is the duty cycle of PWM signal expressed as ratio of ON time over Time Period (D=TON/TSW),
VIN is the voltage level of PWM signal.
If VIN remains constant then desired VOUT can be achieved by simply generating a PWM signal with
duty cycle D=VOUT/VIN in an open loop system. However, in the real world, VIN varies depending upon
the source. For instance if VIN is supplied from battery then voltage may be higher when battery is
fully charge compared to when charge is low. Similarly if power source is solar panel voltage may vary
based on the light. Therefore an open loop system may fail to work and closed loop system with
negative feedback is required to regulate the output voltage with variable VIN.
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As shown in Figure 2-2, the feedback voltage, VFB which is scaled version of VOUT is compared with
constant reference VREF to generate error signal VERR. Error signal is processed through compensator
to generate the control signal VCTRL which is converted to PWM signal by PWM modulator. Since
PWM modulator cannot supply high current, it requires a power stage to drive the large current. The
switching PWM signal VSW is then passed through a low-pass filter which suppresses all the switching
harmonics and converts the PWM signal into desired DC voltage (with small ripple content). VOUT is
actually the average of the VSW (which is expressed by Equation 2-1) with small ripple content. The
negative feedback automatically adjusts duty cycle D in case of varying VIN to ensure constant VOUT.
Power Low Pass VOUT IOUT

Stage VSW Filter
Load
β
VPWM PWM VCTRL VERR - VFB

Compensator
Modulator
+
VREF
Figure 2-2 Block diagram of a switching regulator
The output voltage VOUT can be programmed either by changing feedback factor β or reference
voltage VREF which can expressed as:
Equation 2-2 VOUT = VREF

𝛽
Building Blocks
As shown in Figure 2-2, a switching regulator consists of following blocks:
1. Low Pass Filter

Since filter has to supply the high load current, a very low loss filter is required. An ideal inductor has
zero loss (zero impedance) at dc, hence LC low-pass filter makes an ideal choice for dc-dc converter.
L
VOUT
VSW
C
Figure 2-3 An ideal LC Low-pass Filter
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In reality, inductor has a small series resistance call DCR and LC Low-pass filter in Figure 2-3 becomes
a RLC filter as shown in Figure 2-4 which further modifies as Figure 2-5 with presence of resistive
load ROUT.
L R
VOUT
VSW
C
Figure 2-4 A non-ideal LC Low-pass Filter
L R
VOUT
VSW
C ROUT
Figure 2-5 A non-ideal LC Low-pass Filter with resistive load ROUT
Exercise 2-1 Derive the AC transfer function of LC low-pass filters shown in Figure 2-3, Figure 2-4 and
Figure 2-5. Find expressions for centre frequency Wo and quality factor Qo for all the three filters.
Study the effect of R and ROUT on Wo and Qo.
Selecting L and C
The values and inductor L and capacitor C is selected based on two factors (1) Switching frequency (2)
Inductor ripple current. The cut-off frequency of LC filter is selected 50-100 times lower than switching
frequency to minimize the output voltage ripple. Value of inductor is selected to minimize the inductor
ripple current for reduced RMS losses and also prevent the inductor from getting saturated. Since
larger inductor value comes at the cost of bigger area, there is always a trade-off between inductor
size and efficiency. The minimum value of an inductor is quite often chosen such that peak-to-peak
ripple current of inductor does not exceed 1.5-2 time of the maximum load current while maximum
value depends upon the required light load efficiency.
The peak-to-peak inductor ripple current can be expressed as:

VIN −VOUT 𝐷
Equation 2-3 ∆I𝐿 = 𝐿
∙𝐹
𝑆𝑊
Where D is the duty cycle and FSW is the switching frequency of the PWM signal VSW. The output
ripple voltage can be derived by integrating the inductor ripple current and expressed as:
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VIN −VOUT 𝐷
Equation 2-4 ∆V𝑂 = 𝐿
∙ 8∙𝐶∙𝐹 2
𝑆𝑊
The behaviour of inductor ripple current and output ripple voltage is shown in Figure 2-6.
There might be inductors with different dc and saturation current ratings for the same value and one
should be careful in choosing the inductor to ensure that peak inductor current does not exceed the
inductor saturation current under any operating conditions.
Exercise 2-2 For a constant VOUT, derive the duty cycle D for which ΔIL is maximum. Plot the
characteristic of ΔIL Vs. D for D=0 to 1 for VIN=5V, L=10uH and FSW=500KHz.
TSW
VIN
TON TOFF
VSW
0
ΔIL
+
2
IL ΔIL
IOUT(DC)
-
2
ΔVO
+
VOUT 2
ΔVO
VOUT(DC)
-
2
Figure 2-6 Inductor ripple current and output ripple voltage of LC Low-pass Filter with PWM input
2. Compensator
The RLC filter possesses double poles which are complex in nature hence causing 180 Degree phase
shift. Negative feedback with 180 Degree phase shift makes the system unstable hence need to be
compensated. As per the rule, in order to have a stable system, there could be only one dominant
pole in a closed loop system with negative feedback. The compensator in a dc-dc converter can be
used to either cancel one of the poles of LCR filter by using type-3 compensation or push both the
poles outside unity gain bandwidth by using type-1 compensation.
Type-1 Compensation
Type-1 compensation uses a single pole low pass filter or integrator such that the UGB of the loop is
much less (5-10 times) of the double pole frequency of LC filter. Figure 2-7 shows a first order
opamp-RC filter used as type-1 compensator.
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R2
C1
R1
VFB
OA
VCTRL VREF
Figure 2-7 Fist order opamp-RC filter as type-1 compensator
Connecting positive terminal of opamp to VREF performs the function of subtraction (VERR=VREF-VFB)
and low pass filter processes the error signal to get VCTRL. Ideally, we desire zero dc error between VFB
and VREF which can only be achieved by having infinite gain at dc. The feedback resistor R2 in the low
pass filter limits the dc gain hence an opamp-RC integrator is preferred over lowpass filter as type-1
compensator.
C1
R1
VFB
OA
VCTRL VREF
Figure 2-8 Opamp-RC integrator as type-1 compensator
Type-1 compensation can only be used with slower system where fast transient response or tracking
speed is not needed as low bandwidth of the loop makes the system very slow.
Exercise 2-3 Draw the bode plots of lowpass filter and integrator shown in Figure 2-7 and Figure 2-8,
respectively. Find the expression for unity gain bandwidth (UGB) for the two circuits.
Type-3 Compensation
Unlike type-1 compensator which pushes the double LC poles out of UGB by reducing the loop
bandwidth, type-3 compensator cancels one of LC poles and extends the loop bandwidth. Type-3
compensator offers fast transient response and tracking speed due to higher bandwidth. The
compensator is also known as PID as it possesses Proportional (P), Integral (I) and Derivative (D)
components. Circuit diagram of a type-3 compensator is shown in
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C2
C1 R2 R1
C3 R3
VFB
OA
VCTRL VREF
Figure 2-9 Opamp-RC integrator as type-1 compensator
3. PWM Modulator
PWM modulator is used to convert the control voltage, VCTRL to PWM signal by comparing VCRTL with
a fixed frequency ramp signal as shown in Figure 2-10. Duty cycle of the PWM signal is proportional
to VCTRL and can be expressed as:
𝑇𝑂𝑁 𝑉𝐶𝑇𝑅𝐿
Equation 2-5 𝐷= =
𝑇𝑆𝑊 𝑉𝑀
Tsw
Ramp
Generator
VRAMP
VCTRL VPWM
VM
VRAMP VCTRL
TSW VCTRL
TON TON
VPWM TOFF TOFF
TSW TSW
Figure 2-10 PWM Modulator
4. Power Stage
Since PWM comparator is not strong enough to drive high current, it requires high current
complementary switches MP and MN. These switches are usually power MOSFETs with high gate
capacitance hence also require gate drivers to ensure small rise/fall times. Non-overlap clock
generator is used to avoid any circuit current between VIN-GND via MP-MN which may damage the
circuitry. Non-overlap time can be adjusted by changing values if capacitors CP and CN.
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VIN
VPWM INP VGATE_P
MP
CP
VGATE_N
Gate
CN Driver VSW
VGATE_P
INN VGATE_N
MN
Non-overlap Clock Generator
VPWM
VGATE_P
Non-overlap
time
VGATE_N
Figure 2-11 Power Stage with Non-overlap Clock Generator and Gate Driver
The complete LED driver using Type-I and Type-III compensator are shown in Figure 2-12 and Figure
2-13, respectively. Open loop or loop gain transfer function of the LED driver can be expressed as:
1
Equation 2-6 𝐻(𝑠) = 𝛽 ∙ 𝐻𝑐𝑜𝑚𝑝 (𝑠) ∙ ∙ 𝑉𝐼𝑁 ∙ 𝐻𝐿𝑆 (𝑠)
𝑉𝑀
Where,
VM is the peak-to-peak amplitude of ramp signal (VRAMP), VIN is the input supply of power stage and β
is the small signal feedback factor and can be derived from Equation 2-2 as:
𝛥𝑉𝑅𝐸𝐹 𝛥𝑉𝑅𝐸𝐹
Equation 2-7 𝛽= = =1
𝛥𝑉𝑂𝑈𝑇 𝛥𝑉𝑅𝐸𝐹 +𝛥𝑉𝐹_𝐿𝐸𝐷
Where VF_LED is the LED forward voltage which remains constant (i.e. Δ VF_LED=0)
HCOMP(s) is the transfer function of compensator and HLS(s) is the transfer function of LC low-pass
filter.
Current into LED (IOUT) can be expressed as:

𝑉𝑅𝐸𝐹
Equation 2-8 𝐼𝑂𝑈𝑇 =
𝑅𝑆𝐸𝑁𝑆𝐸
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Power Stage
VIN
PWM Modulator
Tsw MP
Non-overlap Clock
Ramp LPF
Gate Driver
Generator
Generator
VRAMP VSW L VOUT
VPWM
C IOUT
MN
C1 LED
R1 VFB
VCTRL
OA RSENSE
VREF
Type-I Compnesator
Load
Figure 2-12 Circuit diagram of a dc-dc converter based LED driver using Type-I compensator
Power Stage
VIN
PWM Modulator
Tsw MP
Non-overlap Clock
Ramp LPF
Gate Driver
Generator
Generator
VRAMP VSW L VOUT
VPWM
C IOUT
MN
C2
C1 R2 R1 LED
C3 R3 VFB
OA RSENSE
VCTRL VREF
Type-III Compnesator
Load
Figure 2-13 Circuit diagram of a dc-dc converter based LED driver using Type-III Compensator
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References:
1. http://www.electronics-tutorials.ws/opamp/opamp_6.html
2. https://www.allaboutcircuits.com/textbook/semiconductors/chpt-8/differentiator-
integrator-circuits/
3. http://fab.cba.mit.edu/classes/961.04/topics/pwm.pdf
4. http://www.ti.com/lit/an/sloa020a/sloa020a.pdf
5. https://en.wikipedia.org/wiki/Phase_margin
6. http://www.mit.edu/afs.new/athena/course/2/2.010/www_f00/psets/hw3_dir/tutor3_dir/t
ut3_g.html
7. http://www.linear.com/solutions/4449
8. https://www.allaboutcircuits.com/technical-articles/negative-feedback-part-4-introduction-
to-stability/
9. https://www.allaboutcircuits.com/technical-articles/negative-feedback-part-5-gain-margin-
and-phase-margin/
10. https://www.allaboutcircuits.com/technical-articles/negative-feedback-part-6-new-and-
improved-stability-analysis/
11. https://www.allaboutcircuits.com/technical-articles/negative-feedback-part-9-breaking-the-
loop/
12. Type-I compensation of a switching dc-dc converter (Part-1)
13. Type-I compensation of a switching dc-dc converter (Part-2)
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EXPERIMENT-1: RAMP GENERATOR AND PWM MODULATOR
Circuit Diagram
Ramp or triangle wave generator is actually an oscillator which is designed using opamp-RC
integrator and Schmitt trigger. PWM is generated by comparing the ramp signal (VRAMP) with control
signal (VCTRL). Common mode voltage of ramp signal should be around VDD/2 hence might require to
decouple the dc voltage and set common mode at VBIAS (around VDD/2). In case common mode of
VRAMP is VDD/2, CBIAS and RBIAS may not be needed and VRAMP can be directly connected to comparator
input (VRAMP_B).
C1 Ramp Generator
R3
VDD R1 VDD
VDD
R2
R OPA1
VCM=VDD/2
VCM CMP1 VSQR
R VCM
VRAMP
Tsw
VM VCM
VBIAS
Tsw CBIAS VRAMP_B
RBIAS CMP2 VPWM
VBIAS VCTRL
PWM Modulator
Figure 2-14 Ramp Generator Circuit
The peak-peak amplitude of the ramp is defined by the equation:

𝑅2
Equation 2-9 𝑉𝑀 = 2 ∙ ∙ 𝑉𝐶𝑀
𝑅3
The oscillation frequency of the ramp is given by equation:

𝑅3
Equation 2-10 𝐹𝑆𝑊 𝑜𝑟 1/𝑇𝑆𝑊 =
4∙𝑅2 ∙𝑅1 ∙𝐶1
Specifications
• Supply voltage (VDD) = 5V
• Frequency (1/TSW) = 100KHz
• Peak-peak ramp amplitude (VM) = 1V
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List of Components
• OPA1: MCP6004 or equivalent alternate part
• CMP1 and CMP2: LM339 (open collector – requires a pullup resistor between VDD and VOUT)
List of Measurements
1. Set VIN=5V, VCM = VBIAS = VIN/2, VCTRL = VDD/2
2. Capture integrator output (VRAMP) and Schmitt trigger output (square wave)
3. Measure and record frequency of VRAMP and square wave
4. Measure amplitude of VRAMP
5. Capture the ramp waveform VRAMP_B and measure the amplitude and dc bias
6. Measure and record frequency of VRAMP_B
7. Capture VPWM, measure frequency and duty cycle
8. Capture and measure
9. Sweep VCTRL between 0 to 1V to get duty cycles of 0%, 25%, 50%, 75% and 100%. Measure
and record value of VCTRL and VPWM duty cycle.
Pre-Lab Exercises
1. For the ramp generator circuit in Figure 2-14, derive the expression for ramp amplitude
(Equation 2-9) and frequency (Equation 2-10).
2. Simulate the ramp generator circuit shown in Figure 2-14 and verify the expressions in
Equation 2-9 and Equation 2-10. Observe the effect of variation in R1, R2, R3 and C1 on ramp
amplitude and frequency.
3. Plot the waveforms and perform measurements 1-9 using simulation.
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EXPERIMENT-2: POWER STAGE AND LPF
Circuit Diagram
Power stage uses VPWM from PWM modulator as input and drives LC LPF through power MOSFETs MP
and MN. VGATE_P and VGATE_N must be non-overlapped (break before make) to avoid short circuit
condition which may damage bread board and circuitry. Non-overlap time of the power stage can be
adjusted by varying CP and CN. It is recommended to disconnect power supply (VIN) from MP for
testing the non-overlap time. Once non-overlap time is verified, VIN can be connected back.
VIN
VPWM INP VGATE_P
MP
CP
VGATE_N LPF
Gate VSW L VOUT
CN Driver
VGATE_P
VGATE_N C
INN MN
Non-overlap Clock Generator
Figure 2-15 Power stage and LPF
Specifications
• Supply voltage (VIN=VDD) = 5V
• PWM Frequency (1/TSW) = 100KHz
List of Components
• NAND Gates: SN74AHC00N or equivalent alternate part
• Inverters: CD4069UBE or equivalent alternate part
• Gate Driver: TC427EPA or equivalent alternate part
• Power MOSFETs: IPP45P03P4L-11 (PMOS) and NTD3055L104-1G (NMOS) or equivalent
alternate parts
• Inductor (L): RCH875NP-101K (100µH) or equivalent
• Capacitor (C): 47µF
1. Set VDD=VIN=5V, PWM duty cycle (D)=50%
2. disconnect VIN from MP and input VPWM from Experiment-1
3. Capture VGATE_P and VGATE_N, measure non-overlap time
4. Connect VIN back to MP
5. Capture VSW and measure dead time, duty cycle and frequency. Observe the difference
between VPWM and VSW
6. Plot VOUT, measure average value, ripple amplitude and frequency
7. Vary PWM duty cycle (D) from 0 to 100% with 25% step by adjusting VCTRL and repeat 6.
Verify relationship, D = VOUT/VIN
8. Set D=50% and apply resistive load to draw 50mA from VOUT
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9. Observe difference in VOUT with and without load. What could be the possible reasons
for differences?
Pre-Lab Exercises
1. Design the power stage shown in Figure 2-15 in LTSpice and verify the functionality through
simulation.
2. Perform measurements 1-9 using simulation. Capture all the graphs.
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EXPERIMENT-3: COMPENSATOR AND MDODULE INTEGRATION
Circuit Diagram
For simplicity, type-I (integrator) compensator is used for loop compensation.
C1
R1
VFB
OA
VCTRL VREF
Figure 2-16 Type-I (Integral) Compensator
VIN
VPWM VGATE_P
INP MP
CP
VGATE_N LPF
Gate VSW L VOUT
Ramp Generator C1 CN Driver
R3 VGATE_P
VGATE_N C IOUT
VDD R1 INN MN
VDD
R2
OPA1
CMP1 VCM Non-overlap Clock Generator
VCM
VRAMP LED
VCM VM
VBIAS
VFB
VRAMP_B Tsw C1
RSENSE
VPWM
RBIAS R1
CMP2
VBIAS VCTRL
OPA2
VREF Load
PWM Modulator
Type-I Compnesator
Figure 2-17 Complete LED Driver
Generating VREF
VREF applied at positive terminal of OPA2 determines the current into LED (see Equation 2-8). For
standalone LED driver, VREF can be supplied from the power supply.
Stability Analysis
Stability analysis of the complete LED driver ( is done by modelling the circuit in continuous domain
to get the open loop transfer function of Equation 2-6 so that bode plot can be used to analyse the
transfer function.
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Power
Stage HLC(s)
VPWM VSW L RL VOUT

VIN
IOUT
C
1
PWM VM
Modulator HCOMP(s) β
C1
RLED
R1 VFB
VCTRL
OPA2
VREF RSENSE
Figure 2-18 Continuous time model of siwtching LED driver with Type-I compensator
LED can be replaced by an equivalent resistor RLED and VFB can be expressed as:
𝑅𝑆𝐸𝑁𝑆𝐸
Equation 2-11 𝑉𝐹𝐵 = 𝑉
𝑅𝑆𝐸𝑁𝑆𝐸 +𝑅𝐿𝐸𝐷 𝑂𝑈𝑇
Since VFB=VREF
𝑉𝑅𝐸𝐹 𝑅𝑆𝐸𝑁𝑆𝐸
Equation 2-12 𝛽= =
𝑉𝑂𝑈𝑇 𝑅𝑆𝐸𝑁𝑆𝐸 +𝑅𝐿𝐸𝐷
Using Equation 2-7 and Equation 2-12, RLED can be calculated as:
𝑉𝐹_𝐿𝐸𝐷
Equation 2-13 𝑅𝐿𝐸𝐷 = 𝑅𝑆𝐸𝑁𝑆𝐸 ∙
𝑉𝑅𝐸𝐹
Forward voltage of LED (VF_LED) can be found from the datasheet and is usually in the range of 2V to
3.3V depending upon the LED colour and current.
For PWM modulator and power stage, gain can be realized using voltage controlled voltage source
(VCVS) or a simple ideal gain element if available in the simulator’s ideal component library.
Once the circuit is modelled, stability analysis can be performed by breaking the loop (to get the loop
gain transfer function) as shown in Figure 2-19. The break point must be chosen such that the transfer
function is not disturbed. For instance, if loop is broken between L and RL then it will eliminate the
inductor from loop gain which will change the transfer. Similarly, RLED and RSENSE are forming the
feedback factor so they can’t be separated out. Therefore, ideal break point should a node where one
side is low impedance while other is high (e.g. VOUT, VCTRL, VSW etc.). The input must be applied on
the high impedance side while output should be measured on the low impedance side. In this example,
the loop is broken at VOUT. Since impedance looking towards the RLC side VOUT is low and RLED side
is high, input must be applied on RLED side. Loop gain AC analysis is performed by applying AC input
of amplitude 1 at vin_ac. And plot the AC magnitude and phase response at vout_ac.
21 | P a g e
Power
Stage HLC(s)
VPWM VSW L RL VOUT

VIN
C
vout_ac
Break Point
1
PWM VM vin_ac
Modulator HCOMP(s) β
C1
RLED
R1 VFB
VCTRL
OPA2
VREF RSENSE
Figure 2-19 Breaking the loop for stability analysis
The above method works only with ideal component as they don’t require DC biasing. However, when
using real components such as supply limited non-ideal op-amps, they must be biased at their proper
DC operating points. Since, loop gain transfer function is needed only for AC, DC operating points of
the circuit should not be disturbed after breaking the loop. In order to preserve the DC operating point
of the circuit, loop can be broken in such a way that it should behave like a closed loop circuit for DC
but open loop for AC. This can be achieved by breaking the loop using inductor and capacitor as shown
in Figure 2-20. Since inductor behaves like a short circuit for DC and capacitor as open circuit, loop will
remain closed at DC. While for AC inductor behaves as open and capacitor as short, circuit will behave
like open loop for AC.
Values of Lbreak and Cbreak should be large (order of Mega Henry and Mega Farad) so that they don’t
interference with actual ac response of the circuit.
Power
Stage HLC(s)
VPWM VSW L RL VOUT

VIN
Break Point
C vout_ac
Lbreak
Cbreak
PWM 1 vin_ac
VM
Modulator HCOMP(s)
C1 β
RLED
R1 VFB
VCTRL
OPA2
VREF RSENSE
Figure 2-20 Breaking the loop using L and C
22 | P a g e
Stability of the circuit can be checked by looking at the phase margin. Phase margin is defined as
(phase difference of total loop phase shift from 0 or 360 degrees at unity gain or 0dB (condition for
Barkhausen criteria). The frequency at unity gain is called unity gain bandwidth (FUGB) or unity gain
frequency (FUGF). Even though a system with > 0 degree phase margin is theoretically stable, in reality
phase margin of a stable system should be greater than 45 degrees. However, it is recommended to
have the phase margin ≥ 60 degrees and gain margin > 20dB for better transient response (no
significant ringing in the output). Gain margin is defined as the gain needed to make the overall loop
gain = 1 (0dB) a the frequency where overall phase shift is 0 or 360 degrees (condition of Barkhausen
criteria).
Open Loop Gain
FUGB
Open Loop
Phase
Figure 2-21 Phase Margin of a feedback system
More details on Type-I compensation and finding the values of resistor and capacitor, refer to video
lectures:
• Type-I compensation of a switching dc-dc converter (Part-1)

• Type-I compensation of a switching dc-dc converter (Part-2)
Specifications
• Phase Margin > 60 Degree
• IOUT (ILED) = 50mA
• RSENSE = 5 Ohm
23 | P a g e
List of Components
• Op-Amp (OPA2): MCP6004 or equivalent
• Inductor (L=100uH): RCH875NP-101K
• LED: 151053YS04500
• Sense Resistor (RSENSE=5Ω): MOSX1CT52R5R1J
1. Set VDD=VIN=5V, connect VREF to power supply and set VREF=0V
2. Verify that VOUT=0V, LED is OFF (IOUT=0) and there is no switching i.e., VPWM=VSW=0.
Measure VCTRL.
3. Slowly increase VREF to a value (few mV) where LED starts turning ON. Measure and
plot VOUT, VFB, VRAMP, VCTRL, VPWM and VSW. Verify that PWM duty cycle, D = (VCTRL-
VRAMP_MIN)/VM = VOUT/VIN
4. Repeat step 3 for VREF = 0V, 50mV, 100mV, 150mV, 200mV and 250mV. Measure the
LED current and observe change in LED brightness.
5. Turn OFF VREF first and then VIN.
6. Use function generator to supply VREF. Select square wave of amplitude 250mV (with
low level=0V and high level=250mV), frequency = 1Hz, duty cycle = 25%
7. Set VIN=5V and turn on VIN power supply first and then VREF from function generator.
Observe blinking LED light. Increase duty cycle if LED does not blink. Measure and
capture VOUT, VFB, VRAMP, VCTRL, VPWM and VSW.
8. Now turn OFF VREF from function generator and set it to sinusoid with frequency 1Hz
and pk-pk amplitude 250mV (Vmin=0V, Vmax=250mV).
9. Turn ON VREF and observe LED light. It should follow the sinusoid pattern. Capture
voltages VOUT, VFB, VCTRL, VPWM and VSW for one cycle of sinusoid.
10. Sweep the sinusoid frequency from 1 Hz to 1KHz and observe LED light. Does LED
stop blinking at higher frequency? What is that frequency?
Pre-Lab Exercise
1. For the LED driver in Figure 2-17, Find the loop gain transfer function with and without type-I
compensator. Calculate the values of R1 and C1 of the compensator for phase margin > 60
degrees and gain margin = -20dB. Use continuous time model (Equation 2-6, Equation 2-7,
Equation 2-11, Equation 2-12, Equation 2-13 and Figure 2-18).
2.
3. Calculate VREF for LED current of 10mA, 25mA and 50mA. If VREF is fixed at 250mV, how will
you program the LED current to 10mA, 25mA and 50mA?
4. Design switching LED driver shown in Figure 2-17 and perform the AC or stability analysis
using simulation (see Figure 2-19, Figure 2-20 and Figure 2-21). Capture AC magnitude and
phase response with and without compensator.
5. Perform measurements 1-10 on simulation. Observe LED current. Capture all the graphs. In
case LED model is not available in LTSpice then use multiple PN junction diodes connected in
series to get the LED forward voltage.
24 | P a g e
Chapter 3 Class-D Audio Amplifier
Class-D amplifier module is same as EE3703: Analog Circuits Lab with few minor changes. Details about
class-d amplifier can be found at:
http://www.ee.iitm.ac.in/vlsi/courses/ec330_2011/finalproject/classdamp
References:
1. Wikipedia article
2. Notes on Class D amplifier from Georgia Institute of Technology
3. Notes from Elliott Sound Products
4. Brett Forejt, Vijay Rentala, Jose Duilio Arteaga, and Gangadhar Burra, "A 700+-mW Class D
Design With Direct Battery Hookup in a 90-nm Process," IEEE Journal of Solid-State Circuits,
Volume 40, Issue 9, Sep. 2005, pp. 1880-1887.
5. Varona et al., "A Low-Voltage Fully-Monolithic ΔΣ-Based Class-D Audio
Amplifier," Proceedings of the 1999 European Solid State Circuits Conference, pp. 545-548.
(This has an example of switch sizing. This is not the type of class D amplifier you are required
to design)
6. Putzeys B., "Digital audio's final frontier," IEEE Spectrum vol. 40, no. 3, Mar. 2008. pp. 34-41.
7. Berkhout M., "Audio at low and high power," Proceedings of the 2008 European Solid State
Circuits Conference pp. 40-49.
8. Application notes from companies
a. Texas Instruments: http://www.ti.com/audio/ (e.g. Class-D LC Filter Design, 07 Jan
2008; TPA3101D2 Mono Amplifier Configuration, 16 Apr 2007)
b. Maxim Integrated Circuits: http://www.maxim-
ic.com/appnotes.cfm/appnote_number/3977 (The bridged three level topology
shown here may be a bit confusing. See the TI datasheet for a simpler topology-
logically they are the same)
c. Analog Devices: http://www.analog.com/library/analogDialogue/archives/40-
06/class_d.html
d. International Rectifier: http://www.irf.com/product-info/audio/classdtutorial.pdf
e. http://www.infineon.com/dgdl/an-
1071.pdf?fileId=5546d462533600a40153559538eb0ff1
List of Difference between EE3703 and EE2019 Class-d Amplifier:
Parameters EE2019 Class-d EE3703 Class-d

PWM Frequency 100KHz 300KHz
Ramp Generator Op-Amp and Comparator based BJT based
(used from experiment-1)
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EXPERIMENT-4: SINGLE ENDED-TO-DIFFERENTIAL INPUT CONVERTER AND PWM

MODULATOR
Circuit Diagram:
PWM Modulator
VPWM_P
CMP1
Analog input Vin_a+

Vin_a Vin_a-
Note: triangular wave and signal inputs to the

comparators must be around the same bias point
VPWM_N
VRAMP_CLASS-D
CMP2
100KHz
Figure 3-1 Block diagram of single ended-to-differential converter and PWM modulator
Single ended-to-differential converter can be designed using op-amp based inverting amplifier as
shown in Figure 3-2.
R2
Cin R1
Vin_a VIn_a-
Analog input VCM
VIn_a+
Figure 3-2 Circuit diagram of single ended-to-differential converter using op-amp
Input capacitor Cin should be large enough to make sure input audio signal is not attenuated.
For R1=R2:
Vin_a+ = Vin_a (ac) + VCM
Vin_a- = -Vin_a(ac) + VCM
26 | P a g e
Since outputs (Vin_a+ and Vin_a-) and VRAMP are biased around VCM, common mode shifting of VRAMP is
not needed. Therefore VRAMP_CLASS-D can be directly connected to VRAMP. In case common mode of
VRAMP is not VCM then it must be shifted to VCM by using a coupling capacitor and resistor as it was
done in Experiment-1 (Figure 2-14) to generate VRAMP_B.
Specifications
• PWM Frequency = 100KHz
List of Components
• INV1, INV2 and INV3: MC14069
1. Set VDD=VIN=5V
2. From function generator, set sinusoid wave of 1kHz and use as input to single ended-to-
differential converter. Peak-to-peak amplitude of the sinusoid should be same as peak-to-
peak amplitude of the triangular wave.
3. Measure amplitude and frequency of waveforms at input, Vin+ and Vin-. Capture oscilloscope
waveform and verify that Vin+ and Vin- are 180 degrees out of phase and have same
amplitude as input.
4. Measure and capture duty cycle at VPWM_P and VPWM_N. Duty cycle should follow the same
pattern as Vin_a+ and Vin_a-. Verify that VPWM_N has inverter duty cycle (1-D) of VPWM_P (D).
5. Add an RC filter at VPWM_P and VPWM_N with 3dB cut-off frequency of 10-20KHz and observe the
output. Verify that output has the same shape as Vin_a+ and Vin_a-.
Pre-Lab Exercise
1. Drive the expression for Vin+ and Vin- in terms of input and prove that Vin+ and Vin- have
sane amplitude but of opposite polarity.
2. Find the expression for differential PWM signal, VPWM_P-VPWM-N and prove that average output
is amplified version of analog input to single ended to differential converter. Find the gain of
amplifier.
3. Build the complete circuit shown in Figure 3-1 and Error! Reference source not found. in L
TSpice. Verify the functionality in simulation with measurements 1-5.
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EXPERIMENT-5: H-BRIDGE DRIVER AND INTEGRATION
Circuit Diagram:
Figure 3-3 shows the circuit diagram of half-bridge driver. The driver is the output stage of class-D
amplifier and is the key to obtaining good efficiency. The switches (Qp and Qn) of the half-bridge driver
are implemented using NPN and PNP transistors and driven with CMOS inverter buffers. Use a base
resistance (bases of Qp and Qn) of a few kΩ to limit the base current. If you find that the drive is
insufficient (i.e. the transistors don't saturate with a heavy load), reduce the base resistances so that
they saturate. If you find that the drive is still not sufficient, you can omit the base resistor, and connect
two inverters in parallel to drive the base of the transistors. The non-overlap generator can be
designed using the circuit in experiment-2 or the one shown in Figure 3-4.
Half-Bridge Driver
VPWM VOUT
Figure 3-3 Half-bridge speaker driver
Figure 3-4 Non-overlap clock generator
28 | P a g e
In order to test the half-bridge circuit, VPWM from one of the PWM modulators (VPWM_P or VPWM_N) of
experiment-4 can be used as input. VOUT can be initially tested without load and then 32Ω resistive
load is applied.
For simulation, actual electrical model of speaker can be used as shown in Figure 3-5. L is the coil
inductance which is usually within the range of few 100s to a 1000 uH depending upon the size of
coil. RL is coil resistance which depends upon power rating of the speaker.
RL/2
1
Speaker
1
2 L
RL/2
2
Figure 3-5 Electrical model of a speaker
Figure 3-6 shows the circuit diagram of complete class-d amplifier. The PWM output from single ended
to differential converter and PWM modulator designed in experiment-4 is fed to H-Bridge driver which
drives the speaker load. H-bridge driver consist of two identical half-bridge drivers. The complete
class-D amplifier should be tested with resistive load first and then actual speaker.
H-Bridge Driver
Half-Bridge Driver
VPWM_P VOUT_P
Vin_a+
Vin_a
Half-Bridge Driver
Vin_a-
VPWM_N
VOUT_N
VRAMP_CLASS-D
Figure 3-6 Circuit diagram of the complete class-d amplifier
29 | P a g e
Specifications
• PWM Frequency = 100KHz
• Load Resistance (RL) = 32Ω
List of Components
• Inverters: MC14069 or CD4069
• NAND Gates: SN74AHC00N
• BJTs: 2NXXXX series or alternate parts
1. Set VDD=VIN=5V, RL=32 Ω
2. From function generator, set sinusoid wave of 1KHz and use as input to single ended-to-
differential converter. Peak-to-peak amplitude of the sinusoid should be same as peak-to-
peak amplitude of the triangular wave.
3. Measure and capture duty cycle at VOUT+ and VOUT-. Duty cycle should follow the same pattern
as Vin_a+ and Vin_a-. Verify that VOUT- has inverter duty cycle (1-D) of VOUT+ (D).
4. Add an RC filter at VOUT+ and VOUT- with 3dB cut-off frequency of 10-20KHz and observe the
output. Verify that output has the same shape as Vin_a+ and Vin_a-. RC filter is only to observe
the average value of output hence should not be in the load path (i.e. load should be
connected directly between VOUT+ and VOUT-).
5. Verify 2-4 with speaker and do hearing test. Reduce the amplitude of input sinusoid and
observe the change in sound level. Repeat hearing test for 5 different frequency tones
between 0.5KHz to 5KHz and observe the sound.
NOTE: capture oscilloscope waveform only for one condition to show the functionality of circuit.
Pre-Lab Exercise
1. Build the complete circuit shown in Figure 3-1 and Error! Reference source not found. in L
TSpice. Verify the functionality by simulation with measurements 1-5. Use speaker model
from Figure 3-5 as load and plot current through inductor. Inductor current should be average
of differential output voltage (VOUT_P-VOUT_N) divided by RL.
30 | P a g e
Chapter 4 Analog Filter, Adder and Peak Detector
Introduction and Circuit Diagrams

Analog filters are used to pass desired frequency signals and reject other frequencies. The objective
of this module is to design a second order high-Q bandpass filter which will pass only a fixed frequency
audio tone. Output of the filter is used as input signal to LED driver and class-D amplifier at later stage
when we integrate all the modules and build complete system.
R22
R11 C
Vin
Vout
R33
Figure 4-1 A second order bandpass filter
For basic theory and different types of filter, refer to the following documents:
• http://www.ti.com/lit/an/sbfa001c/sbfa001c.pdf
• https://focus.ti.com/lit/ml/sloa088/sloa088.pdf
For multiple frequency tones, multiple filters, centred at different frequencies, can be used. Filter
outputs can be added using an inverting adder shown in Figure 4-2.
R3
R1
Vin1
R2
Vin2 Vout
Figure 4-2 An opamp based adder
The output voltage of adder can be expressed as:

𝑅 𝑅3
Equation 4-1 𝑉𝑜𝑢𝑡 = − ( 3 𝑉𝑖𝑛1 + 𝑉 )
𝑅1 𝑅2 𝑖𝑛2
If R1=R2=R3 then:
Equation 4-2 𝑉𝑜𝑢𝑡 = −(𝑉𝑖𝑛1 + 𝑉𝑖𝑛2 )
31 | P a g e
Since, reference voltage to LED driver is dc, the ac output signal of the above bandpass filter must be
converter to dc using a peak detector. Following document provides detailed description about the
peak detector circuit.
• http://ww1.microchip.com/downloads/en/AppNotes/01353A.pdf
Figure 4-3 shows the circuit of a basic peak detector. It is based on a half-wave rectifier (AC-to-DC
converter). Since VIN must be greater than forward voltage of diode (D1) for conduction, the circuit
does not work for input voltages lower than diode forward voltage (~0.7V).
Figure 4-3 A basic peak detector curcuit
An op-amp based peak detector shown in Figure 4-5 is used in this module. First order high pass filter
(R1-C1) is used to de-couple any dc bias of the input Vin. Feedback from Vpeak to op-amp inverting
input ensures that D1 is always conducting for positive voltage of Vin_ac. Since diode remains reverse
biased for negative voltage, capacitor (C2) holds the peak value of Vin_ac at Vpeak.
D1
Vpeak
Vin_ac OPA
Vin C2 R2
C1 R1
Figure 4-4 Op-amp based peak detector curcuit
Resistors R2 provides the discharge path to Vpeak so that output voltage can be reduced if amplitude
of the input is reducing. The discharge rate of Vpeak depends upon the RC time constant defined as:
τ=R2∙C2 and must be chosen high enough to ensure low ripple at Vpeak and low enough so that Vpeak
can track any slow changes in the input signal amplitude. Generally, time constant (τ) is kept around
10 times of the time period of input signal.
The dc voltage obtained at Vpeak may have higher voltage than the maximum specified value of VREF
in the LED driver. Peak detector circuit of Figure 4-4 can be modified by splitting R2 into R2-R3 to form
a voltage divider. The desired level of VREF can be achieved by adjusting the values of R2 and R3. The
values of R2+R3 should be order of 10s of KOhms or higher as lower values may cause current drawn
from op-amp output higher than its drive capability. Maximum output current of the op-amp can be
checked from the datasheet before selecting the values of R2 and R3.
32 | P a g e
D1
Vpeak
Vin_ac OPA
Vin C2 R2
C1 R1 VREF
VREF = Vpeak·R3/(R2+R3) R3 C3 (to LED driver)
Figure 4-5 Modified op-amp based peak detector curcuit
Capacitor (C3) can also be added at VREF to filters out the ripple further and get a cleaner dc voltage.
EXPERIMENT-6: BANDPASS FILTER

The objective of experiment-6 is to design two different bandpass filters in Figure 4-6. Audio input
(Vin_audio), which is a fixed frequency sinusoid tone, is used as input to the bandpass filter. Each
bandpass filter is designed to respond to a desired frequency tone and reject other frequencies.
Bandpass Filter-1
Ca
R22a
R11a Ca
OPA1 Vout_bpf1
R33a VCM
Vin_audio Bandpass Filter-2

Cb
R22b
R11b Cb
OPA2 Vout_bpf2
R33b VCM
Figure 4-6 Bandpass Filters
Specifications
• Supply voltage: VDD=5V
• VCM=VDD/2=2.5V
• Bandpass filter Gain (Ao1=Ao2)=1 (0 dB)
• Bandpass filter Q-factor (Qo1=Qo2) = 10
• Bandpass Filter-1 center frequency (fo1) = 1kHz, Bandpass Filter-2 center frequency (fo2) =
3kHz
List of Components
• OPA1 and OPA2: MCP6004 (Op Amps Quad 1.8V 1MHz)
33 | P a g e
1. Set VDD=5V, VCM=2.5V
2. Tune Bandpass Filter-1 center frequency (fo1) = 1kHz, Bandpass Filter-2 center frequency (fo2)
= 3KHz, gain (Ao1=Ao2)=1 and Qo1=Qo2=10.
3. From function generator, set sinusoid wave of 1kHz and use as input to bandapss filters
(Vin_audio). Peak-to-peak amplitude of the sinusoid should be 0.9 times of peak-to-peak
amplitude of the ramp signal of experiment-1.
4. Measure and capture the output of bandpass filters (Vout_bpf1 and Vout_bpf2) and verify the
amplitude as per the filter response. Reduce the amplitude of Vin_audio and verify that
Vout_bpf1 follow the change in amplitude. Set the amplitude back to its maximum value
(0.9xVm)
5. Change the frequency of Vin_audio to 3kHz and repeat 4.
6. Now sweep the frequency of Vin_audio from 100Hz to 5kHz) and verify that Vout_bpf1 and
Vout_bpf2 do not respond to any other frequencies except their respective center frequencies
(fo1=1kHz and fo2=3kHz)
Pre-Lab Exercise
1. Derive the transfer function of bandpass filter shown in Figure 4-1 and prove that it is a second
𝑤
𝐴𝑜 ∙ 𝑜 ∙s
𝑄𝑜
order bandpass filter having transfer function equivalent to: H(s) = 𝑤 . Find the
𝑠2 + 𝑜 𝑠+𝑤𝑜2
𝑄𝑜
values of resistors and capacitors for BPF-1 and BPF-2 based on values (Ao, fo and Qo)
provided in the Specifications.
2. Simulate and perform measurement 3-6. Capture all the plots and mark values.
NOTE:
• Center frequencies (fo1 and fo2) may be slightly off from simulation results when
implemented on breadboard. This is mainly due to the tolerance in resistors and capacitors.
In that case, you can tune the frequency of Vin_audio to match the center frequency of the
bandpass filter. Exact center frequency of BPF-1 (fo1) can be found by sweeping the frequency
of Vin_audio around 1kHz and look for the maximum amplitude of Vout_bpf1. Similarly , Exact
center frequency of BPF-2 (fo2) can be found by sweeping the frequency of Vin_audio around
3kHz and look for the maximum amplitude of Vout_bpf2.
34 | P a g e
EXPERIMENT-7: ADDER and PEAK DETECTOR

The objective of experiment-7 is to add the band pass filtered signals (Vout_bpf1 and Vout_bpf2) from
experiment-6 and converter the added signal into a dc voltage (VREF) using peak detector.
Adder Peak Detector

R
R
Vin1
D1
(From filters)
Vpeak
Vin_ac OPA4
R OPA3 C2 R2
Vin2 VCM C1 R1 VREF
Vout_adder R3 C3 (to LED driver)
VREF = Vpeak·R3/(R2+R3)
(to Class-D Amplifier)
Figure 4-7 Adder and Peak Detector
Specifications
• Maximum peak-to-peak ripple at Vpeak = 100mV
• Maximum peak-to-peak ripple at VREF = 10mV
• Maximum peak to peak amplitude of Vin1 and Vin2 = 0.9xVm (Vm is the peak-to-peak
amplitude of the ramp signal obtained from experiment-1 at VDD=5V)
• Maximum value of VREF (for maximum amplitude of Vin1 and Vin2) = 250mV
List of Components
• OPA3 and OPA4: MCP6004 (Op Amps Quad 1.8V 1MHz)
• D1: 1N4148TR (Diodes - General Purpose)
1. Set VDD=5V, VCM=2.5V
2. From function generator, apply sinusoid wave of amplitude=0.9xVm, frequency=1kHz at Vin1
and Vin2 with common mode (dc offset) set at 2.5V.
3. Measure and capture the output of adder (Vout_add) and verify that:
𝑉𝑜𝑢𝑡_𝑎𝑑𝑑 − (𝑉𝑖𝑛1 + 𝑉𝑖𝑛2 )
4. Plot Vin_ac and verify that signal is biased around 0V.

5. Change the frequency of input sinusoid to 3kHz and repeat 3 and 4.
6. Measure and plot Vpeak average and peak to peak ripple. Verify that average is approximately
same as peak level of Vin_ac and prak-to-peak ripple is within the specification (100mV).
7. Measure and plot VREF and verify the average value is 250mV and ripple is within 10mV.
8. Reduce the amplitude of Vin1 and Vin2 and verify that Vout_add and VREF follow the change
in amplitude.
9. Now connect Vin1 to the output of Bandpass Filter-1 (Vout_bpf1) and Vin2 to Bandpass Filter-
2 output (Vout_bpf2). From function generator, apply sinusoid wave of 1kHz as input to
bandapss filters (Vin_audio). Peak-to-peak amplitude of the sinusoid should be 0.9 times of
peak-to-peak amplitude of the ramp signal of experiment-1. Repeat measurement 6 and 7.
Reduce the amplitude of Vin_audio and verify that Vout_add and VREF follow the change in
amplitude.
10. Change the frequency of input sinusoid to 3kHz and repeat 9.
35 | P a g e
11. Now sweep the frequency of Vin_audio from 100Hz to 5kHz) and verify that Vout_ac
amplitude is 0.9xVm and VREF is 250mV at frequencies 1kHz and 3kHz but remain very low
(~0V) at other frequencies.
Pre-Lab Exercise
1. Calculate the values of R, R1, R2, R3, C1, C2 and C3 for the frequency and ripple provided in
the Specifications.
2. Design and simulate the entire circuit shown in Figure 4-7 with above calculated values. Verify
the operation with measurements 1 to 11.
NOTE:
• The gain of the bandpass filter at center frequency should be unity. If not then adjust the value
of R11. Alternatively, the gain can be changed by selecting proper values of values of R1, R2
and R3 in the adder (Figure 4-2).
• The center frequencies (fo1 and fo2) may be slightly off from simulation results when
implemented on breadboard. This is mainly due to the tolerance in resistors and capacitors.
In that case, you can tune the frequency of Vin_audio to match the center frequency of the
bandpass filter. Exact center frequency can be found by sweeping the frequency of Vin_audio
around 1KHz and look for the maximum amplitude of Vout_bpf.
36 | P a g e
Chapter 5 Top Level Integration
Top level integration combines all the four modules (LED Driver, Class-D Amplifier, Filtes and
Adder+Peak Detector designed during experiments 1-7) to build the complete system. Figure 5-1
shows the block diagram of the complete system after integrating all the modules.
VDD1
VDD2
LED DRIVER
CLASS-D AMPIFIER (Experiments 1,2,3) VCTRL
(Experiments 4,5) VRAMP_B
Speaker
VOUT_P
VOUT
VOUT_N
VRAMP VRAMP
VREF
VFB
VRAMP_CLASS-D
Vin_a+ LED
Vin_a- VSS1
VPWM_P Vin_a
VPWM_N RSENSE
VDD3
VSS2
(Fixed frequency audio tone
VREF
Vout_ad
from function generator) Vin_audio Vin_audio Vout_bpf1 Vin1
Vout_bpf2 Vin2 Vpeak
POWER SUPPLY ADDER AND
V+ GND PEAK
FILTERS DETECTOR
(Experiment 6) (Experiment 7)
VDD1
VDD2
VDD3
VSS1
VSS2
VSS3
VSS3
Figure 5-1 Block diagram of the complete system after integration
Vin_audio is a fixed frequency audio tone generated from function generated as it was used in
experiment-6 and 7. All the interface signals going from one module to other should be connected
properly. In order to prevent noise coupling from one module to other, VDD and GND (VSS) of each
module should be connected directly to power supply and not shorted locally on the breadboard. If
required, decoupling capacitors of few µF can be connected locally between VDD and GND of each
module. If analog modules (non-switching) within the modules are affected from switching noise then
VDD and GND of each analog module can be separated as well and connected directly to the power
supply.
37 | P a g e
Integration Guidelines
1. Makes sure all the individual modules are working before integrating them together.
2. Before starting board level integration, integrate all the modules together on LTSpice and
verify the functionality.
3. Label all the signals shown in the block diagram of Figure 5-1 using a small piece of paper and
tape. Wires connecting to these labelled signals should be brought to for measurement. Rest
of the signals can left inside the board.
4. Try to use different colour wires for VDD, GND and signals. For example, red can be used for
VDD, black from GND and other colours for signals.
5. Putting tape around the circuits may help in keeping the connections intact. Signal wires which
are brought out for measurement can also be fastened locally on board using tape to protect
from popping out of the holes.
6. VDD and GND (VSS) of each module should be connected directly to power supply and not
shorted locally on the breadboard. If required, decoupling capacitors of few µF can be
connected locally between VDD and GND of each module.
7. Check the short between VDD, GND and signals before turning the power supply ON.
8. Limit the power supply current to prevent the circuit from damaging in case of accidental
short. Usually current limit is set slightly higher (1.5x or so) than the maximum total current
drawn by the circuits.
Final Demo
Final demo will be based on both LTSpice and board level design. Students will not be given extra time
to work on circuits on the day of final demo hence all students should have their modules ready before
start of the demo. Students will be asked to demonstrate following:
1. LTSpice simulation results. Must be implemented individually by each group mate.

2. Hardware functionality demo (in group).
3. Probe signals listed in Figure 5-1.
4. Capability of operating instruments used in EE2019 lab (oscilloscope, power supplies, function
generator etc.)
5. Answering questions related to circuits designed in EE2019 lab experiments.
38 | P a g e

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EE2019 ANALOG SYSTEMS LAB

EE2019 Analog Systems Lab

Last updated on: 16 February 2023 at 12:26 PM

Chapter 3 Class-D Audio Amplifier ........................................................................................................ 25

Chapter 1 Analog Systems Lab Overview

DC-DC Converter VOUT

Class-D Audio Bandapss

Chapter 2 DC-DC Converter Based LED Driver

Figure 2-1 Voltage Vs Current Characteristic of LED

Figure 2-2 shows the block diagram of a switching dc-dc converter.

Equation 2-1 VOUT = D ∙ VIN

Power Low Pass VOUT IOUT

VPWM PWM VCTRL VERR - VFB

Equation 2-2 VOUT = VREF

1. Low Pass Filter

Figure 2-3 An ideal LC Low-pass Filter

Figure 2-4 A non-ideal LC Low-pass Filter

Figure 2-5 A non-ideal LC Low-pass Filter with resistive load ROUT

The peak-to-peak inductor ripple current can be expressed as:

Figure 2-7 Fist order opamp-RC filter as type-1 compensator

Figure 2-9 Opamp-RC integrator as type-1 compensator

Figure 2-10 PWM Modulator

Non-overlap Clock Generator

Current into LED (IOUT) can be expressed as:

EXPERIMENT-1: RAMP GENERATOR AND PWM MODULATOR

The peak-peak amplitude of the ramp is defined by the equation:

The oscillation frequency of the ramp is given by equation:

EXPERIMENT-2: POWER STAGE AND LPF

Non-overlap Clock Generator

Figure 2-15 Power stage and LPF

EXPERIMENT-3: COMPENSATOR AND MDODULE INTEGRATION

Figure 2-17 Complete LED Driver

VPWM VSW L RL VOUT

VPWM VSW L RL VOUT

Figure 2-19 Breaking the loop for stability analysis

VPWM VSW L RL VOUT

Figure 2-20 Breaking the loop using L and C

Open Loop Gain

Figure 2-21 Phase Margin of a feedback system

• Type-I compensation of a switching dc-dc converter (Part-1)

Chapter 3 Class-D Audio Amplifier

List of Difference between EE3703 and EE2019 Class-d Amplifier:

Parameters EE2019 Class-d EE3703 Class-d

EXPERIMENT-4: SINGLE ENDED-TO-DIFFERENTIAL INPUT CONVERTER AND PWM

Analog input Vin_a+

Note: triangular wave and signal inputs to the

Figure 3-2 Circuit diagram of single ended-to-differential converter using op-amp

Vin_a+ = Vin_a (ac) + VCM

Vin_a- = -Vin_a(ac) + VCM

EXPERIMENT-5: H-BRIDGE DRIVER AND INTEGRATION

Figure 3-3 Half-bridge speaker driver

Figure 3-4 Non-overlap clock generator

Figure 3-6 Circuit diagram of the complete class-d amplifier

Chapter 4 Analog Filter, Adder and Peak Detector

Introduction and Circuit Diagrams

Figure 4-1 A second order bandpass filter

Figure 4-2 An opamp based adder

The output voltage of adder can be expressed as:

Figure 4-3 A basic peak detector curcuit

Figure 4-4 Op-amp based peak detector curcuit