Eetop - CN - iSSCC 2022 T1 Analog in BCD Tutorial

ISSCC 2022 Tutorials
Analog Circuit Design in Bipolar-CMOS-DMOS (BCD)

Technologies
Marco Berkhout
Goodix Technology, Nijmegen, The Netherlands
mberkhout@goodix.com
Live Q&A Session: Feb. 20, 2022, 8:40-9:00am, PST

Marco Berkhout 1 of 169
© 2022 IEEE International Solid-State Circuits Conference

Marco Berkhout
 1992/1996 MSc/PhD Electrical Engineering,
Twente University, The Netherlands
 1996-2020: Senior Principal Design Engineer
Philips / NXP Semiconductors, The Netherlands
 2020–present: Fellow
Goodix Technology, The Netherlands
 Expert Class-D Audio Power Amplifiers

 25+ patents
 20+ papers at IEEE conferences / journals
 Technical Program Committees

 ESSCIRC 2008–2018
 ISSCC 2013-2016, 2020-present
Marco Berkhout T1: Analog Circuit Design in Bipolar-CMOS-DMOS (BCD) Technologies 2 of 169

IEEE Milestone
 May 18, 2021, the invention of BCD technology was commemorated with an
IEEE Milestone
 https://spectrum.ieee.org/three-chips-in-one-the-history-of-the-bcd-integrated-circuit

BCD Applications
home lighting
battery chargers induction cooking

display drivers
wireless charging
audio amplifiers
electrical vehicles
solar inverters motor drivers LED matrix lighting

BCD Technology
 Analog
 high speed, high precision
 feedback control, references, signal processing
 Digital
 high density CMOS
 control logic, interfacing, digital signal processing
 BCD follows CMOS roadmap with about 10 years lag
 Power
 high voltage
 high current

What is High Voltage ?
 circuit design: any voltage high enough to damage gate-oxide
 application optimized BCD process nodes

 8V - 20V mobile / laptop
 40V - 80V automotive / home
 400V – 1200V mains
 4kV – 6kV galvanic isolation
 high voltage comes at the price of silicon area

 critical electric field
 device terminal distance
 isolation spacing

What is High Current ?
 circuit design: any current that causes significant conduction loss
 high current requires low-ohmic connections

 1A - 5A battery chargers, PMICs
 10A - 30A audio amplifiers, motor drivers
 process/package features
 ultra thick Cu metallization
 thick (multiple) bondwires [19]
 bonding over active areas

Outline
 Introduction & Motivation
 BCD Process Technology & Devices
 Device Characteristics & Figures-of-Merit
 Applications
 Circuit Design

Outline
 Applications
 Circuit Design

What is BCD Technology[1] ?
 Bipolar
 CMOS
 DMOS

CMOS

CMOS
 symmetrical devices
 interchangeable source and drain
 well contacts
 shared by multiple devices
B S G D D G S B
p+ n+ n+ p+ p+ n+
p-well n-well
p- substrate NMOS PMOS

CMOS
 symmetrical devices  p-n junctions
 interchangeable source and drain  shorted
 reverse biased
 well contacts
 shared by multiple devices
B S G D D G S B
p+ n+ n+ p+ p+ n+
p-well n-well

CMOS
 reverse biased
 well contacts  bipolar parasitics
 shared by multiple devices  latch-up
B S G D D G S B
p+ n+ n+ p+ p+ n+
p-well n-well

CMOS
 reverse biased
 well contacts  bipolar parasitics
 shared by multiple devices  latch-up
VDD
B S G D D G S B
p+ n+ n+ p+ p+ n+
p-well n-well
NMOS PMOS GND

p- substrate

CMOS
 latchup design rules
 part of standard design rule check
 checks distance to nearest well connnection
NMOS PMOS
 digital layout poly
 standard cells (NANDs, NORs, etc) n-well
n+
 well contacts part of fixed layouts
p-well
 well contacts are inserted by layout tool p+
 correct by construction
 analog layout
B S G D D G S B
 well contact rings around devices

Isolated CMOS
B S G D D G S B
p+ n+ n+ p+ p+ n+
p-well n-well

Isolated CMOS
 deep n-well  isolation from substrate
 ‘triple well’  NMOS body can be at different
 high energy ion implantation voltage than substrate
 inverse doping gradient
 highest doping below n/p-well
 does not affect surface behaviour
B S G D D G S B
p+ n+ n+ p+ p+ n+
p-well n-well
deep n-well

Bipolar Junction Transistor

Bipolar Junction Transistor (BJT)
 bipolar
E B C
 both electrons and holes are
n+ p n involved in transistor operation
 three regions with different dopant

 heavily doped emitter
 lightly doped collector
 narrow, moderately doped base
 two pn-junctions
space charge regions
 NPN or PNP

 forward biased base-emitter junction
E B C
 large electron current flowing from
emitter to base
 small hole current flowing from base
e- to emitter
h+
VBE

 forward biased base-emitter junction
E B C
 large electron current flowing from
emitter to base
 small hole current flowing from base
e- to emitter
h+  reverse biased base-collector junction

 few electrons recombine in base
 most electrons swept up by space-
IB IC charge region base-collector junction
 high current gain

VBE VCB
 IC/IB = <50,200>

E B C
 additional p-body diffusion
 base width determined by difference in
vertical diffusion p-body and n+ emitter
 vertical diffusion profile yields NPN with high
dopant conc. (log)

current gain
 high doping in bottom deep n-well reduces
collector contact resistance
B E C
p+ n+ n+
p-body
n-well
n+ p n n+
deep n-well
p- substrate VNPN depth

DMOS

DMOS
 ‘D’ => double-diffused  fixed channel length
 refers to n+ source and p-body  difference in lateral diffusion
diffusions n+ source / p-body
 self-alignment: poly gate  only channel width can be scaled
S/B G D
p+ n+ n+
p-body
n-well
channel region
deep n-well
p- substrate DMOS

DMOS
 VDSmax >> VGSmax  field plate
 step in poly-gate
 drift region  reduced surface field (RESURF)
 lightly doped region between
channel and drain contact  deep n-well
 determines on-resistance  isolate source/body form substrate
S/B G D
p+ n+ n+
p-body
n-well
drift region
deep n-well
p- substrate DMOS

DMOS
S B D
 asymmetrical
 drain and source not
interchangeable
 very effective bipolar parasitic
dopant conc. (log)

 lateral diffusion profile similar to
NPN
S/B G D
p+ n+ n+
p-body
n-well
n+ p n n+
deep n-well
p- substrate DMOS depth

DMOS
 assymetrical  body always shorted to source to
 drain and source not prevent turn-on parasitic NPN
interchangeable  diode between source and drain
 very effective bipolar parasite  explicitly drawn in device symbol
 lateral diffusion profile similar to
NPN
S/B G D
D D D
p+ n+ n+
p-body
G G G
n-well
deep n-well
p- substrate DMOS S/B S/B S/B

DMOS
G
 device model
 NMOS with JFET cascode
 JFET pinch-off limits internal NMOS S/B JFET D
drain voltage NMOS
 drain source diode
 forward conduction characterized
S/B G D
Body Diode
p+ n+ n+
p-body
n-well
deep n-well
p- substrate DMOS

BJT + CMOS + DMOS
 combining BJT, CMOS and DMOS on same wafer yields BCD technology
 lateral isolation with p-well barriers

 lateral spacing scales with breakdown voltage
B E C B S G D D G S B S/B G D
p+ n+ n+ p+ p+ n+ n+ p+ p+ n+ p+ p+ n+ n+
p-body p-body
n-well p-well p-well n-well p-well n-well
deep n-well deep n-well deep n-well
p- substrate VNPN NMOS PMOS DMOS

HV-PMOS ?

HV-PMOS
 p-type DMOS  extended drain PMOS (EDPMOS)
 possible but unusual due to higher  p-well drift region
on-resistance (hole mobility)  field plate
 requires additional diffusions  deep n-well isolation
D G S B D G S B
p+ p+ n+ p+ p+ n+
n-well p-well n-well
deep n-well
p- substrate PMOS EDPMOS

HV-NMOS
 extended drain NMOS (EDNMOS)  cheaper alternative to BCD
 HV derivative of standard CMOS  no p-body diffusion needed
 no vertical NPN
 higher on-resistance than DMOS
B S G D D G S B
p+ n+ n+ p+ p+ n+
p-well n-well p-well n-well
deep n-well deep n-well
p- substrate EDNMOS EDPMOS

Folding

DMOS
S/B G D
p+ n+ n+
p-body
n-well
deep n-well
p- substrate DMOS

DMOS
 Folding: Drain Centered
S/B G D G S/B
p+ n+ n+ n+ p+
p-body p-body
n-well
deep n-well
p- substrate DMOS

DMOS
 Folding: Source Centered
D G S/B G D
n+ n+ p+ n+ n+
p-body
n-well n-well
deep n-well
p- substrate DMOS

DMOS
 power device  net device area
 folded many times (e.g. >100)  pitch x gate width
 pitch  independent of folding
 centre source to centre drain  excluding isolation area / guard rings
pitch
S/B G D G S/B G D G S/B G D G S/B
p+ n+ n+ n+ p+ n+ n+ n+ p+ n+ n+ n+ p+
p-body p-body p-body p-body
n-well n-well n-well
deep n-well
p- substrate DMOS

Isolation

Isolated DMOS
 parasitic drain to substrate diode
D
 forward biased when drain below
substrate
 minority carrier injection G
 latch-up risk
S/B G D G S/B S/B substrate
p+ n+ n+ n+ p+
p-body p-body
n-well
deep n-well
e-
p- substrate DMOS

Isolated DMOS
 parasitic drain to substrate diode  n-guard ring
 forward biased when drain below  collect minority carriers
substrate  connect to positive voltage
 minority carrier injection
 latch-up risk
N-guard S/B G D G S/B N-guard
n+ p+ n+ n+ n+ p+ n+
p-body p-body
n-well n-well n-well

e-
deep n-well
p- substrate DMOS

Isolated DMOS
 parasitic substrate PNP  p-guard ring
 active if source above drain  fix substrate potential
 current flows to substrate i.s.o. drain
 majority carrier injection
 high dissipation
p-guard n-guard S/B G D G S/B n-guard p-guard
p+ n+ p+ n+ n+ n+ p+ n+ p+
p-body p-body
p-well n-well n-well n-well p-well

h+
deep n-well
p- substrate DMOS

Isolation Area
 guard rings increase device
area
 lateral spacing increases with
breakdown voltage DMOS
 relatively expensive for small

HV devices
poly
 design economy
n-well
 only use HV devices when n+
S/B G D G S/B
absolutely necessary p-well
p+
n-guard
p-guard

Fully Isolated DMOS
 full vertical isolation  expensive
 no drain to substrate diode  buried layers
 less effective substrate PNP  deep diffusions for vertical contact
 better control of parasitic currents
p-guard n-guard S/B G D G S/B n-guard p-guard
p+ n+ p+ n+ n+ n+ p+ n+ p+
p-body p-body
p-well deep-n p-well p-well deep-n p-well

n-well
buried-p
buried-n
p- substrate DMOS

Deep Trench Isolation (DTI)
 lateral dielectric isolation  very expensive
 deep trenches (e.g. 30μm)  area / waferprice trade-off
 area reduction
 replaces guard rings
S/B G D G S/B
p+ n+ n+ n+ p+
DTI
DTI
p-body p-body
n-well
buried-p
buried-n
p- substrate DMOS

Silicon-On-Insulator (SOI)[3]
 buried oxide (BOX)  very, very expensive
 full dielectric isolation  requires special wafers
 no latch-up  warping limits wafer size to 8’’
 no leakage between components
 high temperature operation > 175oC
S/B G D G S/B
p+ n+ n+ n+ p+
DTI
DTI
p-body p-body
SOI
n-well
BOX
p- substrate DMOS

Outline
 Applications
 Circuit Design

Safe Operating Area (SOA(R))
 voltage limit BVDS
 breakdown voltage
 operating voltage < BVDS IMAX
ILIM
log ID
 current limit IMAX
 electromigration
 bondwires
 protection circuits limit to ILIM < IMAX
 dissipation limit PMAX(t)

 thermal BVDS
 time dependent log VDS

Temperature Range
 -40oC to 150oC
 normal operating range (DC)
IMAX
ILIM
 150oC to 200oC
log ID
 thermal protection kicks in (msec)
 e.g. sustained short circuit
 200oC to 350oC
 short thermal overshoot (<μsec)
 e.g. hard switching transitions
BVDS
 beyond 350oC log VDS

 catastrophic failure

Temperature Range
 -40oC to 150oC
 normal operating range (DC)
 150oC to 200oC
 thermal protection kicks in (msec)
 e.g. sustained short circuit
 200oC to 350oC
 short thermal overshoot (<μsec)
 e.g. hard switching transitions
 beyond 350oC
 catastrophic failure

Breakdown Voltage BVDS
BVDSon
 bias dependent
 on-state BVDSon < off-state BVDSoff ID[A]
 maximum operating voltage VOPmax VOPmax
4
 no lifetime reduction
gradual
degradation
3
2
BVDSoff
VDS[V]
0
0 5 10 15 20 25 30 35

Breakdown Voltage BVDS
BVDSon
 bias dependent VESD
 on-state BVDSon < off-state BVDSoff ID[A]
 maximum operating voltage VOPmax VOPmax
4
 no lifetime reduction
gradual
degradation
3
 ESD protection
 trigger voltage VTRIG
 hold voltage VHOLD 2
BVDSoff
 max ESD voltage VESD
1 VHOLD
 supply voltage VSUP VTRIG
VDS[V]
 VSUP < min(VHOLD, VOPmax) 0
 max(VTRIG,VESD) < BVDSon 0 5 10 15 20 25 30 35

On-Resistance
 linear region:
 x𝑉 < 𝑉 − 𝑉 ID[A]
 x𝐼 = 𝛽 · 𝑉 −𝑉 − ·𝑉
4
VGS = VGSmax
VDS[V]
0
0 5 10 15 20 25 30 35

On-Resistance
 linear region:
 x𝑉 < 𝑉 − 𝑉 ID[A]
 x𝐼 = 𝛽 · 𝑉 −𝑉 − ·𝑉
0,8
VGS = VGSmax
 how to determine RDSon ?
0,6
1 𝑑𝐼
 x𝑅
=
𝑑𝑉 ,
0,4
0,2
VDS[V]
0
0 0,1 0,2 0,3 0,4 0,5

On-Resistance
 linear region:
 x𝑉 < 𝑉 − 𝑉 ID[A]
 x𝐼 = 𝛽 · 𝑉 −𝑉 − ·𝑉
0,8
VGS = VGSmax
 how to determine RDSon ?
0,6
1 𝑑𝐼
 x𝑅 =
𝑑𝑉 ,
0,4
 equation disregards drift region
 measure ID @ VDS=100mV 0,2
 x
𝑉 VDS[V]
𝑅 =
𝐼 ,
0
0 0,1 0,2 0,3 0,4 0,5

Specific On-Resistance RSP[4]
 inversely proportional to device area 25
 RDSon x Area product [mΩmm2]
 net area = pitch x gatewidth
20
RSP[mΩmm2]
 most important FoM in BCD process
15
comparisons
10
 scales with BVDS
 1-D silicon limit: RSP≈BVDS2.5
5
 determined at 25oC
 RDSon temperature dependent 0
10 20 30 40 50
BVDS[V]

Specific Gate Charge QGSP
 gate charge needed to turn from RD
VDSmax
full OFF to full ON VDS
 full OFF: VGS = 0; VDS = VDSmax VD
VDSmax
 full ON: VGS = VGSmax; VDS = 0 IG
VGSmax CGD
VG
𝑄 = 𝐼 · 𝑑𝑡 CGS
full
OFF
 proportional to device area VGSmax VGS
 QG / Area ratio [nC/mm2] full
VTH ON time
t0: start t1: finish

MOSFET FoMs
 specific on-resistance
 RDSon x Area product [mΩmm2]
 conduction loss
 specific gate charge

 QG / Area ratio [nC/mm2]
 switching loss
 area independent product

 RDSon x QG [mΩnC]
 most used FoM for discrete FETs and technologies (e.g. Si, SiC, GaN)

Outline
 Applications
 Circuit Design

Applications of BCD Technology
 Power Conversion [5]
 Motor Drivers [6]
 Industrial [7]
 Class-D Audio Amplifiers [8-11,19]
 Automotive CAN/LIN [12]

 Biomedical [13]
 Wireless Charging [14]
 SSL LED drivers [15,16]
 Energy Harvesting [17]
 Display Drivers [18]
 Common Denominator: Power Switches

Power Switches
 lowside switch VSUP VSUP
 load ground ≠ ground
 heating / lighting
 simple ctrl load ctrl
 higside switch
 load (dis)connected VOUT VOUT
 safety (automotive)
 load ground = ground ctrl load
 complex ctrl
 half bridge

Half Bridge ?
www.goldegate.org

Half Bridge
 stack of lowside & highside switch VSUP
 something inductive in the load

 inductor, loudspeaker, motor windings, etc..
 break-before-make ctrl
 (flyback) diodes VOUT
 conductive path to supply / ground
 class-D = switch mode

 class-D (audio) amplifiers
 switch mode power supplies (SMPS)
 Pulse Width Modulation (PWM)

Pulse Width Modulation
 input signal VSIG  PWM signal VPWM
 duty-cycle proportional to VSIG
 high frequency reference VTRI
 triangular or sawtooth  after low pass filter VLPF
 FPWM >10 x FSIG  input signal VSIG
 plus a (small) high frequency ripple
VSIG VLPF
VPWM
VPWM
VTRI

Single Half-Bridge
VIN
VIN
VOUT
𝑉 =𝐷·𝑉 VLOAD
VLOAD
VOUT IL
IL
0 TSW
DTSW
DC-DC Buck Converter


Single Half-Bridge
VLOAD
VLOAD
VOUT
VIN
VOUT 𝑉 IL
IL 𝑉 =
1−𝐷 VIN
0 TSW
DTSW
DC-DC Boost Converter


2 Half Bridges make a Full Bridge
VSUP VSUP
VSPKP VSPKN
VOUTP VOUTN
VSPKP
VSPKN
Class-D Audio Amplifier [8]


VSUP VSUP
VOUTP
IL
M VOUTN
(DC+ripple)
DC-Motor Driver

VSUP VSUP
www.tdk.com
VOUTP VOUTN
IL
@ resonance
Qi Wireless Charging Transmitter


3 Half Bridges make a 3-Phase Full Bridge
VSUP VSUP VSUP
Φ1 VOUT1
VOUT2
Φ2 VOUT1
VOUT2
VOUT1 VOUT1
Φ3 Φ1
Φ3
Φ2
N
3-Phase Power Inverter

3 Half Bridges make a 3-Phase Full Bridge
VSUP VSUP VSUP
VOUT1
VOUT2
IM2
VOUT1
VOUT2
VOUT1 VOUT1
IM1 IM3
Φ1
Φ3
Φ2
Brushless DC-Motor Driver [6]


More Legs ?
VSUP VSUP VSUP VSUP
VOUTP1 VSPKP VSPKN VOUTN2

VOUTP2 VOUTN1
VSPKP
VSPKN
Multi-Phase PWM Class-D Audio Amplifier [19]


Outline
 Applications
 Circuit Design

Half Bridge Switch Implementation
 external (discrete) powerFETs VSUP
 voltage x current > 1000VA
 GaN / SiC
 ctrl IC in BCD technology
VGH
MH
 integrated powerFETs VOUT
ctrl
 voltage x current < 400VA
 DMOS
VGL
ML

Challenges of High Current
 dissipation
 conduction loss I2xRDSon
 thermal design
 high current switching

 high dI/dt in ground / supply lines
 large voltage excursions
 parasitic inductance
 bondwires, lead fingers, PCB tracks
 separate power ground

Challenges of High Voltage
 for circuit design Voltage becomes High Voltage when VSUP > VGSmax
 design measures needed to prevent damage
 limit voltage swings

 voltage clamps
 high voltage cascodes
 use local (low) voltage supply domains

 beware voltage domain crossings
 ESD
 beware floating nodes !!!!!

 standby / powerdown modes

 design economy
 only use HV devices when absolutely necessary
 usually, more area efficient solutions are possible
Wilson active cascode

 beware of floating nodes
 biasing switched off in standby / powerdown modes => floating nodes
 leakage through body diode => oxide damage
high voltage
clamp pulldown
leakage current
pd floating node pd pd

 limit voltage swings
 clamps => inactive during normal operation
 beware overdrive cases
high voltage supply

zener bypass

Half Bridge Essentials
 PowerFETs VDDH VDDP
 BST
 highside gatedrive voltage BST GDRV OCP
VGH
MH
 GDRV
 powerFET gate driver
VOUT
VDDA VDDL
 LSH
 levelshifters
CTRL LSH GDRV OCP
VGL
ML
 OCP
 overcurrent protection VSSA
VSSP

 BST
VGH
MH
 GDRV
VOUT
VDDA VDDL
 LSH
 levelshifters
CTRL LSH GDRV OCP
VGL
ML
 OCP
VSSP

Design Considerations on PowerFETs
 powerFET design target: resistance in ON state VDDP
 conduction loss
 intrinsic RDSon
 determine size using RDSon * Area VGH
MH
 account for interconnect resistance VOUT
 account for temperature dependence
VGL
ML
VSSP

PowerFET Interconnect
 typical BCD technology
 4 to 6 interconnect layers
 Alumin(i)um (Al) or Copper (Cu) UTM

 Cu has 40% lower resistivity
 ultra thick top metal (UTM)

M3
 3μm Cu: 6mΩ/□
M2
 3μm Al: 10mΩ/□
M1

 first metal: M1
 alternating source/drain
 low-ohmic gate connection
SDSDSDSDSDSDSDSDSDSDSDSDSDSDS

 second metal: M2
 perpendicular to M1
 maximize vias
D
D
S

 second metal: M2
 maximize vias
D
 M1 stripes connect in parallel S

 negligible contribution M1 to
D
total resistance
S
D
S

 third metal: M3
 maximize vias
S D S D S D

 third metal: M3
 maximize vias
 M2 stripes connect in parallel

 negligible contribution M2 to
total resistance
S D S D S D

 top metal UTM
 ultra thick
 maximize vias
 tapered fingers
D S

 top metal UTM
 ultra thick
 maximize vias
 tapered fingers
 uniform current density

 minimal resistance D S
 approximate resistance
 R□UTM x Aspect Ratio
 more accurate
 3D resistive extraction tools

 example: class-D audio amplifier (Paper 31.2)

Temperature Dependence On-Resistance
2
R/R(25oC)
normalized on-resistance
1,75
+40% @ 150oC
1,5
1,25
0,75
-25%
0,5 @ -40oC
0,25
Temp [oC]
0
-50 -25 0 25 50 75 100 125 150

Dissipation & Heat Flow
 dissipation
 conversion of (electrical) power into heat
silicon die
heat flow (junction)
die pad
(case)
heatsink
ambient

Thermal Modeling
 electrical equivalent
 current power dissipation
 voltage temperature
 thermal circuit
 thermal resistance RTH [K/W]
TJ
 thermal capacitance CTH [K/J]
ΔT RTH
 ambient temperature TAMB
TAMB
PDISS CTH
 junction temperature TJ TAMB

Thermal Modeling
 electrical-thermal co-simulation  sequential iterations
 electrical simulation yields PDISS
 simultaneous  thermal simulation yields TJ
 not all circuit simulators can do this  rerun simulations until convergence
TJ
ID RTH
ΔT
VDS TAMB
PDISS CTH
VGS MPWR
TAMB
PDISS=VDS x ID

 BST
VGH
MH
 GDRV
VOUT
VDDA VDDL
 LSH
 levelshifters
CTRL LSH GDRV OCP
VGL
ML
 OCP
VSSP

Bootstrap
VDDP
 lowside gatedriver supply VDDL
 limit VGS of ML VDDH
GDRV
VGH
MH
VOUT
VDDL
GDRV
VGL
ML
VSSP

Bootstrap
VDDP
 linear regulator GDRV

 external decoupling CREG VGH
MH
VOUT
VDDL
VREG
GDRV
VGL CREG
ML
VSSP

Bootstrap
VDDP
 linear regulator GDRV

 external decoupling CREG VGH
MH
 gate charge QGL drawn from VDDP

VOUT
 via regulator VDDL
VREG
QGL
GDRV
VGL CREG
ML
VSSP

Bootstrap
VDDP
 highside gatedriver supply VDDH
 limit VGS of MH VDDH
GDRV
VGH
MH
VOUT
VDDL
VREG
GDRV
VGL CREG
ML
VSSP

Bootstrap
VDDP
 external cap CBST GDRV

 diode DBST connection to VDDL VGH CBST
DBST MH
VOUT
VDDL
VREG
GDRV
VGL CREG
ML
VSSP

Bootstrap
VDDP

DBST MH
 turn on lowside ML VOUT

 CBST charged via DBST from VDDP VDDL
VREG
GDRV
VGL CREG
ML
VSSP

Bootstrap
VDDP
QGH
DBST MH
 turn on lowside ML VOUT

 CBST charged via DBST from VDDP VDDL
VREG
 turn on highside MH
GDRV
 DBST reverse biased VGL CREG
ML
 gate charge QGH drawn from CBST
VSSP

Bootstrap Switch
VDDP
 turn off MBST when VOUT is high
 body diode reverse biased VDDH
 turn on MBST when VOUT is low GDRV

 body diode bypassed VGH CBST
MBST MH
 no forward diode voltage drop
VOUT
VDDL
VGL CREG
ML
VSSP

Bootstrap Switch
VDDP
MBST MBST VDDH

on off
VA
VA-VOUT
GDRV
VB VGH CBST
latch toggles MBST MH
VB-VOUT
MLSH
VOUT
VDDL
VOUT
VGL
VGL CREG
ML
VSSP

Integrated Bootstrap [20]
VDDP
 two stage bootstrap
VB VDDH
 small HV capacitor CHV
VDDP DHV MHV
 output VOUT low GDRV
 switch MHV off CHV VGH CBST
DBST MH
 CBST charged to VDDL
 CHV charged to VDDP
VOUT
VDDL
 output VOUT high
 switch MHV on
 CHV discharges to CBST
VGL CREG
 QGH = CHV x (VDDP-VDDL) ML
VSSP

Chargepump[21] + Regulator
 input voltage DBST DOUT
VDDP VDDQ
 VIN = VDDP – VSSH
 output voltage CBST

VCLK COUT
 VDDQ = VDDP + VIN
 attractive in applications with VREG VDDP

VSSH
multiple half bridges
 e.g. 4-channel class-D audio
VDDQ
amplifier would need 8 bootstrap
caps
VDDP
VSSP
VSSH
1/fCLK

 BST
VGH
MH
 GDRV
VOUT
VDDA VDDL
 LSH
 levelshifters
CTRL LSH GDRV OCP
VGL
ML
 OCP
VSSP

Inverter Gate Drivers
VDDH VDDP
 lowside gatedriver
MPH
 supply VDDL (regulator)
 (local) ground VSSP
VGH
MH
 highside gatedriver MNH
 supply VDDH (bootstrap)
 (local) ground VOUT VOUT
VDDL
MPL
VGL
ML
MNL
VSSP

Parasitic Capacitances
VDDH VDDP
 lowside gatedriver
MPH
 supply VDDL (regulator)
CGDH
 (local) ground VSSP
VGH
CGSH MH
 highside gatedriver MNH
 supply VDDH (bootstrap)
 (local) ground VOUT VOUT
VDDL
 switching dymanics MPL
 gate driver size CGDL
 parasitic capacitances powerFETs
VGL
CGSL ML
MNL
VSSP

Zero Current Switching

VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
MNH
0 VOUT
VGSL time VDDL
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
INH MH
CGSH
MNH
0 VOUT
VGSL time VDDL
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
dead time MNH
0 VOUT
VGSL time VDDL
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
𝑉 =𝑉 MNH
0 VOUT
VGSL time VDDL
MPL
IPL CGDL
VGL
CGSL ML
VSSP MNL
VSSP

VDDH VDDP
VDDP MPH
VOUT
𝑑𝑉 𝐼 CGDH
VGSH =−
𝑑𝑡 𝐶 VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL
MPL
IPL CGDL
VGL
CGSL ML
VSSP MNL
VSSP

VDDH VDDP
VDDP MPH
VOUT
𝑑𝑉 𝐼 CGDH
VGSH =−
𝑑𝑡 𝐶 VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL
MPL
IPL CGDL
VGL
CGSL ML
VSSP MNL
VSSP

VDDH VDDP
VDDL(VDDH)
MPH
MPL CGDH
prevent shoot-through:
VGH
IPL MH
CGSH
MNH
(W/L)NH : (W/L)PL
VGL(VGH) VOUT
VDDL
MPL
VGH < VTH IPL CGDL
MNH
VGL
CGSL ML
VSSP(VOUT) MNL
VSSP

VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL
MPL
IPL CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Soft Switching

Soft Switching
VDDH VDDP
VOUT
VDDP 𝑉 =𝑉 −𝐼 ·𝑅 MPH
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Soft Switching
VDDH VDDP
VOUT
VDDP MPH
CGDH
VGSH 2 VGH
𝑉 ≅𝑉 + ·𝐼 INH MH
𝛽 MNH
CGSH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Soft Switching
VDDH VDDP
VOUT
VDDP MPH
CGDH
VGSH
VGH
INH MH
CGSH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
𝑑𝑉 𝐼
=− VGL
𝑑𝑡 𝐶 CGSL ML
VSSP MNL
VSSP

Soft Switching
VDDH VDDP
VOUT
VDDP MPH
CGDH
VGSH
VGH
INH MH
CGSH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
𝑑𝑉 𝐼
=− VGL
𝑑𝑡 𝐶 CGSL ML
VSSP MNL
VSSP

Soft Switching
VDDH VDDP
VOUT
VDDP MPH
CGDH
VGSH
VGH
INH MH
CGSH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
VGL
body diode conduction CGSL ML
VSSP MNL
VSSP

Soft Switching
VDDH VDDP
VOUT
VDDP MPH
CGDH
VGSH
VGH
INH MH
CGSH
dead time MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Soft Switching
VDDH VDDP
VOUT
VDDP MPH
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
IPL CGDL
VGL
𝑉 =𝑉 −𝐼 ·𝑅 CGSL ML
VSSP MNL
VSSP

Hard Switching

Hard Switching
VDDH VDDP
VDDP
VOUT
𝑉 =𝑉 +𝐼 ·𝑅 MPH
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Hard Switching
VDDH VDDP
VDDP body diode conduction MPH
VOUT
CGDH
VGSH
VGH
INH MH
CGSH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Hard Switching
VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
dead time MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Hard Switching
VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
MNH
𝑉 >𝑉
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
IPL CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Hard Switching
VDDH VDDP
VDDP MPH
VOUT
𝐼 =𝐼 𝐼 =0 CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
IPL CGDL
VGL
CGSL ML
VSSP MNL
VSSP

Reverse Recovery
Forward Current IF Reverse Recovery Time: tRR
IF tRR
time
0.25 IRR QRR
IRR
Reverse Recovery Charge: QRR

Hard Switching
VDDH VDDP
VDDP MPH
VOUT IRR
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
2 IPL CGDL
𝑉 ≅𝑉 + · 𝐼 +𝐼
𝛽 VGL
CGSL ML
VSSP MNL
𝑃 ≅ 𝑉 −𝑉 × 𝐼 +𝐼
VSSP

Hard Switching
VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
𝑑𝑉 𝐼 IPL
=− CGDL
𝑑𝑡 𝐶 VGL
CGSL ML
VSSP MNL
VSSP

Hard Switching
VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
𝑑𝑉 𝐼 IPL
=− CGDL
𝑑𝑡 𝐶 VGL
CGSL ML
VSSP MNL
VSSP

Hard Switching
VDDH VDDP
VDDP MPH
VOUT
CGDH
VGSH
VGH
CGSH MH
MNH
VTH
0 VOUT
VGSL time VDDL IOUT
MPL
IPL CGDL
VGL
CGSL ML
VSSP MNL
𝑉 =𝑉 +𝐼 ·𝑅 VSSP

Dead Time
VOUT
VDDP VDDP
VOUT Hard Switching Soft Switching
VGSH VGSH
VTH VTH
0 0
VGSL time VGSL time
dead dead
time time
VSSP VSSP

Dead Time[22]
VOUT
VDDP VDDP
VOUT Hard Switching Soft Switching
VGSH VGSH
VTH VTH
0 0
VGSL time VGSL time
VSSP VSSP

Adaptive Gatedriver[10]
 adjustable driver sizes
 optimize size per scenario
VDDH VDDP
 negative dead-time
 elimitate reverse recovery MPH3 MPH2 MPH1
GDRV
logic VGH
MH
MNH2 MNH1
VOUT

Chargepump Gatedriver[19]
VDDQ
 constant chargepump voltage
 VDDQ = VDDP + 5V
VDDH
VDDP
 integrated bootstrap capacitor
 VDDH = VOUT + 3.3V + VTHn
 charge current multiplier CBST VGH

MH
VOUT
 5-channel multiphase class-D audio amplifier
 2 external caps for chargepump i.s.o. 20 bootstrap caps

 BST
VGH
MH
 GDRV
VOUT
VDDA VDDL
 LSH
 levelshifters
CTRL LSH GDRV OCP
VGL
ML
 OCP
VSSP

Levelshifters
HV Domain
(e.g VDDH = 60V, VSSH = 58.2V)
 circuit that transfers (logic) signals
VDDH
between voltage domains
 output voltage domain can DOUT

 positive / negative
VSSH
 static / dynamic
 robustness / sensitivity
VDDL
?
DIN
LV Domain
(e.g. VSSL = 0V, VDDL = 1.8V)
VSSL

Levelshifters
 capacitive
VDDH
 very fast VH
DOUT
 HV domain can be both positive or
VSSH
negative
 no HV devices required CSH

 other than CSH VDDL
DIN
VL
VSSL

Levelshifters
 no signal gain
VDDH
 VH swing < VL swing
 capacitive load CSH top plate VH
DOUT
 top plate voltage drift
VSSH
 DC biasing
 requires regular activity
 not suitable for static signals CSH
VDDA
 sensitive to VSSH transients
 cannot distinguish between DIN
VL
transient on VL and VSSH
VSSA

Levelshifters
 differential operation
VDDH
 shift capacitors driven in anti-phase
 cross-coupled latch fixes low level VHP VHN
VHP/N to VSSH
VSSH
CSHP CSHN
VDDA
DIN
VLP VLN
VSSA

Levelshifters[23]
CFB1
VIN VINX
CFB2
CLKCH
CIN1
VHP VHN
VIN VINX VOUT
CIN2
CLKCH CLKCH
VDDA CSH1 CSH2
 Example: HV input chopper CLKCH VLP VLN

 resistor fixes low level VHP/N to VIN
 ±30V input CM range
VSSA

Levelshifters
 static
VDDH
 only one HV pulldown device RPU
 positive HV domain only
 complementary version for VH DOUT
negative HV domains
VSSH
 no floating nodes
 static & dynamic signals IPD
 VH swing PVT sensitive VDDL
 current consumption when active VL MPD
DIN
 speed / power trade-off
VSSL

Levelshifters[24]
 Example: clamping
VDDH
 differential operation
 non-overlapping NMOS/PMOS
DOUT
clamps VHP VHN
 insensitive to VSSH transients
VSSH
 VSSH swing 0 – 50V
 propagation delay <5ns
VDDL
DIN
VSSL

Levelshifters
 fix VH swing
VDDH
 match IBIAS to RPU RPU
 speed-up capacitor CPD VH DOUT

 current spike at rising edge VL
VSSH
IPD
VDDL
VL MPD
DIN IBIAS
VSSL CPD

Levelshifters[25]
 Example: multichannel
 feedback loop regulates VH swing VDDH
R’PU RPU
to match VDDH-VSSH
 biasing efficiently shared by 32 VH DOUT
channels
 VSSL/VDDL = 0V/3V
VSSH
 VSSH/VDDH = 6V/9V
IPD
VDDL
MPD
DIN
VSSL

Levelshifters[26]
 highside latch
VDDH
 cross coupled inverters
 HV PMOS devices terminate

pulldown currents
 no DC current after transition VSSH
 good for bootstrapped highside
drivers
 requires careful dimensioning to VDDL
cover PVT corners
DIN
 expensive
 4 HV devices required for 1 signal
VSSL

 BST
VGH
MH
 GDRV
VOUT
VDDA VDDL
 LSH
 levelshifters
CTRL LSH GDRV OCP
VGL
ML
 OCP
VSSP

Overcurrent Protection
 latch-off  series current sensing
 permanent shutdown  (external) sense resistors
 accurate
 hiccup mode  power loss
 periodic restart
 parallel current sensing
 cycle-by-cycle current limiting  replica FETs
 continue operation  matching
 prevent ‘audio-holes’  lossless

Replica FET[27]
VD
 replica MREF IREF
 ratio 1:N (e.g. 1:10000)
 gates & sources connected
 matching (geometric & thermal)
ID
 overcurrent comparator VG
 MREF biased at constant current IREF
 overcurrent flag oc if MPWR
oc
ID > N x IREF
 only accurate for positive currents MREF

 diode conduction not homogeneous
1:N VS

Matching
VD
 DMOS has fixed channel length
 only width scaling
 powerFET
 very big (e.g. 10cm gate width)
 many (folded) fingers in parallel VG VG
 replica stacking
 increase ratio 1:N
 increase matching (larger area) MPWR
MREF
1:N VS

Overcurrent Comparator
VD
 current ratio only valid in on-state IREF
 VGS = VGSmax: FETs in linear region
 VDS small
 off-state VDS can be very high

 damage comparator inputs VG
 disconnect switch VSENSE
MPWR
oc
VREF VGmax
MREF
1:N VS

Overcurrent Comparator
VD
 current ratio only valid in on-state IREF
 VGS = VGSmax: FETs in linear region
 VDS small
 off-state VDS can be very high

 damage comparator inputs VG
 disconnect switch VSENSE
MX2
MPWR
oc
 divider switch MX1/MX2 VREF VGmax
 MR and MX1 always on
 off-state: pulldown VX MREF MX1
 on-state: linear division of VDS
 increase ratio 1:N 1:2N VS

Lowside Overcurrent Comparator
VOUT
IREF
VOUT
VGL
VGL
VSENSEL
MX2
ML
ocl
ocl VREFL VDDL
MREF MX1
VREFL
VSENSEL
time
1:2N VSSP

Lowside Overcurrent Comparator
VOUT
 lowside comparator inputs IREF
 VREFL & VSENSEL low voltage w.r.t. VSSP
 straightforward LV compartor design

 low voltage domain [VSSP,VDDL] VDDL
VGL
VSENSEL
MX2
ML
ocl
VREFL VDDL
MREF MX1
VSSP

Highside Overcurrent Comparator
VDDP
 highside comparator inputs IREF
 VREFH & VSENSEH low voltage w.r.t. VOUT
 straightforward LV compartor design CPAR

 switching voltage domain [VOUT,VDDH] VDDH
VGH
VSENSEH
 HV levelshifter
MX2
 och w.r.t switching node VOUT MH
och
 fast & dV/dt insensitive VREFH VDDH
MREF MX1
 capacitive coupling to static nodes
 e.g. IREF to supply VDDP
VOUT

Highside Overcurrent Comparator (2)
VDDP
 input switches
 connect to highside gate MREF MX1
 disconnect inputs in off-state VDDH
VSENSEH
 inputs clamped to VDDP

och
 limited CM swing VGH
VREFH
MX2
MH
 straightforward comparator design VSSH
 output in highside LV domain [VSSH,VDDP]
IREF
 HV levelshifter
 no dV/dt requirement VOUT

Highside Overcurrent Comparator (3)
VDDP
 chargepump voltage VDDQ
 MREF and MX1 always on MREF MX1
 VSENSEH and VREFH close to VDDP VDDQ
VSENSEH
 inputs close to VDDP

och
 limited CM swing VGH
 no clamps needed
VREFH
MX2
MH
IREF
VOUT

Papers to see at ISSCC2022
 Session 14: GaN, High-Voltage and Wireless Power
 14.4 “A 2.5−5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC
Converter Adopting Ladder SC Network with Capacitor Assisted Dual Inductor
Filtering”
 14.6 “A 27W D2D Wireless Power Transfer System with Compact Single-Stage
Regulated Class-E Architecture and Adaptive ZVS Control”
 14.7 “A 1.2W 51%-Peak-Efficiency Isolated DC-DC Converter with a Cross-
Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI
Standard”
 Session 18: DC-DC Converters

 18.2 “A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9μs 1%
Settling Time for a 3A/20ns Load Transient”
 18.7 “A 2−5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR
Boosting Scheme Achieving 91% Efficiency at a Conversion Ratio of 12”

Papers to see at ISSCC2022 (2)
 Session 30: Power Management Techniques
 30.2 “A 130V Triboelectric Energy-Harvesting Interface in 180nm BCD with
Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling
Technique”
 30.3 “A Reconfigurable Series-Parallel Charger for Dual-Battery Applications with
89W 97.7% Efficiency in Direct Charging Mode”
 Session 31: Audio Amplifiers

 31.2 “A 121.4 dB DR -109.8 dB THD+N Capacitively-Coupled Chopper Class-D Audio
Amplifier”
 31.4 “A -91 dB THD+N, Resistor-Less Class-D Piezoelectric Speaker Driver using a Dual
Voltage/ Current Feedback for LC Resonance Damping”

References
1. A. Andreini, Claudio Contiero and Paola Galbiati, “A New Integrated Silicon Gate Technology Combining Bipolar Linear, CMOS
Logic, and DMOS Power Parts”, IEEE Transactions on Electron Devices, Vol ED-33, No. 12, December 1986
2. C. Contiero, A. Andreini and Paola Galbiati, “Roadmap Differentiation and Emerging Trends in BCD Technology”, ESSDERC 2002
3. P. Wessels, et al, “Advanced BCD technology for automotive, audio and power applications”, Solid-State Electronics, No 51. pp
195-211, 2007
4. F. Hébert, et al., “Building blocks of past, present and future BCD technologies”, 33rd ISPSD, 2021
5. J. Wittmann, T.Rosahl, B.Wicht, “A 50V High-Speed Level Shifter with High dv/dt Immunity for Multi-MHz DCDC Converters”,
ESSCIRC 2014
6. V. de Smedt, J. Thoné and M. Wens, “A 650 V, 3 A three-phase fully-integrated BLDC motor driver with charge pump and level
shifters”, ESSCIRC2016
7. Q.Fan, J. Huijsing, K.Makinwa, “A Capacitively Coupled Chopper Instrumentation Amplifier with a ±30V Common-Mode Range,
160dB CMRR and 5μV Offset”, ISSCC 2012
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10. M. Berkhout, “A 460W Class-D Output Stage with Adaptive Gate Drive”, ISSCC 2009
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2014
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Analog MPPT Algorithm Reaching up to 88% End-to-End Efficiency”, ISSCC 2013
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JSSC 1976
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ISSCC 2022 Tutorials

Analog Circuit Design in Bipolar-CMOS-DMOS (BCD)

Live Q&A Session: Feb. 20, 2022, 8:40-9:00am, PST

© 2022 IEEE International Solid-State Circuits Conference

 Expert Class-D Audio Power Amplifiers

 Technical Program Committees

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

battery chargers induction cooking

solar inverters motor drivers LED matrix lighting

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

 application optimized BCD process nodes

 high voltage comes at the price of silicon area

© 2022 IEEE International Solid-State Circuits Conference

 high current requires low-ohmic connections

© 2022 IEEE International Solid-State Circuits Conference

 Introduction & Motivation

 BCD Process Technology & Devices

 Device Characteristics & Figures-of-Merit

© 2022 IEEE International Solid-State Circuits Conference

 Introduction & Motivation

 BCD Process Technology & Devices

 Device Characteristics & Figures-of-Merit

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

p- substrate NMOS PMOS

© 2022 IEEE International Solid-State Circuits Conference

p- substrate NMOS PMOS

© 2022 IEEE International Solid-State Circuits Conference

p- substrate NMOS PMOS

© 2022 IEEE International Solid-State Circuits Conference

NMOS PMOS GND

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

p- substrate NMOS PMOS

© 2022 IEEE International Solid-State Circuits Conference

p- substrate NMOS PMOS

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

 three regions with different dopant

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

h+  reverse biased base-collector junction

 high current gain

© 2022 IEEE International Solid-State Circuits Conference

dopant conc. (log)

p- substrate VNPN depth

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference

dopant conc. (log)

p- substrate DMOS depth

© 2022 IEEE International Solid-State Circuits Conference

p- substrate DMOS S/B S/B S/B

© 2022 IEEE International Solid-State Circuits Conference

© 2022 IEEE International Solid-State Circuits Conference