JSPM’S Group of Polytechnics.

Chapter 1
8086 16-bit Microprocessor: - 14 Marks
Course Outcome: Analyze the Functional Block of 8086 Microprocessor

2.1 Salient features

Pin descriptions
Architecture of 8086 - Functional Block diagram
Register organization
Concepts of pipelining
Memory segmentation
Physical memory addresses generation.

2.2 Operating Modes of 8086

8284 Clock Generator
8288 Bus Controller
74LS245 Bi-directional Buffer
74LS373 Octal Latch
Minimum Mode operation and its timing diagram
Maximum Mode operation and its timing diagram

Objective:
➢ Define the functions of different pins
➢ Draw functional block diagram of 8086
➢ Understand the operating modes of 8086

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2.1.1 Silent Features of 8086 Microprocessor:

1. It is 16 bit microprocessor means it can read, write or perform operation on 16 bit data at
a time.
2. It consists of 29000 transistors of HMOS type.
3. It is available in 40 pin DIP IC.
4. The operating clock frequencies are 5MHz, 8MHz and 10MHz.
5. It provides 256 types of vectored software interrupts.
6. The instruction set is powerful, flexible and can be used for high level language.
7. It has 20 address lines so it can provide 1Mbytes of memory.
8. From 20 address lines, 16 address lines are multiplexed with data lines named as AD0-
AD7 and remaining four address lines are also multiplexed with status signal.
9. It generates 16 bit I/O address so it can access maximum 64k I/O devices.
10. It operates in minimum and maximum mode to achieve high performance level.
11. It supports multiprogramming.
12. It provides separate instructions for string manipulation.
13. It can operate in single processor and multiprocessor configuration.
14. It provides 6 bytes of instruction queue for pipelining of instruction execution.
15. It is developed by Intel in 1978 which requires 5v power supply.

Question:

1. List any four silent features of 8086 microprocessor (summer 15).

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2.1.2 PIN CONFIGURATION OF 8086:

GND 1 VCC
40
AD14 2 AD15
39
AD13 3 A16/S3
38
AD12 4 A17/S4
37
AD11 5 A18/S5
36
AD10 6 A19/S6
35
AD9 7 BHE/S7
34
AD8 8 MN/MX
33
AD7 9 RD
32
Microprocessor
AD6 10 RQ/GT0
core 8086 31 HOLD
AD5 11 RQ/GT1
30 HLDA
AD4 12 LOCK
29 WR
AD3 13 S2
28 M/IO
AD2 14 S1
27 DT/R
AD1 15 S0
26 DEN
AD0 16 QS0
25 ALE
NMI
17 QS1
24 INTA
INTR
18 TEST
CLK 23
19 READY
GND 22
20 RESET
21

20
20

Maximum Minimum
Mode Signals Mode Signals

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Fig.1 Pin Configuration of 8086 Microprocessor.

JSPM’S Group of Polytechnics.

2.1.2.1 Pin diagram Description:

1. AD0-AD15:

These lines are time-multiplexed bi-directional address/data bus. During T1 clock cycle of bus
cycle, they carry lower 16 bit address. During T2, T3 & T4 they carry 16 bit data. Hence AD0-
AD7 lines carry lower order byte of data and AD8 – AD15 carry high order byte of data.

2. A16-A19/S3-S6:

These are time multiplexed address and status lines. During T1 clock cycle, these lines carry upper
four bits address and during I/O operation these lines are low.

During T2, T3 & T4 clock cycle S3 &S4 carry status signal. These signal used to identify memory
segments.

S4 S3 Segment Register
0 0 ES(Extra Segment)
0 1 SS(Stack Segment)

1 0 CS(Code Segment)
1 1 DS(Data Segment)

S5 is an interrupt enable status signal.

3. BHE/S7 (Bus High Enable/Status):

When this signal is low it indicates the transfer of data over higher order bus. BHE pin with A0
determines whether a byte or word will be transferred from or to memory locations.

4. RD(Read):

It is active low read signal used by microprocessor that indicates processor is performing read
operation depending on the status signal M/IO.

5. READY:

It is active high input signal. It indicates that the peripheral device is ready to transfer data.
This pin is used to add wait state. When this pin is activated gives information about 8086 is

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ready and operate normally. When this pin is low it indicates 8086 is in wait state. During wait
state the signals on the buses remaining the same as they at the start of the wait state.

6. REAET: It is used to reset the system. When this signal is high it indicates processor enter
into reset state and terminates current activity and start execution from FFFF0H.
7. INTR (Interrupt Request): It is level triggered interrupt request input. If any interrupt
request is occurred the processor enters into the interrupt acknowledge cycle.
8. NMI (Non- Maskable Interrupt): this interrupt is not avoided by software. It is an edge
triggered input interrupt request.
9. TEST: It is used to test the status of co-processor like 8087. If this pin is low then execution
will continue else the processor remains in an idle state.
10. CLK (Clock input): It provides timing to the processor operations. The range of frequency
for different 8086 versions is from 5MHz to 10MHz.
11. VCC: +5V power supply for the operations of microprocessor.
12. GND: It provides ground for internal circuitry.
13. MN/MX: this pin indicates operating modes of 8086. There are two operating modes as
below-
1. Minimum Mode
2. Maximum Mode

When this pin is high or VCC then processor operates in minimum mode. When this pin is
connected to GND processor operates in maximum mode.

Minimum Mode pins:

14. DEN (Data Enable): It is an active low signal issued by processor indicating the
availability of valid data over AD0-AD15.
15. DT/R (Data transmit/ receive): This is output signal used to decide the direction of data
flow through 8286 bi-directional buffer. When processor sends data out, this signal is high
and when the processor receives data then this signal is low.
16. M/IO (Memory/Input output): this signal indicates either microprocessor accessing
memory or I/O device. When this signal is high memory is accessed and when signal is
low then I/O device is accessed by microprocessor.
17. WR (Write): It is an active low signal issued by processor to write data to memory or I/O
device depending on the status signal M/IO pin.
18. HLDA (Hold Acknowledge): This is an active high output signal generated by processor
after receiving the HOLD signal.
19. HOLD: This is an active high input signal. When this pin is high the it indicates other
master controller is takes control on address and data buses of microprocessor.

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20. ALE (Address Latch Enable): It is active high pulse issued by processor during T1 state
of bus cycle to indicate availability of valid address on the AD0-Ad15.
21. INTA: It is active low output signal. When processor INTR interrupt, then INTR interrupt
is acknowledge by generating this signal.

Maximum Mode pins:

22. QS1, QS0 (Queue Status): These lines provide information about the status of instruction
queue during clock cycle after which the queue operation is performed.
23. S0, S1 & S2(Status Signal): These pins indicates different types of operations performed
by microprocessor and required by controller Intel 8288.
24. LOCK: this is an active low output signal used to prevent the bus master from gaining the
system bus. It prevents the HOLD signal.
25. RQ/GT0, RQ/GT1 (Request/Grant): These pins are used by other local bus master in
maximum mode to gain the control of local buses at the end of processor current bus cycle.
These are bi-directional pin which has highest priority.

Questions:

1. Draw the pin diagram of 8086.(Summer 14)

2. State the functions for the following pins of 8086.

i) TEST
ii) BHE
iii) INTA
iv) DT / R (summer 14)

3. State the functions of following pins of 8086 microprocessor:

(i) ALE
(ii) DT / R
(iii) M / IO
(iv) HOLD (winter 14)

4. State the function of the following pins of 8086

(i) NMI
(ii) TEST
(iii) DEN
(iv) MN/MX (summer 15).

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2.1.3 INTERNAL ARCHITECTURE OF 8086:

Memory interface

C BUS

B BUS 6
5 BIU
ES
4
Instruction
CS 3
Queue
2
SS
1
DS

IP
CONTROL SYSTEM

A BUS

EU
ALU
AH Al
BH BL
CH CL
DH DL
SP

BP OPERANDS

SI FLAGS
DI

Fig. 2 Architecture of 8086 Microprocessor 2.7

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The 8086 CPU is divided into two functional parts:

1. Execution Unit (EU)

2. Bus Interface Unit(BIU)

1. Execution Unit:

The execution unit is responsible to perform the execution of instruction by bus interface unit
(BIU). The EU contains the control circuitry to perform various internal operations. The EU
contains of 8 general purpose register, two 16 bit pointer register, 16bit ALU and flag register.

i. ALU (Arithmetical and Logical Unit): The ALU is of 16 bit hence, it is called as 16 bit
microprocessor. The ALU is responsible to perform all arithmetical and logical
operations like addition subtraction, multiplication , division , ANDing, Oring etc.
ii. General Purpose Register: the execution unit has 8 general purpose register
AH,AL,BH,BL,CH,CL,DH,DL. These registers can be used as 8 bit register
individually for temporary storage. The AL register is called Accumulator. These
register can be used in pairs as AH-AL, BH-BL,CH-CL and DH-DL.
The AH-AL referred as AX.
BH-BL referred as BX.
CH-CL referred as CX.
DH-DL referred as DX.

AX (Accumulator): AX is a 16 bit accumulator with the lower 8 bit of AX designed as

AL and upper 8 bit of AX designed as AH. Al can be used as 8 bit accumulator for 8
bit operation. It is the most important general purpose register having multiple function.

BX (Base Register): For memory related instruction register BX is used to store 16 bit
effective address of the corresponding memory locations.

CX (Counter): For string instruction microprocessor use CX register as 16 bit counter.

Similarly for rotate shift and loop instruction microprocessor will use register CL as 8
bit counter.

DX (Data Register): for IN and OUT instruction 16 bit port address is stored in register
DX during certain I/O instruction. If the result of multiplication is more than 16 bits
the lower order16 bit are stored in AX and high order 16 bit stored in DX register.

iii. SP and BP (Pointer Register and Base Pointer): the other register in execution unit are
SP, BP i.e. stack pointer and base pointer which is called pointer register. These register
are used during stack memory related operation and also used to hold 16 bit offset
within the particular segment.
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iv. SI and DI (Source Index and destination index): the 8086 microprocessor has two 16
bit index register as source index (SI) and destination index (DI). These are particularly
used for string manipulation. The SI is generally used to store the offset of source data
or string the date segment. While DI is used to store the offset of the destination in data
or extra segment.
v. Operands: the 8086 microprocessor has 16 bit temporary register as operand register,
these register are only used by microprocessor.
vi. Flag Registers: A flag is a flip flop which indicates some condition produced by the
execution of an instruction or control certain operation of the EU. Flag Register is a 16
bit register.
The flag register consist of the status as well as the control flags as below:

I. Status Flags:
1. Carry Flag
2. Parity Flag
3. Auxiliary carry Flag
4. Zero Flag
5. Sign Flag
6. Overflow Flag

II. Control Flags:

1. Trap Flag
2. Interrupt Flag
3. Direction Flag

D15 D14 D13 D112 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

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X X X X OF DF IF TF SF ZF X AF X PF X CF

Overflow Flag
Carry Flag
Direction Flag
Parity Flag
Interrupt Flag

Trap Flag Sign Flag Zero Flag Auxiliary carry Flag

Fig.3 Flag Register.

1. Carry Flag (CF): it is set to 1 when carry generated from MSB position either it will reset
to 0.
2. Auxiliary Flag(AF): If an operation performed in ALU generates a carry / borrow from
lower nibble to upper nibble i.e. carry is generated at D3 bit of 8 bit data then this flag will
be set to the 1 either it will reset to 0.
3. Parity Flag (PF): it indicates parity of result. If lower order 8 bit of result of an operation
contains even numbers of 1’s then parity flag will set to the 1 and for odd number of 1’s ,
the parity flag is reset to 0.
4. Zero Flag (ZF): it is set, if the result of arithmetic or logical operation is zero else it will be
reset.
5. Sign Flag (SF): it gives magnitude of a number is indicated by MSB bit. If the result of
operation is negative, sign flag is set either it will reset.
6. Overflow Flag (OF): In case of the signed arithmetic operation. The overflow flag is set, if
the result is low large to fit in the number of bits available to accommodate it.
This flag has no significance in unsigned arithmetic operation.
7. Trap Flag (TF): it is used for single step control. When trap flag is set. The program can be
run in single step mode. It allow user to execute one instruction of a program at a time for
debugging.
8. Interrupt Flag (IF): It is an interrupt enable / disables flag. If it is set, Maskable interrupt
INTR of 8086 is enable and if it is reset the interrupt is disable.
9. Direction Flag (DF): It is used in string in string operation. If DF is set, string bytes are
read or write from higher memory address to lower memory address.

2. Bus Interface Unit (BIU):

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The BIU is responsible to perform all bus related operation including transferring address on
address line, transferred and receiving data with data line and generating control signals etc.

The BIU consist of four 16 bit segment registers ES,DE,CS,SS and 16 bit instruction pointer (IP).
Address generator unit six 8 bit register in IQ. i.e. Instruction Queue.

Various section of BIU are given below:

i. Segment Register: there are four segment register 16 bit each.

Code Segment (CS) register is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.
Data Segment(DS) register points to the date segment of the memory where the data is
stored.
Stack segment(SS) , is used to addressing stack segment of the memory which is aslo
used to store stack related data.
Extra Segment (ES) , which is essentially another data segment of the memory thus it
is used to store data and result.
ii. Instruction Pointer (IP): the instruction pointer register holds the 16 bit address of next
code bit within the code segment. The value stored in IP is called offset or
displacement.
iii. Instruction Queue (IQ): To increase the execution speed BIU fetches as many as six
instruction bytes ahead to time from memory. All the six bytes register are then held in
the first in first out (FIFO) 6 byte register called instruction queue. Then all bytes have
to be given to EU.

Queue Speed up Processing of 8086 Microprocessor:

While BIU fetches the instruction byte the EU execute previously decoded instruction
concurrently. Hence it is quite fats than sending out an address to the memory and waiting for the
memory to send back the next instruction byte.

To speed up the program execution, the BUS interface Unit (BIU) fetches. Six instruction byte
ahead of time from memory. These perfected instruction byte are held for the execution unit (EU)
in a FIFO group of register called as queue. While BIU fetches the instruction byte, the EU
executes the previously decoded instruction concurrently. Hence, it is quite faster and waiting for
the memory to send back the next instruction byte. In this way, the queue speed up the processing
of 8086.

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2.1.4 Register Organization:

AH AL
BH BL General Purpose
CH CL Register

DH DH
SP
Pointer Register
BP

SI
Index Register
DI

CS

DS

SS
Segment Register
ES

IP
Instruction pointer and
FLAGS Flag Register

Fig. 4 Register Organization

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Questions:

1. Draw the flag register format of microprocessor 8086 and explain any two flags.(summer
14)
2. Draw the neat labeled functional block diagram of 8086. (Summer 14).
3. State the names of segment registers in 8086 microprocessor (winter 14)
4. List the names of flags in flag register of 8085 microprocessor (winter 14)
5. List & explain the functions of all general purpose registers of 8085 microprocessor.
(winter14)
6. Draw the neat labeled architecture of flag register of 8086 microprocessor (winter 14)
7. Write any four important functions of any two units of 8086 microprocessor (winter 14)
8. List all 16 bit registers in 8086 and write their functions (summer 15)
9. Draw architecture of 8086 and label it. Write the functions of BIU and EU (summer 15).

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2.1.5 Concept of pipelining:

The concept of fetching one instruction while other is being execution is called as pipelining. In
microprocessor 8086, the BIU and EU both operate simultaneously, i.e. when BIU fetches one
instruction at the same time, EU performs the execution of another pre- fetched instruction.
Initially all the instruction of a program is present in the code segment.

Whenever BIU fetches any instruction from code memory segment, it stores it in instruction
queue (IQ).

F D E F D E F D E

Clock Cycle I1 I1 I1 I2 I2 I2 I3 I3 I3
1 1 1 1 1 1 1

Fig. 5. Non – Pipelined processor.

F I1 I2 I3 I4 I5
1 1 1 1

D I1 I2 I3 I4
1 1 1 1

E I1 I2 I3
1 1

Fig 6. Pipelined execution of three instructions

In non – pipelined processor, nine clock cycles are required for the individual fetch, decode and
execute cycle for the three instruction as shown in fig 7. In a pipelined processor where fetch
decode and execute operations are performed in parallel only five cycles are required as shown
in fig 8. first instruction requires three cycles to complete. So while executing first instruction in
a queue. Processor decodes second instruction and fetch 3rd instruction from memory.

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Advantages of pipelining:

i. It speed the execution of the processor.

ii. Pipelining eliminates the waiting time of EU and speed up the processing.
iii. Pipelining results in a tremendous performance gain.
iv. It allows execution to be done in fewer clock cycles.
v. The EU always reads the next instruction byte from the queue in the BIU. This is
much faster than sending out an address to the memory and waiting the next
instruction byte to come.

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2.1.6 Memory Organization:

The memory in 8086 based system is organized as segmented memory. 8086 has 20 address lines
therefore the maximum memory which can be interfaced is memory 2 20 = 1MB.

This 1MB memory is divided into number of logical segments. Each segment is 64k bytes in size
and addressed by one of the segment register.

FFFFFH

7FFFFH
EXTRA
SEGMENT(64K)
70000H

5FFFFH
STACK
50000H SEGMENT(64K)

3FFFFH
CODE
30000H SEGMENT(64K)

2FFFFH Top of DS

20000H DATA SEGMENT(64K)

0000H Base of DS

Fig.7 Memory Segmentation of 8086.

The four segment register in the segment register to hold the upper 16 bit of starting address of
four memory segments that the 8086 is working with at a particular time.

The four memory segment are the code segment (CS), the stack segment (SS), Extra segment (ES)
and Data Segment (DS).
00000H
The fig shows how these four segments might be positioned in memory at a given time. The four
segments can be separated as shown or for small program which do not need all 64kbytes in each

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segment, they can overlap. Segment register is used to hold the upper 16 bits of the starting address
for each of the segments.

The address of the segment be assigned as 0000H to F000H respectively. The offset address values
are from 0000H to FFFFH. So that the physical address ranges from 0000H to FFFFFH. The
segment register contains the higher order 16 bit of the starting address for four memory segments.
As shown in fig the base address is nothing but the staring address for each segment. For example
the starting address of data segment is 20000H. For code segment base address is 30000H.. for
stack segment 50000H respectively. In other words, a 64kbyte segment can be located anywhere
within the 1Mbytes address space. But the segments will always start at an address with zeros in
the lowest 4 bits.

The 16 bits offset or the displacement is added to the 16 bits segment base register after shifting
the contents of it towards left one digit to get the 20bit physical address.

Advantages of Segmentation:

1. With the use of segmentation the instructions and data is never overlapped.
2. The major advantage of segmentation is dynamic relocability of program which means that
a program can easily be transferred from one code memory segment to another code
memory segment without changing the effective address
3. Segmentation can be used in multi user time shared system.
4. Segmentation allows two processes to share data.
5. Segmentation allows you to extend the addressability of a processor.
6. Program and data can be stored separately from each other in segmentation.
7. Segmentation makes it possible to write program which are position independent or
dynamically relocatable.

Questions:

1. State the maximum size of memory that can be interfaced (summer 14) with
microprocessor 8086. Why?( summer 14)
2. Describe memory segmentation in 8086 microprocessor and list it’s four advantages.
(Summer 15)

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2.1.7 Physical Memory Address Generation:

The segment register are used to hold 16 bit of the staring address of four memory segment. Even
memory location has 20 bit physical address in microprocessor 8086. The physical address is the
combination of base address and effective address. The 20 bits starting physical address of memory
segment is called as base address which is always present in segment register. The address
associated with any instruction or data type is only 16 bit called as effective address or
displacement or logical address. To obtain the 20 bit physical address the base address is added
with effective address to obtain the 20 bit physical address. However the address outputted by BIU
is 20 bit called as physical address. Fig. shows how 8086 calculates physical address from the
effective address.

Effective Segment 0000

address address

ADDER

20 bit Physical Address

Fig.8 Physical address generation

For example CS = 348A and IP = 4214

16 bit offset in IP is added to the 16 bit segment base address in CS to produce the 20 bit physical
address.

Two 16 bit no are not directly added in the line because the CS register contains the only 16 bits
of the base address of the code segment. The BIU automatically inserts zeros for the lowest 4 bit
of the segment base address. If the CS register for example contains 348A i.e. the starting address
or base address of CS register is 348A0.

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When BIU adds the offset of IP 4214H in the IP to this segment base address, the result is 20 bit
physical address.

STEP 1: the CS register contains the upper 16 bits of the starting address of the code segment.

CS register contains:

3 4 8 A

STEP2: the BIU automatically insert zeros for the lowest four bits of the segment base address to
get the 20 bits of the segment base address to get 20 bit physical address for the starting of code
segment.

So, starting address of CS is :

3 4 8 A 0

BIU adds this zero

STEP 3: the IP register contains the offset. The offset here is 4214H

i.e. IP register contains:

4 2 1 4

STEP 4 : add the starting address of code segment CS from this address (offset) to get the
physical address of the location contain the next code byte as follows,

Starting address of CS 3 4 8 A 0

Offset in IP register 4 2 1 4

Physical address of 3 8 A B 4
the location
containing next code
byte

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Examples On Physical address generation:

Example No.1.

CS = 3490 H OFFSET (IP) = 1200 H

Base address – 34900

Effective address - 1200

Physical address - 35B00

Example No. 2.

CS = 4567 H OFFSET (IP) = 5690 H

Base address – 45670

Effective address - 5690

Physical address - 4AD00

Example No. 3.

CS = C239 H OFFSET (IP) = 8ABC H

Base address – C2390

Effective address - 8ABC

Physical address - CAE4C

Example No. 4.

CS:IP = 4370 H : 561E H

Base address – 43700

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Effective address - 561E

Physical address - 48D1

Example No. 5.

ES = 7A32 H DI = 0038 H

Base address – 7A320

Effective address - 0038

Physical address - 7A358

Questions:

1. State the concept of pipeling of 8086.(summer 14)

2. Calculate the physical address in the following cases:
i) CS: 1200 H, IP: DEOOH
ii) DS: 1FOO, BX: 1AOO for MOV AX, [BX] (summer 14)
3. Define pipelining. What is the size of instruction prefetch queue in 8086 microprocessor
? (winter 14)
4. Describe the physical memory address generation process in 8086 microprocessor. If, CS
= 69FAH & IP = 834CH, calculate the physical address generated. (winter 14)
5. Describe how 20 bit physical address is generated in 8086 microprocessor. Give one
example.(summer 15)
6. Explain pipelining in 8086 microprocessor. How is queuing useful in speeding up the
operation of 8086 microprocessor (summer 15)

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2.2 Operating modes of 8086 microprocessor:

The microprocessor 8086 can be operated in two modes i.e. minimum & maximum mode. In
minimum mode all control signals are generated by the microprocessor 8086 itself. So, it can be
used in single microprocessor based system. In maximum mode, all control signals are generated
by bus controllers 8288 not by the microprocessor 8086. So it can be used in multiprocessor
system. When microprocessor based system contains external math co-processor like 8087.

2.2.1 8284A Clock Generator

The 8284A is an ancillary component to the 8086/8088 microprocessor. Without the clock
generator, many additional circuits to generate the clock (CLK in an 8086/8088 based system. The
clock Generator 8284A provides the following basic functions or signals: clock generation,
RESEST synchronization, READY synchronization, and a TTL level peripheral clock signal

Fig.9 pin diagram of 8284.

Pin Functions: The 8284A is an 18-pin integrated circuit designed specifically for use with the
8086/8088 microprocessors as shown in fig1. The following is a list of each pin and its function.

AEN1 and AEN2: The address enable pins are provided to qualify the ready signals. RDY1 and
RDY2, respectively. Which are used to cause wait states, along with the RDY1 and RDY2
inputs. Wait states are generated by the READY pin of the 8086/8088 microprocessor. This is
controlled by these two inputs.

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RDY1 and RDY2: The bus ready inputs are provided in conjunction with the AEN1and AEN2
pins to cause wait states in an 8086/8088 microprocessor based system.

ASYNC: The ready synchronization selection input selects either one or two stages of
synchronization for the RDY1 and RDY2 inputs.

READY: Ready is an output pin that connects to the 8086/8088 microprocessor READY input.
This signal is synchronized with the RDY1 and RDY2 inputs.

X1 and X2: The Crystal Oscillator pins connect to an external crystal used as the timing source
for the clock generator and all its functions.

F/C: The Frequency/Crystal select input results the clocking source for the 8284A. If this pin is
held high, an external clock is provided to the EFI input pin, and if it is held low, the internal
crystal oscillator provides the timing signal.

EFI: The External Frequency input is used when the F/C is pulled high. EFI supplies the timing
whenever the F/C pin is high.
.
CLK: The clock output pin provides CLK input signal to the 8086/8088 microprocessors and
other components in the system. The CLK pin has an output signal that is one-third of the crystal
or EFI input frequency and has a 33 percent duty cycle, which is required by the 8086/8088
microprocessors.

PCLK: The Peripheral Clock signal is one-sixth the crystal or EFI input frequency and has a 50
percent duty cycle. The PCLK output provides a clock signal to the peripheral equipment in the
system.

OSC: The Oscillator output is a TTL level signal that is at the same frequency as the crystal or
EFI input. (The OSC output provides and EFI input to other 8284A clock generators in some
multiple processor systems).

RES: The reset input is an active-low input to the 8284A. The RES pin is often connected an RC
network that provides power-on resetting.

RESET: The Reset output is connected to the 8086/8088 microprocessors RESET input pin.

CSYNC: The clock synchronization pin is used whenever the EFI input provides
synchronization in systems with multiple processors. When the internal crystal oscillator is used,
this pin must be grounded.

GND: The ground pin is connects to ground.

Vcc: This power supply pin connects to + 5.0V with a tolerance of ± 10 percent.

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2.2.2 8284 clock generator:

The 8284 clock generator performs three different functions as given below:

1] Generating system clock for the 8086.

2] Generating READY signal for the 8086.

3] Generating RESET signal for 8086.

F/C CSYNC

X1 CLOCK
Clock Logic
X2 OSC

EF1 PCLK

RDY1
Ready logic
AEN1 READY

RDY2

AEN2
Reset Logic
RES RESET

Fig.10 . Logical block diagram of 8284 clock generator

A] clock logic:

The clock logic generates 3 different output signals i.e. CLK, OSC AND PCLK. The F/C decides
whether crystal or EFI the clk output signal.

The PCLK is a TTL clock signal whose frequency is half of the CLK signal frequency and not
synchronization signal which synchronizes multiple 82845 in the system.

B] Ready Logic:

This logic generates READY signal for the microprocessor 8086. There are 2 pairs of input signals which
can make READY low.

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• RDY 1 and AEN 1

• RDY2 and AEN 2
C] RESET Logic:

This logic generates RESET signal for the 8086 microprocessor.

The reset logic generates high active RESET signal for microprocessor 8086 when the RES input pin is
low.

X1 +5V
VCC
CRYSTAL +5V
8284
VCC
X2
+5V
VCC F/C
CLK CLK

RESET RESET
OSC
READY READY
External
R
RC
integrator RES 8086
for power
on reset AEN1

RDY1
C PCLK
AEN2 Clock to the peripheral
EF1
RDY2

Fig 11 Interfacing of 8284 with 8086 microprocessor.

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2.2.3 Bus controller 8288:

8288 is bus controller IC used to generate different control signals which are necessary for interfacing
memory and I/O devices in maximum mode of 8086.

• Generate ALE signal to control address latch 74LS373 or 8282.

• Generate DT/R and DEN signals to control data bus Trans receiver 74LS245.
• Generate read / write signal.
8288 bus controller consists of two sections:

a. Bus command logic

b. Control signal logic

MRDC
SO MWTC
BUS
S1 AMWC
CONTROL
S2 IORC
LOGIC
AIOWC

INTA

CONTROL
AEN DT/R
SIGNAL
CEN DEN
LOGIC
CLK ALE

IOB MCN/PDEN

Fig 12 block diagram of bus controller 8288

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A] Bus control logic:

Bus control logic accepts signals on S0, S1, S2 and decode these status signals to generate different
control signals. The signals generated by 8288 for different combination of bus status signals are shown
in table.

Bus Status 8086 State Command signals name

S0 S1 S2
0 0 0 Interrupt acknowledge
INTA
0 0 1 Read I/O port
IORD
0 1 0 Write I/O port
IOWC & AIOWC
0 1 1 Halt
None
1 0 0 Instruction fetch
MRDC
1 0 1 Read Memory
MRDC
1 1 0 Write Memory
MWTC & AMWC
1 1 1 Passive
None

B] Control Signal Logic:

Control signal logic generates signal for controlling the hardware connected to 8086 address and data bus.
The DT/R signal is used to set the direction of data through the data bus transceiver.

DEN signal indicates when data bus has to be active. When DEN is high, the data bus transceiver is
enabled and when DEN is low it is disabled.

ALE is used to demultiplexed address latch. The MCE/ PDEN is a dual function and called master
cascade enable IORD is low.

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2.2.4 74LS245 bidirectional Buffer/ Transreciever:

Bidirectional bus is used to increase the driving capability of the data bus and also called as octal
bus transreciever. It is used to separate data bus from address / data multiplex lines. 8086
microprocessor has 16 data lines and this is octal bus transceiver so to separate 16 dat lines we
require two octal transreciever.

2.2.5 74LS373 Octal Latch:

This octal latch is used to separate the address lines from address/ data multiplex lines. 8086
microprocessor has 20 address lines so to separate 20 address lines we require more than 2 octal
latches.

Questions:

State all the control signals generated by S0, S1, S2 with their functions. (winter 14)

Draw the interfacing of 8284 clock generator with 8086 microprocessor. List and explain
interfacing signals. (Winter 14)

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2.2.6 MINIMUM MODE 8086 SYSTEM AND TIMINGS:

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX pin to logic1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system. The
remaining components in the system are latches, transreciever, clock generator, memory and I/O
devices. Some type of chip selection logic may be required for selecting memory or I/O devices,
depending upon the address map of the system.

The latches are generally buffered output D-type flip-flops, like, 74LS373 or 8282. They are used
for separating the valid address from the multiplexed address/data signals and are controlled by
the ALE signal generated by 8086. Trans receivers are the bidirectional buffers and sometimes
they are called as data amplifiers. They are required to separate the valid data from the time
multiplexed address/data signal. They are controlled by two signals, namely, DEN and DT/R. The
DEN signal indicates that the valid data is available on the data bus, while DT/R indicates the
direction of data, i.e. from or to the processor. The system contains memory for the monitor and
users program storage. Usually, EPROMS are used for monitor storage, while RAMs for users
program storage. A system may contain I/O devices for communication with the processor as well
as some special purpose I/O devices. The clock generator generates the clock from the crystal
oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate
timing reference for the system. The clock generator also synchronizes some external signals with
the system clock. The general system organization is shown in Fig. Since it has 20 address lines
and 16 data lines, the 8086 CPU requires three octal address latches and two octal data buffers for
the complete address and data separation.

The working of the minimum mode configuration system can be better described in terms of the
timing diagrams rather than qualitatively describing the operations. The opcode fetch and read
cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing
diagram for read cycle and the second is the timing diagram for write cycle.

The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal and also
M/IO signal. During the negative going edge of this signal, the valid address is latched on the local
bus. The BHE and A0 signals address low, high or both bytes. From Tl to T4, the M/IO signal
indicates a memory or I/O operation. At T2 the address is removed from the local bus and
is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2
.The read (RD) signal causes the addressed device to enable its data bus drivers. After RD goes
low, the valid data is available on the data bus. The addressed 26 device will drive the READY
line high, when the processor returns the read signal to high level, the addressed device will again
tristate its bus drivers.

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Fig. 13 Minimum Mode of 8086.

A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO
signal is again asserted to indicate a memory or I/O operation. In T2 after sending the address in
Tl the processor sends the data to be written to the addressed location. The data remains on the bus
until middle of T4 state. The WR becomes active at the beginning ofT2 (unlike RD is somewhat
delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper
byte or bytes of memory or I/O word to be read or written. The M/IO, RD and WR signals indicate
the types of data transfer as specified in Table

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Fig.14 Read Cycle Timing Diagram for Minimum Mode

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Fig.15 Write Cycle Timing Diagram for Minimum Mode

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2.2.7 MAXIMUM MODE 8086 SYSTEM AND TIMINGS:

In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In this
mode, the processor derives the status signals S2, S1 and S0. Another chip called bus controller
derives the control signals using this status information. In the maximum mode, there may be more
than one microprocessor in the system configuration. The other components in the system are the
same as in the minimum mode system. The general system organization is as shown in the fig1.1
The basic functions of the bus controller chip IC8288, is to derive control signals like RD and WR
(for memory and I/O devices), DEN, DT/R, ALE, etc. using the information made available by the
processor on the status lines. The bus controller chip has input lines S2, S1 and S0 and CLK. These
inputs to 8288 are driven by the CPU. It derives the outputs ALE, DEN, DT/R, MWTC, AMWC,
IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are especially useful for multiprocessor
systems. AEN and IOB are generally grounded. CEN pin is usually tied to +5V.

Fig.16 Maximum mode of 8086.

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The significance of the MCE/PDEN output depends upon the status of the IOB pin. If IOB is
grounded, it acts as master cascade enable to control cascaded 8259A; else it acts as peripheral
data enable used in the multiple bus configurations. INTA pin is used to issue two interrupt
acknowledge pulses to the interrupt controller or to an interrupting device. IORC, IOWC are I/O
read command and I/O write command signals respectively. These signals enable an IO interface
to read or write the data from or to the addressed port. The MRDC, MWTC are memory read
command and memory write command signals respectively and may be used as memory read and
write signals. All these command signals instruct the memory to accept or send data from or to the
bus. For both of these write command signals, the advanced signals namely AIOWC and AMWTC
are available. They also serve the same purpose, but are activated one clock cycle earlier than the
IOWC and MWTC signals, respectively. The maximum mode system is shown in fig. The
maximum mode system timing diagrams are also divided in two portions as read (input) and write
(output) timing diagrams. The address/data and address/status timings are similar to the minimum
mode. ALE is asserted in T1, just like minimum mode. The only difference lies in the status signals
used and the available control and advanced command signals. The fig. shows the maximum mode
timings for the read operation while the fig. shows the same for the write operation.

Fig.17 Memory Read Timing in Maximum Mode

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Fig.18 Memory Write Timing in Maximum Mode

2.2.8 Difference between minimum mode and maximum mode:

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Minimum Mode Maximum Mode

MN/MX pin is connected to VCC. MN/MX pin is connected to ground

Single Microprocessor in Minimum mode Multiprocessor configuration in Max.mode

system

Bus controller 8288 is not required Bus controller 8288 is required

Control signals M/IO, RD, WR are directly Control signal are generated using S0, S1 and
available. S2.

Control signals IOR, LOW, MEMW, and Control signals are generated using 8288 bus
MEMR are present. controller.

HOLD &HLDA signals are available for RQ/GT0, RQ/GT1 are available for
interfacing interfacing.

Status of instruction queue is not available. Status of instruction queue QS0 and QS1 are
available.

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2.2.9 Difference between 8085 and 8086 microprocessor:

8085 microprocessor 8086 microprocessor

It is 8 bit microprocessor. It is 16 bit microprocessor.

Address bus is 16 bit. Address bus is 20 bit.

Data bus is 8 bit. Data bus is 16 bit.

General purpose registers are of 8 bit General purpose registers are of 16 bit size.
size.

It has five hardware interrupt i.e. Only two hardware interrupt i.e. NMI and
TRAP,RST7.5,RST6.5,RST5.5 and INTR.
INTR.
Operates only in single mode Operate in two modes
1. Minimum Mode
2. Maximum mode
Instruction queue is not present Instruction queue is present.

5 addressing modes 24 addressing modes

It do not support memory segmentation. It supports memory segmentation.

Pipelining facility is absent. Pipelining facility is present.

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Questions:

1. Compare maximum mode and minimum mode configurations of 8086 (any four points)
(summer 14)

2. With the neat diagram, describe the maximum mode operation of 8086. List & describe
functions of signals of maximum mode of 8086.(winter 14)
3. Compare microprocessors 8085 and 8086 (any four points) (summer 14)
4. Draw and describe the maximum mode diagram of 8086.(sumer 14)
5. Compare 8085 microprocessor & 8086 microprocessor. (with respect to)

(i) No. of data lines

(ii) No. of address lines
(iii) Frequency of operation
(iv) Registers (winter 14)

6. Explain the minimum mode configuration of 8086microprocessor. Write comparison

between 8086 in minimum mode and maximum mode. (Summer 15).

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