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Exercise List-Vlsi - For - Beginners

This document provides contact information for the National Institute of Electronics and Information Technology lab in Calicut and outlines 7 exercises for designing basic logic gates and arithmetic circuits using Verilog HDL. Students are asked to design OR, AND, NOT, NAND, XOR, and NOR gates as well as half adders, full adders, half subtractors, full subtractors, 4:1 multiplexers, and a 4-bit up counter. They are to simulate and capture waveforms for each circuit using dataflow, behavioral, and structural modeling in Verilog. Mr. Sreejeesh SG is listed as the contact point for the lab and can be reached by email or WhatsApp.

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53 views

Exercise List-Vlsi - For - Beginners

This document provides contact information for the National Institute of Electronics and Information Technology lab in Calicut and outlines 7 exercises for designing basic logic gates and arithmetic circuits using Verilog HDL. Students are asked to design OR, AND, NOT, NAND, XOR, and NOR gates as well as half adders, full adders, half subtractors, full subtractors, 4:1 multiplexers, and a 4-bit up counter. They are to simulate and capture waveforms for each circuit using dataflow, behavioral, and structural modeling in Verilog. Mr. Sreejeesh SG is listed as the contact point for the lab and can be reached by email or WhatsApp.

Uploaded by

Radhika
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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NATIONAL INSTITUTE OF ELECTRONICS AND INFORMATION

TECHNOLOGY, CALICUT

VLSI for Beginners

Verilog HDL Exercises

Contact Point for the Lab

Mr. Sreejeesh SG

Senior Technical Officer

Email: sreejeesh@nielit.gov.in

Ph.: 9447769756 (WhatsApp Preferred)

Prepared by Sreejeesh SG Lab Manual-Verilog/FPGA

i
1. Design & test the following basic Logic Gates using Verilog HDL and capture the waveforms: a)OR,
B)AND, c)NOT, d)NAND, e)XOR, f)NOR

2. Design a Half Adder using Verilog HDL, Simulate and capture the waveforms in a)Dataflow
modelling, b)Behavioral modelling and c)Structural modelling

3. Design a Full Adder using Verilog HDL, Simulate and capture the waveforms in a)Dataflow
modelling, b)Behavioral modelling and c)Structural modelling

4. Design a Half Subtractor using Verilog HDL, Simulate and capture the waveforms in a)Dataflow
modelling, b)Behavioral modelling and c)Structural modelling

5. Design a Full Subtractor using Verilog HDL, Simulate and capture the waveforms in a)Dataflow
modelling, b)Behavioral modelling and c)Structural modelling

6. Design and simulate 4:1 Multiplexer using Verilog HDL and capture the waveforms

7. Design and test a 4-Bit Up Counter (Synchronous) , write it’s test bench and capture the waveforms
in Behavioral modelling

Lab Manual-Verilog/ FPGA

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