Nokia

DXT Plug-in Unit Descriptions

ET16
DN0592435
Issue 1-7
 ET16

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2 © 2016 Nokia DN0592435 Issue: 1-7

ET16

Table of Contents
This document has 32 pages

Summary of changes .................................................................... 6

1 ET16 overview............................................................................... 7

2 Capacity and performance of ET16............................................... 8

3 Structure of ET16........................................................................... 9
3.1 Mechanical structure of ET16 plug-in unit......................................9
3.2 Logical structure of ET16 plug-in unit.............................................9
3.3 Operating principles......................................................................11
3.3.1 Microprocessor (CPU) and memories.......................................... 11
3.3.2 Bus architecture........................................................................... 15
3.3.3 Programmable logic..................................................................... 16
3.3.4 Clocking scheme..........................................................................17
3.3.5 Reset structure.............................................................................18
3.3.6 Interrupt structure.........................................................................18
3.4 Interfaces..................................................................................... 19
3.4.1 Framer..........................................................................................19
3.4.2 Line interface................................................................................20
3.4.3 Backplane interface......................................................................20

4 Operation of ET16........................................................................21

5 Power consumption of ET16........................................................ 23

6 ET16 C109519............................................................................. 24
6.1 Emerson ET16 (versions 1-4)...................................................... 24
6.2 Emerson ET16 (version 5 onwards).............................................25
6.3 Interphase ET16...........................................................................26
6.4 Interchangeability settings............................................................27

7 Connector maps of ET16............................................................. 28

7.1 Backplane connectors..................................................................28

DN0592435 Issue: 1-7 © 2016 Nokia 3

 ET16

List of Figures
Figure 1 The operating environment of the ET16............................................... 7
Figure 2 Block diagram of the ET16 (Emerson)............................................... 10
Figure 3 Block diagram of the ET16 (Interphase)............................................. 11
Figure 4 Interfaces of the ET16........................................................................ 19
Figure 5 Front panel of the ET16......................................................................21
Figure 6 Jumpers and micro switches of the Emerson ET16 (version 1)......... 24
Figure 7 Jumpers and micro switches of the Emerson ET16 (version 5
onwards).............................................................................................25
Figure 8 Jumpers and micro switches of the Interphase ET16.........................26

4 © 2016 Nokia DN0592435 Issue: 1-7

ET16

List of Tables
Table 1 MPC850 Hardware cofiguration......................................................... 12
Table 2 The basic parameters for the Boot Flash........................................... 16
Table 3 Interchangeability code (ICC) settings (B2 / W2 / W1)....................... 27
Table 4 Connector P5 pin order...................................................................... 28
Table 5 Connector P4 pin order...................................................................... 29
Table 6 Connector P2 pin order...................................................................... 30
Table 7 Meanings of the backplane connector signals....................................31

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Summary of changes ET16

Summary of changes
Changes between document issues are cumulative. Therefore, the latest document
issue contains all changes made to previous issues.
Changes made between issues 1-7 and 1-6
Information on W2 in Figure 7 Jumpers and micro switches of the Emerson ET16 has
been corrected. W2 has been added to the caption of Table 3 Interchangeability code
(ICC) settings (B2 / W1).
Changes made between issues 1-6 and 1-5
Layout figure of ET16 Emerson version 2 added.
Changes made between issues 1-5 and 1-4
Information returned to section Structure of ET16. Topic Synchronization (TCL and
RSYNC) signal updated.
Changes made between issues 1-4 and 1-3
Information on the Interphase ET16 variant added to sections Structure of ET16, Power
consumption of ET16 and ET16 C109519. Redundant information removed from
sections Structure of ET16 andCapacity and performance of ET16.
The name of the Force ET16 changed to Emerson ET16.
Changes made between issues 1-3 and 1-2
Information for Interchangeability switch changed.
Changes made between issues 1-2 and 1-1
Setting instructions for Line Interface Mode added.
Changes between issues 1-0 and 1-1
Setting instructions for Line Interface Mode removed.
Figure 2 corrected.
Table 7 corrected.
Editorial corrections.
Issue 1-0
This is the first issue of ET16.

6 © 2016 Nokia DN0592435 Issue: 1-7

ET16 ET16 overview

1 ET16 overview
This document describes the ET16 exchange termination plug-in unit.
Purpose of the plug-in unit
The ET16 is an exchange terminal unit. It has sixteen external E1/T1 interfaces, interface
to switching network and to the HDLC/LAPD channel, on-board power supply, and clock
system for generating the 8 kHz synchronising signal to the synchronisation unit. The
ET16 can be installed in the GT4C-A, GT6C-A and TC2C-A cartridges.
The ET16 plug-in unit complies with the E1 and T1 standards and connects sixteen
2.048 Mbit/s E1 lines or sixteen 1.544 Mbit/s T1 lines to a DX 200 based network
element.
The ET16 provides the following:

• sixteen E1/T1 interfaces

• four 8Mbit/s interfaces between the ET16 and the Group switch
(GSW1KB/GSW2KB)
• one synchronization output towards the exchange clock system
Operating environment of ET16 unit
The ET16 plug-in unit is connected to sixteen external 2.048 Mbit/s (E1) or sixteen
external 1.544 Mbit/s (T1) lines. The ET16 is connected to the switching network with
four duplicated 8 Mbit/s internal PCM circuits. T1 (1.544 Mbit/s) PCM circuits are first
converted to 2.048 Mbit/s and then multiplexed, four PCM circuits to one cable. E1
(2.048 Mbit/s) PCM circuits are multiplexed without conversion, four PCM circuits to one
cable. The ET16 is connected to the controlling computer with either one LAPD link
which is connected to time-slot 0 of the PCM circuit 0, or with 4 LAPD links which are
connected to time-slots 0 of the PCM circuits 0, 4, 8 and 12.
Operating voltages required by the units are formed with an on board integrated power
unit from an external -48 V voltage.
The following figures display the operating environment of the ET16 plug-in unit.

Figure 1 The operating environment of the ET16

GSW1KB/
16xE1/T1 4x8M 4x8M 16xE1/T1
GSW2KB
PSTN ET16 ET16 BSS/BSC
LAPD LAPD

ET16 ET16

ET- ET-
Signalling controlling Signalling controlling
computer computer computer computer

DN0596291

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Capacity and performance of ET16 ET16

2 Capacity and performance of ET16

The capacity of the ET16 is sixteen E1/T1 lines.
The ET16 has

• Sixteen E1/T1 ports in the backplane

• MPC85x PowerQUICC processor at 50MHz
• 8MByte SDRAM main memory at 50MHz
• 1MByte Boot Flash
• Serial I2C EEPROM for Board Information Block
• Backplane interface
– 8.192MBit/s serial interface
– 64kBit/s HDLC/LAPD interface

• Hardware support for installing the echo cancelling daughter board in the future
• Seventeen LED indicators on the front panel
• FPGA for timing adaptation, clock supervision and glue logic.

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ET16 Structure of ET16

3 Structure of ET16

3.1 Mechanical structure of ET16 plug-in unit

ET16 plug-in unit
The ET16 plug-in unit consists of a single printed wiring board (PWB), the size of which
is 233 mm x 220 mm. Line interface connectors are located in the backplane. There are
seventeen red LED indicators on the front panel, one clock alarm LED and 16 link alarm
LEDs.
The ET16 plug-in unit is connected to the backplane of the cartridge with four Z-pack
HM-type connectors.

3.2 Logical structure of ET16 plug-in unit

The following block diagram of the ET16 plug-in unit illustrates the logical structure.

DN0592435 Issue: 1-7 © 2016 Nokia 9

Structure of ET16 ET16

Figure 2 Block diagram of the ET16 (Emerson)

Framer+
LIU
0

Framer+
LIU
1

Framer+
SDRAM LIU
2

Framer+
Boot
LIU
Flash
3

DN0596307 LocalBus

MPC850

CPMinHDLCMode

Backplane
Connectors
FPGA
including
alarm
register

10 © 2016 Nokia DN0592435 Issue: 1-7

ET16 Structure of ET16

Figure 3 Block diagram of the ET16 (Interphase)

8Mb/s TDM

Octal
Framer
2Mb/s
Freescale TDM TDMmux 8Mb/s
MPC853T
FPGA TDM
Processor
Octal
Framer

Peripheral
databus

FLASH SDRAM Backplane

256Kx16 4Mx16 Connectors

3.3Vto1.8V -48Vto3.3V3A
DC/DC isolatedDC/DC

DN70481516

3.3 Operating principles

3.3.1 Microprocessor (CPU) and memories
Depending on the vendor, the ET16 includes one Motorola PowerQUICC device
MPC850 or MPC853. The device is a versatile, single-chip intergrated microprocessor
and CPM that is ideally suited for controller applications in network and communication
products. The MPC850/MPC853 provides the ET16 with the following:

• Embedded 32bit MPC8xx core with 2kByte data and 1kByte instruction cache and
memory management unit (MMU)
• External 32bit data bus
• External 26bit address bus (256MByte addressable)
• System integration unit (SIU) with software watchdog, clock synthesizer,
decrementer and reset controller

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Structure of ET16 ET16

• Memory controller for eight banks, glueless interface for SDRAM, SRAM and Flash
devices
• Four 16-bit general-purpose timers
• Interrupt controller with up to 20 external and 15 internal interrupts
• Communication processor module (CPM) with 32bit scalar RISC communication
processor and 8kByte of dual-port RAM
• Serial Communication controller (SCC) that is configured for HDLC mode
• Serial management controller (SMC) that is configured for UART mode
• I²C bus interface
• Time slot assigner (TSA) which allows the SCC to operate in multiplexed TDM
operation mode
Hardware configuration
To ensure proper operation, some the MPC850 features must be configured during
power-on reset and during the hardware reset.
While _PORESET (power-on reset) is asserted, the reset configuration of the SPLL is
sampled on the MODCK[1-2] pins. The SPLL immediately begins to use the
multiplication factor value and external clock source for the SPLL determined by the
sampled MODCK[1-2] pin and attempts to achieve lock.
When a hardware reset event occurs and when the signal _RSTCONF is pulled low at
the same time, the MPC850 determines its initial mode of operation by sampling the
values present on the data bus D[0-31]. The signals D[0-31] are pulled down internally,
therefore only configuration pins that need a logic HIGH must be driven externally. The
table below shows the necessary hardware configuration of the MPC850 during reset.

Table 1 MPC850 Hardware cofiguration.

MPC 850 pin Value Description

MODCK[1-2] 10 Core frequency is 50MHz oscillator input

EXTCLK

D0 0 Internal arbitration for bus interface

D1 1 Interrupt exceptions are vectored to physical

address 0x000n.nnnn

D3 0 Memory controller is acivated after reset so that

it matches all addresses and starts booting from
_CS0

D[4-5] 01 Boot Flash size is 8bit

D[7-8] 00 Internal memory region is 0xFFF0.0000

D[9-10] 11 Debug pin configuration

D[11-12] 11 Debug port pin configuration

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ET16 Structure of ET16

Table 1 MPC850 Hardware cofiguration. (Cont.)

MPC 850 pin Value Description

D[13-14] 00 External bus is running at core frequency

(50MHz)

Memory controller
The MPC850 processor contains a memory controller for up to eight memory banks that
are shared between a general-purpose chip-select machine (GPCM) and a pair of
sophisticated user-programmable machines (UPMA and UPMB).
The GPCM provides interfacing for simpler and lower-performance memory resources
and memory-mapped devices. The GPCM does not support bursting. The GPCM
provides a _CS signal for each memory region, _WE signals for write cycles for each
byte written to memory, and _OE signal for read cycles. Timing for these signals can be
configured very flexibly via the memory controller register set.
The UPM provides both more features and, because it supports bursting, higher
performance. Therefore it is typically used to interface with higher-performance memory
such as SDRAM. The UPM supports address multiplexing of the external bus, periodic
timers, and generation of programmable control signals for row address and column
address strobes to allow for a glueless interface to DRAM devices. The periodic timers
allow refresh cycles to be initiated while the address multiplexing provides row and
column addresses. The UPM is a microsequencer that requires microinstructions or
RAM words to generate signal timings for different memory cycles. The contents of the
internal-memory RAM array specifies the logical value driven on the external memory
controller pins for a given clock cycle. Timing resolution for the signals is one quarter of
the external bus clock CLKOUT, that is used as SDRAM clock. The UPM provides a _CS
signal for memory bank activation, four dedicated byte select signals _BST[0:3] and six
general-purpose signals _GPL[1:5] and _GPL0.
Serial management controller
The two serial management controllers (SMC) of MPC850 are fullduplex ports that can
be configured independently to support one of three protocols:

• UART mode (in use on the ET16)

• Transparent mode
• General circuit interface

The following main features are supported by the SMC in UART mode:

• Flexible message-oriented data structure

• Programmable data length (514 bits)
• Programmable 1 or 2 stop bits
• Even/odd/no parity generation and checking
• Frame error, break, and IDLE detection
• Transmit preamble and break sequences
• Received break character length indication
• Continuous receive and transmit modes
• Clocking by internal baud rate generator or clock pin.
Serial communication controller

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Structure of ET16 ET16

The MPC850 used on the ET16 has one serial communication controller (SCC2), which
can be configured to implement different protocols for bridging functions, routers, and
gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary
networks. The SCC has many physical interface options such as interfacing to a TDM
bus, an ISDN bus, or a standard modem interface.
The choice of protocol is independent from the choice of interface. When the SCC is
programmed to a certain protocol or mode, it implements functionality that corresponds
to parts of the protocols' link layer. The following protocols / modes are supported by the
SCC:

• UART mode
• HDLC mode (in use on the ET16)
• Transparent mode
• Ethernet mode

On the ET16, a 64kbit/s HDLC/LAPD link is provided via the backplane. The link is used
for software downloading, for supervision and control of the ET16 board. The link resides
in timeslot 0 of the PCM circuit 0.
The serial communication controller SCC2 is responsible for handling the HDLC/LAPD
link. SCC2 must be configured for the HDLC mode.
Time Slot Assigner
The selected TDM line is connected to the serial interface (SI) of the MPC850 which is
configured in the TDM mode. The following TDM pins are provided by the MPC850 TSA:

• L1RXDA Connected to receive data of the TDM line

• L1TXDA Connected to transmit data of the TDM line

In addition, some pins are needed for clocking and synchronisation of the TSA. The
signals are “generated” within programmable logic:

• L1RSYNCA, L1RCLKA Receive synchronisation (frame pulse) and clock

• L1TSYNCA, L1TCLKA Transmit synchronisation (frame pulse) and clock

The TSA simply routes pre-programmed portions of the received data frame from the
TDM pins to the target SCC2, while the target SCC2 processes the received data
according to the configured protocol. The routing information for the TDM line is
contained in the 512Byte SI RAM inside the MPC850. The SI RAM has 128 32bit entries
- 64 entries each for transmit and receive routing, when TSA is configured for static
mode. For the ET16 application only, one timeslot (8Bit) out of 128 timeslots is routed to
the target SCC2. Therefore, the ten SI-RAM entries are sufficient when they are
programmed as in the example below (where TS5 is selected):

• RAM entry 1 covers TS0...TS4 - 5Bytes

• RAM entry 2 covers TS5 - 1Byte
• RAM entry 3 covers TS6...TS15 - 10Bytes
• RAM entry 4 covers TS16...TS31 - 16Bytes
• ....
• RAM entry 10 covers TS112...TS127 - 16Bytes
I²C interface and board information block

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The MPC850 processor includes a I²C controller for access to serial devices like
EEPROMs. The main features of the I2C controller are:

• Independent programmable baud rate generator

• Two signal interface via SDA and SCL
• Master and slave operation
• Support of 7bit addressing

Connected to the I²C interface of the MPC850 is one 24C04 EEPROM device (4kBit) that
is used to store the following information:

• Variant information
• Version information
• Unit identification information
General-purpose I/O functions
The MPC850 provides 49 general-purpose I/O pins (GPIO). On the ET16, the GPIO pins
are used for the following main functions:

• TSA pins
• UART interface
• I2C bus interface
• FPGA configuration
• Reset generation
• Alarm LED activation.
• Connection to FPGA and backplane signals

3.3.2 Bus architecture

The MPC850 external bus is a synchronous, burstable bus that can support multiple
master and slave devices. Accesses to 32, 16 and 8-bit slaves are controlled by the
memory controller. On the ET16, only slave devices are connected to the bus interface.
Note that the bit numbering of the MPC850 follow the PowerPC architecture definition,
which means that bit0 is the most significant bit and is the least significant bit.
The bus interface features are:

• 26bit address / 32bit data bus

• Access to 32, 16 and 8bit devices
• Glueless interface to slave devices
• Synchronous architecture
Memory controller machine configuration
Two different memory controller machines are used to access the different devices that
are attached to the external bus. The GPCM is used to access the BootFlash and the
PM4354 Framers. The control signal timing must be configured by different GPCM
registers. The UPMA is used to access the SDRAM while UPMB is used to access the
UART.
Boot flash memory
At least 1MByte of Boot flash memory is supported on the ET16. The basic parameters
for the Boot Flash are given below.

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Structure of ET16 ET16

Table 2 The basic parameters for the Boot Flash

Used Device AMD AM29LV081B

Organisation 1M x 8bit

Power Supply 3.3V

Used Memory Machine GPCM

Used Chip Select CS0#

All provisions are made (interface signals, memory size information, layout and software)
to support 2 Mbyte of Boot Flash memory.
The control signals _CS0, _OE and _WE are driven by the general-purpose chip select
machine GPCM. The _CS0 signal is the boot chip select output and its operation differs
from the other external chip select outputs on the system reset. Boot chip select
operation allows address decoding for a boot device before system initialization occurs.
When the MPC850 internal core begins accessing memory after system reset, _CS0 is
asserted for the complete address range. The boot chip select provides a programmable
port size during system reset by using the BPS field of the hard reset configuration word.
SDRAM memory
16 MByte of SDRAM memory is available on the ET16.
The control signals for the SDRAM are generated by the UPMA. The _CS on the
SDRAM is connected to _CS1 on the MPC850. The DQM signals of the used SDRAM
device select byte lanes and are connected to the appropriate byte strobe _BS0:3
signals on the MPC850. SDRAM address A10 is connected to _GPL0 on the MPC850
because it is required that A10 acts as an address line and a control line. _RAS, _CAS
and _WE are generated by MPC850 signals _GPL2, _GPL3 and _GPL4 respectively.
The SDRAM clock is driven by the MPC850s CLKOUT signal. The used SDRAM has
2048 rows and 256 columns, and therefore 11-row address lines and 8-column address
lines must be used. The _BS1:0 lines are connected to MPC850 address lines A9:10
and are used as high order address bit.
Framer interface
The control signals _CS2, _OE and _WE for access to the registers of the PM4354
Framers are driven by the general-purpose chip select machine GPCM.

3.3.3 Programmable logic

Some special functions of the ET16 are implemented in the programmable logic. The
ET16 contains one Xilinx SpartanII XC2S15 FPGA. The FPGA is a SRAM-based Gate
Array that is In-System configurable in slave serial mode via MPC850 processor pins.
The FPGA image must be included in the Boot Flash device. The FPGA will loose its
configuration in case of powerdown.
The main functions implemented in the FPGA are:

• Timing adaption for interface to/from GSW1KB/GSW2KB

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ET16 Structure of ET16

• Clock supervision
• Clock distribution to PM4354 framers
• Frame sync adaption for PM4354 framers and MPC850
• TCL clock generation and RSYNC divider
• Multiplexer MX3-MX6 for TDM line routing
• Alarm generation
• Debouncing of changeover signal
• Timeslot reordering for T1
• Additional test functions

3.3.4 Clocking scheme

The ET16 has the following independent clock domains: processor core, SDRAM, serial
terminals, H-MVIP interface, synchronization (TCL) signal, clock supervision.
Processor core
The MPC850 processor is running at a core frequency of 50.0MHz. This clock is
provided to the EXTCLK pin of the processor by an Epson SG710-type oscillator. The
frequency stability of the oscillator is 50ppm. The oscillator needs 3.3V supply voltage.
SDRAM
CLKOUTs clock signal is used to clock the SDRAM interface.
H-MVIP interface
The system provides an 8kHz and 8.192MHz clock via the backplane interface. These
two clock signals are the timing reference for the 8.192MBit/s data TDM line. All further
clocks for PM4354 backplane interface and MPC850 TSA are derived from these two
clocks.
Synchronization (TCL and RSYNC) signal
Synchronization Signal (RSYNC) which is either

• 1.544MHz or
• 2.048MHz

The source of RSYNC is software-programmable, but in implementation fixed to port 0.

RSYNC is provided to the backplane pin RTCP and connected to the FPGA to generate
the 8kHz TCL signal that is also provided to the backplane connector.
The TCL backplane driver is always enabled. In case of LOS, the framer automatically
disables the RSYNC output and helds RSYNC high during the LOS condition.In case of
equipment loopback, AIS reception, frame alignment loss and CRC multiframe alignment
loss condition and an interrupt is issued to the MPC850 and the software has to disable
TCL generation (TCL is held high) inside the FPGA by setting the signal DisableTCL.
Clock supervision
The clock supervision (implemented in the FPGA) generates a clock alarm if one of the
following disruptions are observed in the 8 kHz or 8.192 MHz clock: too much / too few
pulses in frame, clock missing or clock stucked at “0” or “1”.

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Structure of ET16 ET16

3.3.5 Reset structure

Different sources and levels are defined for the reset structure:

1. The voltage monitor supervises the on-board power supply. During power-on, the
monitor asserts _PORESET signal. The typical reset pulse width is 200ms.
_PORESET is connected to the MPC850.
2. When _PORESET is asserted, the MPC850 samples the MODCK bits and
configures the internal PLL. The MPC850 enters the power-on reset state and stays
there until both of the following events occur: – Internal PLL enters lock state and
system clock is active – _PORESET is deasserted
3. With the negation of _PORESET or PLL lock, the MPC850 enters the state of
internal initiated _HRESET, and drives _HRESET for 512 clock cycles (10us). Once
the 512 cycles are elapsed, the MPC850s hardware configuration is sampled from
the data signals and the core stops internally asserting _HRESET. During _HRESET
the UART and the BootFlash are also reset.
4. With the negation of _HRESET the MPC850 starts reading basic firmware code from
the BootFlash memory. After basic register initialization, the FPGA are configured via
MPC850 GPIO pins.
5. _FPGA_RESET, _FRAMER_RESET and _DCARD_RESET are driven by the
MPC850 and therefore are automatically held active during the complete power-on,
_HRESET and FPGA configuration procedure. After the FPGA configuration is
finished the software has to release these reset signals.

3.3.6 Interrupt structure

An interrupt controller with up to 20 external and 15 internal interrupts is included in the
MPC850 processor. The following external signals are connected to the interrupt
controller:

• _INT1 PM4354#1 interrupt

• _INT2 PM4354#2 interrupt
• _INT3 PM4354#3 interrupt
• _INT4 PM4354#4 interrupt
• _INT6 FPGA general purpose interrupt (ALTST)
• _INT7 FPGA general purpose interrupt (clock supervision)

All interrupts are maskable by software. _INT1 has the highest priority and _INT4 has the
lowest priority.

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ET16 Structure of ET16

3.4 Interfaces
Figure 4 Interfaces of the ET16

8Mb/s TDM

Octal
Framer
2Mb/s
Freescale TDM TDMmux 8Mb/s
MPC853T
FPGA TDM
Processor
Octal
Framer

Peripheral
databus

FLASH SDRAM Backplane

256Kx16 4Mx16 Connectors

3.3Vto1.8V -48Vto3.3V3A
DC/DC isolatedDC/DC

DN70481516

3.4.1 Framer
The ET16 includes four PMC-Sierra PM4354 COMET-QUAD devices . One device
contains a four-channel combined E1/T1 frame with line interface unit in a single chip.
The following features of PM4354 are essential for the ET16:

• E1/T1 line interface unit

• Software selectable between E1 and T1 operation
• Encoding and decoding of the B8ZS, HDB3 and AMI line codes
• Receive equalization, clock recovery and line performance monitor
• Transmit and receiver jitter attenuation
• Selectable de-jittered E1 or T1 recovered line clock for system clock synchronisation
• Programmable pulse shape to adapt LIU to line length (E1: short haul, T1: long haul)
• Transparent forwarding of national SA bits

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Structure of ET16 ET16

• Through timing mode from backplane interface or loop mode

• E1 CRC-4 multiframe, doubleframe and unframed mode
• T1 SF, ESF and unframed mode
• 8.192Mbit/s H-MVIP backplane interface for all E1 and T1 links. Device operates in
H-MVIP clock slave mode with elastic store
• 8.192Mbit/s H-MVIP interface for channel associated signaling (CAS) extraction from
T1 ESF or SF including robbed bit signalling (RBS) support
• 8bit multiprocessor interface for configuration, control and status monitoring and
performance statistics
• Possibility to generate interrupt when line status changes
• Line, payload and diagnostic loopback modes

3.4.2 Line interface

At start-up, line interface mode (E1/T1) is selected with DIP switch. Connector panel
CPETC is needed for asymmetric 75Ω and connector panel CPETS for symmetric 120Ω
E1 interface and T1 interface.
After LAPD channel to controlling computer has been established, software settings
define interface and framing modes.
Symmectric (120Ω) E1 Interface
Symmetric E1 line interface consists of interface protection with magnetics, and line
interface with LIU and framer (integrated in the PM4354). For the symmetric E1
interface, no overvoltage protetcion is needed. Overvoltage protection circuitry, however,
exists in the external connector panel (the same panel used for both symnmetric E1 and
T1 interfaces). External connector panel shall always be used for interfacing symmetric
E1.
Coaxial (75Ω) E1 interface
The E1 line interface between ET16 and external connector panel is always symmetric
(120Ω). Conversion from symmetric to coaxial is realized in the external connector panel.
A special connector panel type is used for coaxial E1 interface. Overvoltage protection
circuitry is not included in the coaxial connector panel. External connector panel shall
always be used for interfacing coaxial E1.
T1 Interface
The T1 line interface consists of interface protection with magnetics, and line interface
with LIU and framer. Overvoltage protection circuitry exists in the external connector
panel. The external connector panel is always used for interfacing T1.

3.4.3 Backplane interface

The ET16 has four 8.192MBit/s backplane interfaces that carry all E1/T1 timeslots.

20 © 2016 Nokia DN0592435 Issue: 1-7

ET16 Operation of ET16

4 Operation of ET16
Front panel of ET16 plug-in unit
Figure 5 Front panel of the ET16

LINE
ALARMS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

DN0596322

LED indicator
The front panel of the ET16 plug-in unit has seventeen red alarm LED indicators. It is
provided together with the lightpipe. The following functions are defined:

1. If there are no alarms or errors, the LEDs are off.

2. If there is a clock alarm, the uppermost LED is on (red colour)
3. If the following special situations occur in incoming or outgoing PCMs, the
corresponding LED is on (red colour):
• loss of incoming signal or frame
• AIS in incoming or outgoing direction
• BER in incoming direction > 10E-3
• equipment or line loop is activated.

g Note: ALTST signal does not turn the red LED on.

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Operation of ET16 ET16

Backplane connector
The ET16 plug-in unit is connected to the backplane with a four Z-pack HM-type
connectors (P5, P4, P2 and P1). For connector map, see Connector maps of ET16.

22 © 2016 Nokia DN0592435 Issue: 1-7

ET16 Power consumption of ET16

5 Power consumption of ET16

The permissible maximum power consumption of the ET16 is 16W. The typical power
consumption of the ET16 is 11W for the Emerson variant and 8W for the Interphase
variant.

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ET16 C109519 ET16

6 ET16 C109519
The ET16 has two vendors that differ in layout and function of the interface switch. They
can be distinguished from each other by the differences in the PWB.

6.1 Emerson ET16 (versions 1-4)

Figure 6 Jumpers and micro switches of the Emerson ET16 (version 1)

P5

P4

SW1
B2
Lineinterfacemode
OFF
2 1
SW1
ON
P2

Interchangeability
7 5 3 1

P1 B2 8 6 4 2

DN0596334

Configuration settings
The line interface mode settings are presented in the table below (SW1). Line interface
mode can be overridden by SW settings

Switch Function
1 2

OFF OFF E1 (default)

OFF ON T1

g Note: E1 setting applies to both symmetric (120Ω) and asymmetric (75Ω) interfaces.
Conversion from symmetric to asymmetric is realized in connector panel CPETC.
Connector panel CPETS is needed for symmetric E1 interface.

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ET16 ET16 C109519

6.2 Emerson ET16 (version 5 onwards)

Figure 7 Jumpers and micro switches of the Emerson ET16 (version 5 onwards)

P5

SW1

P4
W2 Lineinterfacemode

SW1 2
ON OFF
1

P2 Interchangeability
8 7
6 5
W2 4 3
2 1
P1

DN0950516

Configuration settings
The line interface mode settings are presented in the table below (SW1). Line interface
mode can be overridden by SW settings

Switch Function
1 2

OFF OFF E1 (default)

OFF ON T1

g Note: E1 setting applies to both symmetric (120Ω) and asymmetric (75Ω) interfaces.
Conversion from symmetric to asymmetric is realized in connector panel CPETC.
Connector panel CPETS is needed for symmetric E1 interface.

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ET16 C109519 ET16

6.3 Interphase ET16

Figure 8 Jumpers and micro switches of the Interphase ET16

P5

ON

P4 SW1 OFF

1 2

W1 2 4 6 8 10

SW1 W1
P2
1 3 5 7 9

P1

DN70480735

Configuration settings
The line interface mode settings are presented in the table below (SW1). Line interface
mode can be overridden by SW settings

Switch Function
1 2

OFF OFF JT1

OFF ON T1

ON OFF E1/75R (not in

use)

ON ON E1/120R

g Note: E1 setting applies to both symmetric (120Ω) and asymmetric (75Ω) interfaces.
Conversion from symmetric to asymmetric is realized in connector panel CPETC.
Connector panel CPETS is needed for symmetric E1 interface.

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ET16 ET16 C109519

6.4 Interchangeability settings

The setting of the interchangeability code is presented in the table below (B2 / W2 / W1).

Table 3 Interchangeability code (ICC) settings (B2 / W2 / W1).

ICC code Setting
7-8 5-6 3-4 1-2

A ON ON ON ON

B ON ON ON OFF

C ON ON OFF ON

D ON ON OFF OFF

E ON OFF ON ON

F ON OFF ON OFF

G ON OFF OFF ON

H ON OFF OFF OFF

J OFF ON ON ON

K OFF ON ON OFF

L OFF ON OFF ON

M OFF ON OFF OFF

N OFF OFF ON ON

P OFF OFF ON OFF

R OFF OFF OFF ON

S OFF OFF OFF OFF

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Connector maps of ET16 ET16

7 Connector maps of ET16

7.1 Backplane connectors

The ET16 has four backplane connectors, P1, P2, P4 and P5. There are no connections
to connector P1.

Table 4 Connector P5 pin order

E D C B A

1 GND T1-0 R1-0 R-0 T-0

2 GND

3 GND T1-1 R1-1 R-1 T-1

4 GND

5 GND T1-2 R1-2 R-2 T-2

6 GND

7 GND T1-3 R1-3 R-3 T-3

8 GND

9 GND T1-4 R1-4 R-4 T-4

10 GND

11 GND T1-5 R1-5 R-5 T-5

12 GND

13 GND T1–6 R1–6 R-6 T-6

14 GND

15 GND T1–7 R1–7 R-7 T-7

16 GND

17 GND T1–8 R1–8 R-8 T-8

18 GND

19 GND T1–9 R1–9 R-9 T-9

20 GND

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ET16 Connector maps of ET16

Table 4 Connector P5 pin order (Cont.)

21 GND T1–10 R1–10 R-10 T–10

22 GND

Table 5 Connector P4 pin order

E D C B A

1 GND T1-11 R1–11 R-11 T-11

2 GND

3 GND T1–12 R1–12 R-12 T-12

4 GND

5 GND T1–13 R1–13 R-13 T-13

6 GND

7 GND T1–14 R1–14 R-14 T-14

8 GND

9 GND T1–15 R1–15 R-15 T-15

10 GND

11 GND

12 -UB -UB B0V B0V

13 -UB -UB B0V B0V

14

15 GND R00-0B R00-0A T00-0B T00-0A

16 GND R01-0B R01-0A T01-0B T01-0A

17 GND R10-0B R10-0A T10-0B T10-0A

18 GND R11-0B R11-0A T11-0B T11-0A

19 GND R00-1B R00-1A T00-1B T00-1A

20 GND R01-1B R01-1A T01-1B T01-1A

21 GND R10-1B R10-1A T10-1B T10-1A

22 GND R11-1B R11-1A T11-1B T11-1A

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Connector maps of ET16 ET16

Table 5 Connector P4 pin order (Cont.)

23 GND TCL0B TCL0A

24 GND

25 GND RCTP

Table 6 Connector P2 pin order

E D C B A

1 GND

2 GND

3 GND ALTST _AL1

4 GND 8MB 8MA 8kB 8kA

5 GND

6 GND

7 GND

8 GND

9 GND BP_LAPD SET_3 SET_2 NTIM_1 NTIM_0

10 GND CGSB CGSA

11 GND

12 GND

13 GND CR00_B CR00_A CT00_B CT00_A

14 GND CR01_B CR01_A CT01_B CT01_A

15 GND

16 GND

17 GND +3.3V

18 GND SLOT_ID4 SLOT_ID3 SLOT_ID2 SLOT_ID1 SLOT_ID0

19 GND

20 GND

21 GND

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ET16 Connector maps of ET16

Table 6 Connector P2 pin order (Cont.)

22 GND

The table below presents the meanings of the backplane connectors.

Table 7 Meanings of the backplane connector signals.

Pin Meaning

-UB, B0V Accumulator voltage

GND Ground

D0V Digital ground. Overvoltage ground and digital ground are separate on the
PWB, and they are connected together in the cartridge.

8M0A, 8M0B, 8K0A, Basic timing signals.

8K0B

R00-xA, R00-xB, R01-xA, 8Mbit/s TDM circuits of the switching network.

R01-xB, R10-xA, R10-xB,
R11-xA, R11-xB

R1-x, T1-x E1/T1 interfaces 0 - 15 from the external connector panel

R-x, T-x E1/T1 interfaces 0 - 15 to the external connector panel.

CR00_x, CR01_x Separate control TDM inputs (8Mbit/s TDM). Line receiver of type MAX9201.
These signals are not used in ET16.

CT00_x, CT01_x Separate control TDM outputs (8Mbit/s TDM). Line transmitter of type
MAX3032.
These signals are not used in ET16.

TCL0A, TCL0B Synchronizing signal of the synchronization unit.

CGSA, CGSB Inputs to changeover signal invoice.

SLOT-IDx Slot identification signals. Pullup resistor is connected on ET16 board to

SLOT_IDx signals.

_AL1 Basic timing alarm signal. Connected parallel in the cartridge and taken to
specific cabling place. Open-collector transistor is used to prevent
overloading in case of a blown fuse.

ALTST Alarm test signal. Connected parallel in the cartridge and taken to specific
cabling place.

+5VA +5V output from ET4. Connected to +5V through a resistor of 100 Ohm and
diode. Connected in parallel in the cartridge.

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Connector maps of ET16 ET16

Table 7 Meanings of the backplane connector signals. (Cont.)

Pin Meaning

NTIM_0, NTIM_1 Timing mode.

These bits are set in the cabling connector in the cartridge backplane and
latched during boot up only. If the setting of these bits is changed, new
setting is effective only after reboot or power-up of ET16.
NTIM_0 = “1”: PCM signals are connected to the switching network have
nominal timing.
Default setting.
NTIM_0 = “0”: transmitted PCM signals are advanced by 31 ns and sampling
of received PCM signals is delayed by 31 ns.
NTIM_1 = “1”: PCM signals conneted to the swtching network have nominal
timing.
Default setting.
NTIM_1 = “0”: transmitted PCM signals are advanced by 62 ns and sampling
of received PCM signals is delayed by 62ns.
Note that it is allowed to set only NTIM_0 or NTIM_1 to “0”, not both of them
at the same time.

NTIM signals are parallel connected cartridge wide and taken to the cabling
connector in the cartridge back plane.

NTIM is equipped on the ET with a 4.7 kOhm pull-up resistor. In series with
the pull-up resistor there is a diode to prevent the decrease in the signal level
caused by a blown fuse. In addition, a resistor of 1 kOhm is connected in
series with CMOS input.

BP_LAPD LAPD link mode selection signal. Pullup resistor on the board needed. LAPD
= "1": LAPD (1x64kbit/s link) transferred in time slot 0 of PCM0 (default)
LAPD = "0": LAPD (4x64kbit/s links) transferred in time-slot 0 of PCM0,
PCM4, PCM8 and PCM12.

RCTP Test point receive clock.

SET_2, SET_3 Reserved for future use.

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