UNIT 2 : DESIGN OF COMBINATIONAL CIRCUITS

Introduction to Combinational circuits - Analysis and design procedures

Half Adder, Full Adder-Half Subtractor, Full Subtractor
Carry look ahead Adder- Decoders- Encoders-Priority Encoder
Multiplexers- Demultiplexers

2.1 Introduction to Combinational circuits

Combinational Logic Circuits are made from the basic and universal gates. The
output is defined by the logic and it is depend only the present input states not the
previous states.
Inputs and output(s) : logic 0 (low) or logic 1 (high).

Fig. Block diagram of a combinational circuits

Analysis and design procedures

The following are the basic steps to design a combinational circuits
1. Define the problem.
2. Determine the number of input and output variables.
3. Fix a letter symbols to the input and the outputs. (eg. A,B,C ,w, x, Y,F, etc)
4. Get the relationship between input and output from the truth table.
5. By using K-map obtain the simplified Boolean expression for the outputs.
6. Draw the logic diagram using gates.

Example : Design a combinational logic circuit with three inputs , the output is at logic 1
when more than one inputs are at logic 1.
Solution: Assume A, B, C are inputs and Y is output .

Truth table K map Simplification

Inputs Output
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 Boolean Expression
1 0 0 0 Y=AC + BC + AB
1 0 1 1
1 1 0 1 Logic Diagram
1 1 1 1

2.2 Adder
The Basic operation in digital computer is binary addition. The circuit which
perform the addition of binary bits are called as Adder.

The logic circuit which perform the addition of two bit is called Half adder and three bit
is called Full adder.
Rules for two bit addition
0+0=0
0+1=1
1+0=1
1 + 1 = 102

2.2.1 Half Adder

The two inputs of the half adders are augend and addend, the outputs are sum and
carry.
Block diagram of Half adder
K-map simplification

Truth table of Half adder

Inputs Outputs
A B Carry Sum
0 0 0 0 Logic diagram
0 1 0 1
1 0 0 1
1 1 1 0

2.2.2 Full Adder

The three inputs of the full adders are augend , addend and the carry input from
the previous addition, the outputs are sum and carry
Block diagram of Full adder
 Truth table K-map simplifications
Inputs Outputs
A B Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
The Full Adder can be implement using Two Half Adders and OR gates

The expression for sum is

The Expression for carry is

Logic Diagram
2.3 Subtractor
Subtractor is the logic circuit which is used to subtract two binary number (digit)
and provides Difference and Borrow as a output. In digital electronics we have two
types of subtractor, Half Subtractor and Full Subtractor.

Rules for two bit addition

0-0=0
0 - 1 = 1 with borrow 1
1-0=1
1-1=0

2.3.1 Half Subtractor

Half Subtractor is used for subtracting one single bit binary digit from another single bit
binary digit.The truth table of Half Subtractor is shown below.

Truth table of Half adder K-map for Difference and Borrow

Inputs Outputs
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logic Diagram
2.3.2 Full Subtractor
A logic Circuit Which is used for Subtracting Three Single bit Binary digit is
known as Full Subtractor.The inputs are A,B, Bin and the outputs are D and Bout.
Truth table K-map for D and Bout
Inputs Outputs
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0 Logic Diagram
1 1 0 0 0
1 1 1 1 1

We can further simplify the function of the Difference (D)

Simplified Logic diagram

2.4 Parallel Adder – Subtractor

2.4.1 Four bit Parallel binary Adder

In practical situations it is required to add two data each containing more than
one bit. Two binary numbers each of n bits can be added by means of a full adder
circuit. Consider the example that two 4-bit binary numbers B 4B 3B 2B 1 and A 4A 3A 2A
1 are to be added with a carry input C 1. This can be done by cascading four full adder
circuits. The least significant bits A 1, B 1, and C 1 are added to the produce sum output
S1 and carry output C 2. Carry output C 2 is then added to the next significant bits A2 and
B2 producing sum output S 2 and carry output C 3. C 3 is then added to A3 and B3 and so
on. Thus finally producing the four-bit sum output S 4S 3S 2S 1 and final carry output
Cout.
2.4.2 Four Bit Parallel Binary Subtractor
We can design a four bit parallel subtractor by connecting three full subtractors and one
half subtractor. In the figure A = A3 A2 A1 A0 is minuend B = B3 B2 B1 B0 is subtrahend
giving the difference D = D3 D2 D1 D0.

Fig.Block diagram of 4 bit binary parallel Subtractor

The subtraction operation can be performed using 1’s and 2’s complement addition, so
we can design Full subtractor using Full Adder.

Fig.Four bit binary subtractor using Full Adder

2.4.3 Parallel binary Adder – Subtractor

 The addition and subtraction operations can be perform using a common adder
circuit, where a EX-OR gate is connected in the second input along with the mode
selection bit M. if M=0 the circuit act as a adder, M=1 then substractor. If M=0 then
output of the EX-OR gate is B act as adder, if M=1 then B’ act as a subtractor.

Fig.Parallel binary Adder – Subtractor

2.4.4 Carry look ahead Adder

In the parallel adder the carry input of each stage is depends on the carry output
of the previous stage. This processes leads to time delay in addition.This delay is called
propagation delay. The process can be speeding up by eliminating the inter stage carry
delay called look ahead carry addition. In uses two functions carry generate and carry
propagate.

Fig.Full Adder Circuit

The output sum and carry can be expressed as

Gi is called carry generate and Pi is called carry propagate.

The Boolean function for the carry output of each stage can be

From the above functions it can be seen that C 4 does not have to wait for C3 and
C2. All the carries are propagating at the same time.

Fig.Logic diagram of a look-ahead carry generator

 Decoder is a combinational circuit.
Decoder
It has N inputs and 2N outputs.
2X4 Decoder: 2 to 4 Decoder

It has 2 inputs and 22 = 4 outputs.

2X4 Decode Block Diagram

Truth Table

Logic Diagram
2 to 4 Decoder with Enable input

Truth Table

Logic Diagram
3 to 8 Decoder
It has 3 inputs and 23 = 8 outputs.
Logic Diagram

2.7 Encoders
Encoders is a combinational circuit which takes 2N inputs and gives out N outputs, the
enable pin should be kept 1 for enabling the circuit.

4 to 2 Encoder
It has 22 inputs and 2 outputs.
Truth Table

2.7.1 Priority Encoders

A Priority Encoder works opposite of the decoder circuit. If more than one input is
active, the higher order input has priority.

4 to 2 Priority Encoders

D0-D3 - inputs

A1,A0 – outputs

Active (A)– Valid indicator. It indicates the output is valid or not

Output is invalid when no inputs are active .i.e, A=0

Output is valid when at least one input is active .i,e, A=1

Truth Table

K-map simplification
Logic Diagram

3 to 8 Priority Encoder

2.8 Mutliplexer (Mux)

Multiplexer is a combinational circuit that selects binary information from one of many
inputs and directs it into single output.

The selection of particular input is controlled by a set of selection line

Mutliplexer has 2n inputs, n select line (control input) and one output
It also called as Data selector

2 to 1 Multiplexer

has 21 inputs, 1 select line and one output

Circuit diagram

4 to 1 MUX

4 to 1 MUX has 22 = 4 inputs, 2 select line and one output

8 to1 MUX
8 to1 MUX has 23 = 8 inputs, 3 select line and one output
2.8.1 MUX as universal combinational modules

Each minterm of the function can be mapped to a data input of the multiplexer.
For each row in the truth table, where the output is 1, set the corresponding data input
of the mux to 1.Set the remaining inputs of the mux to 0.

Example 1: Implement the following Boolean function using 4:1 MUX

F(x,y,z) = Σm(1, 2, 6, 7)

Truth Table

Multiplexer Implementation
Example 2: Implement the following Boolean function using 8:1 MUX

F(A,B,C,D) = Σm(1, 3, 4, 11,12-15)

2.9 Demultiplexer (DEMUX)
Demultiplexer has 2n outputs , n select lines, one input.

A demultiplexer is also called a data distributor.

1-to-2 demultiplexer
has 22 outputs , 2 select lines, one input.

The truth table

Logic diagram
1-to-4 Demultiplexer

It has one input,2 select lines,4 outputs

The truth table

 Logic Diagram

1-to-8 Demultiplexer

Has one input

3-select lines

8-outputs

The truth table

Logic Diagram
1-to-8 DEMUX using Two 1-to- 4 Demultiplexers

1-to-8 demultiplexer can be implemented by using two 1-to-4 demultiplexers with a

proper cascading.

In the above figure, the highest significant bit A of the selection inputs are connected to
the enable inputs such that it is complemented before connecting to one DEMUX and to
the other it is directly connected.By this configuration, when A is set to zero, one of the
output lines from Y0 to Y3 is selected based on the combination of select lines B and C.
Similarly, when A is set to one, based on the select lines one of the output lines from Y4
to Y7 will be selected.

2.9.1 Applications of Demultiplexer

 Synchronous data transmission systems

 Boolean function implementation (as we discussed full subtractor function above)
 Data acquisition systems
 Combinational circuit design
 Automatic test equipment systems