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Issues in Code Generator-Pages-2

The document discusses the code generation phase of a compiler. It describes the input, output, and key issues in code generation including memory management, instruction selection, register allocation, and evaluation order. It also provides details about the target machine including its instruction set and addressing modes.

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26 views

Issues in Code Generator-Pages-2

The document discusses the code generation phase of a compiler. It describes the input, output, and key issues in code generation including memory management, instruction selection, register allocation, and evaluation order. It also provides details about the target machine including its instruction set and addressing modes.

Uploaded by

sumitashetty19
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MODULE-4 CODE GENERATION

The final phase in compiler model is the code generator. It takes as input an intermediate
representation of the source program and produces as output an equivalent target program. The
code generation techniques presented below can be used whether or not an optimizing phase
occurs before code generation.

Position of code generator

source front end intermediate code intermediate code target


program code optimizer code generator program

symbol
table

ISSUES IN THE DESIGN OF A CODE GENERATOR

The following issues arise during the code generation phase :

1. Input to code generator


2. Target program
3. Memory management
4. Instruction selection
5. Register allocation
6. Evaluation order

1. Input to code generator:


 The input to the code generation consists of the intermediate representation of the source
program produced by front end , together with information in the symbol table to
determine run-time addresses of the data objects denoted by the names in the
intermediate representation.

 Intermediate representation can be :


a. Linear representation such as postfix notation
b. Three address representation such as quadruples
c. Virtual machine representation such as stack machine code
d. Graphical representations such as syntax trees and dags.

 Prior to code generation, the front end must be scanned, parsed and translated into
intermediate representation along with necessary type checking. Therefore, input to code
generation is assumed to be error-free.

2. Target program:
 The output of the code generator is the target program. The output may be :
a. Absolute machine language
- It can be placed in a fixed memory location and can be executed immediately.
b. Relocatable machine language
- It allows subprograms to be compiled separately.

c. Assembly language
- Code generation is made easier.

3. Memory management:
 Names in the source program are mapped to addresses of data objects in run-time
memory by the front end and code generator.

 It makes use of symbol table, that is, a name in a three-address statement refers to a
symbol-table entry for the name.

 Labels in three-address statements have to be converted to addresses of instructions.


For example,
j : goto i generates jump instruction as follows :
 if i < j, a backward jump instruction with target address equal to location of
code for quadruple i is generated.
 if i > j, the jump is forward. We must store on a list for quadruple i the
location of the first machine instruction generated for quadruple j. When i is
processed, the machine locations for all instructions that forward jumps to i
are filled.

4. Instruction selection:
 The instructions of target machine should be complete and uniform.

 Instruction speeds and machine idioms are important factors when efficiency of target
program is considered.

 The quality of the generated code is determined by its speed and size.

 The former statement can be translated into the latter statement as shown below:

5. Register allocation
 Instructions involving register operands are shorter and faster than those involving
operands in memory.

 The use of registers is subdivided into two subproblems :


 Register allocation – the set of variables that will reside in registers at a point in
the program is selected.
 Register assignment – the specific register that a variable will reside in is
picked.

 Certain machine requires even-odd register pairs for some operands and results.
For example , consider the division instruction of the form :
D x, y

where, x – dividend even register in even/odd register pair


y – divisor
even register holds the remainder
odd register holds the quotient

6. Evaluation order
 The order in which the computations are performed can affect the efficiency of the
target code. Some computation orders require fewer registers to hold intermediate
results than others.

TARGET MACHINE

 Familiarity with the target machine and its instruction set is a prerequisite for designing a
good code generator.
 The target computer is a byte-addressable machine with 4 bytes to a word.
 It has n general-purpose registers, R0, R1, . . . , Rn-1.
 It has two-address instructions of the form:
op source, destination
where, op is an op-code, and source and destination are data fields.

 It has the following op-codes :


MOV (move source to destination)
ADD (add source to destination)
SUB (subtract source from destination)

 The source and destination of an instruction are specified by combining registers and
memory locations with address modes.

Address modes with their assembly-language forms

MODE FORM ADDRESS ADDED COST

absolute M M 1

register R R 0

indexed c(R) c+contents(R) 1

indirect register *R contents (R) 0

indirect indexed *c(R) contents(c+ 1


contents(R))

literal #c c 1

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