ALU DESIGN PLAN

Presented by
G.Kaladhar
MISSDV0716
 Table of Contents
Chapter 1:
1.1. Introduction
1.2. Features
1.3. Functions and blocks of ALU
1.31. Opcode Decoder
1.32 Arithmetic Block
1.33. Logical Block
1.34. Comparator Block
1.35. Shifter/Rotator Block
1.36. Code converter Block

Chapter 2:
2.1. Opcode decoder
2.1.1. Description with an example
2.2. Arithmetic block
2.2.1. description with an example
2.3. Logical block
2.3.1. description with an example
2.4. Comparator block
2.4.1. description with an example
2.5. Shifter/Rotator block
2.5.1. description with an example
2.6 Code conversion block
2.6.1. description with an example
2.7. Logic fetch block
2.7.1. description with an example

Chapter 3: Integration (design block diagram)

Chapter 4: Conclusion and Enhancement

Chapter 5: EDA Playground Link

 CHAPTER-1
1.1 Introduction:
The Basic Arithmetic Logic Unit (ALU) is a fundamental component of a digital computer's central
processing unit (CPU). It performs arithmetic and bitwise logical operations on input data according to the
instructions provided by the CPU. An ALU performs basic arithmetic and logic operations. Examples of
arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are
comparisons of values such as NOT, AND, and OR.

All information in a computer is stored and manipulated in the form of binary numbers, i.e. 0 and 1.
Transistor switches are used to manipulate binary numbers since there are only two possible states of a
switch: open or closed. An open transistor, through which there is no current, represents a 0. A closed
transistor, through which there is a current, represents a 1.

1.2 Features of Alu:

Advantages:
 ALUs support parallel architecture and applications.
 They can provide the desired output simultaneously, handling both integer and floating-point
variables.
 ALUs can carry out instructions on a large set of data items.
 They have a high level of precision, making them versatile for various computational tasks.
 ALUs can carry out instructions on a large set of data items.
 They have a high level of precision, making them versatile for various computational tasks.

Disadvantages:
 Memory space should be definite. Else bugs would occur in our result.
 Their circuit is complex and therefore amateurs find it difficult to understand.
 Floating variables have more delays.
 Design controller is still more difficult to understand.
 Rounding off is another con to be noted. Large numbers are generally rounded off thus
impacting accuracy.
 Applications:
In this project, we have taken basic operations and we have used an 8-bit accumulator and auxiliary -
b register as inputs and a 16-bit output register along with 3 flags which are zero flags, carry flags, and done
flags.
Zero flag – 1 indicates the result of all Zeros.
-0- indicates the result is non-zeroes.

1.3 Functional blocks:

1)Opcode decoder:
The opcode decoder examines the fetched opcode to determine what operation it represents. This
usually involves looking up the opcode in a table or using some logic to identify the instruction.
2) Arithmetic Block:
This block consists of arithmetic logic units (ALUs) responsible for performing arithmetic and
logic operations such as addition, subtraction, AND, OR, etc.
3)Logical Block:
The logical block contains logic gates and circuits for executing logical operations such as AND,
OR, NOT, XOR, etc. It's responsible for executing bitwise logical operations on binary data.
4) Comparator block:
The comparator block includes circuits for comparing two binary values and generating output
signals based on the result of the comparison. The comparator block typically generates flags or
status bits indicating the result of the comparison (e.g., equal, less than, greater than).
5)shifter Block:
The shifter block contains circuits for shifting binary data left or right by a certain number of
positions.
6)Code Conversion block:
Code conversion is essential for interfacing with peripherals, communication protocols, and
storage devices that use different data representations.
7)result fetching Block:
After executing an instruction, the result fetching block retrieves the computed result from
the appropriate location (e.g., register, memory).
 CHAPTER-2
2.1 Opcode decoder:
The proposed design consists of a primary opcode decoder unit which activates the respective
function block based on the instruction’s opcode executed by the processor and forwarded to the ALU block.
The decoder is a 4:16 unit i.e. it takes 4bits opcode as input and activates the respective functional block to
perform the desired operation. using a case implementation statement, we can select and activate the
respective functional block for the required operation.

2.2 Arithmetic Block:

The block implements arithmetic operations such as Addition, Subtraction, Multiplication, and
Division. The Accumulator and the auxiliary B register feed as inputs to this Block.

1) addition:
This is the basic addition of two 8-bit numbers. The output is 8 bits of sum and carry bit in the carry
flag of the 8th bit.
Eg: 1st input acc=8'b10100101; b_reg=8'b01100010;
opcode=4'b0001;//addition
The sum of the above two numbers is 1-00000111: here Msb bit is the carry bit and the
remaining 8 bits are the sum output. After the addition operation, the status register [4]bit-carry flag will be
affected.
Carry Flag-1- indicates there is a carry occurred after the addition.
-0- indicates there is no carry.

2) subtraction:
This is the basic addition of two 8-bit numbers. The output is 8 bits of sum and carry bit in the carry
flag of the 8th bit.
Eg: acc=8'b10010101; b_reg=8'b00011110;
opcode=4'b0010;//subtraction
The difference between the above two numbers is 1_00000111: Here Msb bit is the carry bit and the
remaining 8 bits are the difference output. After the subtraction operation, the status register [4] bit-carry
flag will be affected.
3) Multiplication:
Here the multiplication of two 8-bit numbers will be performed. The product to 8 bits is stored in a
16-bit final output register.
Eg: acc=8'b00001000; b_reg=8'b00001011;
opcode=4'b0011;//multiplication
The result of this 0000_0000_0101_1000.
 4) Divider:
The division operation takes the input of two 8-bit numbers and performs the division operation.
Here we don’t use any flags.
Eg: acc=8'b10110111; b_reg=8'b01100010;
opcode=4'b0100;//division
The result is 0000_0000_0000_0001.

2.3 Logical block:

This block comprises basic logic gate units such as AND, OR, NOT, XOR, etc. Such operations on data
operands are served by this block. Outputs are stored in respective latches. The entire logical block
comprises one dedicated output register
2.3.1 And operation:
The bitwise operation will be performed between two 8-bit operands and the result will be stored in
the logical-out register of 8-bit capacity.

Eg: The bitwise operation between acc=8’b01110011 & b_reg=8’b01000100;

Opcode=4’b0101;//and operation and the output is=0100_0000.
2.3.2 Or operation:
The bitwise operation will be performed between two 8-bit operands and the result will be stored in
the logical-out register of 8-bit capacity.

Eg: The bitwise operation between acc=8’b01110011| b_reg=8’b01000100;

Opcode=4’b0110;//and operation and the output is=011100111;

2.3.3 Not operation:

The bitwise operation will be performed on 8-bit operands and the result will be stored in the logical-
out register of 8-bit capacity.
Eg: The bitwise operation between acc=8’b01110011; b_reg=8’b01000100;
Opcode=4’b0111;//and operation and the output is=10001100.

2.3.4 Nand operation:

The bitwise operation will be performed between two 8-bit operands and the result will be stored in
the logical-out register of 8-bit capacity.
Eg: The bitwise operation between acc=8’b01110011; b_reg=8’b01000100;
Opcode=4’b1000;//and operation and the output is=0100_0000.
2.3.5 Nor operation:
The bitwise operation will be performed between two 8-bit operands and the result will be stored in
the logical-out register of 8-bit capacity.
Eg: The bitwise operation between acc=8’b01110011; b_reg=8’b01000100;
Opcode=4’b0101;//and operation and the output is=0100_0000.

2.3.6 Xor Operation:

The bitwise operation will be performed between two 8-bit operands and the result will be stored in
the logical-out register of 8-bit capacity.
Eg: The bitwise operation between acc=8’b01110011; b_reg=8’b01000100;
Opcode=4’b0101;//and operation and the output is=0100_0000.
2.4 Comparator Block:
This block consists of combinational circuit VHDL code that performs bit matching and
comparisons. Respective outputs may be used to branch instructions based on a comparison. Similarly,
numerically larger or smaller indications on respective operands may be used.
 If acc is greater than b_reg then the result is set to 8’h80-
Eg: acc=8'b10110111; b_reg=8'b01100010;
opcode=4'b1100;//comparator(a>b)
 if acc is less than b_reg then output is set to 8’h01.

Eg:acc=8'b01110100; b_reg=8'b10010110;
opcode=4'b1100;//comparator(a<b)
 If acc is equal to b_reg the carry bit is set to zero and the zero flag is also set to high.
Eg: acc=8b00011100; b_reg=8’b00011100;
Opcode=4’b1100;(==)
2.5 shifter/rotate block:
This block consists of a basic shifter and mechanisms for bit rotation. They accept only one 8-bit
operand. Thus, the type of rotation and the type of shifting command are specified by [7:4] and [3:0]
respectively.
The reference for shift/rotate selection is as follows:
Right shift:0000(opcode)
Left shift:0001
Circular Left shift:0010
Circular Right shift:0011
 The right shift operator (>>) is a binary operator that takes two numbers.
 The left shift operator (<<) is a binary operator that takes two numbers.
 In a circular left shift, we move all the bits of a binary number to the left.
 The bits that fall off from the left end are put back at the right end.
 In a circular right shift, we move all the bits of a binary number to the left.
 The bits that fall off from the right end are put back on the left side.

Right Shift

Left Shift

Circular Left shift

Circular Left shift

Fig: Types of shifting and its process

2.6: Code Conversion:
This block consists of basic 4-bit binary code conversions with a flag bit “done” indicator. The LSB
[3:0] from the b-reg provides the type of code conversion the MSB [7:4] from the b-register provides the
4bit data to be converted. This block has the option to select the 8-bit value from the external switches Dip
which are mapped to b_reg.
If shifting is done Flag bit=1`b1; The shifted result will be selected as input and if the flag is 0 then the input
will be taken from external switches.
The reference for code selection is as follows:
Conversion opcode
Bin to Gray 0001
Bin to xs-3 0010
Bin to xs-5 0011
Bin to BCD 0100
Other than the above opcodes remaining opcodes may be used for future operations and in this project
opcodes have no operation taken(output all zeros). After enabling the done signal, the result is stored in a
register and forwarded to the final output.

2.7 Result Fetching block:

In this block, we used a final mux of 16to1 with all the opcodes connected. To the mux and single
output is taken of 16-bit o/p and for the status block we used another mux connecting with all 16 decoder
flag outputs. Here in this block, I used muxes for representing flags and 16-bit output.
There are two more things output status and flags.
Refresh (1011): This signal is used to reset all the output registers and status registers.
Status (1111): Flags that will show previous operation opcode.
In status, previous states' opcodes in the final output are represented in the final
output.

The resulting block works as:

1) InitOpcodestatus “previous operation opcode”
2) Initopcoderefresh “final_out=16’b0; zero_f=1’b0; carry=1’b0; done_f=1’b0.
3) Initopcode”selected operation”operation is stored in a registerconcatenated with final
output.
 CHAPTER-3
Output As Follows for Given Inputs:

Waveform:
BLOCK DIAGRAM:
All blocks are integrated and the whole block follows:
 CHAPTER-4
Conclusions & Enhancements
 The alu is designed based on the specification given. By using this Alu we can perform arithmetic
operations like addition, subtraction, multiplication, division with data size of 8-bit, logical operations,
comparison of two 8-bit numbers, shifting/rotation operations, converting the 4bit binary number into Gray,
xs-3, xs-5, Bcd code.
This alu has some limitations. This alu will provide only integer type values when a division
operation is performed. In this design, the input & output registers are of the same bit width, and for status,
they have 4bits to show the opcode.

CHAPTER-5
Eda reference link:Reference:
Eda link: https://www.edaplayground.com/x/hHLe