Serial Special

Connect Your TEC to the Zilog SIO

Communicate with SPI and I2C Devices

Bit Banging Serial for the TEC

TEC PCB Revision History (with Pics)

Modding Your TEC

.....And More......
Editorial
Table of Contents
Welcome to the New Talking Electronics Computer
(TEC) Journal.
P3 - Bit Banging Your TEC
There has been some excellent TEC contributions
and ideas over the last few years. Most of these
'posts' have been on the Facebook group. They P5 - TEC Mods
seem to get lost forever, I thought it would be good
to start a NEW magazine that collates these projects
and makes them more permanent and visible. P6 - TEC PCB Revision History

This issue focuses on the Serial interface with the

TEC. There has been some great work done on P10 - How to use a Zilog SIO
getting Serial Communication from your computer to
the TEC. This is something I think is extremely
p13 - TEC Community Page
valuable in these modern times if you are serious
about programming the TEC.
p15 - TEC -> SPI and I2C Guide
For the next issues, it's up to YOU, The TEC
Community! We want you to contribute and share
your work, whether big or small on all things TEC p19 - Jim's Serial Routines
related. To contribute, just add your work to the TEC
Journal GitHub directory. When there are enough
articles, I'll get around and publish them. There may
be 2 to 4 issues a year, depending on how popular (or
not) this concept is. I would also like to hear from
the people who make up the TEC Community and
find out why they are into the TEC.

Who am I? My name is Brian Chiha and like most of

us discovered Talking Electronics when I was a
teenager. I was able to build a TEC-1B back in the
early nineties. I can't find it anymore, but one striking
thing was that the Seven Segments Displays that I How to Contribute
used had a different pinout. I had to wire wrap them
from the board to their legs, creating some 3-D To get your work published in the TEC Journal, just
popout display. Fast forward about 30 years, I found upload your files/pictures/pdfs to the /pending
the TEC-1D and built it. By then I was already a directory of the TEC Journal GitHub page. This
software engineer and had a better understanding of requires you to create a GitHub account and click
programming and electronics. I eventually went all on the 'Add File' button. If you prefer to format your
out and built an LED 8x8, DAT, NVRam, SIO and article, use the 'Article-Template.docx' file and the
Expansion board for the TEC. I also created a bunch fonts provided in the /template_and_fonts
of software, like TEC Invaders Mk2, A Maze Game and directory. Important: Put your name on the article
Game of Life. to get credited!

I've designed the magazine to look and feel like the © Copyright
original TE mags. I hope you enjoy the read! All articles, text and pictures are the property of
the named author. Any reproduction of their work
Brian. must be granted first by the owner. This journal is
a collection of individual works.

Useful Links
* TEC 1 Resources Page: https://github.com/tec1group GitHub TEC-Journal pending directory
* TEC Journal GitHub: https://github.com/tec1group/TEC-Journal
* TEC Facebook Page: https://www.facebook.com/groups/tec1z80
* TEC 1 Emulator: https://tec1group.github.io/wicked-tec1/
* Z80 Assembler and debugger: https://www.asm80.com/
* Z80 Reference: https://clrhome.org/table/ Add file button on GitHub

TEC Journal #1 2
 Bit banging a serial port is an easy and
Bit Banging cheap way to connect your TEC to the
outside world. In this article we will look at

serial for how bit banged serial transmit and receive

can be implemented in Z80 assembly
language.
the TEC
By Craig RS Jones

Start Stop
Asynchronous Serial Character
8N1 = 8 bits, no parity, 1 stop bit, character length = 10 bits

An asynchronous serial byte or character is shown above, it’s

called asynchronous serial because there is no common clock
signal between the receiver and the transmitter, instead each
character or byte has start and stop bits added to provide BAUD = delay constant for Baud rate
synchronisation.
Each of the bits, including the start and stop bit are output for
;--------------------------------------------
the same amount of time, this ‘bit time’ is equal to 1/ number of
;transmit a serial character
Bits Per Second(BPS) or Baud rate . For example, at 4800 Baud
;--------------------------------------------
the bit time would be 1/4800 = 208us.
The most important thing for successful transmission is to have ; C = character to transmit
the receiver and the transmitter using the same Baud rate! ;
;
;send the start bit
Serial Transmit
;
There are three parts to the transmit code, the first is to send
LD a,$00
the start bit, the second to send the data and the last part to
send the stop bit or bits. OUT (PORT),A ;start bit = 0
LD HL,(BAUD)
1. Start Bit transmission CALL BITIME
;one bit time delay
The FTDI USB to serial converter expects the RXI (Receive Input) ;
to normally be High, so to send the start bit our code simply ; set up to shift out the character
makes the data line Low and delays for one bit time. ;
LD B,08H ; 8 bits to transmit
2. Send the data byte RRC C
To send the data byte we must output each bit in turn for the SHIFTOUT:
bit time on the output pin. The serial data output is the Bit 6 ; move all the bits one position to the right
position in the output register for the TEC so we have to shift all RRC C
the bits in the data byte to the bit 6 position for output. LD A,C
AND 40H
The RRC instruction shifts the bits in the register one bit to the
;output the bit and delay for the bit time
right, shifting the bit in position 0 into the bit 7 position with
OUT (PORT),A
each shift.
LD HL,(BAUD)
CALL BITIME ;one bit time delay
To start we put the loop or bit count in B, the first RRC
;have we done all the bits?
instruction moves all the bits one position to the right, bit 0
DJNZ SHIFTOUT ;jump if not finished
moves into the now empty bit 7 position.
;
Now we just execute the loop 8 times, shifting each bit into the ; send the stop bit (or bits)
bit 6 position for output and then doing a bit time delay. ;
LD A,$40
3. Stop Bit transmission OUT (PORT),A ;stop bit=1
Finally, set the output pin high and output each stop bit for the LD HL,(BAUD)
bit time. The next character can then be sent, any additional CALL BITIME ;send the stop bit
delay here is usually called the ‘inter-character delay’. CALL BITIME ;or two if required
RET
 Start Stop

Serial Receive Routine

Receiving a character is a little more complicated and starts
with synchronising, waiting in a loop until the falling edge of the
start bit arrives.
1. Start bit detection
Once the falling edge is detected we delay for only half a bit
time, until time ‘0’ in the diagram above. To calculate the delay
time we divide the BAUD variable, which is the bit time delay ;-----------------------
value, by 2 by shifting the 16-bit HL register one bit to the right. ; receive a serial character
The instruction, SRL (Logical shift right), shifts the byte in the H ;-----------------------
register one bit right, shifting Bit 0 into the carry, the next ; wait for the start bit falling edge
instruction, RR (Rotate Right through carry) shifts the bit out of STARTLOOP:
the carry into the bit 7 position of the L register. Using these two IN A,(KEYBUF)
instructions on the H and L registers performs a divide by 2 on BIT 7,A
the 16-bit register HL .
JR NZ,STARTLOOP
Once the half bit time delay finishes another check of the input
; delay for half the bit time
level is done, if it is still low we have a valid start bit, if not then
LD HL,(BAUD)
we have what is called a ‘framing error’, so we just go back and
SRL H
wait for the next falling edge of a start bit.
RR L
2. Receive the data byte
You can see in the diagram that we are now at time 0, halfway CALL BITIME
into the start bit, now we can simply read in the data byte ; is the start bit still low?
delaying one full bit time before reading the middle of the next IN A,(KEYBUF)
bit in the eight bit character. BIT 7,A
Since we are reading our data in on bit 7of the input register, we JR NZ,STARTLOOP
do a RL, (Rotate Accumulator Left) on the input byte, shifting bit ; shift in the character
7 into the carry bit and then doing a RR,( Rotate Right through LD B,08H ;8 bits to receive
carry) to move the received bit into the C register where our SHIFTIN:
received byte will be assembled. After 8 bits have been LD HL,(BAUD)
received our character is in the C register. CALL BITIME ;one bit time delay
3. Check the stop bits? IN A,(KEYBUF)
,We don’t really care about checking our stop bits and there is RL A
probably something we want to do with our received byte, time RR C
is of the essence when receiving bit banged serial!
DJNZ SHIFTIN
We don’t bother checking the stop bits and just return the
RET ;character returned in c
received character from the subroutine.
;---------------
; BIT TIME DELAY
Conclusion ;---------------
Bit Banging a serial port is a simple and effective way to connect BITIME:
a resource limited ‘minimum system’ like the TEC to a
PUSH HL ;HL = delay time
computer.
PUSH DE
The ability to communicate this way opens up many
LD DE,0001H
possibilities for input and output, debugging, data logging,
BITIM1 :
downloading/uploading code and data, communicating with
serial peripherals; modems, radios etc. SBC HL,DE
Of course bit banged serial consumes all of the processor time JP NC,BITIM1
during transmission and reception, which is why dedicated POP DE
hardware devices such as the Z80 SIO and MC6850 ACIA were POP HL
designed to offload the transmission and reception of serial RET
data.

References:
Southern Cross Monitor TXDATA and RXDATA subroutines.
Jack Ganssle has a good description and some routines here;
http://www.ganssle.com/articles/auart.htm
Sparkfun have an extensive tutorial;
https://learn.sparkfun.com/tutorials/serial-communication
 TEC Mods!
Welcome to the TEC Mods page! A place where upgrading has no limit....
If you like to tinker with your TEC and would like to share your work, send us your plans via GitHub and it
will be shared here.

Add Serial to
your TEC

EDITORS NOTE:
Craig Jones nicely posted
this picture on Facebook.
It came with no
description, just the
picture. It is labelled as
"TEC-1 Bit Bang Serial to
USB Converter". Its title
says it all and the
schematic is self-
explanatory. It will work
with the code that is
explained in his article on
the previous pages. Just
set KEYBUF to 0 and PORT
to 1.

Credit: Craig Jones (Picture)

IO Decoder Exapander

The IO port decoder on the TEC only Decodes A0-A2 address lines. This means the TEC IO map 'wraps around'
every 8 ports. This can be fixed with the first mod - which ensures the IO ports only occupy IO space 00h-3fh.
This frees 40H onwards for other modules e.g. a 6850 at 80h for Grant Searle's Tiny Basic.

The Second mod is similar - the Memory decoder’s highest connected address line is A13, hence the memory
wraps around every 16k. Memory address 0000h is also address 4000h, 8000h and C000h. If you want to
add more than 16k of memory, you need to make this mod, which ensures the whole 64k address space is fully
decoded without the wrap-around effect.

The TEC-1B rev.1 boards and newer already have this mod built in. Look for the two diodes near the 70ls138
memory decoder – if present, you have the mod.

The mods work on an original TEC with no additional chips required, by borrowing the two otherwise unused
gates of the 4049 inverter. If you have a crystal oscillator, you can use an additional inverter chip - a 4049 or a
74xx14 will do nicely here as would almost any inverter gate. Credit: Craig Hart

TEC Journal #1 5
A brief history of TEC-1 PCBs
The TEC-1 PCB has undegone several revisions over time. Although the designs
are all very similar and generally software bacwards-compatible (Same
memory map, IO port map, keyboard layout etc.), there are some subtle
differences that may be of interest to collectors and the like.
By Craig Hart
PCB's were generally made in mods for JMON and MON1/2 10 cover. Designed by Ken Stone
batches of 100 at TE and typically select switch. and John Hardy. PCB Artwork by
changed colour each batch (but Ken Stone. Only 5 of this version
not always). Between the basic TEC-1D Reproduction board by exist, distributed to TE staff and
design revision and the colour, the Ben Grimmit, 2018. John Hardy. The clock capacitor
age of the machine can thus be was marked as 220pf (Changed
roughly dated. TEC-1E "MIT-Z" design by Ken later to 100pf) and the speaker
Stone, 2020. LED was hidden by the speaker
No precise record was kept of and had to be moved.
manufacturing dates and boards TEC-1F Reproduction of the TEC- * TEC-1 Batch ?. White text blue
were not serial-numbered, so this 1D board by Craig Jones, 2021. speaker on green PCB. Issue 11
information is being 'reverse Major improvements to cover.
engineered' and is mainly modernise the board. * TEC-1 Batch ?. White text black
educated guesswork on the part speaker on green PCB.
of TEC owners and former TE staff. Detailed cronology * TEC-1 Batch ?. Blue text and
It is not to be taken as absolute or white speaker on green PCB.
100% accurate. follows * TEC-1 Batch ?. Yellow text blue
speaker on green PCB.
First "Z-80 computer" prototype.
In short, the This was not actually called a * TEC-1A prototype. Bare
following major TEC-1, and was unlike any that are fibreglass. No silk screen overlay.
shown in the photos. It was New disply latch validation design.
design revisions exist casually refered to as Orac. It has (There is a single 1A with the
not survived. Built by John Hardy. regulator mounted above the PCB,
TEC-1 (Issue 10, original, 1983).
7805 regulator above PCB bottom but at right angles to its former
First TEC-1 prototype. No silk location, and provision is made for
left corner. 8212 dispaly latch
screen. Incorrect track work. It bolding it to the PCB. This board is
chips. no Shift key. MON-1 monitor
was scrapped and is presumed the prototype 1A made to test the
ROM by John Hardy.
lost, possibly sold as part of a new latches, and has no solder
grab-bag. Built by Ken Stone. Last mask or overlays.)
TEC-1A (Issue 12). Issue 12 page 14
seen by Craig Hart in the scrap
states "The regulator is mounted
pile at TE, late 1980's. Issue 12 page 13 claims that over
under the PC board so that it
cannot be bent over and broken 1000 TECs were sold by this point.
Second TEC-1 prototype. Bare
off, the 2,200uf electrolytic has
fibreglass. No silk screen. Cut-out * TEC-1A Issue 12 page 13 shows a
been changed to 1,000uf and the
on top left corner. First to work 1A model in a monochrome photo
output latches have been
without corrections to the PCB featuring the diagonal stripes
changed to 74LS273 (or 74LS 374
track work. Built by Ken Stone. across the top left corner and the
or 74LS377). In all other respects,
This unit was mounted in a small Retex case and with 7805
the boards are identical."
rack case and displayed a pseudo mounted under PCB.
error message to demonstrate
TEC-1B (Issue 13). Adds SHIFT key
one of the possibilities of * TEC-1A Batch ?. 2 x (dark)
and MON-2 Monitor ROM by Ken
computerised portable trafic diagonal stripes, white text on
Stone.
lights. The board was notched to green??? PCB. (B&W photo
clear the power transformer. The reference issue 12, p13. single
TEC-1B Rev.1 (Just before issue 15,
keypad was paralleld by a touch proto???)
1990). Minor improvements by
keyboard on the front of the case,
Craig Hart including improved
likewise the LED display. The ROM * TEC-1A Batch ?. White Text
labelleing of IO, memory port &
is labeled "DYCO" Yellow stripes on Blue PCB.
other CPU pins.
* TEC-1 Batch 1. 1983. Red text
TEC-1C (After Issue 15, 1991). CAD
white speaker on blue PCB. Issue Cont....
version by Craig Hart including
TEC Journal #1 6
* TEC-1B Issue 13 introduces the TEC-1B. mask side. Added some mods to incorporate JMON
Monochrome photo on page 9. It now features the requirements (e.g. 4k7 keyboard mod resistor), MON
SHIFT key and MON-2. Red with white speaker on select switch, Mini PCB speaker. Coverted to Protel
green PCB with diagonal stripes. Ken stone and John Autotrax PCB CAD package. Previous PCBs were all
Hardy names removed. done by hand with traditional tape and stencil on
vellum. The 1C may have been the last run produced
* TEC-1B Batch ?. Red diagonal stripes, white text on by TE as TE was all but out of business by the mid
green PCB. 90's. I believe that only one batch of 1C PCBs was
* TEC-1B Batch ?. Blue diagonal stripes, yellow text on ever produced. I did have this unit for a number of
green PCB. years but has been misplaced in various house
* TEC-1B Batch ?. Blue diagonal stripes, white text on moves over the years.
green PCB.
* TEC-1D 2018 Reproduction board by Ben Grimmit.
* TEC-1B Issue 14. No PCB mods but the idea of the White on green PCB. TEC 1D annotation on solder
MON 1/2 switch (mod by cutting a link on the PCB top mask side. Revision information listed below the
side and adding a switch) was introduced here. keyboard, componenet side. Made with Colin
Mitchell's blessing.
TEC-1B Rev.1. 1989/90 PCB design mods by Craig Hart.
Released just prior issue 15. Red text white speaker * TEC-1E 2020 "MIT-Z" design by Ken Stone. Many
on green PCB. Added labels to the memory and I/O new features. Currently at prototype stage. Not 100%
port pins denoting the address range and port TEC-1 compatible. (Ken coments: actually, it is, if you
number. Returned Ken Stone and John Hardy's copy an original EPROM to a larger EPROM, but plans
names to solder mask. I believe that a yellow on were to change the location of the stack)
green 1B PCB exists but I can't locate photos just now.
* TEC-1F 2021 Major improvements around address
* TEC-1B CAD Prototype designed by Craig Hart. decoding from 2K to 8K blocks which are switchable.
Possibly a prototype but not made in production (as I Incorporate a 4MHz clock along with the original
recall -Craig). CMOS clock. Extra lines to connect a UART receiver/
transmitter. Added a latch on Port 0 for easier input
* TEC-1C 1991 PCB designed by Craig Hart. All white receiving. An On/Off switch! Aligned Z80 pins
on green PCB; no stripe. TEC 1C annotation on solder headers and labelled vias on top of the board.

Original Issue 10 Cover Machine

TEC Journal #1 7
 TEC 1 Second Prototype TEC 1 Blue / White / Green

TEC 1A Prototype

TEC 1A White / Yellow / Blue

TEC 1C TEC 1D

TEC Journal #1 8
 TEC 1E

TEC 1F

TEC Journal #1 9
Connect your TEC to the Zilog SIO
If you are a stickler for consistency and would like to use the Zilog chipsets for
your serial communication then using the Zilog SIO (Serial Input / Output) chip
is perfect for your data transmission needs. No need to send/receive a bit at
a time, the SIO does all the hard work. This guide will go through the
configuration, code and pin connections needed to get the SIO working on the
TEC.
By Brian Chiha
The Zilog SIO is quite a powerful have a Zilog CTC (Clock) chip, I
chip that can handle lots of just connect these to the TEC
different types of data clock. But wait!, doesn't the TEC
transmission. Some of its run at 4MHz? Yes, it does, but the
features are: SIO can divide this clock rate
down by 16, 32 or 64. Dividing by
* Two independent full-duplex 64 gives us a manageable Baud
channels (A and B) Rate of 62500. Adding D-Flip
* Asynchronous and Synchronous Flops to the circuit can also bring
transmission down the Baud by one half and
* Buffered data for issues with one quarter.
lagging
* CRC and parity checking. Lastly, the RXDA is the receive
data pin, this is connected to the
TX pin on the USB Serial adaptor,
The SIO Chip and TXDA is the transmit data pin,
which is connected to the RX pin
The chip comes in three different on the USB Serial adaptor. SYNCA
versions., SIO/0, SIO/1 and SIO/2. is to be tied high as it's active low
These versions only affect the 'B' and isn't used. RTSA could be
channel and combine or drop connected to the USB serial CTS
some pins. Irrelevant for us, but pin and CTSA/DCDA can be tied
just check the pinout before to Ground as we don't want to
creating a PCB. performed, the chip is to be block transmission. All other pins
Enabled but also instruct the chip can be left as is.
The pinout of the SIO isn't that to which Channel is used and if it's
complicated as most of the pins a Control or Data byte. The TEC I/
directly connect to the TEC. O decoder is connected to A0- Construction
Looking at the pinout diagram, A2. But we can also use A3-A7.
D0-D7, RESET, M1, IORQ, RD, CLK I've connected B/A to A4 and C/D Most of the pins needed to plug
and INT are connected directly to to A5. the SIO onto the TEC have access
the Z80 pins on the TEC. IEO and points on top of the board. These
IEI (Interrupt Enable Input/Output) EG: If we want to send a Control are the A4, A5 and Data pins on
are for daisy-chaining and are not Byte to Channel B, then we use the Expansion port including GND
needed. IEI is to be tied high. OUT (0x37), A. A4 and A5 are high and VCC. Port 07 on the I/O
which gives us 3 and A0-A2 are decoder and the rest from header
This comes to CE, C/D and B/A. high which gives us 7. Or receive a pins. Except for IORQ, this is to be
CE is Chip Enable and this is Data Byte from Channel A, then taken from underneath the
connected to one of the TEC I/O use IN A,(0x07). A4 and A5 are board. Depending on what TEC
Ports. In my setup, I use PORT low, but still, need to activate Port you have, CLK might need to be
07. The SIO needs to know what 7. taken from under the board too.
Channel it is using A or B and if
the data we are sending/receiving This is all the configuration pins Connections to the USB Serial are
is a Control Byte or a Data Byte. connected. Now, lastly is the to be protected using 2K7
Control bytes are used to set up transmission Channel. We will Resistors. I recommend adding 2
the SIO and check the status of only use Channel A. RXCA and D-Flip Flops to manage the Baud
the SIO. Data bytes are the actual TXCA is the BAUD rate for the Rate. Where Q low, feeds back to
data being transmitted. When an transmission. They can be D and Q high feeds into the next
IN or OUT command on the TEC is independently set but are usually Flip Flop Clock. Then take the Q
connected together. Since I don't output you want.
TEC Journal #1 10
 D-Flip Flops to reduce
Baud Rate

Jumpers to set
clock rate

TEC Exapansion Port

SIO to TEC Schematic

Software Setup In the code, setting the Write Registers is done by

using the OTIR command. This command outputs
To use the SIO, it must be configured to what type of data pointing to HL, B times to port C. Looking at
serial transmission is required. To do this, SIO the code, HL points to the CTLTBL. Then B is set as to
registers are to be set. This is where we use the count and C is set at the port. Once this is done HL
Control Byte setting A5 high. There are Read-only points to the first Control Byte to send, and OTIR is
and Write-only Registers. To communicate with a called. The SIO is now ready to receive and transmit
register, first select the Register, by setting bytes on data.
WR0 and then send the desired configuration in the
next output. The program requires a location to store or send the
data (HL) and the length of the data (BC). The READ
The Write Registers that are to be set are WR4, WR3, routine receives bytes from a Terminal to the TEC. It
WR5 and WR1, and they are to be set in this order. On checks bit 0 (Rx Char available) in RR0, if it is set,
WR4 we need x64 clock divide, 1 stop bit and no then it reads one byte from the Terminal. Stores this
parity. On WR3 we need 8-bits received, auto value and repeats until all the data has been
receive and receive enable. On WR5 we need 8-bits received.
transmit and transmit enabled. Lastly, on WR1, we
disable all interrupts. This might seem confusing (it The SEND routine transmits bytes from the TEC to
was to me too), but look at the code to see which the Terminal. It first sends a byte. Then it checks bit
bits are set compared to the Register configuration. 2 (Tx buffer empty) in RR0. if it's still sending, it waits
until the buffer is empty. Once empty, it sends the
Read register RR0 is also important as it lets us know next byte and repeats until all bytes are sent.
when the transmission buffer is empty and if the SIO The Z80 Assembly code and the SIO registers are on
is ready to receive a byte. We check bits 2 and 0 for the next page. I use Coolterm as my Terminal and a
these. USB to Serial adaptor to connect my computer to the
TEC.

TEC Journal #1 11
;SIO to TTY USB ;Send data to USB
;-------------- ;Sends data at address HL for BC bytes
;Port 7 on TEC is connected to CE SEND: ; Send out data to USB
;A5 is connected to Control/Data, and A4 is connected LD A,(HL) ; Load HL to A
;to A/B OUT (SIO_DA),a ; Send out one byte!
SIO_DA EQU 00000111B ; A5 is C/D, and A4 is A/B CHECKSENT:
SIO_CA EQU 00100111B XOR A ; Load A with RR0
SIO_DB EQU 00010111B OUT (SIO_CA),A ; Select RR0
SIO_CB EQU 00110111B IN A,(SIO_CA) ; Read RR0
BIT 2,A ; Check if TX buffer is empty
;Change these below to suit JR Z,CHECKSENT ; Repeat until buffer is empty
ADDRESS EQU 0900H ; Location of Data to receive/send INC HL ; Move to next address
LENGTH EQU 0050H ; Length of Data to recieve/send DEC BC ; Decrease BC
LD A,B ; Load A with B
SETUP: OR C ; Or with C to check for zero
CALL INIT_SIO ; Set up SIO for Async 8-N-1 JR NZ,SEND ; If not zero then send again
LD HL, ADDRESS ; Save start address in HL RST 00 ; All Done..Restart TEC
LD BC, LENGTH ; Save transmission length in BC
;Initialise the SIO for 8-Bit, No Parity, 1 Stop bit
;; INIT_SIO:
;; Do either a JP READ or JP SEND Here LD HL,CTLTBL ; Point HL to Control Table
;; IPORTS: ; Get requires Bytes, Port and
; Data
;Receive data from USB, LD A,(HL) ; Load Control Table (Bytes)
;Stores data in HL address for BC bytes OR A ; Test for zero
READ: ; Read in data from USB RET Z ; Return if zero
XOR A ; Load A with RR0 LD B,A ; Save bytes in B
OUT (SIO_CA),A ; Select RR0 INC HL ; Go to Port Address
IN A,(SIO_CA) ; Read RR0 LD C,(HL) ; Load C with port address
BIT 0,A ; Check bit 0, RX Char. Available INC HL ; Go to Data
JR Z,READ ; If nothing, check again OTIR ; Output HL data, B times, to
IN A,(SIO_DA) ; Read SIO for one byte! ; port C
LD (HL),A ; Load A into HL JR IPORTS ; Jump to the next port if needed
INC HL ; Move HL to next location
DEC BC ; Decrease BC CTLTBL:
LD A,B ; Load A with B DB 09H ; 9 Lines or Bytes
OR C ; Or with C to check for zero DB SIO_CA ; Port Number
JR NZ,READ ; If not zero then read again DB 00011000B ; WR0: channel reset
RST 00 ; All Done..Restart TEC DB 00010100B ; WR0: select WR4 / Reset Int
DB 11000100B ; WR4: presc. 64x, 1 stop bit
; no parity
DB 00010011B ; WR0: select WR3 / Reset Int
The Register Table above is fully explained in the DB 11100001B ; WR3: 8 bits/RX char, auto enable
SIO Technical Manual. Only the Registers used in my ; RX enable
DB 00010101B ; WR0: select WR5 / Reset Int
code are displayed. Use the table to reference the DB 01101000B ; WR5: TX 8 bits, TX Enable
bits set in the code. DB 00010001B ; WR0: select WR1 / Reset Int
DB 00000000B ; WR1: disable all interrupts
DB 00H
References:
* SIO Technical Manual https://archive.org/details/Zilog_Z80-SIO_Technical_Manual
* Z80 Peripherals Manual http://z80.info/zip/um0081.pdf
* Circular Buffer on the TEC https://youtu.be/x_MR-b-TqW4

TEC Journal #1 12
 TECommunity Page

TEC Lovers from all around the world make up the TEC Community.

Craig Hart - Bio

After a few regular visits I broached the subject of a
Age: 51 job, and received 3 hours a Saturday working at 35
Location: Adelaide Rosewarne Ave. I was hooked. This evolved into a full
Profession: Senior IT Engineer time apprenticeship in 1988, doing just about
everything from kit assembly, phone orders, mail
My first exposure to TE was as a teenager in the mid runs, to design, testing, kit repair (from readers
1980's, with the 'cover projects' series which I saw in sending in things they couldn't get working), marking
the newsagents. I didn't buy any of them, but did the digital electronics courses, and later, working at
read them as much as I could standing in the the TE shop.
newsagents shop after school. at the time I was
interested in electronics and computers and had TEC wise, I came to TE at a time after Ken Stone had
some experience with software on an early 8 bit Z80 left, so I volunteered to be the in-house computer
based computer called the Sega SC-3000, and guru of sorts. I burned ROMs by day and programmed
making Dick Smith Funway kits. by night. TE used an ancient Z80 development board
called the MicroProfessor-1 to burn all ROMs, as it
I first met the TEC around 1985, thanks to a TE was considered more trustworthy than the in-house
magazine - possibly issue 13 or 14, which I saw in the design! Myself and TE staffer Paul set up a 286 with a
local jewellers shop - who sold a few kits on desktop publishing program Ventura Publisher that
consignment at the time. I saved my pennies and issue 15 was produced on. I worked closely with Jim
purchased a bare TEC-1B PCB (White on Red batch!) on finishing JMON and issue 15, for which I wrote the
by mail order, then proceeded to buy parts as pocket article to go with the speech module, did most of the
money allowed, a little every few weeks. I eventually artwork, diagrams and lots of other small jobs.
got the TEC going without keyboard buttons or 7-seg
displays, but the start-up beep was very rewarding - I also dabbled in the Microcomp and model railway
and it worked first go. computer, but the TEC was where all the focus was.

With time the TEC got finished and I religiously One TEC peripheral design never made it to market.
explored all the magazines had to offer. I purchased It was called the MEGA-SIGN and was a 7-seg display
an SPO256 speech chip from Tandy in a clearance made of incandescent light bulbs - 4 or 5 to a
sale and built the interface, eventually succeeding to segment. The PCB was laid out such that modules
make a working design - my first ever scratch could be stacked horizontally or vertically with
prototype. connectors at each edge that lined up. Hence, only
one cable was needed. It loaded the Z80 bus so
By late 1986 I was looking for a job and TE was much that each board had a bus buffer chip on board
actually only one suburb away from my childhood - 74LS245 or similar. A PCB run was made but the kit
home of Mentone, so I dutifully packed my precious never saw the light of day.
TEC and veroboard speech module into the car, and
talked dad into driving me up. I met Colin and Another TEC project that never really got going, was a
showed him my work (after 45 minutes typing the video adaptor for CRT displays/televisions. I never
opcodes in by hand); he was amazed and impressed saw it, as it was worked on before my time/externally;
at what I had created. He gifted me a speech module it was effectively cancelled as it was too complex
PCB which TE had developed independently; the and costly - far more complex than the TEC itself
designs were virtually identical, being basically a (30+ chips) - and had rather poor quality output.
'straight off the datasheet' design.

Cont...

TEC Journal #1 13
I was interested in CAD and helped TE move into because obvious that TE was in decline and that
'modern' PCB design with a Roland plotter and Protel Issue 16 was unlikely to ever start (much less get
Autotrax, with external help from Ken who by then completed), Jim moved on to selling his 'Jim’s
had returned to TE as a sort of contractor, to take Package' and ‘TEC times’ newsletter instead.
photos and get out his second model railways book.
A number of small, simple designs (The GNAT FM bug Eventually Jim produced some additional projects
being perhaps the first in-house board) made it to e.g. DAT-2 and 16k NVR but that was after my time at
CAD but I decided to teach myself Protel properly by TE. These were the final ‘original run’ products for the
converting the TEC to CAD. Hence, the TEC-1C was TEC, as far as I am aware.
born, complete with JMON ready mod and other
design revisions. By about 1990, Colin's focus had switched to FM
bugs, phone tapping devices and bug detectors, and
Issue 15 was really the pinnacle of my time at TE - the TE shop. The TEC was lost by the wayside.
one that was worked on quite hard by almost every Manufacturing bugging was devices highly profitable
staff member, for over 12 months. The move to a PC but it was also legally dubious to do so. An article in
and CAD were big leaps and there were issues. the Age newspaper tipped of the Federal Police and
Ventura was unstable and the computer was barely TE was raided. As far as I know, the ensuring legal
powerful enough to handle the page complexity of a outfall eventually ended the business, not to mention
TE magazine. Jim took up residence at TE for several the broader general decline of electronics as a viable
months to see the DAT board and JMON articles industry in Australia.
through to completion. Spending time with Jim
testing, debugging, documenting etc. was very Having left TE, I moved into computers and away
enjoyable and I learned a great deal, especially some from electronics, although I did CRT monitor, PC
of the optimisations to fit JMON into 2k. power supply repairs and other electronics work for
many years. My TECs got set aside and eventually
And then, there was Peter Crowcroft. Peter somehow lost in one or more house moves.
found his way into TE around the time Issue 15 was
reaching readiness for printing, supposedly as Blast forward to 2019, where I discovered the vintage
business development manager tasked with helping computer forums on Facebook. Jim Robertson
TE offshore some parts of the business. Kit happened to contact me via the forums, and lo and
production, magazine printing, component sourcing behold he was looking for a password for a ZIP file of
and the like was supposed to be moved to China source code from 1990 that he created in order to
allowing TE to get on with design work. In reality, keep it out of Peter Crowcroft's hands. By no small
Peter learned all he could about the business, then at miracle, I got the password recovered and for the first
short notice left, returned to his adopted Hong Kong, time in 29 years, we viewed code Jim had written all
and started kits-r-us. Out of kits-r-us came the SC- those years earlier.
1, an obvious evolution of the TEC sharing much
commonality of design, but with some modernisation I was then introduced to the TEC-1 Facebook group
to use more modern components. and had soon reacquainted myself with all things TEC
and SC-1.
I stayed at TE until roughly mid 1991. My last magazine
was the Six BD-679 Projects book; a book created Today I have two TECs and an SC-1 (both modified in
around the fact that Colin purchased 10,000 BD- various ways), and a bit of a passion for all that was,
679s at a distributor clearance sale for something as well as all that could be. The TEC Facebook group
like 5 cents each. The book was created solely to sell has been an amazing resource, and I'm thrilled to see
this inventory at a profit!! By 1991, Issue 15 was out the little machine I had a hand in 30-something years
and the initial sales surge been and gone, so there ago, still a success today.
was preliminary talk of Issue 16 - Jim had ideas about
releasing his utilities ROM, commented JMON
disassembly and more in Issue 16 - however when it

Baud Delay

EDITORS NOTE: To calculator the Baud delay, just use this formula: T-states = Clock Speed / Baud Rate For
instance if the CPU clock is 4MHz and the desired Baud is 4800, the number of T-states is 4MHz/4800=833.
The code that receives/sends one Bit must take 833 T-States to complete. Set the Baud delay to pad out the
routine to achieve this. See http://www.overtakenbyevents.com/tstates/ to help with T-state calculations.

TEC Journal #1 14
Presenting the SPI2C, a simple I/O interface and supporting software for interfacing with
modern peripherals.

By Craig Hart
and SPI bus protocols at the most active at a time. Each SPI device
One of the limitations of the TEC basic level. Full source code is has its own dedicated SS pin. The
platform is a lack of 'usable' I/O to available via Github under an open MOSI, MISO and SCLK lines are
communicate with the outside source license, as are the PCB files. wired in parallel and shared by all
world. TE Issue 14 brought us the I/O devices.
This approach is far more
board, however this design was a educational than just ‘talking to a This is where things start to deviate
very simple parallel style interface smart controller chip’ or calling a from the familiar TEC world.
where each I/O pin was either a software library you don’t have the
fixed input or output. The MISO pin is normally held in tri-
source code to.
state condition by all devices
Many modern chips today tend to (nobody is outputting any logic
communicate using bidirectional, level onto the bus). This is an input
SPI is a very simple synchronous
serial based signalling protocols – pin, so the SPI2C isn’t outputting
serial bus. It has a clock(SCLK) line,
that is, one or two pins are used to anything either; therefore a pull-up
a chip select(SS) line, and two data
transmit and receive data in a serial resistor is supplied to hold the bus
lines read(MISO) and write(MOSI).
form. Until now, these devices were at a logic 1 when idle.
not compatible with the TEC-1 or
SC-1. Only when a slave device is actively
sending data is the pin not tri-
SPI2C implements the two most stated; the SPI standard says this
common interfaces found across a pin is active LOW, so an SPI slave
large range of modern peripherals; Don’t be put off by the unfamiliar
can pull this pin low to transmit
firstly the SPI or Serial Peripheral labels, just mentally substitute (‘In’
data.
Interface bus, and secondly the I2C or ‘read’ for MISO, and ‘Out’ or
(pronounced I squared C or simply ‘write’ for MOSI). Theoretically, an unlimited number
I to C) bus. of SPI devices can share a single
In the above image, the TEC plays
bus, however there are practical
the role of Master, and our
limits to the number of devices; our
peripheral device is the Slave.
In the spirit of TE learning, we have board offers up to 6 Chip Select
not simply dumped a clever When we say the bus is lines; hence we can support up to 6
custom chip onto the Z80 bus. synchronous, we simply mean it devices in the basic design.
Instead, the SPI2C introduces a new has a clock(SCLK) line that dictates
Some slightly non-standard SPI bus
design building block for the TEC – bus timing.
devices also have extra control pins
a bidirectional IO pin. That is a
Data is considered valid when (and for various tasks such as Reset,
single pin that can both read and
only when) the state of the SCLK Backlight enable, mode selection or
write data under software control.
line changes. Our code can be as other custom functions. We can
We have built our interfaces using fast or slow as we please and it easily support these types of
easy to understand 74xxx family does not matter what frequency devices by simply adding extra
TTL logic chips. In this way the the Z80 is running at, or if interrupts control pins. The SPI2C provides
entire operation of the design can are occurring at the same time. the most common signals.
be understood and followed.
The SS line works just like the Chip
Of course, any hardware is only as Select (CS) line we are all familiar
good as the software it comes with, with – allowing multiple SPI slave Duinotech XC-3714: an SPI bus based 8
and so we are providing supporting devices to be connected to the Digit 7-seg display is available for
software that implements the I2C bus, but only one device can be around $10 from Jaycar etc.
 around’ every 16 addresses, so This is important because different
The I2C bus is a similar yet more ports 40h, 50h, 60h and 70h all chips are used for the read and
advanced version of SPI. With I2C, access the same device. write functions, so they need to be
the whole bus is reduced to just selected individually based on
The reason for this, is that the
two wires – clock(SCL) and whether the Z80 is executing an IN
74HC138 just doesn’t have enough
data(SDA). or OUT instruction (IOread or
pins to fully decode just one I/O
IOwrite cycle).
port. The Z80 has plenty of IO port
space so we don’t really care about
the overlap.
The 74HC374 is responsible for the
SC-1 write side of the SPI bus.
The SPI2C is designed to ‘plug in’ to
The bus is also synchronous in The SPI_IOWR signal from the
the SC1’s Expansion connector with
nature just like SPI, however a very 74HC32 enables this chip only
no further modifications.
clever signalling protocol and some when data is written to the SPI port
smart hardware design is used to
eliminate the other control wires
completely. Both the clock and
data lines use the same active-low-
tristate hardware approach as SPI.

Chip select is integrated within the

bus protocol (each I2C device has
a unique 7-bit ‘address’ on the I2C
bus), hence the SDA pin performs 3
functions - data in, data out and
device select.

SPI offloads all the hard work to

software, allowing the hardware to
be as simple as possible.

The hardware design can be broken

SPI2C Circuit Diagram
down into several sections, as TEC-1 – and all 8 bits are latched by this
follows. The 74HC138 chip should be chip.
omitted entirely if you wish to use
the TEC’s built in IO ports e.g. ports
Reading from SPI devices is
The 74HC138 address decoder is 6 and 7.
performed by Gate 4 of the
functionally similar to the TECs own Omit the 74HC138 and connect the 74HC125, and simply gates the
74LS138s – except it decodes the I2C_SEL and SPI_SEL pins to the MISO pin onto the Z80 data bus
IO address range 40h to 7Fh. Note TEC’s IO port select pins 6 and 7 during a read cycle. The SPI bus’s
that we ignore address line A0, so instead. MISO pin is held in tri-state (high
every odd port is a duplicate of the impedance) mode whenever data
preceding even-numbered port. is not actively being sent by a slave
This means port 40h and 41h are an device, hence this pin is shared by
equivalent pair as far as software is The purpose of the 74HC32 is to all SPI slave devices.
concerned (…and port pairs 42h & take our port select signals from The 4k7 pull up resistor holds the
43h, 44h and 45h, etc.) so code can the 74HC138 (or TEC) and combine MISO line high when idle, hence our
address either port and read or them with the Z80’s RD and WR software will read a ‘1’ whenever the
write the same device. signals, to create separate IORead bus is idle. SPI devices only ever
and IOWrite signals. output a logic 0 to the MISO pin
Also, since we are ignoring address
lines A4 and A5, the I/O ports ‘wrap (*never* a logic 1!!)
Reads are gated onto the Z80 data Input is the same as for SPI – the Expansion port and the Z80 CPU.
bus to bit D3 by the 74HC125 in other 74HC125 gate simply gates Some soldering to the TEC PCB will
response to a decoded IORead the SDA line directly onto the Z80 be required to pick up all the
cycle. data bus during an IORead. required signals.

The observant amongst you would Alternatively, use Craig Jones’ TEC
have noted – to read valid data CPU riser board to create an SC-1
The I2C controller is a little more
from the SDA pin, we need to first style expansion bus connector.
complex than SPI. I2C pins are
output a ‘1’ to the SDA pin, in order
active low; therefore held high by
to set it to tri-state mode;
pull-up resistors (devices tri-state)
otherwise a bus short
whenever idle.
could occur.
We need to create an SDA pin that
The Z80 reset line sets the
supports the following abilities:
74HC74 flipflop to a logic 1
a) Be at logic 1 when idle so as to ensure the I2C bus
b) Output a logic 0 or 1 during our is tri-stated at power up.
writes
c) Read an input 0 or 1 state from a Our software should also
slave device (and not our own
ensure a bus clash never
previous output) during reads
d) Be independent of the SCL pin occurs.

We can’t simply use a 74HC374 SCL pin

here as it is not bidirectional and The SCL pin works the
other 74HC24x family chips won’t same way as the SDA pin,
suit either as we can’t address pins except it is only ever
individually (e.g. have one pin as an driven as an output, so we
output at the same time another don’t need a ‘125 gate on The SPI2C PCB
pin is set as an input). this pin, and any data read
of this bit will be undefined.
To overcome these limitations, we
U1 74HC138 (SC-1 only)
have created two independent
U2 74HC32
one-bit latches using a 74HC74 flip Any seasoned TEC builder should U3 74HC74
flop and 2 gates from the 74HC125 find assembly straight forward; U4 74HC125
as our tri-state buffers. simply load the parts onto the PCB U5 74HC374
as shown, the order isn’t critical.
SDA pin
Firstly, the 74HC74 latches our However, first decide if you will be C1 100nF
write of bit D0. building the SC1 version or the TEC C2 100nF
version.
If our write is a logic 1, the I2C bus is R1 4.7k
placed into tri-state as the 7HC74’s R2 4.7k
output latches this value and the R3 4.7k
logic 1 sets the HC125’s output to The SC1 version is easy – fill all
tri-state mode. Since the slave components as shown. The board is
J1 40 pin IDC connector
devices are also idle/tri-state, and designed to plug directly to the
J2 4 pin SIL header
the 4k7 resistor pulls the bus up to expansion header on the SC-1.
J3 7 pin SIL header
logic 1. J4-J9 single pin header
If we write a logic 0, this is latched Omit the 74HC138 and instead
by the 74HC74 and then a 0 is IC Sockets
connect I2C_SEL and SPI_SEL pins
gated onto the bus by the 74HC125. 3 14 pin
to the TEC’s IO port select pins for
1 16 pin
Note the input of the 74HC125 is ports 6 and 7.
1 20 pin
wired to ground – hence we can As the board uses a 40 pin Z80 bus
only ever output a 0 to the I2C bus, header you will also need to pick up 1 SPI2C PCB
never a 1. various signals from the TEC 1 40 pin IDC Cable
 MAX7219 displays as well as on the Of course you can type the HEX
The key to this project is the really internal 7-seg displays so you can bytes in by hand and write your
the software; the hardware itself check it is working correctly. code with pen, paper and opcode
simply handles the electrical lookup tables the way TE did, but
Obviously this program introduces
signals, and all the smart control is you quickly realise this is not
the I2C bus control code, however it
in the software alone. practical when developing
is a much more ‘complete’ program
software.
The latest versions of all the that includes several utility routines
software as well as schematic, PCB such as display scanning, keyboard I strongly suggest and encourage
design, supporting datasheets etc. polling. The program contains use of a modern development
are available at my GitHub site conditional assembly directives to environment, so you can focus on
https://github.com/1971Merlin/SPI2C assemble for either the SC-1 or writing the software and not
TEC-1 hardware platforms. mundane tasks like looking up
A detailed line by line description of opcodes.
the software is beyond this article,
however a quick review as follows: There are numerous development
This program uses a cheap 84x48
platforms such as Oshonsoft.com
mono LCD display, also known as a
and asm80.com available online.
‘Nokia 5110” display driven form the
This program tests basic SPI bus SPI bus. Once again this is a Jaycar
functionality, using a MAX7219 8 part XC4616 and is less than $20. Having introduced some basic
digit 7-segment display module
John Conway’s Game of Life is routines and the ‘raw’ code, well the
such as the Duinotech XC-3714
presented on the LCD, and is a sky is the limit in terms of
which is readily available from
good example of a practical use for possibilities.
Jaycar for around $10.
the system as a whole. Just about any SPI or I2C bus device
The program simply scrolls a
can be used – and my goal is to
display buffer in RAM across the
build over time a library of
displays, but it demonstrates
The code is written and assembled subroutines to support numerous
several code blocks in doing so –
into the final binary using Telemark devices.
initializing and writing to the SPI bus,
TASM – the table based assembler,
as well as managing a simple Any code will of course be
which is available from
display buffer. published on Github as it is
https://www.ticalc.org/archives/file developed. And I encourage
As a side note, it’s mazing that you
s/fileinfo/250/25051.html readers to become familiar with the
can buy EIGHT 7-seg displays, on a
various TEC Github resources
PCB, assembled, with a controller To compile the code, simply run
available in the community.
chip, pin headers etc. for just ten tasm -80 -g0 filename.asm from a
dollars. To build this yourself from command prompt, and it will output Beyond this, I encourage and
discrete parts would be many an .obj file in intel hex, and a .lst file welcome you, dear reader, to start
times more expensive – hence the which is a text file showing the experimenting. Feel free to provide
value in using these cheap modules commented listing and the hex feedback, bug fixes and new
and leveraging the wealth of bytes to be keyed in. features via Github and the TEC-1
products already out there flooding Facebook group, and lets see what
I personally take TASM generated
the Arduino market. we can grow from here.
.obj file and use the the SC-1’s serial
upload feature (Fn 1) to upload the I look forward to receiving your
code from a PC at 4800 baud. input.
This program builds on spi_7segs,
adding support for an I2C bus based
All source code and examples are available from my Github
DS1307 Real Time Clock chip –
again we are using the Duniotech
XC4450 from Jaycar.
https://github.com/1971Merlin/SPI2C
The program implements a simple All my software is free, open source and GPL licensed.
clock reading from the DS1307 and
displaying the time/date on the
Serial Routines for the TEC
This article was published in the "TEC Times" March 1990. It is the last known
publication for the TEC. The Bit Bang code can still work on the TEC and it
shows another way to serialise data.
By Jim Robertson

RECEIVER
;Constants
START_ADR: EQU 0898H ;Start address
This is the routine I use when I wish to download a file END_ADR: EQU 089AH ;End address
from the IBM. It's a simple routine that converts a IN_PORT: EQU 03H ;Input port
OUT_PORT: EQU 01H ;Output port
serial stream into bytes and stores them in RAM
starting at the address provided at 0x0898. The ORG 0900H
routine also has an end address to allow a maximum
; --------------------
file length. This is in case something goes wrong ; Serial Input Routine
with the data transfer. Anything important can be ; --------------------
protected by placing it above the end address. ; Transmit bit is BIT 7 on the selected port
INPUT:
;Start of routine
No hand-shaking is needed as the TEC can cope with LD HL,(START_ADR) ;Load HL with start addr.
the speed of the data stream. It is up to you to RECLOOP: ;Get a byte and increase HL until HL=BC
CALL GET_BYTE ;Call Get Byte routine
ensure the TEC is ready before you send the data. LD BC,(END_ADR) ;Load BC with end address
The serial input is bit 0 of PORT 3. The DAT BOARD OR A ;Clear carry flag
has provision for 2 diodes and a resistor at this input PUSH HL ;Save start address
SBC HL,BC ;Get length of transfer
to clip an incoming RS232 signal. In the RS232 format, POP HL ;Restore HL
a logic 1 is represented by a negative voltage while a JR C,RECLOOP ;More data to receive
logic 0 is a positive voltage. The clipper on the DAT RST 00H ;End

BOARD changes an RS232 logic 0 (positive voltage) GET_BYTE:

into a digital logic 1 while an RS232 logic 1 is clipped ;Receive a byte from serial port
to zero volts and becomes a digital logic 0. IN A,(IN_PORT) ;Check bit 7 on in port
RLCA ;Move into carry
JR NC,GET_BYTE ;Not sent, keep looking
This means that the inputted data must be inverted LD B,40H ;Load B with half baud
back into its true form. This is done with the CPL ;delay
L1: DJNZ L1 ;Delay
instruction at 0x092C. The format of the data is as LD E,00H ;Load E with 0
follows: ;the receive byte
* 2400 BAUD LD C,08H ;Eight bits to receive
GET_BITS:
* NO PARITY IN A,(IN_PORT) ;Get bit 7 on input port
* 8 BITS RLCA ;Move into carry
* STOP BITS OPTIONAL RR E ;Rotate Carry bit into E
;from the right
* TEC SPEED: 3.58 Mhz / 2 LD B,39H ;Load B with baud delay
L2: DJNZ L2 ;Delay
DEC C ;Decrease next bit count
IBM SOFTWARE JR NZ,GET_BITS ;Still more bits
LD A,E ;Save received byte in A
The software I used for receiving the serial is CPL ;Invert bits
PROCOMM. It is a public domain program and can LD (HL),A ;Store in memory
be purchased from the Talking Electronics Shop. Cat INC HL ;Move HL to next address
RET ;Exit
S-449. The protocol to use is ASCII.

The sending software poses a few difficulties. One big problem is that some packages won't send the 1A
character. Actually, I believe the problem is in the DOS serial interrupt and if the software uses it then it won't
send the 1A character.

It is rare that I send anything back to the TEC and when I do, it's with a serial routine Craig Hart wrote and
probably won't work with all computers as it directly manipulates the hardware; not a recommended practice.
It is up to you to experiment around and find something that works.

I would like to hear from anyone who has found or written a good sending routine that doesn't have the 1A
character problem.

Hardware wise, the CTS must be taken high before the IBM will send the data. This means that the IBM to TEC
link consists of three wires: the ground, the serial data line and +5v.

Only ground and the serial data are required for the TEC to IBM link.

TEC Journal #1 19
SERIAL OUTPUT ROUTINE OUTPUT:
This is the complement routine of the serial ;Start of routine
receiver. It will send serial data through the TEC LD HL,(START_ADR) ;Load HL with start addr.
SENDLOOP: ;Send a byte and increase HL until HL=BC
speaker bit. The data is taken from the latch side of CALL SEND_BYTE ;Call Send Byte routine
the base resistor of the transistor inverter and LD BC,(END_ADR) ;Load BC with end address
inputted directly to an RS232 Rx input or the DAT OR A ;Clear carry flag
PUSH HL ;Save start address
BOARD serial input. SBC HL,BC ;Get length of transfer
POP HL ;Restore HL
Strictly speaking the data stream is not RS232 JR C,SENDLOOP ;More data to receive
RST 00H ;End
compatible but in practice it works ok, although the
occasional error may creep in. SEND_BYTE:
;Send a byte to serial port
LD A,80H ;Send start bit
Oh yes, before sending data, the key press beep OUT (OUT_PORT),A ;Output to port
must be turned off. To do this, place 0xFF at 0x0822 CALL DELAY ;Delay for baud rate
and put 0xAA at 0x08FF. LD A,(HL) ;Get byte from memory
INC HL ;Move to next byte
LD B,08H ;Load B with bits to send
The serial sender uses the same start and end SEND_BITS:
buffers as the receive described above with the RRCA ;Put bit in bit 7
XOR 80H ;Flip bit
same speed etc. Two stop bits are sent as this OUT (OUT_PORT),A ;Output to port
provides compatibility with all serial systems. CALL DELAY ;Delay for baud rate
DJNZ SEND_BITS ;Send next bit
XOR A ;Zero A
*This article is a reproduction from the 'TEC Times' OUT (OUT_PORT),A ;Send Stop bit x 2
published March 1990. CALL DELAY ;Call first delay
DELAY:
;Delay for baud rate
PUSH BC ;Save BC
LD B,36H ;Load B with delay
L3: DJNZ L3 ;Delay
POP BC ;Restore BC
RET ;Exit

Image reproduced from TE Magazine Issue 15

TEC Journal #1 20