IEICE Electronics Express, Vol.16, No.

19, 1–6

LETTER
An ultra-low leakage energy efficient level shifter with wide
conversion range
Heng You1,2, Jia Yuan1, Weidi Tang3, Yi Yu1,2, Shushan Qiao1,2a), and Yong Hei1

Abstract An ultra-low leakage energy efficient level shifter that can

convert extremely low input voltage into the supply voltage level is
presented in this paper. In order to reduce the leakage power dissipation,
the super-cut-off mechanism and MTCMOS technique are utilized in the
proposed structure. At the same time, a positive feedback circuit is inserted
to avoid the loss of performance. Post-layout simulation results in a 55-nm
MTCMOS process demonstrate that for the voltage level conversion from
0.3 V to 1.2 V, the proposed level shifter exhibits a propagation delay of
70.77 ns and an energy per transition of 89.55 fJ for input frequency of
1 MHz. Meanwhile, the static power of the proposed level shifter is as low
as 27.82 pW. The proposed level shifter only occupies 7.79 um2, which
demonstrates prominent area efficiency. (a) (b)
Keywords: level shifter, leakage power reduction, wide conversion Fig. 1. Schematic of the conventional level shifters: (a) cross-coupled
range, sub-threshold operation, MTCMOS based level shifter; (b) current-mirror based level shifter.
Classification: Integrated circuits

1. Introduction pull-down networks. Once the VDDL drops to sub-thresh-

old region, the pull-down transistors would be too weak to
In recent years, power consumption becomes the critical overcome the strength of the pull-up transistors. Although
limitation in an increasing number of applications [1, 2, 3], upsizing the pull-down transistors could increase the pull-
and one of the most effective ways to reduce power con- down strength, previous works [14, 15, 16] show that the
sumption is lowing the power supply voltage [4, 5, 6, 7]. required NMOS-to-PMOS ratio grows exponentially in
Hence, voltage scaling technique has been widely adopted the sub-threshold region, which is unacceptable. Fig. 1(b)
in low-power design [8, 9, 10, 11]. Aggressive voltage shows the other conventional level shifter based on current-
scaling into the sub-threshold region would provide better mirror PMOS devices. It utilizes a current-mirror instead
energy efficiency. But when the voltage scaling technique is of the cross-coupled architecture to avoid the contention
utilized for sub/near-threshold operation, the sub-to-supra between pull-up and pull-down networks. Unfortunately,
threshold level conversion is usually unavoidable. There- when the voltage of IN is high, the large standby current
fore, a wide range energy efficient level shifter is highly passing through MP1 and MN1 would result in large
demanded for voltage scaling systems. Once the system standby power.
operates at a low speed such as battery-less processors To realize robust conversions between large supply
[12, 13], the leakage power becomes the major concern. voltage differences, several level shifters have been pro-
Fig. 1(a) shows one of the conventional level shifters posed [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
which uses cross-coupled PMOS devices to achieve low- 29, 30, 31, 32]. In order to balance the strength of the
to-high voltage conversion. The cross-coupled based level pull-up and pull-down networks in cross-coupled based
shifter consists of a half latch structure and consumes near- level shifter, in [18, 26], diode current limiters are inserted
zero leakage current owing to its complementary pull-up in the pull-up networks to reduce the pull-up strength.
and pull-down networks. The major drawback of this kind Another way to reduce the strength of pull-up networks
of level shifter is the strong contention between pull-up and is to insert current generators in pull-up networks shown in
[23]. As for the large standby power of the current-mirror
1
Institute of Microelectronics of Chinese Academy of based level shifter, feedback circuits are usually inserted to
Sciences, Chaoyang, Beijing 100029, China cut-off the static on-current [16, 21, 22, 25, 28, 31].
2
University of Chinese Academy of Sciences, Shijingshan,
The above-mentioned level shifters could provide
Beijing 100049, China
3 robust conversions in sub-threshold regions, but the static
University of Science and Technology of China, Shushan,
Anhui 230027, China power is still hundreds or thousands pW, which is a huge
a) qiaoshushan@ime.ac.cn expense in battery-less systems. In this paper, an ultra-low
DOI: 10.1587/elex.16.20190507
leakage level shifter with wide conversion range is pre-
Received August 6, 2019 sented. With the employment of super-cut-off mechanism
Accepted August 29, 2019
Publicized September 9, 2019
and MTCMOS, the static power decreases to 27.82 pW for
Copyedited October 10, 2019 a 0.3 V to 1.2 V voltage conversion.

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Copyright © 2019 The Institute of Electronics, Information and Communication Engineers
 IEICE Electronics Express, Vol.16, No.19, 1–6

The rest of the paper is organized as follows: Section 2

describes the structure of the proposed level shifter.
Section 3 displays the simulation results and comparisons
with other state-of-the-art level shifters. Finally, Section 4
draws a conclusion.

2. Proposed level shifter

The proposed level shifter is shown in Fig. 2. The main

voltage conversion stage is cross-coupled based. Two
PMOS-diode current limiters (MP3, MP4) are inserted to
reduce the strength of the pull-up networks. As shown in
Fig. 3, if the PMOS-diode current limiters are not applied,
the pull-down networks are too weak to overcome the
strength of the pull-up transistors at VDDL ¼ 0:4 V. On
the contrary, the level shifter could work correctly even if Fig. 2. Schematic of proposed level shifter.
the VDDL is as low as 100 mV once the current limiters
are applied. To optimize the leakage and the delay of the
proposed level shifter, several strategies have been applied
to the proposed design.
In order to realize a wide conversion range, the
pull-down networks need to employ relatively large low
threshold NMOS transistors. As is well known that low
threshold transistors usually lead to significant leakage
power. Fig. 4 exhibits the leakage current of the minimum
size low threshold NMOS as a function of VGS at VDrain ¼ Fig. 3. Analysis on PMOS-diode current limiters.
1:2 V. From the leakage current result, it is obvious that
the transistor would be placed in a super-cut-off state
and consumes much less leakage power once the VGS is
reduced to below −100 mV. In our design, the input
inverter is split to two asymmetric inverters to drive
MN1 and MN2 independently, respectively, to improve
the speed of the level shifter. When the voltage of IN is
VSS, the weak PMOS MP5 will charge the node N5 to
VDDL, and the transistor MN1 will be placed in super-cut-
off state. Similarly, when the voltage of IN is VDDL, the
node N6 will be discharged to VSS through the weak
NMOS MN5, and the transistor MN2 will be placed in Fig. 4. Leakage current of the minimum size low threshold NMOS
super-cut-off state. As a result, the leakage power is greatly versus VGS at VDrain ¼ 1:2 V.
reduced. To remedy the loss of speed due to the stack
structure (MN1 and MN4), a small feedback transistor
MN3 is inserted, when the voltage of IN is VDDL, the
pull-down network will discharge the node N2 to below
VDDH, and the voltage of node N4 will gradually rise
to supra-threshold, then the feedback transistor MN3 will
significantly improve the strength of the pull-down net-
work, which will greatly speed up the conversion. As
shown in Fig. 5, the voltage of N2 can drop faster when
the feedback transistor MN3 is applied. As a result, the
Low to High conversion is speeded up.
The proposed level shifter is further optimized through Fig. 5. Analysis on the feedback transistor MN3.
the MTCMOS technique and sub-threshold device sizing.
To decrease the leakage power, the cross-coupled PMOS
MP1 and MP2 are implemented with HVT transistors. The N1 could charge to VDDH, but could not discharge to
PMOS-diode current limiters are implemented with LVT VSS. Similarly, the node N2 could discharge to VSS but
transistors because the voltage difference between node could not charge to VDDH. To optimize leakage power of
N2/N4 and VDDH will significantly influence the leakage the output inverter, the input of the inverter is split to two
power of MP2/MP1. With the employment of LVT tran- node N1 and N2 so that the inverter could cut-off no matter
sistors, the voltage difference could be greatly eliminated. the output is VDDH or VSS, meanwhile, HVT transistors
With the employment of PMOS current limiters, the node are employed.

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 IEICE Electronics Express, Vol.16, No.19, 1–6

The level shifter operates as follows: When the input IN voltage of 1.2 V and a temperature of 25°C. As discussed
changes from Low to High (VSS to VDDL), MN4 and in previous sections, the pull-down networks need to
MN1 are switched on and MN2 is switched off. The voltage overcome the strength of the PMOS transistors, thus,
of N2 begins to drop and MP2 is switched on. Then the the slow-NMOS fast-PMOS is the worst corner of the
voltage of N3 and N4 begins to rise and MP1 is switched off sub-to-supra threshold level shifter. Moreover, a 10%
gradually. As MP1 is switched off, the voltage of N1 and VDDH supply voltage increase (1.32 V) and a temperature
N2 is further reduced until the voltage of N2 falls to VSS. of −40°C are selected to further weaken the conversion.
As the voltage of node N4 could rise to supra-threshold Correspondingly, the best case includes fast-NMOS, slow-
quickly, the feedback transistor MN3 could speed up the PMOS, a 10% VDDH supply voltage reduction (1.08 V)
falling transition of N1 and N2. Finally, MP7 is switched on and a temperature of 125°C.
and MN6 is switched off, the voltage of OUT is charged to
VDDH quickly. When IN changes from High to Low 3.1 Conversion range
(VDDL to VSS), MN2 is switched on and MN1 is switched To investigate the conversion range of the proposed level
off. The voltage of N4 begins to drop and MP1 is switched shifter, several 500-iteration Monte Carlo simulations have
on. Then the voltage of N1 and N2 begins to rise and MP2 been performed at a 10% VDDH supply voltage increase
is switched off gradually. The voltage of N1 could rise to (1.32 V), a temperature of −40°C. The VDDL supply
VDDH as MN1 is off. Finally, MN6 is switched on and voltage is set to be between 0.1 v and 0.2 v with a step
MP7 is switched off, the voltage of OUT falls to VSS size of 0.01 v. The result shown in Fig. 8 illustrates that
quickly. Since MN1 and MN2 are switched on with differ- the proposed level shifter could operate at VDDL as low as
ent inputs, the connections of MN1 and MN2 are different. 0.12 V under extreme PVT corners.
MN2 adopts a pass-transistor structure to speed up the
falling transition. Fig. 6 shows the transient waveform of
the proposed level shifter in the detail.

Fig. 8. MC simulation waveform for 0.12 V to 1.2 V conversions.

Fig. 6. Transient waveform of the proposed level shifter.

3.2 Static power
The static power dissipation against VDDL is illustrated
in Fig. 9. When the VDDL scales down, the static power
decreases as expected. But the static power increases while
the VDDL scales down to 0.1 V, which is mainly due to
the fact that the super-cut-off mechanism is weakened
while the VGS is only −100 mV. The proposed level shifter
consumes 27.82 pW of static power for the voltage level
Fig. 7. Layout of the proposed level shifter. conversion from 0.3 V to 1.2 V at the typical case. This is
attributed to the employment of the super-cut-off mechan-
ism, the MTCMOS technique and the split output inverter
3. Simulation results and comparison as discussed in Section 2. Both MTCMOS technique and
split inverter are mainly used to decrease the voltage drop
In order to verify the performance of the proposed level of the internal node. The super-cut-off mechanism is used
shifter, the proposed level shifter has been simulated in to suppress leakage current of the LVT pull-down net-
a SMIC 55 nm MTCMOS technology. Fig. 7 shows the works. To evaluate the effect of each optimization strategy,
layout of the proposed level shifter with the core area as Table I shows the static power consumption of cross-
compact as 7.79 um2 (4:96 um  1:57 um). The following coupled based level shifters with different optimization
simulation results are based on post-layout analysis. Three strategies. The static power could be reduced to several
PVT corners should be determined with care for sub- hundred pW with MTCMOS technique and split inverter.
threshold level shifters. The typical case in our design When the super-cut-off mechanism is applied, the static
includes typical NMOS, typical PMOS, a VDDH supply power is further reduced to as low as 27.82 pW.

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 IEICE Electronics Express, Vol.16, No.19, 1–6

Table I. Static power of cross-coupled based level shifters with different

strategies. (0.3 V to 1.2 V voltage conversion)
Super cut-off
HVT- LVT-diode LVT-diode
Strategy No + LVT-diode
diode CL CL CL + SI
CL + SI
Static power
fail 1997.63 603.75 570.99 27.82
(pW)
Norm. --- 71.8 21.7 20.52 1

: CL = current limiter, SI = split inverter.

Fig. 11. Energy per transition at typical case as a function of VDDL.

decreases relatively slowly while the VDDL scales down.

But as the VDDL scales into the deep sub-threshold
regions, the energy per transition appears to rise. This is
duo to the exponentially increasing propagation delay,
which introduces enormous internal short-circuit power.
The optimized energy consumption is obtained between
0.5 V and 0.7 V. For a low supply voltage of 0.3 V, the
proposed level shifter achieves 89.55 fJ energy per transi-
tion in the typical case.
Fig. 9. Static power at typical case as a function of VDDL.

3.4 Comparison
In order to validate the benefits of the proposed level
shifter, a comparative analysis of the proposed level shifter
and some other state-of-the-art level shifters has been
performed. It can be seen in Table II that the proposed
level shifter has the smallest static power among recently
published designs. With the employment of the super-cut-
off mechanism and the MTCMOS technique, the proposed
level shifter consumes only 27.82 pW of static power, far
less than other level shifters. The energy per transition of
the proposed level shifter is similar to other level shifters
Fig. 10. Propagation delay as a function of VDDL. while the input signal frequency is 1 MHz. If the speed is
decreased to sub-KHz, which is widely used in battery-less
systems, the proposed level shifter could provide a much
3.3 Delay and energy per transition smaller energy per transition than other level shifters due to
The post-layout simulations have been performed for three the ultra-low static power. As for the propagation delay, to
PVT corners. The input signal frequency is 1 MHz with a remedy the loss of speed due to the stack structure, a small
transition time of 10 ns. In addition, the output capacitance feedback transistor is inserted. As a result, the propagation
is fixed at 0.1 pF. delay of the proposed level shifter is still comparable to
The propagation delay of the proposed level shifter other level shifters.
against the low supply voltage (VDDL) is shown in
Table II. Performance summary and comparison.
Fig. 10. The propagation delay grows exponentially with
VDDL scales into the sub-threshold regions. The observed Tech.
Min. Delay Energy/tran. Pstatic Area
phenomenon is more severe at the worst case. This is VDDL (ns) (fJ) (pW) (um2)
mainly because when transistors work in the weak inversion TCAS-II
65 nm 0.1
17.5 @
552 @ 0.3 V 20400 9.94
region, the operating current is dominated by the leakage 2010 [16] 0:3 ! 1:2
current, which is significantly affected by the temperature. TCAS-I
65 nm 0.2
162 @
136 @ 0.3 V 4056 16.8
At 300 mV, the worst case delay is 63 times higher than the 2014 [24] 0:3 ! 1:2
best case delay, and at 200 mV, the factor increases to 461. VLSI
90 nm 0.1
16.6 @
77 @ 0.2 V 8700 37.3
While the VDDL drops to 100 mV, the worst case delay 2015 [32] 0:2 ! 1
becomes 1168 times higher than the best case delay. Still, VLSI
40 nm 0.2
66.48 @
72.3 @ 0.3 V 88.4 11.92
the proposed level shifter operates accurately across the 2017 [19] 0:3 ! 1:1
simulated PVT corners. In addition, the delay of the pro- TCAS-II
65 nm 0.1
7.5 @ 123.8 @
2640 7.45
posed level shifter is 70.77 ns when VDDL is 0.3 V, which 2018 [25] 0:3 ! 1:2 0.3 V
is comparable to other state-of-the-art level shifters. This
55 nm 0.12
70.77 @ 89.55 @
27.82 7.79
Fig. 11 shows the energy per transition as a function work 0:3 ! 1:2 0.3 V

of VDDL at the typical case. The energy per transition : re-implemented in [25].

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4. Conclusion variation technique for dynamic voltage scaling and adaptive

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