SYSTEM VERILOG

DATA TYPES:
1.Structural data type:
 Wire – drives the values – wire is z
 Reg – stores the values - reg x unknown
2.Behavioural data type:
 Integer – variables hold values range -231 to 231-1 – integer a[0-64]
 Real – stores 64-bit quantities. – real float(1.43)
Integer and real both are initialized to zero at the start time of simulation.
 Time – 64-bit quantity, $time system task to hold simulation time.
- Time not supported for synthesis only used for simulation purpose.
 Parameter – represents constants, can modify at compilation time not at run time.
-can modify with defparam statement or in the module instance statement.
 Logic – improved version of reg, can be driven by continuous assignments, gates and
modules.
3.Two state data type:
Two state data types improve performance and memory usage over four state type.
 Bit – single bit – unsigned.
 Int – 32 bit integer – signed.
 Byte – 8bit – signed/unsigned.
 Short int – 16 bit – signed/unsigned.
 Long int – 64 bit – signed/unsigned.
4. Void data type – represents non existing data.
5. String data type – it represents variable size, it dynamically allocated array of bytes.- s=”Hello”.
6. Event – used to trigger, changes the value in variable.
7. User defined datatype – user can define a new type using typedef.
8. Enumeration data type – defines set of named values, contains list of names or one/more
variables.
9.Class data type:
Class is a collection of data and a set of sub routines that operate on that data. Data in a
class are referred as class properties, and its subroutines are called methods. Class is declared using
class and endclass keywords.
ARRAYS:
Array is the collection of variables of same data type.
1.Fixed size array – array size will be constant throughout the simulation. Default initialized to 0. -
Int a[6].
2. Packed array – values store in same memory location. Dimensions declare before the object
name.
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Bit [2:0] [7:0] array1

3.Unpacked array – values store in different locations. Dimensions declared after the object name.
Bit [2:0] array1 [7:0]
4. Dynamic array – one dimension of an unpacked array whose size can be set or changed at run
time. Space doesn’t exist until the array is created at run time.
Methods: New[] --> allocates the storage.
Size () --> returns the current size of dynamic array.
Delete() --> empties the array, resulting in a zero-sized array.
5. Associative array – Allocate the storage only when it is used. When the size of the collection is
unknown it it is better option. It stores entries in sparse matrix.
Associative Array Methods:
num() --> returns the number of entries in the associative array.
delete(index) --> removes the entry at the specified index.exa_array.delete(index).
exists(index) --> returns 1 if an element exists at the specified index else returns 0.
first(var) --> assigns the value of first index to the variable var.
last(var) --> assigns the value of last index to the variable var.
next(var) --> assigns the value of next index to the variable var.
prev(var) --> assigns the value of previous index to the variable var.

6. Queues – it is a variable size, ordered collection of homogenous elements. Like dynamic array ,
queues can grow and shrink, queues support adding and removing elements anywhere.
Queue Methods:
size() --> returns the number of items in the queue.
insert() --> inserts the given item at the specified index position.
delete() --> deletes the item at the specified index position.
push front() --> inserts the given element at the front of the queue.
pushback() --> inserts the given element at the end of the queue.
pop front() --> removes and returns the first element of the queue.
pop back() --> removes and returns the last element of the queue.

PROCEDURAL STATEMENTS AND CONTROL FLOW:

1.Blocking assignment – It blocks the execution of next statement until the completion of current
assignment execution. It executes statements in series order.
2. Non-blocking assignment - statements executes in parallel.
3. unique if - Evaluates all the conditions parallel. Simulator issue a run time error/warning in
following conditions: 1. More than one condition is true.
2. No condition is true /false if doesn’t have corresponding else.

4. priority if – It evaluates the all the conditions in sequential order. Simulator issue a run time
error/warning in the following conditions:
 SYSTEM VERILOG

1. No condition is true /false if doesn’t have corresponding else.

5. do while - It is a control flow statement that allows code to be executed repeatedly based on
given
condition.

6. while loop - It is a control flow statement that allows code to be executed repeatedly based on
given
condition. Execution of statements within the loop happens only if the condition is
true.

7. foreach loop - It specifies iteration over the elements of the array. Loop variable is considered
based on elements of an array and no.of loop variable must match the no.of
dimensions of the array.

8. for loop – Enhanced for loop of Verilog.

1. declaration of loop variable within the for loop.
2. one or more initial declaration or assignment within the for loop.
3. one or more step assignment within the for loop.

9. repeat loop - It will execute the statements within the loop for loop variable number of times.

10. forever loop – It executes the statements inside the loop forever.

11. break – execution of break statement leads to end of the loop.

12. continue – execution of continue statement leads to skip the execution of statements followed
by continue and jumps to next loop.

13. event control – Any change in a variable or a net can be detected using the @ event control.

#* typecasting – converting one data type variable into another data type .

PROCESSES-FORK_JOIN:

1. fork-join – it will start the processes inside it parallelly and wait for the completion of all
processes.

2. fork-join any – it will be unblocked after the completion of any of the process.

3. fork-join none – fork block will be non-blocking. Processes inside the fork-join none block will be
started at the same time. Fork block will not wait for the completion of processes
inside the f-j-none.

4. wait fork - causes processes to block until the completion of all processes started from fork
blocks.
 SYSTEM VERILOG

5. disable fork – causes process to kill/terminate all the active processes started from fork blocks.

TASKS AND FUNCTIONS:

Tasks and functions provide a means of splitting code into small parts.

TASKS:
A task can contain a declaration of parameters, input, output, in out arguments, registers, events
and zero or more behavioural statements.
System Verilog task can be static or automatic: Static task share the same storage space for all task
calls. Automatic tasks allocate unique, stacked storage for each task call.

FUNCTIONS :
A Function can contain declarations of range, returned type, parameters, input arguments, registers
and events. A function without a range or return type declaration, returns a one-bit value.
Functions cannot contain any time-controlled statements, and they cannot enable tasks. Functions
can return only one value.
System Verilog function can be static or automatic. Static functions share the same storage space
for all task calls. Automatic functions allocate unique, stacked storage for each task call.

System Verilog provides below means for passing arguments to functions and tasks,
1.by value
2.by reference
3.by name
4.by position
also functions and tasks can have default argument values.

1.Argument pass by value – it works by copying each argument into the sub routine areas. if any
changes to arguments with in the subroutine, those changes will not be visible outside the
subroutine.

2. Argument pass by reference - reference to the original argument is passed to the subroutine. as
the argument with in subroutine is pointing to an original argument, any changes to the argument
with in subroutine will be visible outside. To indicate argument pass by reference, the argument
declaration is preceded by keyword ref.
Any modifications to the argument value in pass by reference can be avoided by using const
keyword before ref, any attempt in changing the argument value in subroutine will lead to
compilation error.
3. default argument value - default value can be specified to the arguments of subroutine. In the
subroutine call, arguments with default value can be omitted from the call. if any value is passed to
an argument with default value, then the new value will be considered.
 SYSTEM VERILOG

4. pass by name - In argument pass by name, arguments can be passed in any order by specifying
name of the subroutine argument.

CLASSES
A class is a user defined data type that includes data (class properties), functions and tasks that
operate on data. functions and tasks are called methods. classes allow objects to be dynamically
created, deleted, assigned, and accessed via object handles.
class properties and methods can be accessed only after creating the object.
class_1 = new();

1.this keyword - used to refer to class properties.

2. class constructs – the new function is called as class constructor. On calling the new() allocates
memory, returns the address to the class handle and initialize the variables to default value.
default value – 0 for 2 state variables.
X for 4 state variables.
3. static class properties – created by using keyword static. Static properties will be created once
and all the class objects will access the same.
4. static methods - same as static properties, static method can access only static properties of the
class and access to the non-static properties is illegal and lead to compilation error.
Note :: static class properties and methods can be used without creating an object of that type.
5. class assignment – object will be created only after doing new to an class handle. With the
assignment both the objects will point to the same memory. Any changes made with-respect to one
packet will reflect on other.
6. shallow copy - class properties were copied from pkt_1 to pkt_2 this is called as "shallow copy".
Shallow copy allocates the memory, copies the variable values and returns the memory handle. In
shallow copy All of the variables are copied across: integers, strings, instance handles, etc.

Note: Objects will not be copied, only their handles will be copied.

7. deep copy - Users has to write the copy method for deep copy. On calling the copy method, new
memory will be allocated new object is created and all the class properties will be copied to new
handle and new handle will be returned.

8. parameterised class - parameters are like constants local to that particular class. default values
can be overridden by passing a new set of parameters during instantiation. this is called parameter
overriding.
 SYSTEM VERILOG

9. classes inheritance - New classes can be created based on existing classes. A derived class by
default inherits the properties and methods of its parent or base class. the derived class may add
new properties and methods or modify the inherited properties and methods.
base class or parent class -> existing class.
derived class or child class -> New class.

Polymorphism - Polymorphism means many forms. Polymorphism in SystemVerilog provides an

ability to an object to take on many forms.

Method handle of super-class can be made to refer to the subclass method, this allows
polymorphism or different forms of the same method.

10. overriding class members - Base class or parent class properties and methods can
be overridden in the child class or extended class.

11. super keyword – used to refer to members of the parent class. by using super keyword parent
class method can be accessed from child class.
12. casting - Dynamic casts can be used to safely cast a super-class pointer (or reference) into a
pointer (or reference) to a subclass in a class hierarchy.
13. data hiding and encapsulation - The technique of hiding the data within the class and making it
available only through the methods, is known as encapsulation.
Local - External access to the class members can be avoided by declaring members as local.
Any violation could result in compilation error.
Accessing local variable outside the class ( Not allowed )
Accessing local variable within the class ( Allowed )
Protected - In some use cases it is requires to access the class members only by the derived class's,
this can be done by prefixing the class members with protected keyword. Any violation could result
in compilation error.
Accessing protected variable outside the class ( Not allowed ).
Accessing protected variable in the extended class ( allowed ).
14. Abstract classes and virtual methods - An abstract class is a class that is declared abstract by
specifying the class to be virtual. Abstract classes cannot be instantiated, but they can be
subclassed. Abstract class is used as prototype for the subclasses.
Abstract classes can also have virtual methods. Virtual methods are a basic polymorphic construct.
A virtual method overrides a method in all the base classes, whereas a normal method only
overrides a method in that class and its descendants.
15. scope resolution operator :: - it is used to specify an identifier defined within the scope of a
class. The scope resolution operator uniquely identifies a member of a particular class.
 SYSTEM VERILOG

16. classes extern methods - The extern qualifier indicates that the body of the method (its
implementation) is to be found outside the class declaration. Before the method name, class name
should be specified with class resolution operator to specify to which class the method corresponds
to. Definition of method can be written outside the body of class.
17. typedef classes - In some cases class variable needs to be declared before the class
declaration.in this type of situation typedef is used to provide a forward declaration of the class.

RANDOMIZATION AND DISABLING RANDOMIZATION

Random variable will get random value on randomization.

class variables can be declared random using the rand and randc type-modifier keywords.
following types can be declared as rand and randc,
 singular variables of any integral type
 arrays
 arrays size
 object handle's
1.rand - Variables declared with the rand keyword are standard random variables. Their values are
uniformly distributed over their range.
rand bit [3:0] addr;
addr is an 4-bit unsigned integer with a range of 0 to 15. on randomization this variable
shall be assigned any value in the range 0 to 15 with equal probability.

2. randc: random-cyclic - Variables declared with the randc keyword, their values doesn't repeat a
random value until every possible value has been assigned.
In order to randomize the object variables, need to call randomize() method.
object.randomize();

3. disabling random variables - The rand_mode() method can be used to disable the randomization
of variable declared with rand/randc.
Note:
1.By default rand_mode value for all the random variables will be 1.
2.after setting rand_mode(0) to any random variable, it will get randomized only after
rand_mode(1).

4.randomize() - The randomize() method is a virtual function that generates random values for all
the active random variables in the object.

5. Pre_randomize();post_randomize():
Every class contains built-in pre_randomize() and post_randomize() functions. on calling
randomize(), pre_randomize() and post_randomize() functions will get called before and after the
randomize call respectively.
 SYSTEM VERILOG

Users can override the pre_randomize() and post_randomize() in any classes.

pre_randomize - function can be used to set pre-conditions before the object randomization.
Post_randomization - function can be used to check perform post-conditions after the object
randomization.

constraint blocks - By writing constraints to an random variable, user can get specific value on
randomization. constraints to an random variable shall be written in constraint blocks.
Constraint blocks are class members, like tasks, functions, and variables. each constraint block will
have unique name within a class.
constraint addr_range { addr > 5; }

1. external constraint blocks - External constraints are Same like external class methods. constraint
blocks can be defined outside the class body, declaration should be with in class body.
2. constraint inheritance - As class members, constraints also will get inherited from parent class to
child class. in a child class, constraint blocks can be overridden by writing constraint block with
same name as in parent class.
3. inside operator - With inside operator, random variables will get values specified within the block
followed by inside operator. values within the inside block can be variable, constant or range.
constraint addr_range { addr inside {1,3,5,7,9}; }
constraint addr_range { addr inside {[5:10]}; }

4. weighted distribution - With dist operator, some values can be allocated more often to an
random variable.
The := operator assigns the specified weight to the item.
addr dist { 2 := 5, [10:12] := 8 };
addr = 2 , weight 5
The :/ operator assigns the specified weight to the item.
addr dist { 2 :/ 5, [10:12] :/ 8 };
addr = 2 , weight 5
addr = 10, weight 8/3
. implication (->) - The implication operator ( –> ) can be used to declaring conditional relations.
expression -> constraint
if the expression is true, then the constraints must be satisfied.
constraint address_range { (addr_range == "small") -> (addr < 8);}

5. if else - If the expression is true, all of the constraints in the first constraint/constraint-block must
be satisfied, otherwise all of the constraints in the optional else constraint/constraint-block must be
satisfied.
6. Iterative constraints – It allow arrayed variables to be constrained using loop variables and
indexing expressions.
constraint values { foreach ( addr[i] ) addr[i] inside {4,8,12,16}; }
 SYSTEM VERILOG

7. constraint modes - The constraint_mode() method can be used to disable any particular
constraint block. By default, constraint_mode value for all the constraint blocks will be
1.constraint_mode() can be used as follo:
addr_range.constraint_mode(0); //disable addr_range constraint

8. static constraints - A constraint block can be defined as static, by including static keyword in its
definition.
static constraint addr_range { addr > 5; }
Any mode change of static constraint will affect in all the objects of same class type.

9. inline constraints - Inline constraints allows to add constraints along with randomize call
statement. Constraints defined inside the class also considered along with the inline constraints.
pkt.randomize() with { addr == 8;};

10. functions in constraints - In some cases constraint can't be expressed in single line, function call
can be used to constraint a random variable.
constraint end_addr_c { end_addr == e_addr(start_addr); }
function bit [3:0] e_addr(bit [3:0] s_addr);
11. soft constraints - A soft constraint is the constraint on random variable, and it will be true
unless contradicted by another constraint. For any random variable, there should not be any
conflict between the constraint declared in parent class and child class or inline constraint,
for example, constraining a < 10 in parent class and
constraining a > 10 in child class or inline constraint.
conflicts in constraints leads to an randomization failure. this kind of problems can be avoided
using soft constraints.
constraint c_name { soft variable { condition }; }
12. Bidirectional constraints – System Verilog constraints solved bidirectionally, which means
constraints on all random variables will be solved parallel.
RANDOM SYSTEM FUNCTIONS
1.$urandom () - The system function $urandom provides a mechanism for generating
pseudorandom numbers. The function returns a new 32-bit random number each time it is called.
The number shall be unsigned
variable = $urandom(seed);
The seed is an optional argument that determines the sequence of random numbers generated.
The seed can be any integral expression.
 SYSTEM VERILOG

2. $random() - $random() is same as $urandom() but it generates signed numbers.

3. $urandom_range() - The $urandom_range() function returns an unsigned integer within a
specified range.
$urandom_range( int unsigned maxval, int unsigned minval = 0 );
addr1 = $urandom_range(30,20);

SYNCHRONIZATION AND COMMUNIACTION MECHANISAMS

The process through which processes communicate/synchronizes each other is known as Inter
Process Communication/synchronization.
1.Semaphore:
semaphores are used for shared resources asses control.
Imagine a situation where two processes try to access a shared memory area where one process
tries to write to a memory location when the other process is trying to read. this leads to an
unexpected results.
Conceptually, a semaphore is a bucket. When a semaphore is allocated, it contains a fixed number
of keys is created.

The process which wants to access the shared resource can first acquire the key/keys, once the
process finishes the access to resource, key/keys shall be put back to the bucket.

If any other process tries to access the same resource, it must wait until a sufficient number of keys
is returned to the bucket.

creating a semaphore is:

semaphore semaphore_name;
Semaphore is a built-in class that provides the following methods:
 new() - Create a semaphore with a specified number of keys - the default number of keys is
‘0’
 get() - Obtain one or more keys from the bucket - The default number of keys is 1.
 put() - Return one or more keys into the bucket - The default number of keys is 1.
 try_get() - Try to obtain one or more keys without blocking - The default number of keys is
1.

2. mailbox:
A mailbox is a communication mechanism that allows messages to be exchanged between
processes.
 SYSTEM VERILOG

The process which wants to talk to another process posts the message to mailbox , which stores the
messages temporarily in a system defined memory object, to pass it to the desired process.
Mailboxes are created as having either a bounded and unbounded queue size.

A bounded mailbox becomes full when it contains the bounded number of messages. A process
that attempts to place a message into a full mailbox shall be suspended until enough space
becomes available in the mailbox queue. Unbounded mailboxes are with unlimited size.

There are two types of mailboxes,

1. Generic Mailbox (type-less mailbox)
The default mailbox is type-less, that is, a single mailbox can send and receive any type of data.
mailbox mailbox_name;

2. Parameterized mailbox (mailbox with particular type)

mailbox is used to transfer a particular type of data.
mailbox#(type) mailbox_name;

Mailbox is a built-in class that provides the following methods:

Below Methods are applicable for both Generic and Parameterized mailboxes
new(); - Create a mailbox
put(); - Place a message in a mailbox
try_put(); - Try to place a message in a mailbox without blocking
get(); or peek(); - Retrieve a message from a mailbox
try_get(); or try_peek(); - Try to retrieve a message from a mailbox without blocking
num(); - Returns the number of messages in the mailbox

3. Event
Events are static objects useful for synchronization between the process.

One process will trigger the event, and the other processes can wait for an event to be triggered.
Events are triggered using -> operator or ->> operator
wait for a event to be triggered using @ operator or wait() construct.
System Verilog events act as handles to synchronization queues, thus, they can be passed as
arguments to tasks, and they can be assigned to one another or compared.

1. -> operator - Named events are triggered via the -> operator. Triggering an event unblocks all
processes currently waiting on that event.
2. ->> operator - Nonblocking events are triggered using the ->> operator.
3. @ operator - wait for an event to be triggered is via the event control operator, @. The @
operator blocks the calling process until the given event is triggered.
NOTE: If the trigger executes first, then the waiting process remains blocked.
4. Wait operator - If the event triggering and waiting for event trigger with @ operator happens at
the same time, @ operator may miss to detect the event trigger.
Where as wait(); construct will detect the event triggering.
 SYSTEM VERILOG

wait(event_name.triggered);
5. wait_order() - The wait_order construct is blocks the process until all of the specified events are
triggered in the given order (left to right). event trigger with out of order will not unblocks the
process.
Wait_order(a,b,c);
6. Merging events - When one event variable is assigned to another, the two become merged.
Thus, executing -> on either event variable affects processes waiting on either event variable.

4.PROGRAM-BLOCK:
The Program construct provides race-free interaction between the design and the testbench, all
elements declared within the program will get executed in Reactive region.

Non-blocking assignments with in the module are scheduled in the active region, initial blocks
within program blocks are scheduled in the Reactive region.

Statements within a program block (scheduled in the Reactive region) that are sensitive to changes
in design signals declared in modules (scheduled in the active region), as active region is scheduled
before the reactive region this avoids the race condition between testbench and design.

The syntax for the program block is,

program test (input clk, input [7:0] addr, output [7:0] wdata)
;
...
Endprogram

Program block,
 can be instantiated and ports can be connected same as module.
 can contain one or more initial blocks.
 cannot contain always blocks, modules, interfaces, or other programs.
 In program variables can only be assigned using blocking assignments. Using non-blocking
assignments with in the program shall be an error.

5. INTERFACE:
Interface construct are used to connect the design and testbench.
 An interface is a named bundle of wires, aim of the interfaces is to encapsulate
communication.
 Also specifies the,
 directional information, i.e. modports
 timing information, i.e. clocking blocks
 An interface can have parameters, constants, variables, functions and tasks.
 modports and clocking blocks are explained in later chapters.
 A simple interface declaration is,

interface interface_name;
...
 SYSTEM VERILOG

interface_items
...
endinterface

 An interface can be instantiated hierarchically like a module, with or without ports.

interface_name inst_name;
 Interface can have parameters, constants, variables, functions and tasks.
Advantages of interface over the traditional connection,
 allows number of signals to be grouped together and represented as a single port, single
port handle is passed instead of multiple signal/ports.
 interface declaration is made once and the handle is passed across the
modules/components.
 addition and deletion of signals is easy.

6. Virtual interface:
A virtual interface is a variable that represents an interface instance.
Syntax:
virtual interface_name instance_name;
example:
virtual mem_intf intf;

 A virtual interface is a pointer to an actual interface in SystemVerilog. It is most often used in

classes to provide a connection point to allow classes to access the signals in the interface through
the virtual interface pointer.
 accessing the uninitialized virtual interface result in a run-time fatal error.
 Virtual interfaces can be declared as class properties, which can be initialized procedural or
by an argument to new().
 Virtual interface variables can be passed as arguments to the tasks, functions, or methods.
 All the interface variables/Methods can be accessed via virtual interface handle. i.e
virtual_interface.variable
7. mod ports:
Modport groups and specifies the port directions to the wires/signals declared within in the
interface.
By specifying the port directions, modport provides access restrictions.
The keyword modport indicates that the directions are declared as inside the module.
The Interface can have any number of modports, wire declared in the interface can be grouped in
many modports.
wires declared in the modport are accessed as,
modport_name.wire;

8. clocking block:
A clocking block specifies timing and synchronization for group of signals.
The clocking block specifies,
 The clock event that provides a synchronization reference for DUT and testbench.
 The set of signals that will be sampled and driven by the testbench.
 SYSTEM VERILOG

 The timing, relative to the clock event, that the testbench uses to drive and sample those
signals.
Clocking block can be declared in interface, module or program block.
Clocking event:
The event specification used to synchronize the clocking block, @(posedge clk) is the clocking
event.

Clocking signal:
Signals sampled and driven by the clocking block, from_DUT and to_DUT are the clocking signals,

Clocking skew:
Clocking skew specify the moment (w.r.t clock edge) at which input and output clocking signals are
to be sampled or driven respectively. A skew must be a constant expression and can be specified as
a parameter.

9. Input and output skews:

Input (or inout) signals are sampled at the designated clock event. If an input skew is specified then
the signal is sampled at skew time units before the clock event. Similarly, output (or inout) signals
are driven skew simulation time units after the corresponding clock event.

A skew must be a constant expression and can be specified as a parameter. In case if the skew does
not specify a time unit, the current time unit is used.

10. Clocking block events:

The clocking event of a clocking block is available directly by using the clocking block name,
regardless of the actual clocking event used to declare the clocking block.
The clocking event of the cb clocking block can be used to wait for that particular event:
@( cb );
The above statement is equivalent to @(posedge clk).

11. cycle delay:##

The ## operator can be used to delay execution by a specified number of clocking events, or clock
cycles.

SYSTEM VERILOG ASSERTIONS

 SYSTEM VERILOG

1.Building blocks of SVA:

1.Boolean expression - The functionality is represented by the combination of multiple logical

events. These events could be simple Boolean expressions.

2. sequence - Boolean expression events that evaluate over a period of time involving
single/multiple clock cycles. SVA provides a key word to represent these events called "sequence."
syntax:
sequence name_of_sequence;
……
endsequence
3. property - A number of sequences can be combined logically or sequentially to create more
complex sequences. SVA provides a key word to represent these complex sequential behaviors
called "property”.
4. Assert - The property is the one that is verified during a simulation. It has to be asserted to take
effect during a simulation. SVA provides a key word called "assert" to check the property.

The steps involved in the creation of a SVA checker,

2. SVA sequence:
Sequence seq_1 checks that the signal "a" is high on every positive edge of the clock. If signal "a" is
not high on any positive clock edge, the assertion will fail.
sequence seq_1;
@(posedge clk) a==1;
endsequence

1. Sequence with logical relationship:

Below sequence seq_2 checks that on every positive edge of the clock, either signal "a" or signal "b"
is high. If both the signals are low, the assertion will fail.
sequence seq_2;
 SYSTEM VERILOG

@(posedge clk) a || b;
endsequence
2. Sequence Expressions:
By defining arguments in a sequence definition, the same sequence can be re-used for the similar
behavior.
For example, we can define a sequence as follows.

sequence seq_lib (a, b)

a || b ;
endsequence

3. sequence with timing relationship:

In SVA, clock cycle delays are represented by a "##" sign. For example, ##2 means 2 clock cycles.
For the signal "a" being high on a given positive edge of the clock. If signal "a" is not high, then the
sequence fails. If signal "a" is high on any given positive edge of clock, then signal "b" should be
high 2 clock cycles after that. If signal "b" is not asserted after 2 clock cycles, the assertion fails.

sequence seq;
@(posedge clk) a ##2 b;
Endsequence

Note :: sequence begins when signal "a" is high on a positive edge of the clock.

A clock can be specified in a sequence, in a property or even in an assert statement.

clock defined in the sequence definition:

Clock defined in the property definition:

sequence seq;
a ##2 b;
endsequence

property p;
@(posedge clk) seq;
endproperty
a_1 : assert property(p);
 SYSTEM VERILOG

In general, it is a good idea to define the clocks in property definitions and keep the sequences
independent of the clocks. This will help increase the re-use of the basic sequence definitions.
A separate property definition is not needed to assert a sequence. the expression to be checked can
be
called from the assert statement directly.

4. Forbidding a property:
sequence checks that if signal "a" is high on a given positive edge of the clock, then after 2 clock
cycles, signal "b" shall not be high. The keyword "not" is used to specify that the property should
never be true.
sequence seq;
@(posedge clk) a ##2 b;
endsequence

property p;
not seq;
endproperty
a_1: assert property(p);

3.Implication operator:
Implication is equivalent to an if-then structure. The left hand side of the implication is called the
"antecedent" and the right hand side is called the "consequent." The antecedent is the gating
condition. If the antecedent succeeds, then the consequent is evaluated. The implication
construct can be used only with property definitions. It cannot be used in sequences.

sequence seq;
@(posedge clk) a ##2 b;
Endsequence
In the above sequence we can observe that, sequence starts on every positive edge of the clock and
it looks for "a" to be high on every positive clock edge. If signal "a" is not high on any given positive
clock edge, an error is issued by the checker.
If we want sequence to be checked only after “a” is high, this can achieved by using implication
operator.

There are 2 types of implication:

 Overlapped implication
 Non-overlapped implication

1.Overlapped implication - Overlapped implication is denoted by the symbol |->.

If there is a match on the antecedent, then the consequent expression is evaluated in the same
clock cycle.
Below property checks that, if signal "a" is high on a given positive clock edge, then signal "b"
should also be high on the same clock edge.
property p;
 SYSTEM VERILOG

@(posedge clk) a |-> b;

endproperty
a: assert property(p);

2. Non-overlapped implication - Non-Overlapped implication is denoted by the symbol |=>.

If there is a match on the antecedent, then the consequent expression is evaluated in the next clock
cycle.

Below property checks that, if signal "a" is high on a given positive clock edge, then signal "b"
should be high on the next clock edge.AaaAAA CX
property p;
@(posedge clk) a |=> b;
endproperty
a: assert property(p);

3. Implication with a fixed delay on the consequent - Below property checks that, if signal "a" is
high on a given positive clock edge, then signal "b" should be high after 2 clock cycles.
property p;
@(posedge clk) a |-> ##2 b;
endproperty
a: assert property(p);

4. Implication with a sequence as an antecedent - Below property checks that, if the sequence
seq_1 is true on a given positive edge of the clock, then starts checking the seq_2 (“d” should be
low, 2 clock cycles after seq_1 is true ) .

sequence seq_1;
(a && b) ##1 c;
endsequence

sequence seq_2;
##2 !d;
endsequence

property p;
@(posedge clk) seq_1 |-> seq_2;
endpeoperty
a: assert property(p);

5. Timing windows in SVA checkers - Below property checks that, if signal "a" is high on a given
positive clock edge, then within 1 to 4 clock cycles, the signal "b" should be high.

property p;
@(posedge clk) a |-> ##[1:4] b;
endproperty
a: assert property(p);
 SYSTEM VERILOG

6. overlapping timing window - Below property checks that, if signal "a" is high on a given positive
clock edge, then signal "b" should be high in the same clock cycle or within 4 clock cycles.
property p;
@(posedge clk) a |-> ##[0:4] b;
endproperty
a: assert property(p);
7. Indefinite timing window - The upper limit of the timing window specified in the right hand side
can be defined with a "$" sign which implies that there is no upper bound for timing. This is called
the "eventuality" operator. The checker will keep checking for a match until the end of simulation

Below property checks that, if signal "a" is high on a given positive clock edge, then signal "b" will
be high eventually starting from the next clock cycle.

property p;
@(posedge clk) a |-> ##[1:$] b;
endproperty
a: assert property(p);
4. Repetition operators
property p;
@(posedge clk) a |-> ##1 b ##1 b ##1 b;
endproperty
a: assert property(p);

The above property checks that, if the signal “a” is high on given posedge of clock, then signal “b”
should be high for 3 consecutive clock cycles.

The Consecutive repetition operator is used to specify that a signal or a sequence will match
continuously for the number of clocks specified.
Syntax:
signal [*n] or sequence [*n]
"n" is the number of repetitions.
with repetition operator above sequence can be re-written as,
property p;
@(posedge clk) a |-> ##1 b[*3];
endproperty
a: assert property(p);

1. Go-to-repetition - The go-to repetition operator is used to specify that a signal will match the
number of times specified not necessarily on continuous clock cycles.
Signal [->n]

property p;
@(posedge clk) a |-> ##1 b[->3] ##1 c;
endproperty
a: assert property(p);
 SYSTEM VERILOG

the above property checks that, if the signal “a” is high on given posedge of clock, then signal “b”
should be high for 3 clock cycles followed by “c” should be high after ”b” is high for third time.

2. Non-consecutive repetition - This is very similar to "go to" repetition except that it does not
require that the last match on the signal repetition happen in the clock cycle before the end the
entire sequence matching.
Signal [=n]
Only expressions are allowed to repeat in "go to" and "non-consecutive" repetitions. Sequences are
not allowed.

5. SVA methods:

1. $rose - $rose(Boolean expression or signal name)

returns true if the least significant bit of the expression changed to 1. Otherwise, it returns false.
sequence seq_rose;
@(posedge clk) $rose(a);
endsequence

Sequence seq_rose checks that the signal "a" transitions to a value of 1 on every positive edge of
the clock. If the transition does not occur, the assertion will fail.

2. $fell - $fell( Boolean expression or signal name) returns true if the least significant bit of the
expression changed to 0. Otherwise, it returns false.
sequence seq_fell;
@(posedge clk) $fell(a);
endsequence
Sequence seq_fell checks that the signal "a" transitions to a value of 0 on every positive edge of the
clock. If the transition does not occur, the assertion will fail.
3.$stable - $stable( Boolean expression or signal name) returns true if the value of the expression
did not change. Otherwise, it returns false.
sequence seq_stable;
@(posedge clk) $stable(a);
endsequence

Sequence seq_stable checks that the signal "a" is stable on every positive edge of the clock. If the
there is any transition occur, the assertion will fail.

4. $past - $past(signal_name, number of clock cycles) provides the value of the signal from the
previous clock cycle.
property p;
@(posedge clk) b |-> ($past(a,2) == 1);
endproperty
a: assert property(p);
 SYSTEM VERILOG

Below Property checks that, in the given positive clock edge, if the “b” is high, then 2 cycles before
that, a was high.

5.$past construct with clock gating :

The $past construct can be used with a gating signal. on a given clock edge, the gating signal has to
be true even before checking for the consequent condition.

Spast (signal_name, number of clock cycles, gating signal)

Below Property checks that, in the given positive clock edge, if the “b” is high, then 2 cycles before that, a
was high only if the gating signal "c' is valid on any given positive edge of the clock.

Property p;
@(posedge clk) b |-> ($past(a,2,c) == 1);
endproperty
a: assert property(p);

6. Built-in system functions:

1. $onehot(expression) - checks that only one bit of the expression can be high on any given clock
edge.
2. $onehot0(expression) - checks only one bit of the expression can be high or none of the bits can
be high on any given clock edge.
3. $isunknown(expression) - checks if any bit of the expression is X or Z.
4. $countones(expression) - counts the number of bits that are high in a vector.

a_1: assert property( @(posedge clk) $onehot(state) );

a_2: assert property( @(posedge clk) $onehot0(state) );
a_3: assert property( @(posedge clk) $isunknown(bus) ) ;
a_4: assert property( @(posedge clk) $countones(bus)> 1 );

Assert statement a_1 checks that the bit vector "state" is one-hot.
 SYSTEM VERILOG

Assert statement a_2 checks that the bit vector "state" is zero one-hot.
Assert statement a_3 checks if any bit of the vector "bus" is X or Z.
Assert statement a_4 checks that the number of ones in the vector "bus" is greater than one.
7. disable iff - In certain design conditions, we don't want to proceed with the check if some
condition is true. this can be achieved by using disable iff.

Below property checks that, if the signal “a” is high on given posedge of clock, then signal “b”
should be high for 3 clock cycles followed by “c” should be high after ”b” is high for third time.
During this entire sequence, if reset is detected high at any point, the checker will stop.

property p;
@(posedge clk)
disable iff (reset) a |-> ##1 b[->3] ##1 c;
endproperty
a: assert property(p);

8. ended - while concatenating the sequences, ending point of the sequence can used as a
synchronization point.

This is expressed by attaching the keyword "ended" to a sequence name.

sequence seq_1;
(a && b) ##1 c;
endsequence

sequence seq_2;
d ##[4:6] e;
endsequence

property p;
@(posedge clk) seq_1.ended |-> ##2 seq_2.ended;
endpeoperty
a: assert property(p);

Above property checks that, sequence seq_1 and SEQ_2 match with a delay of 2 clock cycle in
between them. the end point of the sequences does the synchronization.

SYSTEM VERILOG COVERAGE

Coverage:
Coverage is used to measure tested and untested portions of the design. Coverage is defined as the
percentage of verification objectives that have been met.

There are two types of coverage metrics.

 Code Coverage
 SYSTEM VERILOG

 Functional Coverage

1.Code coverage - Code coverage measures how much of the “design Code” is exercised. This
includes, execution of design blocks, Number of Lines, Conditions, FSM, Toggle and Path.
Simulator tool will automatically extracts the code coverage from the design code.

2. functional coverage - Functional coverage is a user-defined metric that measures how much of
the design specification has been exercised in verification.
There are two types of functional coverage,

 Data-oriented Coverage - Checks combinations of data values have occurred. We can get
Data-oriented coverage by writing Coverage groups, coverage points and also by cross
coverage.
 Control-oriented Coverage - Checks whether sequences of behaviors have occurred. We can
get assertion coverage by writing System Verilog Assertions.

Defining the coverage model:

Coverage model is defined using Covergroup construct.
The covergroup construct is a user-defined type. The type definition is written once, and multiple
instances of that type can be created in different contexts.

Similar to a class, once defined, a covergroup instance can be created via the new()operator. A
covergroup can be defined in a module, program, interface, or class.

Each covergroup specification can include,

 A clocking event that synchronizes the sampling of coverage points
 A set of coverage points
 Cross coverage between coverage points
 Optional formal arguments
 Coverage options
Defining coverage points:
A covergroup can contain one or more coverage points. A coverage point can be an integral
variable or an integral expression. Each coverage point is associated with “bin”. On each sample
clock simulator will increment the associated bin value.

The bins will automatically created or can be explicitly defined.

1. Automatic/implicit bins – Automatically single bin will be created for each value of the
coverpoint variable range. These are called automatic, or implicit, bins.
For an “n” bit integral coverpoint variable, 2n number of automatic bins will get created.

module cov;
logic clk;
 SYSTEM VERILOG

logic [7:0] addr;

logic wr_rd;

covergroup cg @(posedge clk);

c1: coverpoint addr;
c2: coverpoint wr_rd;
endgroup : cg
cg cover_inst = new();
...
endmodule

Below are the bins, will get created automatically,

for addr: c1.auto[0] c1.auto[1] c1.auto[2] … c1.auto[255]
for wr_rd: c2.auto[0]

2. Explicit bins - “bins” keyword is used to declare the bins explicitly to an variable.
Separate bin is created for each value in the given range of variable or a single/multiple bins for the
rage of values.
Bins are explicitly declared with in curly braces { } along with the bins keyword followed by bin
name and variable value/range, immediately after the coverpoint identifier.

covergroup cg @(posedge clk);

c1: coverpoint addr { bins b1 = {0,2,7};
bins b2[3] = {11:20};
bins b3 = {[30:40],[50:60],77};
bins b4[] = {[79:99],[110:130],140};
bins b5[] = {160,170,180};
bins b6 = {200:$};
bins b7 = default;}
c2: coverpoint wr_rd {bins wrd};
endgroup : cg

3. Bins for transitions - Transition of coverage point can be covered by specifying the sequence,
value1 => value2
It represents transition of coverage point value from value1 to value2.
sequence can be single value or range,
value1 => value2 => value3 ….
range_list_1 => range_list_2
covergroup cg @(posedge clk);
c1: coverpoint addr{ bins b1 = (10=>20=>30);
bins b2[] = (40=>50),(80=>90=>100=>120);
bins b3 = (1,5 => 6, 7);}
c2: coverpoint wr_rd;
endgroup : cg

bins b1 = (10=>20=>30); // transition from 10->20->30

bins b2[] = (40=>50),(80=>90=>100=>120); // b2[0] = 40->50 and b2[1] = 80->90->100-
>120
bins b3 = (1,5 => 6, 7);} // b3 = 1=>6 or 1=>7 or 5=>6 or 5=>7
 SYSTEM VERILOG

4. Ignore bins - A set of values or transitions associated with a coverage-point can be explicitly
excluded from coverage by specifying them as ignore_bins.
covergroup cg @(posedge clk);
c1: coverpoint addr{ ignore_bins b1 = {6,60,66};
ignore_bins b2 = (30=>20=>10); }
endgroup : cg

5. Illegal bins - A set of values or transitions associated with a coverage-point can be marked as
illegal by specifying them as illegal_bins.
covergroup cg @(posedge clk);
c1: coverpoint addr{ illegal_bins b1 = {7,70,77};
ignore_bins b2 = (7=>70=>77);}
endgroup : cg

3. cross coverage
Cross Coverage is specified between the cover points or variables. Cross coverage is specified using
the cross construct.
Expressions cannot be used directly in a cross; a coverage point must be explicitly defined first.

Cross coverage by cover_point name:

bit [3:0] a, b;
covergroup cg @(posedge clk);
c1: coverpoint a;
c2: coverpoint b;
c1Xc2: cross c1,c2;
endgroup : cg
Cross coverage by variable name:
bit [3:0] a, b;
covergroup cov @(posedge clk);
aXb : cross a, b;
endgroup
In the above example, each coverage point has 16 bins, namely auto[0]...auto[15]. The cross of a
and b (labelled aXb), therefore, has 256 cross products, and each cross product is a bin of aXb.

Cross coverage between variable and expression:

bit [3:0] a, b, c;
covergroup cov @(posedge clk);
BC : coverpoint b+c;
aXb : cross a, BC;
endgroup
 SYSTEM VERILOG

The coverage group cov has the same number of cross products as the previous example, but in this
case, one of the coverage points is the expression b+c, which is labelled BC.

4. coverage options
Coverage options control the behavior of the covergroup, coverpoint and cross.

1. at_least:
Minimum number of hits for each bin. A bin with a hit count that is
less than number is not considered covered. default value is ‘1’.

2. auto_bin_max:
Maximum number of automatically created bins when no bins are
explicitly defined for a coverpoint. default value is ‘64’.

3. cross_auto_bin_max:
Maximum number of automatically created cross product bins for a
cross. there is no default value, it is unbounded.

coverage options can be used as below,

covergroup cg @(posedge clk);
c1: coverpoint addr { option.auto_bin_max = 128;}
c2: coverpoint wr_rd { option.atleast = 2;}
c1Xc2: cross c1, c2 { option.cross_auto_bin_max = 128;}
endgroup : cg

SYSTEM VERILOG PARAMETERS AND ‘define

There are two ways to define constants:

 parameter
 `define

1.parameter - Parameters must be defined within module boundaries using the keyword
parameter.

A parameter is a constant that is local to a module that can optionally be redefined on an instance.
Parameters are typically used to specify the width of variables and time delays.

2. Parameter redefinition:
Parameter values are not allowed to modify at runtime but can be modified using
the defparam statement and #delay specification with module instantiation.

‘define Macro:
The `define compiler directive is used to perform global macro substitution and remain active for
all files read/compiled after the macro definition.
 SYSTEM VERILOG

it will available until another macro definition changes the value or until the macro is undefined
using the `undef compiler directive.

`define WIDTH 8
to avoid redefincation `ifdef can be used,

`ifdef WIDTH
// do nothing (better to use `ifndef)
`else
`define WIDTH 8
`endif

`ifndef WIDTH
`define WIDTH 8
`endif

`ifdef can be used as if..else

`ifdef TYPE_1
`define WIDTH 8
`else
`define WIDTH 32
`endif