HCC/HCF40102B

HCC/HCF40103B

8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

40102B 2-DECADE BCD TYPE

.
40103B 8-BIT BINARY TYPE
SYNCHRONOUS OR ASYNCHRONOUS

. PRESET
MEDIUM-SPEED OPERATION : fCL = 3.6MHz

..(TYP.) @ VDD = 10V

CASCADABLE
QUIESCENT CURRENT SPECIFIED TO 20V
EY
(Plastic Package)
F
(Ceramic Package)

..
FOR HCC DEVICE
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100 nA AT 18V AND 25°C

..
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
o
C1
(Chip Carrier)
TATIVE STANDARD N . 13 A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B” ORDER CODES :
SERIES CMOS DEVICES” HCC401XXBF HCF401XXBEY
HCF401XXBC1

DESCRIPTION

The HCC40102B, HCC40103B, (extended tempera-

ture range) and the HCF40102B, HCF40103B (inter- PIN CONNECTIONS
mediate temperature range) are monolithic integrated
circuits, available in 16-lead dual in-line plastic or ce-
ramic package. The HCC/HCF40102B, and
HCC/HCF40103B consist of an 8-stage synchronous
down counter with a single output which is active when
the internal count is zero. The HCC/HCF40102B is
configured as two cascaded 4-bit BCD counters, and
the HCC/HCF40103B contains a single 8-bit binary
counter. Each type has control inputs for enabling or
disabling the clock, for clearing the counter to its
maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on each posi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETEC
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the
JAM input is clocked into the counter on the next
positive clock transition regardless of the state of the
CI/CE input. When the ASYNCHRONOUS
PRESET-ENABLE (APE) input is low, data at the

June 1989 1/13

HCC/HCF40102B/40103B

JAM inputs is asynchronously forced into the theHCC/HCF40103B) regardless of the state of
counter regardless of the state of the SPE, CI/CE, any other input. The precedence relationship be-
or CLOCK inputs. JAM inputs JO-J7 represent two tween control input is indicated in the truth table. If
4-bit BCD words for the HCC/HCF40102B and a all control inputs are high at the tieme of zero count,
single 8-bit binary word for the HCC/HCF40103B. the counters will jump to the maximum count, giving
When the CLEAR (CLR) input is low, the counter a counting sequence of 100 or 256 clock pulses
is asynchronously cleared to its maximum count long. The HCC/HCF40102B and HCC/HCF40103B
(9910 for the HCC/HCF40102B and 25510 for may be cascaded using the CI/CE input and the

FUNCTIONAL DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
V DD * Supply Voltage : HC C Types – 0.5 to + 20 V
H C F Types – 0.5 to + 18 V
Vi Input Voltage – 0.5 to V DD + 0.5 V
II DC Input Current (any one input) ± 10 mA
Pto t Total Power Dissipation (per package) 200 mW
Dissipation per Output Transistor
for T o p = Full Package-temperature Range 100 mW
T op Operating Temperature : HCC Types – 55 to + 125 °C
H CF Types – 40 to + 85 °C
T stg Storage Temperature – 65 to + 150 °C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltages are with respect to VSS (GND).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit
V DD Supply Voltage : H CC Types 3 to 18 V
H C F Types 3 to 15 V
VI Input Voltage 0 to V DD V
Top Operating Temperature : HCC Types – 55 to + 125 °C
H CF Types – 40 to + 85 °C

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 HCC/HCF40102B/40103B

LOGIC DIAGRAMS

40102B

40103B

Detail logic diagram for flip-flops, FF0-FF7 used in logic diagrams for 40102B and 40103B.

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HCC/HCF40102B/40103B

LOGIC DIAGRAMS (continued)

Timing Diagram for 40102B and 40103B

40102B

TRUTH TABLE
Control Inputs
Preset Mode Action
CLR APE SPE CI/CE
1 1 1 1 Inhibit Counter
1 1 1 0 Synchronous Count Down
1 1 0 X Preset on Next Positive Clock Transition
1 0 X X Preset Asynchrounously
Asynchronous
0 X X X Clear to Maximum Count
Notes : 1. 0 = Low level
1 = High level
X = Don’t care
2. Clock connected to clock input.
3. Synchronous operation : changes occur on negative-to-positive clock transitions..
JAM inputs : HCC/HCF010B ; MSD = J7, J6, J5, J4 (J7 is MSB)
LSD = J3, J2, J1, J0 (J3 is MSB)
HCC/HCF40103B Binary ; MSB = J7, LSB = J0

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 HCC/HCF40102B/40103B

STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)

Test Conditions Value
Symbol Parameter VI VO |I O | V D D T L o w* 25 °C T Hi g h * Unit
(V) (V) (µA) (V) Min. Max. Min. Typ. Max. Min. Max.

IL Quiescent 0/ 5 5 5 0.04 5 150

Current 0/10 10 10 0.04 10 300
HCC
Types 0/15 15 20 0.04 20 600
0/20 20 100 0.08 100 3000 µA
0/ 5 5 20 0.04 20 150
HCF
0/10 10 40 0.04 40 300
Types
0/15 15 80 0.04 80 600
V OH Output High 0/ 5 <1 5 4.95 4.95 4.95
Voltage 0/10 <1 10 9.95 9.95 9.95 V
0/15 <1 15 14.95 14.95 14.95
V OL Output Low 5/0 <1 5 0.05 0.05 0.05
Voltage 10/0 <1 10 0.05 0.05 0.05 V
15/0 <1 15 0.05 0.05 0.05
V IH Input High 0.5/4.5 <1 5 3.5 3.5 3.5
Voltage 1/9 <1 10 7 7 7 V
1.5/13.5 < 1 15 11 11 11
V IL Input Low 4.5/0.5 <1 5 1.5 1.5 1.5
Voltage 9/1 <1 10 3 3 3 V
13.5/1.5 < 1 15 4 4 4
I OH Output 0/ 5 2.5 5 – 2 – 1.6 – 3.2 – 1.15
Drive 0/ 5 4.6 5 – 0.64 – 0.51 – 1 – 0.36
HCC
Current
Types 0/10 9.5 10 – 1.6 – 1.3 – 2.6 – 0.9
0/15 13.5 15 – 4.2 – 3.4 – 6.8 – 2.4
mA
0/ 5 2.5 5 – 1.53 – 1.36 – 3.2 – 1.1
HCF 0/ 5 4.6 5 – 0.52 – 0.44 – 1 – 0.36
Types 0/10 9.5 10 – 1.3 – 1.1 – 2.6 – 0.9
0/15 13.5 15 – 3.6 – 3.0 – 6.8 – 2.4
I OL Output 0/ 5 0.4 5 0.64 0.51 1 0.36
Sink HCC
0/10 0.5 10 1.6 1.3 2.6 0.9
Current Types
0/15 1.5 15 4.2 3.4 6.8 2.4
mA
0/ 5 0.4 5 0.52 0.44 1 0.36
HCF
0/10 0.5 10 1.3 1.1 2.6 0.9
Types
0/15 1.5 15 3.6 3.0 6.8 2.4
I IH , I IL Input HCC
0/18 18 ± 0.1 ±10 – 5 ± 0.1 ± 1
Leakage Types
Current
Any Input µA
HCF
0/15 15 ± 0.3 ±10 – 5 ± 0.3 ± 1
Types
CI Input Capacitance Any Input 5 7.5 pF
* TLow= – 55°C for HCC device : – 40°C for HCF device.
* THigh= + 125°C for HCC device : + 85°C for HCF device.
The Noise Margin for both ”1” and ”0” level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5 V min. with VDD = 15V.

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HCC/HCF40102B/40103B

DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, C L = 50pF, R L = 200kΩ,

typical temperature coefficient for all V DD values is 0.3%/°C, all input rise and fall time = 20ns)
Test Conditions Value
Symbol Parameter Unit
V D D (V) Min. Typ. Max.
t PHL , Propagation Clock to-out 5 300 600
tP LH Delay Time 10 130 260 ns
15 95 190
Carry In/Counter 5 200 400
Enable-to-output 10 90 180 ns
15 65 130
Asynchronous 5 650 1300
Preset 10 300 600
Enable-to-output
15 200 400
Clear-to-output 5 375 750
10 180 360 ns
15 100 200
t THL , t T L H Transition Time 5 100 200
10 50 100 ns
15 40 80
tW Pulse Width Clock Pulse 5 300 150
Width 10 180 90 ns
15 80 40
CLR Pulse 5 320 160
Width 10 160 80 ns
15 100 50
APE Pulse Width 5 360 180
10 160 80 ns
15 120 60
t se t u p Setup Time SPE Setup Time 5 280 140
10 140 70 ns
15 100 50
JAM Setup Time 5 200 100
10 80 40 ns
15 60 30
f CL Maximum Clock Input Frequency 5 0.7 1.4
10 1.8 3.6 MHz
15 2.4 4.8

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 HCC/HCF40102B/40103B

Output Low (sink) Current Characteristics. Output High (source) Current Characteristics.

Typical Transition Time vs. Load Capacitance. Typical Propagation Delay Time vs. Load Capacit-
ance (clock to CO/ZD).

Typical Maximum Clock Input Frequency vs. Typical Dynamic Power Dissipation vs. Fre-
Supply Voltage. quency.

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HCC/HCF40102B/40103B

TYPICAL APPLICATIONS
Divide-by-”N” Counter. Programmable Timer.

Microprocessor Interrupt Timer. Synchronous Cascading.

* An output spike (160ns @ VDD = 5V) occurs whenever two or

Microprocessor Interrupt Timer. more devices are cascaded in the parallel-clocked mode be-
cause the clock-to-carry out delay is greater than the carry-in-to-
carry out delay. This spike is eliminated by gating the out put
of the last device with the clock as shown.

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 HCC/HCF40102B/40103B

TEST CIRCUITS
Quiescent Device Current. Input Voltage.

Input Current. Maximum Clock Frequency.

Dynamic Power Dissipation.

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HCC/HCF40102B/40103B

Plastic DIP16 (0.25) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 0.050

P001C

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 HCC/HCF40102B/40103B

Ceramic DIP16/1 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 20 0.787

B 7 0.276

D 3.3 0.130

E 0.38 0.015

e3 17.78 0.700

F 2.29 2.79 0.090 0.110

G 0.4 0.55 0.016 0.022

H 1.17 1.52 0.046 0.060

L 0.22 0.31 0.009 0.012

M 0.51 1.27 0.020 0.050

N 10.3 0.406

P 7.8 8.05 0.307 0.317

Q 5.08 0.200

P053D

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HCC/HCF40102B/40103B

PLCC20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 9.78 10.03 0.385 0.395

B 8.89 9.04 0.350 0.356

D 4.2 4.57 0.165 0.180

d1 2.54 0.100

d2 0.56 0.022

E 7.37 8.38 0.290 0.330

e 1.27 0.050

e3 5.08 0.200

F 0.38 0.015

G 0.101 0.004

M 1.27 0.050

M1 1.14 0.045

P027A

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 HCC/HCF40102B/40103B

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.

 1994 SGS-THOMSON Microelectronics - All Rights Reserved

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