npj | quantum information Article

Published in partnership with The University of New South Wales

https://doi.org/10.1038/s41534-024-00823-y

Pipeline quantum processor architecture

for silicon spin qubits
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S. M. Patomäki1,2 , M. F. Gonzalez-Zalba 1
, M. A. Fogarty1, Z. Cai1,3, S. C. Benjamin1,3 & J. J. L. Morton1,2

We propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as
functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity
of control and interconnect resources. This simplification is achieved by shuttling N-qubit states through a
large layered physical array of structures which realise quantum logic gates in stages. Thus, the circuit
depth corresponds to the number of layers of structures. Subsequent N-qubit states are ‘pipelined’
1234567890():,;
1234567890():,;

densely through the structures to efficiently wield the physical resources for repeated runs. Pipelining thus
lends itself to noisy intermediate-scale quantum (NISQ) applications, such as variational quantum
eigensolvers, which require numerous repetitions of the same or similar calculations. We illustrate the
architecture by describing a realisation in the naturally high-density and scalable silicon spin qubit platform,
which includes a universal gate set of sufficient fidelity under realistic assumptions of qubit variability.

Fault-tolerant quantum computers offer profound computational speed- and interfaced by a common entangling (typically photonic) mode. While
ups across diverse applications, but are challenging to build. However, even such hybrid matter/photon systems have been successfully realised in sev-
in the near term without full error correction, quantum computers have the eral platforms15–17, high gate speeds compatible with the demands of NISQ
potential to offer improvements over classical computing approaches in run algorithms18 may be difficult to achieve.
time scaling1 and energy consumption for certain tasks2. There is a rich and A further consideration when designing NISQ hardware architectures
diverse array of schemes for realising quantum computation, each formally is that NISQ algorithms based on (e.g.) variational approaches18,19 require
equivalent in computational power3–5, with important differences with multiple repetitions of the same quantum circuit—or simple variations
regards to practical realisations. In the gate-based approach, a quantum thereof—to be performed. In turn this requires identical, or similar,
algorithm is expressed as a quantum circuit consisting of a series of quantum sequences of local control fields to be repetitively applied to the qubits,
logic gates. Typically, such gates are applied to a stationary array of qubits presenting an opportunity for more efficient hardware implementations. In
(for example through electromagnetic waves or optical pulses), relying on this Article, we propose a quantum computing architecture for imple-
the delivery of a complex series of accurate, quasi-simultaneous control menting quantum circuits in which all runtime control is applied globally,
pulses to each qubit. This can lead to practical challenges ranging from and local quantum operations such as 1-qubit (1Q) and 2-qubit (2Q) gates
cross-talk in the control pulses between nearby qubits6,7 to increased are ‘programmed’ into the array in advance. This is achieved by shuttling
demands on digital-to-analogue converters (DACs) particularly when fully qubit states through a grid of gated structures which have been electronically
integrating control systems with a cryogenic quantum chip. configured to realise specific gates.
To mitigate the practical challenges associated with high-density In such an approach, each layer of gates in the original quantum circuit
control electronics, global qubit control schemes have been explored8–10. corresponds to a one-dimensional array of structures, such that the scheme
However, these approaches require a precision in the position and homo- is more demanding in terms of physical resources on a chip for confining
geneity of qubit structures, as well as the control pulses, to a degree that is qubits. However, when applying multiple repetitions of the same circuit by
technically challenging with available technology. Alternatively, local pipelining—i.e. running distinct, staggered layers of qubits through the array
addressing can be used to bring qubits into resonance with globally applied simultaneously—the physical resource efficiency becomes broadly equiva-
control fields to create an effective local control11,12. However, this approach lent to more conventional approaches, combined with potential practical
still requires fast run-time control for the addressing13. A second strategy is benefits.
to accept the cost of a much lower effective qubit density in exchange for Below, we introduce the concept of a qubit pipeline in more detail in
mitigating effects such as cross-talk—in such a distributed model of “Qubit pipeline”, before focusing on a potential implementation for the
quantum computing14 qubits, or small qubit registers, are well-separated silicon metal-oxide-semiconductor (SiMOS) electron spin qubit platform in

1
Quantum Motion, 9 Sterling Way, London N7 9HJ, UK. 2London Centre for Nanotechnology, University College London, London WC1H 0AH, UK. 3Department of
Materials, University of Oxford, Parks Road, Oxford OX1 3PH, UK. e-mail: ucapsmp@ucl.ac.uk

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https://doi.org/10.1038/s41534-024-00823-y Article

“Implementation with silicon quantum dots”. We then estimate the by a combination of global control (at least, with widely shared control lines)
expected improvement in run time for an example algorithm in “Applica- to push the qubit states from start to finish, combined with quasi-statically
tion as bespoke hardware for a NISQ eigensolver”. In particular, in “Shut- tuneable elements within the larger number of physical structures used to
tling”, we outline a scheme for synchronous shuttling, and in “Initialization, define the quantum circuit prior to running it.
readout and pre-configuration”, we discuss initialisation, readout, and We assume that while the parameters of the quantum logic gates can be
parallelised pre-configuration, mostly outlining established methods. In “Z- tuned in-situ (e.g. electrically), the type of gate performed in each cell of the
rotation gates with Stark-shifted g-factors–Transversal rotation gates”, we array is defined when fabricating the quantum processor. Indeed, though
show how to realise an universal gate set for the pipeline in the silicon more generally reconfigurable implementations may be possible (see e.g.
electron spin platform including: single-qubit Z-rotations pffiffiffiffiusing local, Supplementary Note 1) and offer potential efficiencies, a suitably chosen
voltage-controllable g-factor Stark shifts, globally-applied X operations pattern of gates is sufficient for universal quantum computation, subject
enabled by B1-drive frequency binning and 2Q SWAP-rotation gates using only to the constraints of the qubit number and circuit depth. Assuming the
the native interaction of nearest neighbour exchange. Each of the above gate quantum processor is restricted to a two-dimensional topology, the pipeline
implementations is designed to accommodate natural variations, such as approach presented here is limited to a linear qubit array. Many quantum
random g-factor differences, across the QDs while enabling synchronized algorithms can be mapped onto such a linear array without significant loss
operation and thus fixed gate times. of efficiency, such as the variational quantum eigensolver for the Fermi-
Hubbard model, a promising task that could be implemented on NISQ
Results hardware18–20 There is no guarantee that mapping the two-dimensional
Qubit pipeline Fermi-Hubbard model to a connected two-dimensional qubit lattice offers
For solid-state quantum processors the qubit array may consist of a two- an overall advantage over a one-dimensional qubit array21. This is intuitively
dimensional lattice with nearest-neighbour couplings (see Fig. 1a). The related to the non-local nature of fermions, which has to be encoded in the
qubit pipeline approach replaces the two-dimensional lattice of stationary simulation of fermionic charge degrees of freedom. Attempts to reconcile
qubits with an N × D grid (see Fig. 1b), such that N qubits are arranged in a this intrinsic non-locality with the two-dimensional-lattice qubit layout
one-dimensional array and propagate through the grid to perform a would lead to encoding schemes that offer a better circuit depth scaling, but
quantum circuit of depth D. Each column therefore represents a single ‘time at a cost of almost doubling the numbers of qubits21,22, thus not necessarily
step’ of quantum logic gates in the corresponding quantum circuit while reducing the overall circuit size. This complication is absent in the simpler
each row of structures forms a ‘pipe’ of computational length D along which one-dimensional qubit array, which instead requires additional Fermionic
a qubit travels. Multiple qubits can simultaneously travel through each pipe, SWAP operations to represent the original connectivity.
at different stages, in order to more efficiently use the physical resource. Conventional approaches to operate an N qubit processor with tune-
Run-time operation begins by initializing a one-dimensional array of N able nearest neighbour couplings demand at least OðNÞ fast signal gen-
qubit states on the input edge. This initialised array is synchronously pushed erators for single-qubit control, for qubit-qubit couplings, and for state
through D structures that have been preconfigured to perform the single- readout. In contrast, the pipeline scheme presented here may require a
and two-qubit gates in the desired quantum circuit. Qubit states are read out constant (even just one) number of fast pulse generators, utilized for shut-
on the opposite output edge. Between initialization and readout, operations tling the qubit states through the grid in a manner analogous to a charge-
on the qubit array alternate between synchronous one- and two-qubit gate coupled device. For example, three waveforms biasing columns
steps and shuttling steps. Figure 1c–f illustrate the equivalence between an d mod 3 ¼ 0; d mod 3 ¼ 1, and d mod 3 ¼ 2, create a local potential
example quantum circuit (Fig. 1c) and time-evolution on the qubit pipeline minimum for a qubit which can then be driven forward through the array23.
(Fig. 1d–f). In this way, local qubit control of the typical qubit grid is replaced Implementing such a shuttling scheme, synchronicity is achieved if gate

(a) (b)
initialisation quantum circuit through pipelining readout

√N N

√N D
(c) (d) 2Q 2Q (e) shuttle shuttle shuttle (f) 1Q 1Q 1Q
ψn 1Q 1Q 1Q n ψ0 χ0 ψ0 χ0 φ0 ψ0 χ0
2Q ψ1 χ1 ψ1 χ1 φ1 ψ1 χ1
ψn+1 1Q 1Q 1Q n+1
2Q n+2 ψ2 χ2 ψ2 χ2 φ2 ψ2 χ2
ψn+2 1Q 1Q 1Q
2Q
ψn+3 1Q 1Q 1Q n+3 ψ3 χ3 ψ3 χ3 φ3 ψ3 χ3
2Q χ4 χ4 φ4 χ4
ψn+4 1Q 1Q 1Q n+4 ψ4 ψ4 ψ4
d d+1 d+2 d+3 d+4 d d+1 d+2 d+3 d+4 d d+1 d+2 d+3 d+4 d d+1 d+2 d+3 d+4
Fig. 1 | The qubit pipeline. a In a typical N-qubit solidpstate
pffiffiffiffi ffiffiffiffi quantum processor, quantum circuit diagram, where an algorithm is decomposed into alternating steps
qubits reside at fixed spatial locations (e.g. on a N × N grid) with nearest- of 1Q and 2Q gates. d–f The qubit pipeline contains physical locations which have
neighbour connectivity. b The qubit pipeline is a weaved grid in which N qubits are been configured to implement 1Q (circles) and 2Q (connected circles) gates. Dif-
shuttled through D locations where fixed single- (1Q) or two-qubit (2Q) logic gates ferent qubit arrays (first (χ0, χ1, . . . ), then (ψ0, ψ1, . . . ), (φ0, φ1, . . . )) can be piped
are implemented. Vertical lines indicate 2Q couplers, while horizontal lines indicate sequentially through the structures, each representing one execution of the con-
shuttling couplers. At runtime, qubits are initialized at one end, synchronously figured quantum circuit.
shuttled through the pipeline, and read out on the opposite end. c An example

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Table 1 | Comparison between the quantum lattice and the (e.g. etched silicon in the case of nwFET and finFET approaches, or through
pipeline processors confining depletion gates in the case of planar MOS). Metal gates (green and
orange shapes) for forming QDs are placed along and over the exposed Si to
Lattice Pipeline
pffiffiffiffi pffiffiffiffi form locally one-dimensional QD arrays, which make 90-degree angles at
Processor size N× N N×D T-junctions to join neighbouring pipes. Such weaving is required for
Run-time control resources N constant entangling all the qubits from different pipes. Extra control from a second
Circuit decomposition flexible limited gate layer aids tuning all QDs to nominally identical setpoints despite
Run-time scaling DNr D + Nr
variability in e.g. charging energies46,47. The metal gates are routed with vias.
The overall architecture can be realised in a variety of silicon QD platforms,
Here, N is the number of qubits, D is the maximum circuit depth, and Nr is the number of repetitions.
including planar MOS, SOI, and finFETs, with cross-sections illustrated in
Fig. 2b–d. In addition, a similar layout can be used in a Si/SiGe architecture
or indeed other types of electron or hole semiconductor spin qubits.
steps take an equal amount of time for all qubits. For example, for logic gates
expressed as expðiωτσÞ for some single- or two-qubit operator σ, we fix a Shuttling
common τ but select ω to control the amount of rotation and thus distin- In the qubit pipeline, we shuttle electrons between different columns d
guish the logic operations. The gate speed ω is varied using parameters such where logical 1Q and 2Q gate operations are performed. Electrons can be
as dc gate voltages and magnetic field amplitudes at the preconfiguration shuttled from one QD to another by inverting the biasing between gates, i.e.
stage. In principle, different columns of gates (e.g. all single-qubit gates, or all by pulsing over the inter-dot charge transition with DQD charge occu-
two-qubit gates) could have different durations, at the cost of a more pancies (1, 0) → (0, 1)48–50. This scheme is also referred to as bucket-brigade
complex shuttling pulse sequence. The three-column approach to shuttling shuttling.
represents the maximum density with which different sets of qubits can be The shuttling time τs is determined by the inter-site tunnel coupling
pipelined through the circuit. frequency tij/h (typically 1 − 20 GHz in two-layer QD arrays using barrier
Due to the statistical nature of measurement in quantum mechanics, gates49) and the electron temperature, which affects charge relaxation rates.
several types of quantum algorithms, such as those that yield an expectation Each barrier gate receives an individual dc bias to tune each tunnel coupling
value following some quantum circuit24,25, must be run a large number of individually. The present architecture does not correct for charge shuttling
times to obtain a meaningful result. Such algorithms are well-suited to the errors, akin to erasure errors. These would propagate into the final state of
pipeline approach as multiple, independent qubit arrays can be pushed each run. Additionally, a charge stuck at a site as a result of a shuttling error
through the pipeline simultaneously, enabling multiple circuit runs in might also affect the subsequent run. As such, it relies on charge shuttling
parallel. The maximum density of independent logical instances of a fidelity to remain well below one error per run. Charge shuttling errors are
quantum circuit which can be pipelined through the structure is determined expected to be minimized when the pulsing rate is slow compared to the
by the physical constraints of ensuring forward shuttling and avoiding inter-dot tunnel coupling37,51, where non-adiabatic Landau-Zener (LZ)
unwanted interactions between qubits. Furthermore, if the duration of transitions are minimal. At tunnel coupling tij/h = 20 GHz, the ramp can be
either the initialisation or readout stage is greater than that of the 1Q/2Q performed adiabatically (PLZ < 10−4) with shuttling times of 9.1 ns or more
gates, this density must be further reduced. Exploiting such pipelining, the (see Supplementary Note 2). Electron charges and spins have been
algorithm runtime is proportional to (D + Nr)τ instead of DNrτ, providing a demonstrated to shuttle reliably over these timescales37,51, so we take 10 ns as
significant speedup for circuits with large number of repetitions Nr, or large the range of target shuttling times τs. The exact shuttling time should be
depths. Here, τ is the timescale of the longest operation: a qubit gate, readout, determined to avoid LZ transitions to excited states, such as valley-orbit
or initialization. Table 1 summarises these main differences between a qubit states. The systematic Z-phases arising from g-factor differences between
lattice and the qubit pipeline. sites can be accounted for as part of single-qubit control, as discussed in “Z-
rotation gates with Stark-shifted g-factors”.
Implementation with silicon quantum dots The pulse sequence depicted in Fig. 2e can realise the shuttling and
We now analyse a hardware implementation well-suited to the qubit logic gate dynamics modulation. To this end, each plunger gate is routed to
pipeline paradigm, i.e. qubits based on single electron spins trapped in an ac + dc voltage combining circuit. The ac nodes from gates from a single
silicon-based QDs. Silicon spin qubits can achieve high density due to their column, and mod 5 steps, are combined at interconnect level with a power
small footprint of Oð50 × 50 nm2 Þ, and can leverage the state-of-the-art splitter, whereas each gate receives an individual dc bias. Bias tees at gate
nanoscale complementary metal-oxide-semiconductor (CMOS) manu- nodes enable applying dc biases from individual dc sources. See Supple-
facturing technology used in microprocessors7,26–28. Quasi-CMOS- mentary Note 2 for footprint estimates. As there are signals with three
compatible electron spin qubits can be patterned as gated planar MOS different periods, we could employ e.g. phase modulation or partially digital
devices29–31, confining electrons at the Si-SiO2 interface below the gates, or signal processing to generate the five shuttling biases, and hence shuttling
using Si/SiGe heterostructures31,32. Typical values for single- and two-qubit biases for the entire pipeline with only three voltage pulse generators. We
gate fidelities measured so far in such systems include 99.96% and 99.48% in can fill the pipeline up to every fifth physical gate column of QDs single
SiMOS33,34 and 99.9% and 99.5% in Si/SiGe32,35,36. Coherent spin shuttling electrons, which we refer to as maximal filling.
has been demonstrated at a transfer fidelity of 99.97% for spin eigenstates,
and 98% for spin-superposition states37,38, while SWAP gates have also be Initialization, readout and pre-configuration
shown to transport arbitrary qubit states with fidelity up to 84%39. In Initialisation and readout is analogous to a shift register for single-electron
addition, silicon on insulator (SOI) nanowire and fin field-effect transistors spins, where electrons are moved through a pipe and electron reservoirs are
(nwFET and finFET) devices40–42 have been used to confine spin qubits located at the input and output ends of the array. Preconfiguration of the
within etched silicon structures, and have been proposed for sparsely- unit cells can be done locally, utilizing initialization and readout nodes like
connected two-dimensional qubit architectures43. These devices typically the one depicted in Fig. 2f. Logical ground states ∣#q i are initialised using
show a large electrostatic gate control of the QDs (larger so-called lever arms spin-dependent reservoir-to-dot tunnelling52. The fidelity is typically
α) which is advantageous for reflectometry readout techniques, or spin- determined by the relative magnitude of the spin Zeeman energy splitting
photon coupling44,45. and kBT where T is the temperature of the electron reservoirs and kB is
To realise the qubit pipeline, we propose a sparse two-dimensional Boltzmann’s constant. For example, at B0 = 1 T, F ≥ 0:9999 at T ≲ 73 mK.
quantum dot(QD) array, which we refer to as a nanogrid (see Fig. 2a). The The initialization time is determined by the reservoir-to-dot tunnelling time
nanogrid is a weaved grid of silicon ‘channels’ in which QDs can be formed 1/ΓψR, which can be controlled with a barrier gate, and can reach tens of

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(a) d d+1 d+2 d+3 x

z y
2Q dielectric
silicon

ment
plunger
n barrier
ψ1 1Q
(b)
1Q
2Q
1Q
ψ2 1Q (c)
n+1

(d)
2Q

(e) τ1Q τs τ2Q τs τ1Q (f)

Vin
ΓψR R ΓφR
ψ φ
Vout
t ψ

Fig. 2 | Silicon quantum dot pipeline unit cell. a Unit cell of a qubit pipeline, dots (magenta blobs) are confined using etched silicon or confinement gates (light
realised as a weaved grid of silicon channels (dark grey grid) which may be defined by yellow). e Sketch of the shuttling pulse sequence (relative pulse durations not to
etching or electrostatically by depletion gates (not shown). Overlapping metal gates scale). Voltages Vin (Vout) are those at which single (zero) electron occupancy of the
(coloured rectangles) are used to confine, shuttle and manipulate electron spin QD becomes the ground state. Single- and two-qubit gates are separated by short
qubits within the channels. Connectivity for five-stage shuttling is shown as coloured shuttling steps—in general, the number of shuttling steps depends on the exact gate
lines where all sites mod 5 (for example, those controlling two subsequent 2Q sites) layout, and depend on e.g. footprints required for routing. f Structures for local
are connected to the same ac voltage source. All barrier gates receive individual dc electron reservoirs (R), for spin readout (with an auxiliary state φ), and hence for
biases. b–d Side views of different gate stacks which could be used in this imple- preconfiguration of quantum states ψ. The operation of these structures, which can
mentation, including (b) planar MOS, (c) SOI nanowire, and (d) finFET. Quantum be placed along pipes between d + 1 and d + 2 (see a), is discussed further in the text.

GHz53. At higher electron reservoir temperatures, required fidelities could be Nevertheless, initialization and readout could be performed using Pauli spin
obtained using real-time monitoring of the qubit through a negative-result blockade or parity projections with an ancilla spin of known orientation (via
measurement at the expense of longer initialization times54. g-factor calibration in the preconfiguration stage) using the structure in Fig.
For readout, we employ the so-called Elzerman readout, where we 2f e.g. using a pulsing protocol similar to that in ref. 60. In the case of singlet-
detect spin states using the reverse of the spin-dependent tunnelling triplet or parity readout, the temperature of operation of the pipeline could
described above, detected by a capacitively-coupled charge sensor, such as a be raised up to 0.5 K while retaining 99.9% fidelity58,61. We consider realistic
single-electron box55,56, at site φ (see Fig. 2(f)). This method is estimated to estimates of processor run-time operating temperatures to be largely outside
yield a spin readout fidelity F ≥ 0:993 in ≤4 μs53, while advances in resonant the scope of this work, but we briefly return to power consumption in the
readout techniques could help increase F ≥ 0:9999 in 50 ns57. context of transversal qubit control in “Transversal rotation gates”.
We highlight Elzerman readout over Pauli spin blockade or parity
readout58 since (i) we operate the pipeline at relatively high B0 fields, B0 ≈ 1 Z-rotation gates with Stark-shifted g-factors
T, see “Z-rotation gates with Stark-shifted g-factors”, (ii) it is not compro- The electron spin g-factor g*, which defines the Larmor frequency
mised by low valley-orbit splitting53,55,59 and (iii) the readout pulsing protocol ω0 = g*μBB0/ℏ (where μB is the Bohr magneton and B0 the applied dc
is simpler since it does not require the state preparation of the ancilla spin60, magnetic field) can be shifted using electric fields from gate voltages. In
making it more amenable to the shift registry operation of the pipeline. SiMOS heterostructures the dominant Stark shift is understood to arise

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(b) (c) (d)

x
Vμ
z y

Vq+1

Vq+1
(a) q-1 q q+1
Vq
Vq-1 Vq-1
(e) (f)
μ q

Fig. 3 | Z-rotation gate using Stark shifts. a Order of magnitude of Stark shift δgq, from the charge configuration (nq+1 nq nq−1) = (001) (blue circle marker) to (010)
with respect to the bulk value gSi ≈ 2.0, as a function of external magnetic field B0 and (red star marker), and to (100) (blue triangle marker). c In the perfectly compensated
single-qubit gate time τ1Q, required for the π-rotation gate Z(π). b Gate layout case with g-factor tuning, the (010) region opens up during the shuttling sequence.
realisation of the g-factor tuning scheme with shuttling through quantum dots under d In the non-compensated case, adjusting Vq to tune the g-factor at q causes the (010)
gates q − 1, to q, and to q + 1. The voltage Vq is used to tune the g-factor at site q, region to shift away from the ground state charge configurations. e Electric field
while the voltage Vμ is used to compensate for the change in the electrochemical gradients evaluated along the cut shown as a grey dotted line in (d). Electric field
potential due to the g-factor tuning. c, d Overlaid stability diagrams of the (q − 1, gradients due to Vq are denoted as blue, and those due to Vμ as orange traces.
q, q + 1) triple quantum dot at the start and end (blue lines), and at the middle (red f Estimated fidelity of Z(π) as a function of variance in actual gate duration and
lines) of the shuttling sequence, illustrate the requirement for electrochemical voltage noise affecting δg, with fixed σG = 10−3gSi, B0 = 1 T, and τ1Q = 1 μs. (see
potential compensation. Using a waveform as shown in Fig. 2e, shuttling proceeds main text).

from wavefunction displacement with respect to the Si/SiO2 interface62. To realise such Stark shifts, we propose to employ the plunger gate as
Linear or quasi-linear shifts δgq(V) with ∂g/∂Ez(V) = ± (1–5) × 10−3 (MV/ the g-factor tuning gate, and a neighbouring gate as a μ-compensating gate
m)−1 have been reported for QDs in planar MOS devices30,63,64 with an in- (gate labelled with μ in Fig. 3b). This additional compensating gate is
plane magnetic field and Ez applied perpendicular to the interface. The sign required to ensure the electrochemical potentials (see Supplementary Note
of the shift depends on the valley state of the electron62,63. The roughness of 3), and hence QD electron occupancies remain correct under the applied
the Si/SiO2 interface also introduces some random contribution Gq to the electric field for g-factor tuning, as illustrated in the triple QD stability
effective g-factor, which can be larger than the tuneability, diagrams shown in Fig. 3c, d. In planar MOS, the plunger gate contributes
Gq ¼ ± Oð103 :::102 Þ64. Hence, the g-factor of a spin at some site q can be dominantly to Ez, while the μ-compensating gate electric field mostly to Ex,
considered as a combination of these shifts on some intrinsic value, gSi, such at site q, having negligible effect on the g-factor. In etched silicon devices, due
that g q ¼ g Si þ Gq þ δg q ðVÞ. In the following, we assume gSi = 2.0. to two facets of Si/SiO2 interface (Fig. 2f), we expect both split gates to
We use the gate-voltage controllable g-factor Stark shift to perform contribute to the Stark shift, but as long as the effects of the two gates to the g-
relative single-qubit Zðφq Þ ¼ eiφq σ z =2 gates by synchronously shuttling the factor Stark shift and the electrochemical potential shift are asymmetric, the
qubit onto a QD structure (see columns d + 1 and d + 3 in Fig. 2a) with pair of gates allows to compensate for the shift in the electrochemical
predetermined dc gate voltages. Spins encoding the qubit state remain at the potential.
same site for a fixed time τ1Q to acquire some phase (relative to a spin with Analytical estimates for the E-field derivatives ∂Ez/∂Vj and ∂Ex/∂Vj due
g = gSi) before synchronously shuttling forward. The gate Z(φq) is achieved to the plunger and μ-compensating voltages Vq and Vμ, as a function of
by selecting a suitable g-factor shift longitudinal position x, close to the MOS interface, are plotted in Fig. 3e,
with simulation details given in Supplementary Note 3. The estimated values
φq 2πr q of the Ez-gradient at site q, together with a conservative figure of ∂g/
δg q ðVÞ ¼μ 1 : ð1Þ
B B0 τ 1Q _
∂Ez = ± 1 × 10−3 (MV/m)−1 suggest a required voltage shift
dVq = 615 V × δgq. For example, a target Stark shift δgπ = ± 3.6 × 10−5,
Here, r q 2 ½0; 1Þ is selected from GqμBB0τ1Qℏ−1 ≔ 2π(nq + rq), for nq 2 Z. would require the dc bias on the gate to be shifted dVq = ± 22 mV. The
Since we only require phase matching up to 2π, the site-to-site randomness corresponding change in μq can be compensated with the μ-compensating
Gq only contributes via 2πrq, which remains in the same order of magnitude gate, by setting the voltage dVμ ≈ − αqq/αqμdVq, where αij is the lever arm
for any Gq. As a result, the randomness does not affect the required between QD at site i and gate j (see Supplementary Note 3).
tuneability to attain a rotation angle over a target gate time. Similarly, We evaluate the sensitivity of this Z(φq) gate to noise using the so-called
systematic phase shifts arising from the other QDs involved in shuttling can process fidelity65 between an ideal and a noisy unitary gate, for the case of
be accounted for as an effective contribution to Gq and corrected in the same τ1Q = 1.0 μs and B0 = 1.0 T. We sample a value for Gq from a normal dis-
way. The order of magnitude of δgq(V) required to generate a π phase shift at tribution with width σG set to 10−3gSi, and use it to find δgq (Eq. (1)) to hit
varying τ1Q and B0 is plotted in Fig. 3a, where we take Gq = 0 for simplicity. φq = π for an ideal gate. For the noisy gate, we consider shuttling time errors of
Tunabilities of at least δg ≈ ± 3.6 × 10−5 and δg ≈ ± 3.6 × 10−4 are required at magnitude δτ that lead to gate time errors, and fluctuations in the gate voltage,
B0 = 1 T for τ1Q = 1 μs and τ1Q = 0.1 μs, respectively. δVq, which lead to impacts in the g-factor according to δgq = δVq/615 V. For

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Fig. 4 | Two-qubit gate family from nearest-neighbour exchange. a Bloch sphere ΔEZ/Jij. e The SWAP-rotation gate can be constructed from the native unitary gate
two-qubit dynamics on the mz = 0 subspace under nearest-neighbour exchange. The with φ = π/2 + 2πn and χ = π/4, as two such native operations separated by single-
mz = 0 states rotate around an axis defined by the relative magnitudes of exchange qubit Z-rotation gates. The phases of the mz = ± 1 components are fixed by sub-
strength and Zeeman energy difference. b–e Circuit identities for the unitary time sequent application of another phase gate and single-qubit Z-rotations. f Bloch
evolution UNNE(ϵ, φ, χ) Eq. (3), describing nearest-neighbour exchange in the pre- sphere representation of the SWAP-rotation identity of (e). g–i Fidelities for the
sence of Zeeman energy differences. Multiples of 2πn are left out of the rotation native gates with (g) ϕ = π + 2πn, realising the Ising ZZ-rotation gate, and (h) ϕ = π/
angles for simplicity. b, c Choice of rotation angle φ = π + 2πn realises the phase 2 + 2πn, realising the Givens(χ) SWAP operation, which, for χ = π/4 is used in the
gates (b) CPhase and (c) Ising ZZ-rotation gate. d Choice of φ = π/2 + 2πn realises a composition of SWAP(θ) (see e), and (i) the composite SWAP(θ) rotation gate as a
gate close to the Givens rotation, where the rotation angle χ depends on the ratio function of rotation angles and tunnel coupling variance σ tij =t ij .

example, shuttling time error is thus assumed to change the gate time from the decoupled mz = ± 1 subspaces merely acquire phases according to their
τ1Q to τ1Q + δτ. These noise contributions δτ and δVq are also sampled from Larmor frequencies. In this analogy, within the mz = 0 subspace, Δij ≈ ΔEZ
normal distributions with varying widths of στ and σV, respectively. corresponds to the qubit-drive detuning, Jij to the transversal coupling
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
In Fig. 3(f), we plot the resulting Z(π) fidelities, averaged over 1000 strength, and Ωij ¼ Δ2ij þ J 2ij =h to the Rabi frequency.
samples at each pair of noise levels. We find that the noise sources for the
gate time and g-tuning errors add up independently. Noise levels of στ ≲ 0.08 This time evolution is our native two-qubit operation. To classify the
ns, i.e. ~ 10−2τs for the target shuttling time of τs = 10 ns, and σV ≲ 100 μV resulting operations, we may represent the unitary operation with two angle
are required to achieve F ½Zðφq Þ ≥ 0:9999. Charge noise acts equivalently to variables, as
gate voltage fluctuations. Based on state-of-the art charge noise spectral
densities in industrial SiMOS devices42,66,67, we would expect voltage fluc- U Nat ðϵ; φ; χÞ ¼^ eiφ cosðχÞ
0 iφZ iαðφ;χÞ 1
tuations of σV ≈ 30. . . 90 μV over a bandwidth of 1 Hz − 1 GHz, which is e

0

0 0
B cosðφÞ þ i sinðχÞ sinðφÞ i cosðχÞ sinðφÞ C
sufficient for our fidelity requirements, whereas there is less experimental × B
B 0
 
0 C
C:
@ 0 i cosðχÞ sinðφÞ cosðφÞ  i sinðχÞ sinðφÞ 0 A
data available on timing errors in shuttling.
0 0 0 eiφZ iαðφ;χÞ

Two-qubit gate family with gate-voltage-tuneable exchange ð3Þ

To perform two-qubit operations, qubits are shuttled to neighbouring sites
that connect adjacent pipes, in order to introduce an exchange interaction Using this parameterization (also see Supplementary Note 4), we observe
whose strength, Jij, can be estimated by that dynamics in the mz = 0 subspace is analogous to the single-qubit
dynamics under the semiclassical Rabi Hamiltonian. This analogue is
2t 2 ΔK
J ij ≈ ½ðΔKÞ2ijϵðtÞ2  : ð2Þ illustrated using a Bloch sphere in Fig. 4a. Here, the angle φ = Ωijτ2Q is set by
the gate time τ2Q and the frequency Ωij, the Rabi frequency analogue. The
angle χ ¼ arctanðxÞ is set by the ratio x = Δij/Jij. Here, Δij is the detuning-
Here, ϵ(t) is the detuning of the single-particle level spacings proportional to analogue, and Jij the transversal coupling analogue. The angle χ is the
chemical potentials and ΔK is the difference between the on-site and inter- analogue of the angle complementary to the single-qubit effective magnetic
site charging energies. Jij can thus be in-situ modulated by the detuning using field polar angle arccos (Δij/Ωij) via arccos ðΔij =Ωij Þ ¼ arccotðxÞ. We also
the plunger gates, or the tunnel coupling using the barrier gates. Both knobs have φZ = (EZ + ΔEZ)φ/Ωij, and αðφ; χÞ ¼ φ cosðχÞ. When x → 0, coincid-
can modulate the exchange strength over several order of magnitude. We ing with negligible Zeeman energy differences, the native operation (3)
choose to use module the tunnel coupling to allow us to operate in the centre reduces to the SWAP-rotation with the rotation angle given by φ (viewed
of the (1, 1) charge configuration, where charge noise is minimised68,69. from the frame from which EZ = 0). But even in the presence of ΔEZ, the
In the logic basis f∣"i "j i; ∣"i #j i; ∣#i "j i; ∣#i #j ig, the interaction native operation (3) can be used to realise several familiar two-qubit
between two exchange-coupled spins with a Zeeman energy difference ΔEZ operations. Figure 4b–e illustrates some circuit identities obtained from it.
(see Supplementary Note 4) generates time-evolution which is analogous to One way to engineer desired gates starts by considering interaction
the single-qubit semiclassical Rabi dynamics in the mz = 0 subspace, while times that correspond to particular numbers of completed rotations with

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https://doi.org/10.1038/s41534-024-00823-y Article
pffiffiffi
respect to the single-qubit analogue of the Rabi frequency. In doing so, are ΔEZ, and a resolution 2πn=ð 2J ij Þ, but we may use g-factor tuneability at
left to fix χ to define the operation. Since we largely do not control the QD j for fine-tuning τ (after which Jij is recalculated). Smaller g-factor
Zeeman energy difference, we choose the polar angle analogue with Jij. By tuneability then requires a longer gate time to minimise gate time errors.
choosing φ = π + 2πn, we realise the diagonal two-qubit phase gates70, as For example, setting the target gate time and rotation angle, as τ = 1 μs,
and χ = π/4, respectively, and assuming ΔK = 1 meV, σG = 10−3gSi, B0 = 1 T
Zðφ11 Þ  Zðφ11 Þeiαiφ U Nat ðϵ ¼ 0; φ ¼ π þ 2πn; χÞ yields the desired Givens-like gate with x = ± 1, and with average exchange
  ð4Þ strength, number of rotations, and average timing errors of Jij ≈ 32 MHz,
¼ CPhase 2αðφ ¼ π þ 2πn; χÞ :
n ≈ 45, and δτ2Q ≈ 0.1 ns. For the phase gates, the protocol is similar, but x is
where we have defined φ11 = − φZ − α(φ, χ), and solved from the desired rotation angle. We note that typically, the two-qubit
gates impose an independent restriction to the g-factor tuneability to ensure
ZðφZ Þ  ZðφZ ÞU Nat ðϵ; φ ¼ π þ 2πn; χÞ that fidelities are not limited by gate timing errors, which we find to be
  ð5Þ
¼ Ising αðφ ¼ π þ 2πn; χÞ þ π : higher than the requirements for single-qubit gates. For example, in the
above, we require ~δg ≥ ± 1 × 10−4 (corresponding to dVq ≤ ± 61 mV).
The circuits are visualised in Fig. 4b, c. See Supplementary Note 5 for their The process fidelities of the native Ising(α + π), Givens(χ)SWAP, and
matrix representations. These gates are maximally entangling (for certain composite SWAP(θ) operations are shown in Fig. 4(g)–(i), as a function of
rotation angles), but e.g. the SWAP gate, or any non-diagonal gate using just rotation angle and relative variance in tunnel coupling noise, σ tij =t ij . They
phase gates and single-qubit Z-rotations is not possible. In general, a larger are evaluated using the exact perturbative Hamiltonian (Supplementary
set of gates allows more efficient decompositions for algorithms. For Note 4), at ϵ = 0. We average over N = 1000 random g-factor pairs. For the
example, the variational eigensolvers for the Fermi-Hubbard model natively Givens-like gate, we determine the sign of χ from the sign of the g-factor
decompose into SWAP-rotations and single-qubit Z-rotations, so we show difference. All gates enable fidelities F ≥ 0:9999 for sufficiently low noise in
how to construct the SWAP-rotation from the native operation. the tunnel coupling. For example, charge noise in the barrier gate voltage
By instead choosing φ = π/2 + 2πn, we obtain a gate close to the so- propagates to noise in the tunnel coupling. The dependence of both rotation
called Givens rotation (see Supplementary Note 5), as angles on tunnel coupling is reflected in the fidelities: angles that require
higher tij are more sensitive to tunnel coupling noise. However, since the
Zðφ11 þ π=2Þ  Zðφ11 þ π=2Þeiαþiφ rotation angles of the SWAP-rotation gate (7) arise from single-qubit Z-
× U Nat ðϵ; φ ¼ π=2 þ 2πn; χÞ ð6Þ rotations, it’s fidelity is approximately independent of rotation angles, and
  expected to be limited by the fidelity of the Givens(χ)SWAP operation.
¼ CPhase 2αðπ=2 þ 2πn; χÞ þ π GivensðχÞSWAP:
Transversal rotation gates
The circuit identity is illustrated in Fig. 4d. The angle of the Givens rotation A gate set enabling universal quantum computing requires another single-
is controllable with the polar angle analogue, although not all rotation angles qubit gate besides the Z(φq) gate and a maximally entangling two-qubit
are attainable equally easily. In particular, rotation angles of 0 and π/2 would gate 73
pffiffiffiffi . To this end, we propose to realise a globally applied
require negligible Zeeman energy difference or exchange strength, respec- X ¼ Ið1 þ iÞ=2 þ σ x ð1  iÞ=2. The gatepcomposes
ffiffiffiffi into
ffiy a single-qubit
pffiffiffi
tively. However, these cases are not interesting, since in the absence of rotation gate e.g. via thepidentity
ffiffiffiffi Yðφ q Þ :¼ X Zðφq Þ X .
Zeeman energy differences, we may employ a SWAP-rotation gate, and in In the nanogrid, a X gate can be applied globally by providing a small
the absence of an interaction the operation is non-entangling. B1 perpendicular to B0 from large resonant structures, such as a dielectric 3D
The rotation angle χ = ± π/4 corresponds to the case where the cavity resonator74, or a superconducting resonator based on a coplanar
(absolute value of the) Zeeman energy difference is equal to the exchange waveguide patterned e.g. over the metal gate layers75, with a resonance
strength. Here, the pmffiffiffiz = 0 matrix elements simplify to frequency coinciding with the average qubit frequency fSi ≈ 28 GHz, and a
jU Nat ðϵ; π=2; π=4Þij j ¼ 1= 2. The native operation UNat(ϵ, π/2, π/4) thus quality factor Q ≈ 100 to cover a bandwidth of 280 MHz corresponding to
acts as a controlled Hadamard operation for the mz = 0 subspace. The Gq ≤ ± 10−2 (>5σG, assuming σG = 10−3gSi). Global control allows avoiding
operation can be used to convert single-qubit Z(θ)-rotations into SWAP- issues related to crosstalk and impedance matching, which would be a
rotations, as challenge with partially or fully local broadband structures76.
      The global X-control together with pipelining provides an extra lim-
SWAPðθÞ ¼ eiθ ± iπ Z 2φZ  Z 2φZ Ising θ  2α  2φ itation for the circuit compilation
pffiffiffiffi and density of pipelining. Since all qubits
 π    on the pipeline undergo the X pulses, the algorithms must be compiled
× U Nat ϵ; 2 ; ± π4 Zð ± θÞ  Zð∓θÞ U Nat ϵ; π2 ; ± π4 :
with periodic X-control. A simple example code block for the pipelined,
ð7Þ global-X-controlled compilation is given by
 
The circuit is illustrated in Fig. 4e. We have written the circuit identity using Zðθ1 Þ; Xðπ=2Þ; Zðθ2 Þ; Zðθ3 Þ; X y ðπ=2Þ; Nativeðθ4 Þ × D=6; ð8Þ
the Ising gate for clarity, but in realising it using Eq. (5), we may absorb the
Z-rotations into the final step, reducing physical gates from 6 to 5. It pro- where Native(θ4) is a native two-qubit gate of the system, as discussed in
vides an exact method to perform SWAP-rotation operations, including the “Two-qubit gate family with gate-voltage-tuneable exchange”. This code
non-entangling SWAP gate, in the presence of Zeeman energy differences block allows pipelining at a filling density of one in every three (logical)
See e.g. refs. 71,72 for prior, related works discussing the non-entangling columns. The code block (8) maps to an equal density of single-qubit Z-
SWAP gate in the mz = 0 subspace. The fidelity of this operation does not rotation gates, Y-rotation gates, and native two-qubit interactions. Due to the
depend on the magnitude of ΔEZ (as long as an equally large exchange variations in g-factor discussed above, driving all spins with a single drive tone
strength is attainable), which means that the gate decomposition can be used is challenging. We instead opt for multitone driving and frequency binning77,
with e.g. micromagnets,
pffiffiffiffiffiffiffiffiffiffiffiffiffi with which ΔEZ ¼ Oð1  10 GHzÞ39. which is discussed in Supplementary Note 8. We show that reaching a
The SWAP operation obtained using identity (7) is visualised
 on the crosstalk-limited fidelity F ≥ 0:9999 for a qubit distribution with Gq ≤ ± 10−2
mz = 0 Bloch sphere as a trajectory for the initial state ∣ #" in Fig. 4f. The is feasible with 112 drive tones and a bin width νbin/(2π) ≥ 5 MHz.
strategy for choosing parameters for the φ = π/2 + 2πn operation is as fol-
lows (also see Supplementary Note 6 for further details). Knowing ΔEZ, we Application as bespoke hardware for a NISQ eigensolver
set Jij = ∣ΔEZ∣. We pffiffiffi are required to set the gate time, as We summarise the proposed qubit control protocols for operating the
τ ¼ ðπ=2 þ 2πnÞ=ð 2J ij Þ. The gate time is limited by a minimum set by silicon spin qubit pipeline from “Implementation with silicon quantum

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https://doi.org/10.1038/s41534-024-00823-y Article

Table 2 | Qubit control protocols on the pipeline

Operation Symbol Time Method

Shuttling τs 10 ns Global bucket-brigade pulses
Single-qubit Z-rotations τ1Q 1 μs (0.1 μs) Local g-factor Stark shifts
Single-qubit X-rotations τ1X 3τ1Q + 8τs = 3.06 μs (0.36 μs) Global B1-drive frequency bins
Two-qubit native gates τ2Q 1 μs (0.1 μs) Native exchange interaction
Two-qubit phase gates τ2P τ2Q + τ1Q + 3τs = 2.0 μs (0.23 μs) Composite from native gates and Z-rotations
Two-qubit SWAP-rotations τ2S 3τ2Q + 2τ1Q + 12τs = 5.1 μs (0.62 μs) Composite from native gates and Z-rotations
Summary of the protocols introduced in “Implementation with silicon quantum dots”. We have marked the gate times assuming τ1Q = τ2Q = 0.1 μs in parenthesis. Numbers that are not in parentheses
assume τ1Q = τ2Q = 1 μs. Faster gate times require higher attainable g-factor tuning to prevent gate time errors from dominating the infidelities.

Table 3 | NISQ Fermi-Hubbard eigensolver run-time on the pipeline

Eigensolver Symbol Run-time overhead Pipelined run-time overhead

flow level
     h     i
Run-time per circuit τconfig D1Q τ 1Q þ 3τ s þ D2Q τ 2S þ 3τ s Nreps ¼ 26 m D1Q þ 2Nreps τ 1Q þ 3τ s þ D2Q þ 2Nreps τ 2S þ 3τ s ¼ 1:7 s (0.25 s)
configuration (3.8 min)
Circuit configurations Nconfigs 3900 3900
Iterations Niters 100 100
Total run-time τrun NitersNconfigsτconfig = 230 months (35 months) NitersNconfigsτconfig = 7.9 days (11 h)
The times in parentheses assume τ1Q = τ2Q = 0.1 μs, whereas otherwise we assume, that τ1Q = τ2Q = 1 μs.

dots” in Table 2. The requirements of synchronous shuttling, lack of local Two types of classical parallelisation are possible. As discussed in “Qubit
runtime control, and qubit frequency variability leads to protocols where we pipeline”, pipelining allows to perform Nr number of repetitions for a circuit
fix gate times and adjust qubit frequencies with dc voltage tuneable para- of depth D in time (D + Nr)τ. For example, at maximal filling, this runtime
meters, namely the g-factor (qubit frequency) and the exchange strength. scaling is (D + 2Nr)τ. For single-qubit and two-qubit gate depths of D1Q and
Each of these protocols are feasible up to fidelities F ≥ 0:9999 in the pre- D2Q, the run-time for Nr repetitions on the nanogrid pipeline (Fig. 2a) with
sence of noise, in the realistic scenario where qubit frequency variabilities are three physical shuttling steps between gates is then (D1Q + 2Nr)
larger than the frequency tuneability. (τ1Q + 3τs) + (D2Q + 2Nr)(τ2S + 3τs). For D1Q = 1174 and D2Q = 219618, and
We now exemplify how these elements propagate into solving a the gate time estimates for Z-rotation and SWAP-rotation gates from Table 2,
quantum computing problem in the NISQ era. Here, we focus on the we find that pipelining reduces the run-time per circuit configuration from
variational eigensolver for the Fermi-Hubbard model, where the resources 25.5 min (assuming τ1Q = 1 μs) to 1.74 s, i.e. by roughly a factor of 880.
required to run the algorithm on a set of physical qubits have been estimated We may also run e.g. different circuit configurations on different
in18, and where the task is to estimate the ground state of a 5 × 5 Fermi- physical pipeline processors in parallel. To estimate the footprint of the
Hubbard Hamiltonian. See supplementary Note 9 for details of this algo- pipeline processor, we expect the width of a single pipe to be ~340 nm, with a
rithm. At the low level, the algorithm breaks down into SWAP-, and single- same-layer gate pitch of 100 nm. Likewise, we expect the length of a single-
qubit Z-rotation gates for the so-called (simulated) state initialisation and qubit or two-qubit gate step to be ~190 nm. Then, for N = 25 qubits, and a
(simulated) state evolution stages, while the bit-string (physical qubit) circuit depth of D = D1 + D2 = 1174 + 2196 = 3370 quantum logic gates, we
initialisation and readout stages also require qubit-selective qubit-flip X(π) estimate the footprint of a single pipeline qubit processor to be
and basis-change X(π/2) operations. We assume that we are not limited by 8.5 μm × 640.3 μm.
initialisation or readout times. That is, we assume that the initialization and
readout times are as fast as the clockspeed of 1 μs. The single-qubit gate Discussion
times, and the two-qubit gate time errors are upper limited by the qubit We have analysed a qubit pipeline architecture for realizing gate based
frequency tuneability. While the tuneability has not been studied on a large quantum computation in the NISQ era. The architecture minimizes run-
number of devices, based on the literature, we expect the processor clock- time local control resources, utilizing instead global run-time, and local pre-
speeds no slower than 1 MHz (at B0 = 1 T). This means that to run an configuration control. This is made possible by a combination of an
algorithm of depth 10000, for example, we require qubit T 2 ≥ 10 ms. increased qubit grid layout size, and by synchronized operation, where steps
We summarise the estimated pipelined run-time, and contributions to of qubit state shuttling and quantum logic gates alternate.
the run-time, of the Fermi-Hubbard variational eigensolver in Table 3, using Having described the architectural paradigm, we focused on a physical
the resource estimates from18. There are several layers at the high level. The implementation case-study in the SiMOS electron spin qubit platform.
algorithm requires a number of iterations. Each iteration consists of a Here, we laid out qubit control protocols under the pipeline- and platform-
number of runs, which is equal to the number of circuit configurations specific restrictions, demonstrating each theoretically with NISQ-high
multiplied by runs per configuration. The number of circuit configurations, fidelities while remaining robust against qubit frequency variabilities
in turn, is determined by the number of parameters, number of measured characteristic for the platform. Our main focus has been to address this
observables, and the number of noise levels, which is part of an error frequency variability, while we may improve robustness against noise with
mitigation protocol78. The number of runs per configuration is determined bespoke control methods in the future. Most of the elements are possible to
by the number of runs for one parameter, to measure one set of commuting implement with present-day technology without further advances, but we
observables, and the extra sampling cost for error mitigation. For each expect more microwave engineering efforts to designing and testing
parameter-observable-set-specific run, we may then evaluate the circuit switchable, dense transmission lines or resonators, and their ability to
run time. support a finite frequency bin. We then assessed the performance of this

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